diff --git a/firmware/ap_types/ap_common.h b/firmware/ap_types/ap_common.h new file mode 100644 index 0000000000000000000000000000000000000000..4d2886cbde0677df934734737548b3437f2b12f8 --- /dev/null +++ b/firmware/ap_types/ap_common.h @@ -0,0 +1,376 @@ +/* + * Copyright 2011-2019 Xilinx, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __AP_COMMON_H__ +#define __AP_COMMON_H__ + +// ---------------------------------------------------------------------- + +// Forward declaration of all AP types. +#include + + +#ifdef __SYNTHESIS__ +#error "The open-source version of AP types does not support synthesis." +#endif // ifdef __SYNTHESIS__ +#define _AP_ENABLE_HALF_ 0 + + +#if _AP_ENABLE_HALF_ == 1 +// Before ap_private definition. +#ifdef __SYNTHESIS__ +#define _HLS_HALF_DEFINED_ +typedef __fp16 half; +#else +class half; +#endif // __SYNTHESIS__ +#endif // _AP_ENABLE_HALF_ + +// ---------------------------------------------------------------------- + +// Macro functions +#define AP_MAX(a, b) ((a) > (b) ? (a) : (b)) +#define AP_MIN(a, b) ((a) < (b) ? (a) : (b)) +#define AP_ABS(a) ((a) >= 0 ? (a) : -(a)) + +#ifndef AP_ASSERT +#ifndef __SYNTHESIS__ +#include +#define AP_ASSERT(cond, msg) assert((cond) && (msg)) +#else +#define AP_ASSERT(cond, msg) +#endif // ifndef __SYNTHESIS__ +#endif // ifndef AP_ASSERT + +#ifndef __SYNTHESIS__ +// for fprintf messages. +#include +// for exit on error. +#include +#endif + +// same disable condition as assert. +#if !defined(__SYNTHESIS__) && !defined(NDEBUG) + +#define _AP_DEBUG(cond, ...) \ + do { \ + if ((cond)) { \ + fprintf(stderr, "DEBUG: " __VA_ARGS__); \ + fprintf(stderr, "\n"); \ + } \ + } while (0) +#define _AP_WARNING(cond, ...) \ + do { \ + if ((cond)) { \ + fprintf(stderr, "WARNING: " __VA_ARGS__); \ + fprintf(stderr, "\n"); \ + } \ + } while (0) +#define _AP_ERROR(cond, ...) \ + do { \ + if ((cond)) { \ + fprintf(stderr, "ERROR: " __VA_ARGS__); \ + fprintf(stderr, "\n"); \ + abort(); \ + } \ + } while (0) + +#else // if !defined(__SYNTHESIS__) && !defined(NDEBUG) + +#define __AP_VOID_CAST static_cast +#define _AP_DEBUG(cond, ...) (__AP_VOID_CAST(0)) +#define _AP_WARNING(cond, ...) (__AP_VOID_CAST(0)) +#define _AP_ERROR(cond, ...) (__AP_VOID_CAST(0)) + +#endif // if !defined(__SYNTHESIS__) && !defined(NDEBUG) else + +// ---------------------------------------------------------------------- + +// Attribute only for synthesis +#ifdef __SYNTHESIS__ +#define INLINE inline __attribute__((always_inline)) +//#define INLINE inline __attribute__((noinline)) +#else +#define INLINE inline +#endif + +#define AP_WEAK +// __attribute__((weak)) + +#ifndef AP_INT_MAX_W +#define AP_INT_MAX_W 1024 +#endif + +#define BIT_WIDTH_UPPER_LIMIT (1 << 15) +#if AP_INT_MAX_W > BIT_WIDTH_UPPER_LIMIT +#error "Bitwidth exceeds 32768 (1 << 15), the maximum allowed value" +#endif + +#define MAX_MODE(BITS) ((BITS + 1023) / 1024) + +// ---------------------------------------------------------------------- + +// XXX apcc cannot handle global std::ios_base::Init() brought in by +#ifndef AP_AUTOCC +#ifndef __SYNTHESIS__ +// for overload operator<< +#include +#endif +#endif // ifndef AP_AUTOCC + +#ifndef __SYNTHESIS__ +// for string format. +#include +// for string. +#include +#endif + +// for detecting if char is signed. +enum { CHAR_IS_SIGNED = (char)-1 < 0 }; + +// TODO we have similar traits in x_hls_utils.h, should consider unify. +namespace _ap_type { +template +struct is_signed { + static const bool value = _Tp(-1) < _Tp(1); +}; + +template +struct is_integral { + static const bool value = false; +}; +#define DEF_IS_INTEGRAL(CTYPE) \ + template <> \ + struct is_integral { \ + static const bool value = true; \ + }; +DEF_IS_INTEGRAL(bool) +DEF_IS_INTEGRAL(char) +DEF_IS_INTEGRAL(signed char) +DEF_IS_INTEGRAL(unsigned char) +DEF_IS_INTEGRAL(short) +DEF_IS_INTEGRAL(unsigned short) +DEF_IS_INTEGRAL(int) +DEF_IS_INTEGRAL(unsigned int) +DEF_IS_INTEGRAL(long) +DEF_IS_INTEGRAL(unsigned long) +DEF_IS_INTEGRAL(ap_slong) +DEF_IS_INTEGRAL(ap_ulong) +#undef DEF_IS_INTEGRAL + +template +struct enable_if {}; +// partial specialization for true +template +struct enable_if { + typedef _Tp type; +}; + +template +struct remove_const { + typedef _Tp type; +}; + +template +struct remove_const<_Tp const> { + typedef _Tp type; +}; +} // namespace _ap_type + +// ---------------------------------------------------------------------- + +// Define ssdm_int and _ssdm_op. +// XXX deleted in open-source version + +#ifndef NON_C99STRING +#define _AP_C99 true +#else +#define _AP_C99 false +#endif + +static inline unsigned char guess_radix(const char* s) { + unsigned char rd = 10; ///< default radix + const char* p = s; + // skip neg sign if it exists + if (p[0] == '-' || p[0] == '+') ++p; + // guess based on following two bits. + if (p[0] == '0') { + if (p[1] == 'b' || p[1] == 'B') { + rd = 2; + } else if (p[1] == 'o' || p[1] == 'O') { + rd = 8; + } else if (p[1] == 'x' || p[1] == 'X') { + rd = 16; + } else if (p[1] == 'd' || p[1] == 'D') { + rd = 10; + } + } + return rd; +} + +// ---------------------------------------------------------------------- + +// Basic integral struct upon which ap_int and ap_fixed are defined. +#ifdef __SYNTHESIS__ +// Use ssdm_int, a compiler dependent, attribute constrained integeral type as +// basic data type. +#define _AP_ROOT_TYPE ssdm_int +// Basic ops. +#define _AP_ROOT_op_concat(Ret, X, Y) _ssdm_op_concat(Ret, X, Y) +#define _AP_ROOT_op_get_bit(Val, Bit) _ssdm_op_get_bit(Val, Bit) +#define _AP_ROOT_op_set_bit(Val, Bit, Repl) _ssdm_op_set_bit(Val, Bit, Repl) +#define _AP_ROOT_op_get_range(Val, Lo, Hi) _ssdm_op_get_range(Val, Lo, Hi) +#define _AP_ROOT_op_set_range(Val, Lo, Hi, Repl) \ + _ssdm_op_set_range(Val, Lo, Hi, Repl) +#define _AP_ROOT_op_reduce(Op, Val) _ssdm_op_reduce(Op, Val) +#else // ifdef __SYNTHESIS__ +// Use ap_private for compiler-independent basic data type +template +class ap_private; +/// model ssdm_int in standard C++ for simulation. +template +struct ssdm_int_sim { + /// integral type with template-specified width and signedness. + ap_private<_AP_W, _AP_S> V; + ssdm_int_sim() {} +}; +#define _AP_ROOT_TYPE ssdm_int_sim +// private's ref uses _AP_ROOT_TYPE. +#include +// XXX The C-sim model cannot use GCC-extension +// Basic ops. Ret and Val are ap_private. +template +inline _Tp1 _AP_ROOT_op_concat(const _Tp1& Ret, const _Tp2& X, const _Tp3& Y) { + _Tp1 r = (X).operator,(Y); + return r; +} +#define _AP_ROOT_op_get_bit(Val, Bit) (Val).get_bit((Bit)) +template +inline _Tp1& _AP_ROOT_op_set_bit(_Tp1& Val, const _Tp2& Bit, const _Tp3& Repl) { + (Val).set_bit((Bit), (Repl)); + return Val; +} +// notice the order of high and low index is different in ssdm call and +// ap_private.range()... +#define _AP_ROOT_op_get_range(Val, Lo, Hi) (Val).range((Hi), (Lo)) +template +inline _Tp1& _AP_ROOT_op_set_range(_Tp1& Val, const _Tp2& Lo, const _Tp3& Hi, + const _Tp4& Repl) { + (Val).range((Hi), (Lo)) = Repl; + return (Val); +} +#define _AP_ROOT_op_and_reduce(Val) (Val).and_reduce() +#define _AP_ROOT_op_nand_reduce(Val) (Val).nand_reduce() +#define _AP_ROOT_op_or_reduce(Val) (Val).or_reduce() +#define _AP_ROOT_op_xor_reduce(Val) (Val).xor_reduce() +// ## is the concatenation in preprocessor: +#define _AP_ROOT_op_reduce(Op, Val) _AP_ROOT_op_##Op##_reduce(Val) +#endif // ifdef __SYNTHESIS__ else + +// ---------------------------------------------------------------------- + +// Constants for half, single, double pricision floating points +#define HALF_MAN 10 +#define FLOAT_MAN 23 +#define DOUBLE_MAN 52 + +#define HALF_EXP 5 +#define FLOAT_EXP 8 +#define DOUBLE_EXP 11 + +#define BIAS(e) ((1L << (e - 1L)) - 1L) +#define HALF_BIAS BIAS(HALF_EXP) +#define FLOAT_BIAS BIAS(FLOAT_EXP) +#define DOUBLE_BIAS BIAS(DOUBLE_EXP) + +#define APFX_IEEE_DOUBLE_E_MAX DOUBLE_BIAS +#define APFX_IEEE_DOUBLE_E_MIN (-DOUBLE_BIAS + 1) + +INLINE ap_ulong doubleToRawBits(double pf) { + union { + ap_ulong __L; + double __D; + } LD; + LD.__D = pf; + return LD.__L; +} + +INLINE unsigned int floatToRawBits(float pf) { + union { + unsigned int __L; + float __D; + } LD; + LD.__D = pf; + return LD.__L; +} + +#if _AP_ENABLE_HALF_ == 1 +INLINE unsigned short halfToRawBits(half pf) { +#ifdef __SYNTHESIS__ + union { + unsigned short __L; + half __D; + } LD; + LD.__D = pf; + return LD.__L; +#else + return pf.get_bits(); +#endif +} +#endif + +// usigned long long is at least 64-bit +INLINE double rawBitsToDouble(ap_ulong pi) { + union { + ap_ulong __L; + double __D; + } LD; + LD.__L = pi; + return LD.__D; +} + +// long is at least 32-bit +INLINE float rawBitsToFloat(unsigned long pi) { + union { + unsigned int __L; + float __D; + } LD; + LD.__L = pi; + return LD.__D; +} + +#if _AP_ENABLE_HALF_ == 1 +// short is at least 16-bit +INLINE half rawBitsToHalf(unsigned short pi) { +#ifdef __SYNTHESIS__ + union { + unsigned short __L; + half __D; + } LD; + LD.__L = pi; + return LD.__D; +#else + // sim model of half has a non-trivial constructor + half __D; + __D.set_bits(pi); + return __D; +#endif +} +#endif + +#endif // ifndef __AP_COMMON_H__ + +// -*- cpp -*- diff --git a/firmware/ap_types/ap_decl.h b/firmware/ap_types/ap_decl.h new file mode 100644 index 0000000000000000000000000000000000000000..ddd00f1c7fd335af69311657a3aebfd106a5d292 --- /dev/null +++ b/firmware/ap_types/ap_decl.h @@ -0,0 +1,212 @@ +/* + * Copyright 2011-2019 Xilinx, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __AP_DECL_H__ +#define __AP_DECL_H__ + +// ---------------------------------------------------------------------- + +#if !defined(__AP_FIXED_H__) && !defined(__AP_INT_H__) && !defined(__AUTOPILOT_CBE_H__) && !defined(__HLS_HALF_H__) +#error "Only ap_fixed.h and ap_int.h can be included directly in user code." +#endif + +// Test __SYNTHESIS__ only for mode +#if !defined(__SYNTHESIS__) && (defined(AESL_SYN) || defined(__HLS_SYN__)) +//#pragma message "AESL_SYN and __HLS_SYN__ should be replaced by __SYNTHESIS__" +#define __SYNTHESIS__ +#endif + +/* for safety*/ +#if (defined(_AP_N) || defined(_AP_C)) +#error One or more of the following is defined: _AP_N, _AP_C. Definition conflicts with their usage as template parameters. +#endif + +/* for safety*/ +#if (defined(_AP_W) || defined(_AP_I) || defined(_AP_S) || defined(_AP_Q) || \ + defined(_AP_O) || defined(_AP_W2) || defined(_AP_I2) || \ + defined(_AP_S2) || defined(_AP_Q2) || defined(_AP_O2) || \ + defined(_AP_N) || defined(_AP_N2)) +#error \ + "One or more of the following is defined: _AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N, _AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2. Definition conflicts with their usage as template parameters." +#endif + +/*for safety*/ +#if (defined(_AP_W3) || defined(_AP_S3) || defined(_AP_W4) || defined(_AP_S4)) +#error \ + "One or more of the following is defined: _AP_W3, _AP_S3, _AP_W4,_AP_S4. Definition conflicts with their usage as template parameters." +#endif + +#if (defined(_AP_W1) || defined(_AP_S1) || defined(_AP_T) || \ + defined(_AP_T1) || defined(_AP_T2) || defined(_AP_T3) || defined(_AP_T4)) +#error \ + "One or more of the following is defined: _AP_W1, _AP_S1, _AP_T, _AP_T1, _AP_T2, _AP_T3, _AP_T4. Definition conflicts with their usage as template parameters." +#endif + +#ifndef __cplusplus +#error "AP data type can only be used in C++" +#endif + +// ---------------------------------------------------------------------- + +#ifndef __SC_COMPATIBLE__ +/// ap_fixed quantification mode +enum ap_q_mode { + AP_RND, //< rounding to plus infinity + AP_RND_ZERO, //< rounding to zero + AP_RND_MIN_INF, //< rounding to minus infinity + AP_RND_INF, //< rounding to infinity + AP_RND_CONV, //< convergent rounding + AP_TRN, //< truncation + AP_TRN_ZERO, //< truncation to zero +}; + +// FIXME for legacy code +#ifndef SYSTEMC_INCLUDED +#define SC_RND AP_RND +#define SC_RND_ZERO AP_RND_ZERO +#define SC_RND_MIN_INF AP_RND_MIN_INF +#define SC_RND_INF AP_RND_INF +#define SC_RND_CONV AP_RND_CONV +#define SC_TRN AP_TRN +#define SC_TRN_ZERO AP_TRN_ZERO +#endif // !defined(SYSTEMC_INCLUDED) + +/// ap_fixed saturation mode +enum ap_o_mode { + AP_SAT, //< saturation + AP_SAT_ZERO, //< saturation to zero + AP_SAT_SYM, //< symmetrical saturation + AP_WRAP, //< wrap-around (*) + AP_WRAP_SM, //< sign magnitude wrap-around (*) +}; + +// FIXME for legacy code +#ifndef SYSTEMC_INCLUDED +#define SC_SAT AP_SAT +#define SC_SAT_ZERO AP_SAT_ZERO +#define SC_SAT_SYM AP_SAT_SYM +#define SC_WRAP AP_WRAP +#define SC_WRAP_SM AP_WRAP_SM +#endif // !defined(SYSTEMC_INCLUDED) + +#else // defined(__SC_COMPATIBLE__) + +// There will not be sc_fxdefs.h, and the emu should be defined by ap_fixed. + +/// ap_fixed quantification mode +enum ap_q_mode { + SC_RND, //< rounding to plus infinity + SC_RND_ZERO, //< rounding to zero + SC_RND_MIN_INF, //< rounding to minus infinity + SC_RND_INF, //< rounding to infinity + SC_RND_CONV, //< convergent rounding + SC_TRN, //< truncation + SC_TRN_ZERO, //< truncation to zero +}; + +#define AP_RND SC_RND +#define AP_RND_ZERO SC_RND_ZERO +#define AP_RND_MIN_INF SC_RND_MIN_INF +#define AP_RND_INF SC_RND_INF +#define AP_RND_CONV SC_RND_CONV +#define AP_TRN SC_TRN +#define AP_TRN_ZERO SC_TRN_ZERO + +/// ap_fixed saturation mode +enum ap_o_mode { + SC_SAT, //< saturation + SC_SAT_ZERO, //< saturation to zero + SC_SAT_SYM, //< symmetrical saturation + SC_WRAP, //< wrap-around (*) + SC_WRAP_SM, //< sign magnitude wrap-around (*) +}; + +#define AP_SAT SC_SAT +#define AP_SAT_ZERO SC_SAT_ZERO +#define AP_SAT_SYM SC_SAT_SYM +#define AP_WRAP SC_WRAP +#define AP_WRAP_SM SC_WRAP_SM + +#endif // defined(__SC_COMPATIBLE__) + +template +struct ap_int_base; + +template +struct ap_int; + +template +struct ap_uint; + +template +struct ap_range_ref; + +template +struct ap_bit_ref; + +template +struct ap_concat_ref; + +template +struct ap_fixed_base; + +template +struct ap_fixed; + +template +struct ap_ufixed; + +template +struct af_range_ref; + +template +struct af_bit_ref; + +/// string base mode +enum BaseMode { AP_BIN = 2, AP_OCT = 8, AP_DEC = 10, AP_HEX = 16 }; + +#ifndef SYSTEMC_INCLUDED +#define SC_BIN 2 +#define SC_OCT 8 +#define SC_DEC 10 +#define SC_HEX 16 +#endif // !defined(SYSTEMC_INCLUDED) + +// Alias C data types +#ifdef _MSC_VER +typedef signed __int64 ap_slong; +typedef unsigned __int64 ap_ulong; +#else // !defined(_MSC_VER) +typedef signed long long ap_slong; +typedef unsigned long long ap_ulong; +#endif // !defined(_MSC_VER) + +enum { + _AP_SIZE_char = 8, + _AP_SIZE_short = sizeof(short) * 8, + _AP_SIZE_int = sizeof(int) * 8, + _AP_SIZE_long = sizeof(long) * 8, + _AP_SIZE_ap_slong = sizeof(ap_slong) * 8 +}; + +#endif // !defined(__AP_DECL_H__) + +// -*- cpp -*- diff --git a/firmware/ap_types/ap_fixed.h b/firmware/ap_types/ap_fixed.h new file mode 100644 index 0000000000000000000000000000000000000000..cd0192bcb991d0c1bc30ea45273ee60f673a62dc --- /dev/null +++ b/firmware/ap_types/ap_fixed.h @@ -0,0 +1,360 @@ +/* + * Copyright 2011-2019 Xilinx, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __AP_FIXED_H__ +#define __AP_FIXED_H__ + +#include +#include +#include + +//--------------------------------------------------------------- + +/// Signed Arbitrary Precision Fixed-Point Type. +// default for _AP_Q, _AP_O and _AP_N set in ap_decl.h +template +struct ap_fixed : ap_fixed_base<_AP_W, _AP_I, true, _AP_Q, _AP_O, _AP_N> { + typedef ap_fixed_base<_AP_W, _AP_I, true, _AP_Q, _AP_O, _AP_N> Base; + // Constructor + /// default ctor + INLINE ap_fixed() : Base() {} + + /// default copy ctor + INLINE ap_fixed(const ap_fixed& op) { Base::V = op.V; } + + /// copy ctor from ap_fixed_base. + template + INLINE ap_fixed(const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, + _AP_O2, _AP_N2>& op) + : Base(op) {} + + template + INLINE ap_fixed(const volatile ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, + _AP_O2, _AP_N2>& op) + : Base(op) {} + + //// from ap_fixed + //template + //INLINE ap_fixed( + // const ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op) + // : Base(ap_fixed_base<_AP_W2, _AP_I2, true, _AP_Q2, _AP_O2, _AP_N2>(op)) {} + + //template + //INLINE ap_fixed( + // const volatile ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op) + // : Base(ap_fixed_base<_AP_W2, _AP_I2, true, _AP_Q2, _AP_O2, _AP_N2>(op)) {} + + //// from ap_ufixed. + //template + //INLINE ap_fixed( + // const ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op) + // : Base(ap_fixed_base<_AP_W2, _AP_I2, false, _AP_Q2, _AP_O2, _AP_N2>(op)) { + //} + + //template + //INLINE ap_fixed( + // const volatile ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op) + // : Base(ap_fixed_base<_AP_W2, _AP_I2, false, _AP_Q2, _AP_O2, _AP_N2>(op)) { + //} + + /// copy ctor from ap_int_base. + template + INLINE ap_fixed(const ap_int_base<_AP_W2, _AP_S2>& op) : Base(op) {} + + template + INLINE ap_fixed(const volatile ap_int_base<_AP_W2, _AP_S2>& op) : Base(op) {} + + //// from ap_int. + //template + //INLINE ap_fixed(const ap_int<_AP_W2>& op) + // : Base(ap_int_base<_AP_W2, true>(op)) {} + + //template + //INLINE ap_fixed(const volatile ap_int<_AP_W2>& op) + // : Base(ap_int_base<_AP_W2, true>(op)) {} + + //// from ap_uint. + //template + //INLINE ap_fixed(const ap_uint<_AP_W2>& op) + // : Base(ap_int_base<_AP_W2, false>(op)) {} + + //template + //INLINE ap_fixed(const volatile ap_uint<_AP_W2>& op) + // : Base(ap_int_base<_AP_W2, false>(op)) {} + + // from ap_bit_ref. + template + INLINE ap_fixed(const ap_bit_ref<_AP_W2, _AP_S2>& op) : Base(op) {} + + // from ap_range_ref. + template + INLINE ap_fixed(const ap_range_ref<_AP_W2, _AP_S2>& op) : Base(op) {} + + // from ap_concat_ref. + template + INLINE ap_fixed(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& op) + : Base(op) {} + + // from af_bit_ref. + template + INLINE ap_fixed( + const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) + : Base(op) {} + + // from af_range_ref. + template + INLINE ap_fixed( + const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) + : Base(op) {} + +// from c types. +#define CTOR(TYPE) \ + INLINE ap_fixed(TYPE v) : Base(v) {} + + CTOR(bool) + CTOR(char) + CTOR(signed char) + CTOR(unsigned char) + CTOR(short) + CTOR(unsigned short) + CTOR(int) + CTOR(unsigned int) + CTOR(long) + CTOR(unsigned long) + CTOR(ap_slong) + CTOR(ap_ulong) +#if _AP_ENABLE_HALF_ == 1 + CTOR(half) +#endif + CTOR(float) + CTOR(double) +#undef CTOR + + INLINE ap_fixed(const char* s) : Base(s) {} + + INLINE ap_fixed(const char* s, signed char rd) : Base(s, rd) {} + + // Assignment + // The assignment operator is technically inherited; however, it is always + // hidden by an explicitly or implicitly defined assignment operator for the + // derived class. + /* XXX ctor will be used when right is not of proper type. */ + INLINE ap_fixed& operator=( + const ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>& op) { + Base::V = op.V; + return *this; + } + + INLINE void operator=( + const ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>& op) volatile { + Base::V = op.V; + } + + INLINE ap_fixed& operator=( + const volatile ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>& op) { + Base::V = op.V; + return *this; + } + + INLINE void operator=( + const volatile ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>& op) volatile { + Base::V = op.V; + } +}; // struct ap_fixed. + +//------------------------------------------------------------------- + +// Unsigned Arbitrary Precision Fixed-Point Type. +// default for _AP_Q, _AP_O and _AP_N set in ap_decl.h +template +struct ap_ufixed : ap_fixed_base<_AP_W, _AP_I, false, _AP_Q, _AP_O, _AP_N> { + typedef ap_fixed_base<_AP_W, _AP_I, false, _AP_Q, _AP_O, _AP_N> Base; + // Constructor + /// default ctor + INLINE ap_ufixed() : Base() {} + + /// default copy ctor + INLINE ap_ufixed(const ap_ufixed& op) { Base::V = op.V; } + + /// copy ctor from ap_fixed_base + template + INLINE ap_ufixed(const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, + _AP_O2, _AP_N2>& op) + : Base(op) {} + + /// copy ctor from ap_fixed_base + template + INLINE ap_ufixed(const volatile ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, + _AP_O2, _AP_N2>& op) + : Base(op) {} + + //template + //INLINE ap_ufixed( + // const ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op) + // : Base(ap_fixed_base<_AP_W2, _AP_I2, true, _AP_Q2, _AP_O2, _AP_N2>(op)) {} + + //template + //INLINE ap_ufixed( + // const volatile ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op) + // : Base(ap_fixed_base<_AP_W2, _AP_I2, true, _AP_Q2, _AP_O2, _AP_N2>(op)) {} + + //template + //INLINE ap_ufixed( + // const ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op) + // : Base(ap_fixed_base<_AP_W2, _AP_I2, false, _AP_Q2, _AP_O2, _AP_N2>(op)) { + //} + + //template + //INLINE ap_ufixed( + // const volatile ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op) + // : Base(ap_fixed_base<_AP_W2, _AP_I2, false, _AP_Q2, _AP_O2, _AP_N2>(op)) { + //} + + /// copy ctor from ap_int_base. + template + INLINE ap_ufixed(const ap_int_base<_AP_W2, _AP_S2>& op) : Base(op) {} + + template + INLINE ap_ufixed(const volatile ap_int_base<_AP_W2, _AP_S2>& op) : Base(op) {} + + //template + //INLINE ap_ufixed(const ap_int<_AP_W2>& op) + // : Base(ap_int_base<_AP_W2, true>(op)) {} + + //template + //INLINE ap_ufixed(const volatile ap_int<_AP_W2>& op) + // : Base(ap_int_base<_AP_W2, true>(op)) {} + + //template + //INLINE ap_ufixed(const ap_uint<_AP_W2>& op) + // : Base(ap_int_base<_AP_W2, false>(op)) {} + + //template + //INLINE ap_ufixed(const volatile ap_uint<_AP_W2>& op) + // : Base(ap_int_base<_AP_W2, false>(op)) {} + + template + INLINE ap_ufixed(const ap_bit_ref<_AP_W2, _AP_S2>& op) : Base(op) {} + + template + INLINE ap_ufixed(const ap_range_ref<_AP_W2, _AP_S2>& op) : Base(op) {} + + template + INLINE ap_ufixed(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& op) + : Base(op) {} + + template + INLINE ap_ufixed( + const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) + : Base(op) {} + + template + INLINE ap_ufixed( + const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) + : Base(op) {} + +#define CTOR(TYPE) \ + INLINE ap_ufixed(TYPE v) : Base(v) {} + + CTOR(bool) + CTOR(char) + CTOR(signed char) + CTOR(unsigned char) + CTOR(short) + CTOR(unsigned short) + CTOR(int) + CTOR(unsigned int) + CTOR(long) + CTOR(unsigned long) + CTOR(ap_slong) + CTOR(ap_ulong) +#if _AP_ENABLE_HALF_ == 1 + CTOR(half) +#endif + CTOR(float) + CTOR(double) +#undef CTOR + + INLINE ap_ufixed(const char* s) : Base(s) {} + + INLINE ap_ufixed(const char* s, signed char rd) : Base(s, rd) {} + + // Assignment + INLINE ap_ufixed& operator=( + const ap_ufixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>& op) { + Base::V = op.V; + return *this; + } + + INLINE void operator=( + const ap_ufixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>& op) volatile { + Base::V = op.V; + } + + INLINE ap_ufixed& operator=( + const volatile ap_ufixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>& op) { + Base::V = op.V; + return *this; + } + + INLINE void operator=(const volatile ap_ufixed<_AP_W, _AP_I, _AP_Q, _AP_O, + _AP_N>& op) volatile { + Base::V = op.V; + } +}; // struct ap_ufixed + + +#if !defined(__SYNTHESIS__) && (defined(SYSTEMC_H) || defined(SYSTEMC_INCLUDED)) +// XXX sc_trace overload for ap_fixed is already included in +// "ap_sysc/ap_sc_extras.h", so do not define in synthesis. +template +INLINE void sc_trace(sc_core::sc_trace_file* tf, + const ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>& op, + const std::string& name) { + tf->trace(sc_dt::sc_lv<_AP_W>(op.to_string(2).c_str()), name); +} + +template +INLINE void sc_trace(sc_core::sc_trace_file* tf, + const ap_ufixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>& op, + const std::string& name) { + tf->trace(sc_dt::sc_lv<_AP_W>(op.to_string(2).c_str()), name); +} +#endif // System C sim + +// Specialization of std containers, so that std::complex can have its +// image part automatically zero-initialized when only real part is provided. +#include + +#endif // ifndef __AP_FIXED_H__ + +// -*- cpp -*- diff --git a/firmware/ap_types/ap_fixed_base.h b/firmware/ap_types/ap_fixed_base.h new file mode 100644 index 0000000000000000000000000000000000000000..1d94b938f04af5316d476d0b6b39d515a5431b85 --- /dev/null +++ b/firmware/ap_types/ap_fixed_base.h @@ -0,0 +1,2354 @@ +/* + * Copyright 2011-2019 Xilinx, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __AP_FIXED_BASE_H__ +#define __AP_FIXED_BASE_H__ + +#ifndef __AP_FIXED_H__ +#error "Only ap_fixed.h and ap_int.h can be included directly in user code." +#endif + +// for ap_int_base and its reference types. +#include +#ifndef __SYNTHESIS__ +#if _AP_ENABLE_HALF_ == 1 +// for half type +#include +#endif +// for std io +#include +#endif + +#ifndef __cplusplus +#error "C++ is required to include this header file" +#else // __cplusplus + +// for warning on unsupported rounding mode in conversion to float/double. +#if !defined(__SYNTHESIS__) && __cplusplus >= 201103L && \ + (defined(__gnu_linux__) || defined(_WIN32)) +#define AP_FIXED_ENABLE_CPP_FENV 1 +#include +#endif + +// ---------------------------------------------------------------------- + +/* Major TODO + long double support: constructor, assign and other operators. + binary operators with ap_fixed_base and const char*. + return ap_fixed/ap_ufixed when result signedness is known. +*/ + +// Helper function in conversion to floating point types. + +#ifdef __SYNTHESIS__ +#define _AP_ctype_op_get_bit(var, index) _AP_ROOT_op_get_bit(var, index) +#define _AP_ctype_op_set_bit(var, index, x) _AP_ROOT_op_set_bit(var, index, x) +#define _AP_ctype_op_get_range(var, low, high) \ + _AP_ROOT_op_get_range(var, low, high) +#define _AP_ctype_op_set_range(var, low, high, x) \ + _AP_ROOT_op_set_range(var, low, high, x) +#else // ifdef __SYNTHESIS__ +template +inline bool _AP_ctype_op_get_bit(_Tp1& var, const _Tp2& index) { + return !!(var & (1ull << (index))); +} +template +inline _Tp1 _AP_ctype_op_set_bit(_Tp1& var, const _Tp2& index, const _Tp3& x) { + var |= (((x) ? 1ull : 0ull) << (index)); + return var; +} +template +inline _Tp1 _AP_ctype_op_get_range(_Tp1& var, const _Tp2& low, + const _Tp3& high) { + _Tp1 r = var; + ap_ulong mask = -1ll; + mask >>= (sizeof(_Tp1) * 8 - ((high) - (low) + 1)); + r >>= (low); + r &= mask; + return r; +} +template +inline _Tp1 _AP_ctype_op_set_range(_Tp1& var, const _Tp2& low, const _Tp3& high, + const _Tp4& x) { + ap_ulong mask = -1ll; + mask >>= (_AP_SIZE_ap_slong - ((high) - (low) + 1)); + var &= ~(mask << (low)); + var |= ((mask & x) << (low)); + return var; +} +#endif // ifdef __SYNTHESIS__ + + +// trait for letting base class to return derived class. +// Notice that derived class template is incomplete, and we cannot use +// the member of the derived class. +template +struct _ap_fixed_factory; +template +struct _ap_fixed_factory<_AP_W2, _AP_I2, true> { + typedef ap_fixed<_AP_W2, _AP_I2> type; +}; +template +struct _ap_fixed_factory<_AP_W2, _AP_I2, false> { + typedef ap_ufixed<_AP_W2, _AP_I2> type; +}; + +/// ap_fixed_base: AutoPilot fixed point. +/** partial specialization of signed. + @tparam _AP_W width. + @tparam _AP_I integral part width. + @tparam _AP_S signed. + @tparam _AP_Q quantization mode. Default is AP_TRN. + @tparam _AP_O saturation mode. Default is AP_WRAP. + @tparam _AP_N saturation wrap value. Default is 0. + */ +// default for _AP_Q, _AP_O and _AP_N set in ap_decl.h +template +struct ap_fixed_base : _AP_ROOT_TYPE<_AP_W, _AP_S> { + public: + typedef _AP_ROOT_TYPE<_AP_W, _AP_S> Base; + static const int width = _AP_W; + static const int iwidth = _AP_I; + static const ap_q_mode qmode = _AP_Q; + static const ap_o_mode omode = _AP_O; + + /// Return type trait. + template + struct RType { + enum { + _AP_F = _AP_W - _AP_I, + F2 = _AP_W2 - _AP_I2, + mult_w = _AP_W + _AP_W2, + mult_i = _AP_I + _AP_I2, + mult_s = _AP_S || _AP_S2, + plus_w = AP_MAX(_AP_I + (_AP_S2 && !_AP_S), _AP_I2 + (_AP_S && !_AP_S2)) + + 1 + AP_MAX(_AP_F, F2), + plus_i = + AP_MAX(_AP_I + (_AP_S2 && !_AP_S), _AP_I2 + (_AP_S && !_AP_S2)) + 1, + plus_s = _AP_S || _AP_S2, + minus_w = + AP_MAX(_AP_I + (_AP_S2 && !_AP_S), _AP_I2 + (_AP_S && !_AP_S2)) + 1 + + AP_MAX(_AP_F, F2), + minus_i = + AP_MAX(_AP_I + (_AP_S2 && !_AP_S), _AP_I2 + (_AP_S && !_AP_S2)) + 1, + minus_s = true, +#ifndef __SC_COMPATIBLE__ + div_w = _AP_S2 + _AP_W + AP_MAX(F2, 0), +#else + div_w = _AP_S2 + _AP_W + AP_MAX(F2, 0) + AP_MAX(_AP_I2, 0), +#endif + div_i = _AP_S2 + _AP_I + F2, + div_s = _AP_S || _AP_S2, + logic_w = + AP_MAX(_AP_I + (_AP_S2 && !_AP_S), _AP_I2 + (_AP_S && !_AP_S2)) + + AP_MAX(_AP_F, F2), + logic_i = AP_MAX(_AP_I + (_AP_S2 && !_AP_S), _AP_I2 + (_AP_S && !_AP_S2)), + logic_s = _AP_S || _AP_S2 + }; + + typedef ap_fixed_base<_AP_W, _AP_I, _AP_S> lhs; + typedef ap_fixed_base<_AP_W2, _AP_I2, _AP_S2> rhs; + + typedef ap_fixed_base mult_base; + typedef ap_fixed_base plus_base; + typedef ap_fixed_base minus_base; + typedef ap_fixed_base logic_base; + typedef ap_fixed_base div_base; + typedef ap_fixed_base<_AP_W, _AP_I, _AP_S> arg1_base; + + typedef typename _ap_fixed_factory::type mult; + typedef typename _ap_fixed_factory::type plus; + typedef typename _ap_fixed_factory::type minus; + typedef typename _ap_fixed_factory::type logic; + typedef typename _ap_fixed_factory::type div; + typedef typename _ap_fixed_factory<_AP_W, _AP_I, _AP_S>::type arg1; + }; + + private: +#ifndef __SYNTHESIS__ + // This cannot handle hex float format string. + void fromString(const std::string& val, unsigned char radix) { + _AP_ERROR(!(radix == 2 || radix == 8 || radix == 10 || radix == 16), + "ap_fixed_base::fromString(%s, %d)", val.c_str(), radix); + + Base::V = 0; + int startPos = 0; + int endPos = val.length(); + int decPos = val.find("."); + if (decPos == -1) decPos = endPos; + + // handle sign + bool isNegative = false; + if (val[0] == '-') { + isNegative = true; + ++startPos; + } else if (val[0] == '+') + ++startPos; + + // If there are no integer bits, e.g.: + // .0000XXXX, then keep at least one bit. + // If the width is greater than the number of integer bits, e.g.: + // XXXX.XXXX, then we keep the integer bits + // if the number of integer bits is greater than the width, e.g.: + // XXX000 then we keep the integer bits. + // Always keep one bit. + ap_fixed_base + integer_bits = 0; + + // Figure out if we can shift instead of multiply + unsigned shift = (radix == 16 ? 4 : radix == 8 ? 3 : radix == 2 ? 1 : 0); + + //std::cout << "\n\n" << val << "\n"; + //std::cout << startPos << " " << decPos << " " << endPos << "\n"; + + bool sticky_int = false; + + // Traverse the integer digits from the MSD, multiplying by radix as we go. + for (int i = startPos; i < decPos; i++) { + // Get a digit + char cdigit = val[i]; + if (cdigit == '\0') continue; + unsigned digit = ap_private_ops::decode_digit(cdigit, radix); + + sticky_int |= integer_bits[AP_MAX(_AP_I, 4) + 4 - 1] | + integer_bits[AP_MAX(_AP_I, 4) + 4 - 2] | + integer_bits[AP_MAX(_AP_I, 4) + 4 - 3] | + integer_bits[AP_MAX(_AP_I, 4) + 4 - 4]; + // Shift or multiply the value by the radix + if (shift) + integer_bits <<= shift; + else + integer_bits *= radix; + + // Add in the digit we just interpreted + integer_bits += digit; + //std::cout << "idigit = " << digit << " " << integer_bits.to_string() + // << " " << sticky_int << "\n"; + } + integer_bits[AP_MAX(_AP_I, 4) + 4 - 3] = + integer_bits[AP_MAX(_AP_I, 4) + 4 - 3] | sticky_int; + + ap_fixed_base fractional_bits = 0; + bool sticky = false; + + // Traverse the fractional digits from the LSD, dividing by radix as we go. + for (int i = endPos - 1; i >= decPos + 1; i--) { + // Get a digit + char cdigit = val[i]; + if (cdigit == '\0') continue; + unsigned digit = ap_private_ops::decode_digit(cdigit, radix); + // Add in the digit we just interpreted + fractional_bits += digit; + + sticky |= fractional_bits[0] | fractional_bits[1] | fractional_bits[2] | + fractional_bits[3]; + // Shift or divide the value by the radix + if (shift) + fractional_bits >>= shift; + else + fractional_bits /= radix; + + //std::cout << "fdigit = " << digit << " " << fractional_bits.to_string() + // << " " << sticky << "\n"; + } + + //std::cout << "Int =" << integer_bits.to_string() << " " << + // fractional_bits.to_string() << "\n"; + + fractional_bits[0] = fractional_bits[0] | sticky; + + if (isNegative) + *this = -(integer_bits + fractional_bits); + else + *this = integer_bits + fractional_bits; + + //std::cout << "end = " << this->to_string(16) << "\n"; + } + + /// report invalid constrction of ap_fixed_base + INLINE void report() { + if (!_AP_S && _AP_O == AP_WRAP_SM) { + fprintf(stderr, "ap_ufxied<...> cannot support AP_WRAP_SM.\n"); + exit(1); + } + if (_AP_W > MAX_MODE(AP_INT_MAX_W) * 1024) { + fprintf(stderr, + "[E] ap_%sfixed<%d, ...>: Bitwidth exceeds the " + "default max value %d. Please use macro " + "AP_INT_MAX_W to set a larger max value.\n", + _AP_S ? "" : "u", _AP_W, MAX_MODE(AP_INT_MAX_W) * 1024); + exit(1); + } + } +#else + INLINE void report() {} +#endif // ifdef __SYNTHESIS__ + + /// @name helper functions. + // @{ + INLINE void overflow_adjust(bool underflow, bool overflow, bool lD, + bool sign) { + if (!underflow && !overflow) return; + if (_AP_O == AP_WRAP) { + if (_AP_N == 0) return; + if (_AP_S) { + // signed AP_WRAP + // n_bits == 1 + Base::V = _AP_ROOT_op_set_bit(Base::V, _AP_W - 1, sign); + if (_AP_N > 1) { + // n_bits > 1 + ap_int_base<_AP_W, false> mask(-1); + if (sign) mask.V = 0; + Base::V = + _AP_ROOT_op_set_range(Base::V, _AP_W - _AP_N, _AP_W - 2, mask.V); + } + } else { + // unsigned AP_WRAP + ap_int_base<_AP_W, false> mask(-1); + Base::V = + _AP_ROOT_op_set_range(Base::V, _AP_W - _AP_N, _AP_W - 1, mask.V); + } + } else if (_AP_O == AP_SAT_ZERO) { + Base::V = 0; + } else if (_AP_O == AP_WRAP_SM && _AP_S) { + bool Ro = _AP_ROOT_op_get_bit(Base::V, _AP_W - 1); + if (_AP_N == 0) { + if (lD != Ro) { + Base::V = ~Base::V; + Base::V = _AP_ROOT_op_set_bit(Base::V, _AP_W - 1, lD); + } + } else { + if (_AP_N == 1 && sign != Ro) { + Base::V = ~Base::V; + } else if (_AP_N > 1) { + bool lNo = _AP_ROOT_op_get_bit(Base::V, _AP_W - _AP_N); + if (lNo == sign) Base::V = ~Base::V; + ap_int_base<_AP_W, false> mask(-1); + if (sign) mask.V = 0; + Base::V = + _AP_ROOT_op_set_range(Base::V, _AP_W - _AP_N, _AP_W - 2, mask.V); + } + Base::V = _AP_ROOT_op_set_bit(Base::V, _AP_W - 1, sign); + } + } else { + if (_AP_S) { + if (overflow) { + Base::V = 1; + Base::V <<= _AP_W - 1; + Base::V = ~Base::V; + } else if (underflow) { + Base::V = 1; + Base::V <<= _AP_W - 1; + if (_AP_O == AP_SAT_SYM) Base::V |= 1; + } + } else { + if (overflow) + Base::V = ~(ap_int_base<_AP_W, false>(0).V); + else if (underflow) + Base::V = 0; + } + } + } + + INLINE bool quantization_adjust(bool qb, bool r, bool s) { + bool carry = (bool)_AP_ROOT_op_get_bit(Base::V, _AP_W - 1); + if (_AP_Q == AP_TRN) return false; + if (_AP_Q == AP_RND_ZERO) + qb &= s || r; + else if (_AP_Q == AP_RND_MIN_INF) + qb &= r; + else if (_AP_Q == AP_RND_INF) + qb &= !s || r; + else if (_AP_Q == AP_RND_CONV) + qb &= _AP_ROOT_op_get_bit(Base::V, 0) || r; + else if (_AP_Q == AP_TRN_ZERO) + qb = s && (qb || r); + Base::V += qb; + return carry && (!(bool)_AP_ROOT_op_get_bit(Base::V, _AP_W - 1)); + } + // @} + + public: + /// @name constructors. + // @{ + /// default ctor. + INLINE ap_fixed_base() {} + + /// copy ctor. + template + INLINE ap_fixed_base( + const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) { + operator=(op); + report(); + } + + template + INLINE ap_fixed_base( + const volatile ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) { + operator=(op); + report(); + } + + template + INLINE ap_fixed_base(const ap_int_base<_AP_W2, _AP_S2>& op) { + ap_fixed_base<_AP_W2, _AP_W2, _AP_S2> tmp; + tmp.V = op.V; + operator=(tmp); + report(); + } + + template + INLINE ap_fixed_base(const volatile ap_int_base<_AP_W2, _AP_S2>& op) { + ap_fixed_base<_AP_W2, _AP_W2, _AP_S2> tmp; + tmp.V = op.V; + operator=(tmp); + report(); + } + +#ifndef __SYNTHESIS__ +#ifndef NON_C99STRING + INLINE ap_fixed_base(const char* s, signed char rd = 0) { + unsigned char radix = rd; + std::string str = ap_private_ops::parseString(s, radix); // will guess rd, default 10 + _AP_ERROR(radix == 0, "ap_fixed_base(const char* \"%s\", %d), str=%s, radix = %d", + s, rd, str.c_str(), radix); // TODO remove this check + fromString(str, radix); + } +#else + INLINE ap_fixed_base(const char* s, signed char rd = 10) { + ap_int_base<_AP_W, _AP_S> t(s, rd); + Base::V = t.V; + } +#endif // ifndef NON_C99STRING +#else // ifndef __SYNTHESIS__ + // XXX _ssdm_string2bits only takes const string and const radix. + // It seems XFORM will do compile time processing of the string. + INLINE ap_fixed_base(const char* s) { + typeof(Base::V) t; + _ssdm_string2bits((void*)(&t), (const char*)(s), 10, _AP_I, _AP_S, _AP_Q, + _AP_O, _AP_N, _AP_C99); + Base::V = t; + } + INLINE ap_fixed_base(const char* s, signed char rd) { + typeof(Base::V) t; + _ssdm_string2bits((void*)(&t), (const char*)(s), rd, _AP_I, _AP_S, _AP_Q, + _AP_O, _AP_N, _AP_C99); + Base::V = t; + } +#endif // ifndef __SYNTHESIS__ else + + template + INLINE ap_fixed_base(const ap_bit_ref<_AP_W2, _AP_S2>& op) { + *this = ((bool)op); + report(); + } + + template + INLINE ap_fixed_base(const ap_range_ref<_AP_W2, _AP_S2>& op) { + *this = (ap_int_base<_AP_W2, false>(op)); + report(); + } + + template + INLINE ap_fixed_base( + const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& op) { + *this = (ap_int_base<_AP_W2 + _AP_W3, false>(op)); + report(); + } + + template + INLINE ap_fixed_base( + const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) { + *this = (bool(op)); + report(); + } + + template + INLINE ap_fixed_base( + const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) { + *this = (ap_int_base<_AP_W2, false>(op)); + report(); + } + + // ctors from c types. + // make a temp ap_fixed_base first, and use ap_fixed_base.operator= +#define CTOR_FROM_INT(C_TYPE, _AP_W2, _AP_S2) \ + INLINE ap_fixed_base(const C_TYPE x) { \ + ap_fixed_base<(_AP_W2), (_AP_W2), (_AP_S2)> tmp; \ + tmp.V = x; \ + *this = tmp; \ + } + + CTOR_FROM_INT(bool, 1, false) + CTOR_FROM_INT(char, 8, CHAR_IS_SIGNED) + CTOR_FROM_INT(signed char, 8, true) + CTOR_FROM_INT(unsigned char, 8, false) + CTOR_FROM_INT(short, _AP_SIZE_short, true) + CTOR_FROM_INT(unsigned short, _AP_SIZE_short, false) + CTOR_FROM_INT(int, _AP_SIZE_int, true) + CTOR_FROM_INT(unsigned int, _AP_SIZE_int, false) + CTOR_FROM_INT(long, _AP_SIZE_long, true) + CTOR_FROM_INT(unsigned long, _AP_SIZE_long, false) + CTOR_FROM_INT(ap_slong, _AP_SIZE_ap_slong, true) + CTOR_FROM_INT(ap_ulong, _AP_SIZE_ap_slong, false) +#undef CTOR_FROM_INT +/* + * TODO: + *Theere used to be several funtions which were AP_WEAK. + *Now they're all INLINE expect ap_fixed_base(double d) + *Maybe we can use '#pragma HLS inline' instead of INLINE. + */ + AP_WEAK ap_fixed_base(double d) { + ap_int_base<64, false> ireg; + ireg.V = doubleToRawBits(d); + bool isneg = _AP_ROOT_op_get_bit(ireg.V, 63); + + ap_int_base exp; + ap_int_base exp_tmp; + exp_tmp.V = + _AP_ROOT_op_get_range(ireg.V, DOUBLE_MAN, DOUBLE_MAN + DOUBLE_EXP - 1); + exp = exp_tmp - DOUBLE_BIAS; + ap_int_base man; + man.V = _AP_ROOT_op_get_range(ireg.V, 0, DOUBLE_MAN - 1); + // do not support NaN + _AP_WARNING(exp == APFX_IEEE_DOUBLE_E_MAX + 1 && man.V != 0, + "assign NaN to fixed point value"); + man.V = _AP_ROOT_op_set_bit(man.V, DOUBLE_MAN, 1); + if (isneg) man = -man; + if ((ireg.V & 0x7fffffffffffffffLL) == 0) { + Base::V = 0; + } else { + int _AP_W2 = DOUBLE_MAN + 2, _AP_I2 = exp.V + 2, _AP_F = _AP_W - _AP_I, + F2 = _AP_W2 - _AP_I2; + bool _AP_S2 = true, + QUAN_INC = F2 > _AP_F && + !(_AP_Q == AP_TRN || (_AP_Q == AP_TRN_ZERO && !_AP_S2)); + bool carry = false; + // handle quantization + unsigned sh_amt = (F2 > _AP_F) ? F2 - _AP_F : _AP_F - F2; + if (F2 == _AP_F) + Base::V = man.V; + else if (F2 > _AP_F) { + if (sh_amt < DOUBLE_MAN + 2) + Base::V = man.V >> sh_amt; + else { + Base::V = isneg ? -1 : 0; + } + if ((_AP_Q != AP_TRN) && !((_AP_Q == AP_TRN_ZERO) && !_AP_S2)) { + bool qb = (F2 - _AP_F > _AP_W2) ? isneg : (bool)_AP_ROOT_op_get_bit( + man.V, F2 - _AP_F - 1); + bool r = + (F2 > _AP_F + 1) + ? _AP_ROOT_op_get_range(man.V, 0, (F2 - _AP_F - 2 < _AP_W2) + ? (F2 - _AP_F - 2) + : (_AP_W2 - 1)) != 0 + : false; + carry = quantization_adjust(qb, r, isneg); + } + } else { // no quantization + Base::V = man.V; + if (sh_amt < _AP_W) + Base::V = Base::V << sh_amt; + else + Base::V = 0; + } + // handle overflow/underflow + if ((_AP_O != AP_WRAP || _AP_N != 0) && + ((!_AP_S && _AP_S2) || + _AP_I - _AP_S < + _AP_I2 - _AP_S2 + + (QUAN_INC || + (_AP_S2 && (_AP_O == AP_SAT_SYM))))) { // saturation + bool deleted_zeros = _AP_S2 ? true : !carry, deleted_ones = true; + bool neg_src = isneg; + bool lD = false; + int pos1 = F2 - _AP_F + _AP_W; + int pos2 = F2 - _AP_F + _AP_W + 1; + bool newsignbit = _AP_ROOT_op_get_bit(Base::V, _AP_W - 1); + if (pos1 < _AP_W2 && pos1 >= 0) + // lD = _AP_ROOT_op_get_bit(man.V, pos1); + lD = (man.V >> pos1) & 1; + if (pos1 < _AP_W2) { + bool Range1_all_ones = true; + bool Range1_all_zeros = true; + bool Range2_all_ones = true; + ap_int_base Range2; + ap_int_base all_ones(-1); + + if (pos2 >= 0 && pos2 < _AP_W2) { + // Range2.V = _AP_ROOT_op_get_range(man.V, + // pos2, _AP_W2 - 1); + Range2.V = man.V; + Range2.V >>= pos2; + Range2_all_ones = Range2 == (all_ones >> pos2); + } else if (pos2 < 0) + Range2_all_ones = false; + if (pos1 >= 0 && pos2 < _AP_W2) { + Range1_all_ones = Range2_all_ones && lD; + Range1_all_zeros = !Range2.V && !lD; + } else if (pos2 == _AP_W2) { + Range1_all_ones = lD; + Range1_all_zeros = !lD; + } else if (pos1 < 0) { + Range1_all_zeros = !man.V; + Range1_all_ones = false; + } + + deleted_zeros = + deleted_zeros && (carry ? Range1_all_ones : Range1_all_zeros); + deleted_ones = + carry ? Range2_all_ones && (pos1 < 0 || !lD) : Range1_all_ones; + neg_src = isneg && !(carry && Range1_all_ones); + } else + neg_src = isneg && newsignbit; + bool neg_trg = _AP_S && newsignbit; + bool overflow = (neg_trg || !deleted_zeros) && !isneg; + bool underflow = (!neg_trg || !deleted_ones) && neg_src; + if ((_AP_O == AP_SAT_SYM) && _AP_S2 && _AP_S) + underflow |= + neg_src && + (_AP_W > 1 ? _AP_ROOT_op_get_range(Base::V, 0, _AP_W - 2) == 0 + : true); + overflow_adjust(underflow, overflow, lD, neg_src); + } + } + report(); + } + + // TODO more optimized implementation. + INLINE ap_fixed_base(float d) { *this = ap_fixed_base(double(d)); } + +#if _AP_ENABLE_HALF_ == 1 + // TODO more optimized implementation. + INLINE ap_fixed_base(half d) { *this = ap_fixed_base(double(d)); } +#endif + // @} + + /// @name assign operator + /// assign, using another ap_fixed_base of same template parameters. + /* + INLINE ap_fixed_base& operator=( + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) { + Base::V = op.V; + return *this; + } + */ + + template + INLINE ap_fixed_base& operator=( + const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) { + + const int _AP_F = _AP_W - _AP_I; + const int F2 = _AP_W2 - _AP_I2; + const int QUAN_INC = + F2 > _AP_F && !(_AP_Q == AP_TRN || (_AP_Q == AP_TRN_ZERO && !_AP_S2)); + + if (!op) Base::V = 0; + bool carry = false; + bool signbit = _AP_ROOT_op_get_bit(op.V, _AP_W2 - 1); + bool isneg = signbit && _AP_S2; + if (F2 == _AP_F) + Base::V = op.V; + else if (F2 > _AP_F) { + unsigned int sh_amt = F2 - _AP_F; + // moves bits right, handle quantization. + if (sh_amt < _AP_W2) { + Base::V = op.V >> sh_amt; + } else { + Base::V = isneg ? -1 : 0; + } + if (_AP_Q != AP_TRN && !(_AP_Q == AP_TRN_ZERO && !_AP_S2)) { + bool qbit = _AP_ROOT_op_get_bit(op.V, F2 - _AP_F - 1); + // bit after LSB. + bool qb = (F2 - _AP_F > _AP_W2) ? _AP_S2 && signbit : qbit; + enum { hi = ((F2 - _AP_F - 2) < _AP_W2) ? (F2 - _AP_F - 2) : (_AP_W2 - 1) }; + // bits after qb. + bool r = (F2 > _AP_F + 1) ? (_AP_ROOT_op_get_range(op.V, 0, hi) != 0) : false; + carry = quantization_adjust(qb, r, isneg); + } + } else { + unsigned sh_amt = _AP_F - F2; + // moves bits left, no quantization + if (sh_amt < _AP_W) { + if (_AP_W > _AP_W2) { + // extend and then shift, avoid losing bits. + Base::V = op.V; + Base::V <<= sh_amt; + } else { + // shift and truncate. + Base::V = op.V << sh_amt; + } + } else { + Base::V = 0; + } + } + // handle overflow/underflow + if ((_AP_O != AP_WRAP || _AP_N != 0) && + ((!_AP_S && _AP_S2) || + _AP_I - _AP_S < + _AP_I2 - _AP_S2 + + (QUAN_INC || (_AP_S2 && _AP_O == AP_SAT_SYM)))) { // saturation + bool deleted_zeros = _AP_S2 ? true : !carry; + bool deleted_ones = true; + bool neg_src = isneg; + bool newsignbit = _AP_ROOT_op_get_bit(Base::V, _AP_W - 1); + enum { pos1 = F2 - _AP_F + _AP_W, pos2 = F2 - _AP_F + _AP_W + 1 }; + bool lD = (pos1 < _AP_W2 && pos1 >= 0) ? _AP_ROOT_op_get_bit(op.V, pos1) + : false; + if (pos1 < _AP_W2) { + bool Range1_all_ones = true; + bool Range1_all_zeros = true; + bool Range2_all_ones = true; + ap_int_base<_AP_W2, false> all_ones(-1); + + if (pos2 < _AP_W2 && pos2 >= 0) { + ap_int_base<_AP_W2, false> Range2; + Range2.V = _AP_ROOT_op_get_range(op.V, pos2, _AP_W2 - 1); + Range2_all_ones = Range2 == (all_ones >> pos2); + } else if (pos2 < 0) { + Range2_all_ones = false; + } + + if (pos1 >= 0 && pos2 < _AP_W2) { + ap_int_base<_AP_W2, false> Range1; + Range1.V = _AP_ROOT_op_get_range(op.V, pos1, _AP_W2 - 1); + Range1_all_ones = Range1 == (all_ones >> pos1); + Range1_all_zeros = !Range1.V; + } else if (pos2 == _AP_W2) { + Range1_all_ones = lD; + Range1_all_zeros = !lD; + } else if (pos1 < 0) { + Range1_all_zeros = !op.V; + Range1_all_ones = false; + } + + deleted_zeros = + deleted_zeros && (carry ? Range1_all_ones : Range1_all_zeros); + deleted_ones = + carry ? Range2_all_ones && (pos1 < 0 || !lD) : Range1_all_ones; + neg_src = isneg && !(carry && Range1_all_ones); + } else + neg_src = isneg && newsignbit; + bool neg_trg = _AP_S && newsignbit; + bool overflow = (neg_trg || !deleted_zeros) && !isneg; + bool underflow = (!neg_trg || !deleted_ones) && neg_src; + if ((_AP_O == AP_SAT_SYM) && _AP_S2 && _AP_S) + underflow |= + neg_src && + (_AP_W > 1 ? _AP_ROOT_op_get_range(Base::V, 0, _AP_W - 2) == 0 + : true); + + overflow_adjust(underflow, overflow, lD, neg_src); + } + return *this; + } // operator= + + template + INLINE ap_fixed_base& operator=( + const volatile ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) { + operator=(const_cast&>(op)); + return *this; + } + + /// Set this ap_fixed_base with ULL. + INLINE ap_fixed_base& setBits(ap_ulong bv) { + // TODO when ull is not be long enough... + Base::V = bv; + return *this; + } + + /// Return a ap_fixed_base object whose this->V is assigned by bv. + static INLINE ap_fixed_base bitsToFixed(ap_ulong bv) { + // TODO fix when ull is not be long enough... + ap_fixed_base t; +#ifdef __SYNTHESIS__ + t.V = bv; +#else + t.V.set_bits(bv); +#endif + return t; + } + + // Explicit conversion functions to ap_int_base. + /** Captures all integer bits, in truncate mode. + * @param[in] Cnative follow conversion from double to int. + */ + INLINE ap_int_base to_ap_int_base( + bool Cnative = true) const { + ap_int_base ret; + if (_AP_I == 0) { + ret.V = 0; + } else if (_AP_I > 0 && _AP_I <= _AP_W) { + ret.V = _AP_ROOT_op_get_range(Base::V, _AP_W - _AP_I, _AP_W - 1); + } else if (_AP_I > _AP_W) { + ret.V = _AP_ROOT_op_get_range(Base::V, 0, _AP_W - 1); + ret.V <<= (_AP_I - _AP_W); + } + /* Consider the following case + * float f = -7.5f; + * ap_fixed<8,4> t = f; // -8 0 0 0 . 0.5 + * int i = t.to_int(); + * the result should be -7 instead of -8. + * Therefore, after truncation, the value should be increated by 1. + * For (-1, 0), carry to MSB will happen, but result 0 is still correct. + */ + if (Cnative && _AP_I < _AP_W) { + // Follow C native data type, conversion from double to int + if (_AP_S && _AP_ROOT_op_get_bit(Base::V, _AP_W - 1) && (_AP_I < _AP_W) && + (_AP_ROOT_op_get_range( + Base::V, 0, _AP_I < 0 ? _AP_W - 1 : _AP_W - _AP_I - 1) != 0)) + ++ret; + } else { + // Follow OSCI library, conversion from sc_fixed to sc_int + } + return ret; + }; + + public: + template + INLINE operator ap_int_base<_AP_W2, _AP_S2>() const { + return ap_int_base<_AP_W2, _AP_S2>(to_ap_int_base()); + } + + // Explicit conversion function to C built-in integral type. + INLINE char to_char() const { return to_ap_int_base().to_char(); } + + INLINE int to_int() const { return to_ap_int_base().to_int(); } + + INLINE unsigned to_uint() const { return to_ap_int_base().to_uint(); } + + INLINE ap_slong to_int64() const { return to_ap_int_base().to_int64(); } + + INLINE ap_ulong to_uint64() const { return to_ap_int_base().to_uint64(); } + + /// covert function to double. + /** only round-half-to-even mode supported, does not obey FE env. */ + INLINE double to_double() const { +#if defined(AP_FIXED_ENABLE_CPP_FENV) + _AP_WARNING(std::fegetround() != FE_TONEAREST, + "Only FE_TONEAREST is supported"); +#endif + enum { BITS = DOUBLE_MAN + DOUBLE_EXP + 1 }; + if (!Base::V) return 0.0f; + bool s = _AP_S && _AP_ROOT_op_get_bit(Base::V, _AP_W - 1); ///< sign. + ap_int_base<_AP_W, false> tmp; + if (s) + tmp.V = -Base::V; // may truncate one bit extra from neg in sim. + else + tmp.V = Base::V; + int l = tmp.countLeadingZeros(); ///< number of leading zeros. + int e = _AP_I - l - 1 + DOUBLE_BIAS; ///< exponent + int lsb_index = _AP_W - l - 1 - DOUBLE_MAN; + // more than 0.5? + bool a = (lsb_index >=2) ? + (_AP_ROOT_op_get_range(tmp.V, 0, lsb_index - 2) != 0) : 0; + // round to even + a |= (lsb_index >=0) ? _AP_ROOT_op_get_bit(tmp.V, lsb_index) : 0; + // ull is at least 64-bit + ap_ulong m; + // may actually left shift, ensure buffer is wide enough. + if (_AP_W > BITS) { + m = (lsb_index >= 1) ? (ap_ulong)(tmp.V >> (lsb_index - 1)) + : (ap_ulong)(tmp.V << (1 - lsb_index)); + } else { + m = (ap_ulong)tmp.V; + m = (lsb_index >= 1) ? (m >> (lsb_index - 1)) + : (m << (1 - lsb_index)); + } + m += a; + m >>= 1; + //std::cout << '\n' << std::hex << m << '\n'; // TODO delete this + // carry to MSB, increase exponent + if (_AP_ctype_op_get_bit(m, DOUBLE_MAN + 1)) { + e += 1; + } + // set sign and exponent + m = _AP_ctype_op_set_bit(m, BITS - 1, s); + //std::cout << m << '\n'; // TODO delete this + m = _AP_ctype_op_set_range(m, DOUBLE_MAN, DOUBLE_MAN + DOUBLE_EXP - 1, e); + //std::cout << std::hex << m << std::dec << std::endl; // TODO delete this + // cast to fp + return rawBitsToDouble(m); + } + + /// convert function to float. + /** only round-half-to-even mode supported, does not obey FE env. */ + INLINE float to_float() const { +#if defined(AP_FIXED_ENABLE_CPP_FENV) + _AP_WARNING(std::fegetround() != FE_TONEAREST, + "Only FE_TONEAREST is supported"); +#endif + enum { BITS = FLOAT_MAN + FLOAT_EXP + 1 }; + if (!Base::V) return 0.0f; + bool s = _AP_S && _AP_ROOT_op_get_bit(Base::V, _AP_W - 1); ///< sign. + ap_int_base<_AP_W, false> tmp; + if (s) + tmp.V = -Base::V; // may truncate one bit extra from neg in sim. + else + tmp.V = Base::V; + int l = tmp.countLeadingZeros(); ///< number of leading zeros. + int e = _AP_I - l - 1 + FLOAT_BIAS; ///< exponent + int lsb_index = _AP_W - l - 1 - FLOAT_MAN; + // more than 0.5? + bool a = (lsb_index >=2) ? + (_AP_ROOT_op_get_range(tmp.V, 0, lsb_index - 2) != 0) : 0; + // round to even + a |= (lsb_index >=0) ? _AP_ROOT_op_get_bit(tmp.V, lsb_index) : 0; + // ul is at least 32-bit + unsigned long m; + // may actually left shift, ensure buffer is wide enough. + if (_AP_W > BITS) { + m = (lsb_index >= 1) ? (unsigned long)(tmp.V >> (lsb_index - 1)) + : (unsigned long)(tmp.V << (1 - lsb_index)); + } else { + m = (unsigned long)tmp.V; + m = (lsb_index >= 1) ? (m >> (lsb_index - 1)) + : (m << (1 - lsb_index)); + } + m += a; + m >>= 1; + // carry to MSB, increase exponent + if (_AP_ctype_op_get_bit(m, FLOAT_MAN + 1)) { + e += 1; + } + // set sign and exponent + m = _AP_ctype_op_set_bit(m, BITS - 1, s); + m = _AP_ctype_op_set_range(m, FLOAT_MAN, FLOAT_MAN + FLOAT_EXP - 1, e); + // cast to fp + return rawBitsToFloat(m); + } + +#if _AP_ENABLE_HALF_ == 1 + /// convert function to half. + /** only round-half-to-even mode supported, does not obey FE env. */ + INLINE half to_half() const { +#if defined(AP_FIXED_ENABLE_CPP_FENV) + _AP_WARNING(std::fegetround() != FE_TONEAREST, + "Only FE_TONEAREST is supported"); +#endif + enum { BITS = HALF_MAN + HALF_EXP + 1 }; + if (!Base::V) return 0.0f; + bool s = _AP_S && _AP_ROOT_op_get_bit(Base::V, _AP_W - 1); ///< sign. + ap_int_base<_AP_W, false> tmp; + if (s) + tmp.V = -Base::V; // may truncate one bit extra from neg in sim. + else + tmp.V = Base::V; + int l = tmp.countLeadingZeros(); ///< number of leading zeros. + int e = _AP_I - l - 1 + HALF_BIAS; ///< exponent + int lsb_index = _AP_W - l - 1 - HALF_MAN; + // more than 0.5? + bool a = (lsb_index >=2) ? + (_AP_ROOT_op_get_range(tmp.V, 0, lsb_index - 2) != 0) : 0; + // round to even + a |= (lsb_index >=0) ? _AP_ROOT_op_get_bit(tmp.V, lsb_index) : 0; + // short is at least 16-bit + unsigned short m; + // may actually left shift, ensure buffer is wide enough. + if (_AP_W > BITS) { + m = (lsb_index >= 1) ? (unsigned short)(tmp.V >> (lsb_index - 1)) + : (unsigned short)(tmp.V << (1 - lsb_index)); + } else { + m = (unsigned short)tmp.V; + m = (lsb_index >= 1) ? (m >> (lsb_index - 1)) + : (m << (1 - lsb_index)); + } + m += a; + m >>= 1; + // carry to MSB, increase exponent + if (_AP_ctype_op_get_bit(m, HALF_MAN + 1)) { + e += 1; + } + // set sign and exponent + m = _AP_ctype_op_set_bit(m, BITS - 1, s); + m = _AP_ctype_op_set_range(m, HALF_MAN, HALF_MAN + HALF_EXP - 1, e); + // cast to fp + return rawBitsToHalf(m); + } +#endif + + // FIXME inherited from old code, this may loose precision! + INLINE operator long double() const { return (long double)to_double(); } + + INLINE operator double() const { return to_double(); } + + INLINE operator float() const { return to_float(); } + +#if _AP_ENABLE_HALF_ == 1 + INLINE operator half() const { return to_half(); } +#endif + + INLINE operator bool() const { return (bool)Base::V != 0; } + + INLINE operator char() const { return (char)to_int(); } + + INLINE operator signed char() const { return (signed char)to_int(); } + + INLINE operator unsigned char() const { return (unsigned char)to_uint(); } + + INLINE operator short() const { return (short)to_int(); } + + INLINE operator unsigned short() const { return (unsigned short)to_uint(); } + + INLINE operator int() const { return to_int(); } + + INLINE operator unsigned int() const { return to_uint(); } + +// FIXME don't assume data width... +#ifdef __x86_64__ + INLINE operator long() const { return (long)to_int64(); } + + INLINE operator unsigned long() const { return (unsigned long)to_uint64(); } +#else + INLINE operator long() const { return (long)to_int(); } + + INLINE operator unsigned long() const { return (unsigned long)to_uint(); } +#endif // ifdef __x86_64__ else + + INLINE operator ap_ulong() const { return to_uint64(); } + + INLINE operator ap_slong() const { return to_int64(); } + + INLINE int length() const { return _AP_W; }; + + // bits_to_int64 deleted. +#ifndef __SYNTHESIS__ + // Used in autowrap, when _AP_W < 64. + INLINE ap_ulong bits_to_uint64() const { + return (Base::V).to_uint64(); + } +#endif + + // Count the number of zeros from the most significant bit + // to the first one bit. Note this is only for ap_fixed_base whose + // _AP_W <= 64, otherwise will incur assertion. + INLINE int countLeadingZeros() { +#ifdef __SYNTHESIS__ + // TODO: used llvm.ctlz intrinsic ? + if (_AP_W <= 32) { + ap_int_base<32, false> t(-1ULL); + t.range(_AP_W - 1, 0) = this->range(0, _AP_W - 1); + return __builtin_ctz(t.V); + } else if (_AP_W <= 64) { + ap_int_base<64, false> t(-1ULL); + t.range(_AP_W - 1, 0) = this->range(0, _AP_W - 1); + return __builtin_ctzll(t.V); + } else { + enum {__N = (_AP_W + 63) / 64}; + int NZeros = 0; + int i = 0; + bool hitNonZero = false; + for (i = 0; i < __N - 1; ++i) { + ap_int_base<64, false> t; + t.range(0, 63) = this->range(_AP_W - i * 64 - 64, _AP_W - i * 64 - 1); + NZeros += hitNonZero ? 0 : __builtin_clzll(t.V); + hitNonZero |= (t != 0); + } + if (!hitNonZero) { + ap_int_base<64, false> t(-1ULL); + t.range(63 - (_AP_W - 1) % 64, 63) = this->range(0, (_AP_W - 1) % 64); + NZeros += __builtin_clzll(t.V); + } + return NZeros; + } +#else + return Base::V.countLeadingZeros(); +#endif + } + + // Arithmetic : Binary + // ------------------------------------------------------------------------- + template + INLINE typename RType<_AP_W2, _AP_I2, _AP_S2>::mult operator*( + const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) + const { + typename RType<_AP_W2, _AP_I2, _AP_S2>::mult_base r, t; + r.V = Base::V; + t.V = op2.V; + r.V *= op2.V; + return r; + } + + // multiply function deleted. + + template + INLINE typename RType<_AP_W2, _AP_I2, _AP_S2>::div operator/( + const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) + const { + typename RType<_AP_W2, _AP_I2, _AP_S2>::div_base r; +#ifndef __SYNTHESIS__ + enum {F2 = _AP_W2-_AP_I2, + _W1=AP_MAX(_AP_W + AP_MAX(F2, 0) + ((_AP_S2 && !_AP_S) ? 1 : 0), _AP_W2 + ((_AP_S && !_AP_S2) ? 1 : 0))}; + ap_int_base<_W1,_AP_S||_AP_S2> dividend,divisior; + ap_int_base<_W1,_AP_S> tmp1; + ap_int_base<_W1,_AP_S2> tmp2; + tmp1.V = Base::V; + tmp1.V <<= AP_MAX(F2,0); + tmp2.V = op2.V; + dividend = tmp1; + divisior = tmp2; + r.V = ((_AP_S||_AP_S2) ? dividend.V.sdiv(divisior.V): dividend.V.udiv(divisior.V)); +#else + #ifndef __SC_COMPATIBLE__ + ap_fixed_base<_AP_W + AP_MAX(_AP_W2 - _AP_I2, 0),_AP_I, _AP_S> t(*this); + #else + ap_fixed_base<_AP_W + AP_MAX(_AP_W2 - _AP_I2, 0) + AP_MAX(_AP_I2, 0),_AP_I, _AP_S> t(*this); + #endif + r.V = t.V / op2.V; +#endif +/* + enum { + F2 = _AP_W2 - _AP_I2, + shl = AP_MAX(F2, 0) + AP_MAX(_AP_I2, 0), +#ifndef __SC_COMPATIBLE__ + shr = AP_MAX(_AP_I2, 0), +#else + shr = 0, +#endif + W3 = _AP_S2 + _AP_W + shl, + S3 = _AP_S || _AP_S2, + }; + ap_int_base dividend, t; + dividend.V = Base::V; + // multiply both by (1 << F2), and than do integer division. + dividend.V <<= (int) shl; +#ifdef __SYNTHESIS__ + // .V's have right signedness, and will have right extending. + t.V = dividend.V / op2.V; +#else + // XXX op2 may be wider than dividend, and sdiv and udiv takes the same with + // as left hand operand, so data might be truncated by mistake if not + // handled here. + t.V = S3 ? dividend.V.sdiv(op2.V) : dividend.V.udiv(op2.V); +#endif + r.V = t.V >> (int) shr; +*/ + return r; + } + +#define OP_BIN_AF(Sym, Rty) \ + template \ + INLINE typename RType<_AP_W2, _AP_I2, _AP_S2>::Rty operator Sym( \ + const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& \ + op2) const { \ + typename RType<_AP_W2, _AP_I2, _AP_S2>::Rty##_base ret, lhs(*this), \ + rhs(op2); \ + ret.V = lhs.V Sym rhs.V; \ + return ret; \ + } + + OP_BIN_AF(+, plus) + OP_BIN_AF(-, minus) + OP_BIN_AF(&, logic) + OP_BIN_AF(|, logic) + OP_BIN_AF(^, logic) + +// Arithmetic : assign +// ------------------------------------------------------------------------- +#define OP_ASSIGN_AF(Sym) \ + template \ + INLINE ap_fixed_base& operator Sym##=( \ + const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& \ + op2) { \ + *this = operator Sym(op2); \ + return *this; \ + } + + OP_ASSIGN_AF(*) + OP_ASSIGN_AF(/) + OP_ASSIGN_AF(+) + OP_ASSIGN_AF(-) + OP_ASSIGN_AF(&) + OP_ASSIGN_AF(|) + OP_ASSIGN_AF(^) + + // Prefix and postfix increment and decrement. + // ------------------------------------------------------------------------- + + /// Prefix increment + INLINE ap_fixed_base& operator++() { + operator+=(ap_fixed_base<_AP_W - _AP_I + 1, 1, false>(1)); + return *this; + } + + /// Prefix decrement. + INLINE ap_fixed_base& operator--() { + operator-=(ap_fixed_base<_AP_W - _AP_I + 1, 1, false>(1)); + return *this; + } + + /// Postfix increment + INLINE const ap_fixed_base operator++(int) { + ap_fixed_base r(*this); + operator++(); + return r; + } + + /// Postfix decrement + INLINE const ap_fixed_base operator--(int) { + ap_fixed_base r(*this); + operator--(); + return r; + } + + // Unary arithmetic. + // ------------------------------------------------------------------------- + INLINE ap_fixed_base operator+() { return *this; } + + INLINE ap_fixed_base<_AP_W + 1, _AP_I + 1, true> operator-() const { + ap_fixed_base<_AP_W + 1, _AP_I + 1, true> r(*this); + r.V = -r.V; + return r; + } + + INLINE ap_fixed_base<_AP_W, _AP_I, true, _AP_Q, _AP_O, _AP_N> getNeg() { + ap_fixed_base<_AP_W, _AP_I, true, _AP_Q, _AP_O, _AP_N> r(*this); + r.V = -r.V; + return r; + } + + // Not (!) + // ------------------------------------------------------------------------- + INLINE bool operator!() const { return Base::V == 0; } + + // Bitwise complement + // ------------------------------------------------------------------------- + // XXX different from Mentor's ac_fixed. + INLINE ap_fixed_base<_AP_W, _AP_I, _AP_S> operator~() const { + ap_fixed_base<_AP_W, _AP_I, _AP_S> r; + r.V = ~Base::V; + return r; + } + + // Shift + // ------------------------------------------------------------------------- + // left shift is the same as moving point right, i.e. increate I. + template + INLINE ap_fixed_base<_AP_W, _AP_I + _AP_SHIFT, _AP_S> lshift() const { + ap_fixed_base<_AP_W, _AP_I + _AP_SHIFT, _AP_S> r; + r.V = Base::V; + return r; + } + + template + INLINE ap_fixed_base<_AP_W, _AP_I - _AP_SHIFT, _AP_S> rshift() const { + ap_fixed_base<_AP_W, _AP_I - _AP_SHIFT, _AP_S> r; + r.V = Base::V; + return r; + } + + // Because the return type is the type of the the first operand, shift assign + // operators do not carry out any quantization or overflow + // While systemc, shift assigns for sc_fixed/sc_ufixed will result in + // quantization or overflow (depending on the mode of the first operand) + INLINE ap_fixed_base operator<<(unsigned int sh) const { + ap_fixed_base r; + r.V = Base::V << sh; +// TODO check shift overflow? +#ifdef __SC_COMPATIBLE__ + if (sh == 0) return r; + if (_AP_O != AP_WRAP || _AP_N != 0) { + bool neg_src = _AP_S && _AP_ROOT_op_get_bit(Base::V, _AP_W - 1); + bool allones, allzeros; + ap_int_base<_AP_W, false> ones(-1); + if (sh <= _AP_W) { + ap_int_base<_AP_W, false> range1; + range1.V = _AP_ROOT_op_get_range( + const_cast(this)->Base::V, _AP_W - sh, _AP_W - 1); + allones = range1 == (ones >> (_AP_W - sh)); + allzeros = range1 == 0; + } else { + allones = false; + allzeros = Base::V == 0; + } + bool overflow = !allzeros && !neg_src; + bool underflow = !allones && neg_src; + if ((_AP_O == AP_SAT_SYM) && _AP_S) + underflow |= + neg_src && + (_AP_W > 1 ? _AP_ROOT_op_get_range(r.V, 0, _AP_W - 2) == 0 : true); + bool lD = false; + if (sh < _AP_W) lD = _AP_ROOT_op_get_bit(Base::V, _AP_W - sh - 1); + r.overflow_adjust(underflow, overflow, lD, neg_src); + } +#endif + return r; + } + + INLINE ap_fixed_base operator>>(unsigned int sh) const { + ap_fixed_base r; + r.V = Base::V >> sh; +// TODO check shift overflow? +#ifdef __SC_COMPATIBLE__ + if (sh == 0) return r; + if (_AP_Q != AP_TRN) { + bool qb = false; + if (sh <= _AP_W) qb = _AP_ROOT_op_get_bit(Base::V, sh - 1); + bool rb = false; + if (sh > 1 && sh <= _AP_W) + rb = _AP_ROOT_op_get_range(const_cast(this)->Base::V, 0, + sh - 2) != 0; + else if (sh > _AP_W) + rb = Base::V != 0; + r.quantization_adjust(qb, rb, + _AP_S && _AP_ROOT_op_get_bit(Base::V, _AP_W - 1)); + } +#endif + return r; + } + + // left and right shift for int + INLINE ap_fixed_base operator<<(int sh) const { + ap_fixed_base r; + bool isNeg = sh < 0; + unsigned int ush = isNeg ? -sh : sh; + if (isNeg) { + return operator>>(ush); + } else { + return operator<<(ush); + } + } + + INLINE ap_fixed_base operator>>(int sh) const { + bool isNeg = sh < 0; + unsigned int ush = isNeg ? -sh : sh; + if (isNeg) { + return operator<<(ush); + } else { + return operator>>(ush); + } + } + + // left and right shift for ap_int. + template + INLINE ap_fixed_base operator<<(const ap_int_base<_AP_W2, true>& op2) const { + // TODO the code seems not optimal. ap_fixed<8,8> << ap_int<2> needs only a + // small mux, but integer need a big one! + int sh = op2.to_int(); + return operator<<(sh); + } + + template + INLINE ap_fixed_base operator>>(const ap_int_base<_AP_W2, true>& op2) const { + int sh = op2.to_int(); + return operator>>(sh); + } + + // left and right shift for ap_uint. + template + INLINE ap_fixed_base operator<<(const ap_int_base<_AP_W2, false>& op2) const { + unsigned int sh = op2.to_uint(); + return operator<<(sh); + } + + template + INLINE ap_fixed_base operator>>(const ap_int_base<_AP_W2, false>& op2) const { + unsigned int sh = op2.to_uint(); + return operator>>(sh); + } + + // left and right shift for ap_fixed + template + INLINE ap_fixed_base operator<<( + const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& + op2) { + return operator<<(op2.to_ap_int_base()); + } + + template + INLINE ap_fixed_base operator>>( + const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& + op2) { + return operator>>(op2.to_ap_int_base()); + } + + // Shift assign. + // ------------------------------------------------------------------------- + + // left shift assign. + INLINE ap_fixed_base& operator<<=(const int sh) { + *this = operator<<(sh); + return *this; + } + + INLINE ap_fixed_base& operator<<=(const unsigned int sh) { + *this = operator<<(sh); + return *this; + } + + template + INLINE ap_fixed_base& operator<<=(const ap_int_base<_AP_W2, _AP_S2>& sh) { + *this = operator<<(sh.to_int()); + return *this; + } + + template + INLINE ap_fixed_base& operator<<=( + const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& + sh) { + *this = operator<<(sh.to_int()); + return *this; + } + + // right shift assign. + INLINE ap_fixed_base& operator>>=(const int sh) { + *this = operator>>(sh); + return *this; + } + + INLINE ap_fixed_base& operator>>=(const unsigned int sh) { + *this = operator>>(sh); + return *this; + } + + template + INLINE ap_fixed_base& operator>>=(const ap_int_base<_AP_W2, _AP_S2>& sh) { + *this = operator>>(sh.to_int()); + return *this; + } + + template + INLINE ap_fixed_base& operator>>=( + const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& + sh) { + *this = operator>>(sh.to_int()); + return *this; + } + +// Comparisons. +// ------------------------------------------------------------------------- +#define OP_CMP_AF(Sym) \ + template \ + INLINE bool operator Sym(const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, \ + _AP_O2, _AP_N2>& op2) const { \ + enum { _AP_F = _AP_W - _AP_I, F2 = _AP_W2 - _AP_I2 }; \ + if (_AP_F == F2) \ + return Base::V Sym op2.V; \ + else if (_AP_F > F2) \ + return Base::V Sym ap_fixed_base(op2).V; \ + else \ + return ap_fixed_base(*this).V Sym op2.V; \ + return false; \ + } + + OP_CMP_AF(>) + OP_CMP_AF(<) + OP_CMP_AF(>=) + OP_CMP_AF(<=) + OP_CMP_AF(==) + OP_CMP_AF(!=) +// FIXME: Move compare with double out of struct ap_fixed_base defination +// and combine it with compare operator(double, ap_fixed_base) +#define DOUBLE_CMP_AF(Sym) \ + INLINE bool operator Sym(double d) const { return to_double() Sym d; } + + DOUBLE_CMP_AF(>) + DOUBLE_CMP_AF(<) + DOUBLE_CMP_AF(>=) + DOUBLE_CMP_AF(<=) + DOUBLE_CMP_AF(==) + DOUBLE_CMP_AF(!=) + + // Bit and Slice Select + INLINE af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> operator[]( + unsigned index) { + _AP_WARNING(index >= _AP_W, "Attempting to read bit beyond MSB"); + return af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(this, index); + } + + template + INLINE af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> operator[]( + const ap_int_base<_AP_W2, _AP_S2>& index) { + _AP_WARNING(index < 0, "Attempting to read bit with negative index"); + _AP_WARNING(index >= _AP_W, "Attempting to read bit beyond MSB"); + return af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(this, + index.to_int()); + } + + INLINE bool operator[](unsigned index) const { + _AP_WARNING(index >= _AP_W, "Attempting to read bit beyond MSB"); + return _AP_ROOT_op_get_bit(const_cast(this)->V, index); + } + + INLINE af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> bit( + unsigned index) { + _AP_WARNING(index >= _AP_W, "Attempting to read bit beyond MSB"); + return af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(this, index); + } + + template + INLINE af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> bit( + const ap_int_base<_AP_W2, _AP_S2>& index) { + _AP_WARNING(index < 0, "Attempting to read bit with negative index"); + _AP_WARNING(index >= _AP_W, "Attempting to read bit beyond MSB"); + return af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(this, + index.to_int()); + } + + INLINE bool bit(unsigned index) const { + _AP_WARNING(index >= _AP_W, "Attempting to read bit beyond MSB"); + return _AP_ROOT_op_get_bit(const_cast(this)->V, index); + } + + template + INLINE af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> get_bit( + const ap_int_base<_AP_W2, true>& index) { + _AP_WARNING(index < _AP_I - _AP_W, + "Attempting to read bit with negative index"); + _AP_WARNING(index >= _AP_I, "Attempting to read bit beyond MSB"); + return af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>( + this, index.to_int() + _AP_W - _AP_I); + } + + INLINE bool get_bit(int index) const { + _AP_WARNING(index >= _AP_I, "Attempting to read bit beyond MSB"); + _AP_WARNING(index < _AP_I - _AP_W, "Attempting to read bit beyond MSB"); + return _AP_ROOT_op_get_bit(const_cast(this)->V, + index + _AP_W - _AP_I); + } +#if 0 + INLINE af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> get_bit( + int index) { + _AP_WARNING(index < _AP_I - _AP_W, + "Attempting to read bit with negative index"); + _AP_WARNING(index >= _AP_I, "Attempting to read bit beyond MSB"); + return af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>( + this, index + _AP_W - _AP_I); + } +#endif + + template + INLINE bool get_bit(const ap_int_base<_AP_W2, true>& index) const { + _AP_WARNING(index >= _AP_I, "Attempting to read bit beyond MSB"); + _AP_WARNING(index < _AP_I - _AP_W, "Attempting to read bit beyond MSB"); + return _AP_ROOT_op_get_bit(const_cast(this)->V, + index.to_int() + _AP_W - _AP_I); + } + + INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> range(int Hi, + int Lo) { + _AP_WARNING((Hi >= _AP_W) || (Lo >= _AP_W), "Out of bounds in range()"); + return af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(this, Hi, Lo); + } + + // This is a must to strip constness to produce reference type. + INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> range( + int Hi, int Lo) const { + _AP_WARNING((Hi >= _AP_W) || (Lo >= _AP_W), "Out of bounds in range()"); + return af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>( + const_cast(this), Hi, Lo); + } + + template + INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> range( + const ap_int_base<_AP_W2, _AP_S2>& HiIdx, + const ap_int_base<_AP_W3, _AP_S3>& LoIdx) { + int Hi = HiIdx.to_int(); + int Lo = LoIdx.to_int(); + return this->range(Hi, Lo); + } + + template + INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> range( + const ap_int_base<_AP_W2, _AP_S2>& HiIdx, + const ap_int_base<_AP_W3, _AP_S3>& LoIdx) const { + int Hi = HiIdx.to_int(); + int Lo = LoIdx.to_int(); + return this->range(Hi, Lo); + } + + INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> range() { + return this->range(_AP_W - 1, 0); + } + + INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> range() const { + return this->range(_AP_W - 1, 0); + } + + INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> operator()( + int Hi, int Lo) { + return this->range(Hi, Lo); + } + + INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> operator()( + int Hi, int Lo) const { + return this->range(Hi, Lo); + } + + template + INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> operator()( + const ap_int_base<_AP_W2, _AP_S2>& HiIdx, + const ap_int_base<_AP_W3, _AP_S3>& LoIdx) { + int Hi = HiIdx.to_int(); + int Lo = LoIdx.to_int(); + return this->range(Hi, Lo); + } + + template + INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> operator()( + const ap_int_base<_AP_W2, _AP_S2>& HiIdx, + const ap_int_base<_AP_W3, _AP_S3>& LoIdx) const { + int Hi = HiIdx.to_int(); + int Lo = LoIdx.to_int(); + return this->range(Hi, Lo); + } + + INLINE bool is_zero() const { return Base::V == 0; } + + INLINE bool is_neg() const { + if (_AP_S && _AP_ROOT_op_get_bit(Base::V, _AP_W - 1)) return true; + return false; + } + + INLINE int wl() const { return _AP_W; } + + INLINE int iwl() const { return _AP_I; } + + INLINE ap_q_mode q_mode() const { return _AP_Q; } + + INLINE ap_o_mode o_mode() const { return _AP_O; } + + INLINE int n_bits() const { return _AP_N; } + + // print a string representation of this number in the given radix. + // Radix support is 2, 8, 10, or 16. + // The result will include a prefix indicating the radix, except for decimal, + // where no prefix is needed. The default is to output a signed representation + // of signed numbers, or an unsigned representation of unsigned numbers. For + // non-decimal formats, this can be changed by the 'sign' argument. +#ifndef __SYNTHESIS__ + std::string to_string(unsigned char radix = 2, bool sign = _AP_S) const { + // XXX in autosim/autowrap.tcl "(${name}).to_string(2).c_str()" is used to + // initialize sc_lv, which seems incapable of handling format "-0b". + if (radix == 2) sign = false; + + std::string str; + str.clear(); + char step = 0; + bool isNeg = sign && (Base::V < 0); + + // Extend to take care of the -MAX case. + ap_fixed_base<_AP_W + 1, _AP_I + 1> tmp(*this); + if (isNeg) { + tmp = -tmp; + str += '-'; + } + std::string prefix; + switch (radix) { + case 2: + prefix = "0b"; + step = 1; + break; + case 8: + prefix = "0o"; + step = 3; + break; + case 16: + prefix = "0x"; + step = 4; + break; + default: + break; + } + + if (_AP_I > 0) { + // Note we drop the quantization and rounding flags here. The + // integer part is always in range, and the fractional part we + // want to drop. Also, the number is always positive, because + // of the absolute value above. + ap_int_base int_part; + // [1] [ I ] d [ W - I ] + // | | | + // | W-I 0 + // W + int_part.V = _AP_ROOT_op_get_range( + tmp.V, _AP_W - _AP_I, _AP_W); + str += int_part.to_string(radix, false); + } else { + str += prefix; + str += '0'; + } + + ap_fixed_base frac_part = tmp; + + if (radix == 10) { + if (frac_part != 0) { + str += "."; + while (frac_part != 0) { + char digit = (frac_part * radix).to_char(); + str += static_cast(digit + '0'); + frac_part *= radix; + } + } + } else { + if (frac_part != 0) { + str += "."; + for (signed i = _AP_W - _AP_I - 1; i >= 0; i -= step) { + char digit = frac_part.range(i, AP_MAX(0, i - step + 1)).to_char(); + // If we have a partial bit pattern at the end, then we need + // to put it in the high-order bits of 'digit'. + int offset = AP_MIN(0, i - step + 1); + digit <<= -offset; + str += digit < 10 ? static_cast(digit + '0') + : static_cast(digit - 10 + 'a'); + } + if (radix == 16) + str += "p0"; // C99 Hex constants are required to have an exponent. + } + } + return str; + } +#else + // XXX HLS will delete this in synthesis + INLINE char* to_string(unsigned char radix = 2, bool sign = _AP_S) const { + return 0; + } +#endif +}; // struct ap_fixed_base. + +template +INLINE void b_not( + ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret, + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) { + ret.V = ~op.V; +} + +template +INLINE void b_and( + ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret, + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op1, + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) { + ret.V = op1.V & op2.V; +} + +template +INLINE void b_or( + ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret, + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op1, + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) { + ret.V = op1.V | op2.V; +} + +template +INLINE void b_xor( + ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret, + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op1, + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) { + ret.V = op1.V ^ op2.V; +} + +template +INLINE void neg( + ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret, + const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) { + ap_fixed_base<_AP_W2 + !_AP_S2, _AP_I2 + !_AP_S2, true, _AP_Q2, _AP_O2, + _AP_N2> + t; + t.V = -op.V; + ret = t; +} + +template +INLINE void lshift( + ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret, + const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op, + int i) { + enum { + F2 = _AP_W2 - _AP_I2, + _AP_I3 = AP_MAX(_AP_I, _AP_I2), + _AP_W3 = _AP_I3 + F2, + }; + // wide buffer + ap_fixed_base<_AP_W3, _AP_I3, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> t; + t.V = op.V; + t.V <<= i; // FIXME overflow? + // handle quantization and overflow + ret = t; +} + +template +INLINE void rshift( + ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret, + const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op, + int i) { + enum { + F = _AP_W - _AP_I, + F2 = _AP_W2 - _AP_I2, + F3 = AP_MAX(F, F2), + _AP_W3 = _AP_I2 + F3, + sh = F - F2, + }; + // wide buffer + ap_fixed_base<_AP_W3, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> t; + t.V = op.V; + if (sh >= 0) + t.V <<= (int) sh; + t.V >>= i; + // handle quantization and overflow + ret = t; +} + +//// FIXME +//// These partial specialization ctors allow code like +//// char c = 'a'; +//// ap_fixed_base<8, 8, true> x(c); +//// but what bout ap_fixed_base<9, 9, true> y(c) ? +// + +#ifndef __SYNTHESIS__ +INLINE std::string scientificFormat(std::string& input) { + if (input.length() == 0) return input; + + size_t decPosition = input.find('.'); + if (decPosition == std::string::npos) decPosition = input.length(); + + size_t firstNonZeroPos = 0; + for (; input[firstNonZeroPos] > '9' || input[firstNonZeroPos] < '1'; + firstNonZeroPos++) + ; + + int exp; + if (firstNonZeroPos > decPosition) + exp = decPosition - firstNonZeroPos; + else + exp = decPosition - firstNonZeroPos - 1; + std::string expString = ""; + if (exp == 0) + ; + else if (exp < 0) { + expString += "e-"; + exp = -exp; + } else + expString += "e+"; + + if (exp < 10 && exp > 0) { + expString += '0'; + expString += (char)('0' + exp); + } else if (exp != 0) { + std::string tmp; + + std::ostringstream oss; + oss << exp; + + tmp = oss.str(); + expString += tmp; + } + + int lastNonZeroPos = (int)(input.length() - 1); + for (; lastNonZeroPos >= 0; --lastNonZeroPos) + if (input[lastNonZeroPos] <= '9' && input[lastNonZeroPos] > '0') break; + + std::string ans = ""; + ans += input[firstNonZeroPos]; + if (firstNonZeroPos != (size_t)lastNonZeroPos) { + ans += '.'; + for (int i = firstNonZeroPos + 1; i <= lastNonZeroPos; i++) + if (input[i] != '.') ans += input[i]; + } + + ans += expString; + return ans; +} + +INLINE std::string reduceToPrecision(std::string& input, int precision) { + bool isZero = true; + size_t inputLen = input.length(); + for (size_t i = 0; i < inputLen && isZero; i++) + if (input[i] != '.' && input[i] != '0') isZero = false; + if (isZero) return "0"; + + // Find the first valid number, skip '-' + int FirstNonZeroPos = 0; + int LastNonZeroPos = (int)inputLen - 1; + int truncBitPosition = 0; + size_t decPosition = input.find('.'); + for (; input[FirstNonZeroPos] < '1' || input[FirstNonZeroPos] > '9'; + FirstNonZeroPos++) + ; + + for (; input[LastNonZeroPos] < '1' || input[LastNonZeroPos] > '9'; + LastNonZeroPos--) + ; + + if (decPosition == std::string::npos) decPosition = inputLen; + // Count the valid number, to decide whether we need to truncate + if ((int)decPosition > LastNonZeroPos) { + if (LastNonZeroPos - FirstNonZeroPos + 1 <= precision) return input; + truncBitPosition = FirstNonZeroPos + precision; + } else if ((int)decPosition < FirstNonZeroPos) { // This is pure decimal + if (LastNonZeroPos - FirstNonZeroPos + 1 <= precision) { + if (FirstNonZeroPos - decPosition - 1 < 4) { + return input; + } else { + if (input[0] == '-') { + std::string tmp = input.substr(1, inputLen - 1); + return std::string("-") + scientificFormat(tmp); + } else + return scientificFormat(input); + } + } + truncBitPosition = FirstNonZeroPos + precision; + } else { + if (LastNonZeroPos - FirstNonZeroPos <= precision) return input; + truncBitPosition = FirstNonZeroPos + precision + 1; + } + + // duplicate the input string, we want to add "0" before the valid numbers + // This is easy for quantization, since we may change 9999 to 10000 + std::string ans = ""; + std::string dupInput = "0"; + if (input[0] == '-') { + ans += '-'; + dupInput += input.substr(1, inputLen - 1); + } else { + dupInput += input.substr(0, inputLen); + ++truncBitPosition; + } + + // Add 'carry' after truncation, if necessary + bool carry = dupInput[truncBitPosition] > '4'; + for (int i = truncBitPosition - 1; i >= 0 && carry; i--) { + if (dupInput[i] == '.') continue; + if (dupInput[i] == '9') + dupInput[i] = '0'; + else { + ++dupInput[i]; + carry = false; + } + } + + // bits outside precision range should be set to 0 + if (dupInput[0] == '1') + FirstNonZeroPos = 0; + else { + FirstNonZeroPos = 0; + while (dupInput[FirstNonZeroPos] < '1' || dupInput[FirstNonZeroPos] > '9') + ++FirstNonZeroPos; + } + + unsigned it = FirstNonZeroPos; + int NValidNumber = 0; + while (it < dupInput.length()) { + if (dupInput[it] == '.') { + ++it; + continue; + } + ++NValidNumber; + if (NValidNumber > precision) dupInput[it] = '0'; + ++it; + } + + // Here we wanted to adjust the truncate position and the value + decPosition = dupInput.find('.'); + if (decPosition == std::string::npos) // When this is integer + truncBitPosition = (int)dupInput.length(); + else + for (truncBitPosition = (int)(dupInput.length() - 1); truncBitPosition >= 0; + --truncBitPosition) { + if (dupInput[truncBitPosition] == '.') break; + if (dupInput[truncBitPosition] != '0') { + truncBitPosition++; + break; + } + } + + if (dupInput[0] == '1') + dupInput = dupInput.substr(0, truncBitPosition); + else + dupInput = dupInput.substr(1, truncBitPosition - 1); + + decPosition = dupInput.find('.'); + if (decPosition != std::string::npos) { + size_t it = 0; + for (it = decPosition + 1; dupInput[it] == '0'; it++) + ; + if (it - decPosition - 1 < 4) { + ans += dupInput; + return ans; + } else { + ans += scientificFormat(dupInput); + return ans; + } + } else if ((int)(dupInput.length()) <= precision) { + ans += dupInput; + return ans; + } + + ans += scientificFormat(dupInput); + return ans; +} + +template +INLINE void print( + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& x) { + if (_AP_I > 0) { + ap_int_base<_AP_I, _AP_S> p1; + p1.V = x.V >> (_AP_W - _AP_I); + print(p1.V); // print overlaod for .V should exit + } else { + printf("0"); + } + printf("."); + if (_AP_I < _AP_W) { + ap_int_base<_AP_W - _AP_I, false> p2; + p2.V = _AP_ROOT_op_get_range(x.V, 0, _AP_W - _AP_I); + print(p2.V, false); // print overlaod for .V should exit + } +} +#endif // ifndef __SYNTHESIS__ + +// XXX the following two functions have to exist in synthesis, +// as some old HLS Video Library code uses the ostream overload, +// although HLS will later delete I/O function call. + +/// Output streaming +//----------------------------------------------------------------------------- +// XXX apcc cannot handle global std::ios_base::Init() brought in by +#ifndef AP_AUTOCC +#ifndef __SYNTHESIS__ +template +INLINE std::ostream& operator<<( + std::ostream& out, + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& x) { + // TODO support std::ios_base::fmtflags + unsigned width = out.width(); + unsigned precision = out.precision(); + char fill = out.fill(); + std::string str = x.to_string(10, _AP_S); + str = reduceToPrecision(str, precision); + if (width > str.length()) { + for (unsigned i = 0; i < width - str.length(); ++i) + out << fill; + } + out << str; + return out; +} +#endif // ifndef __SYNTHESIS__ + +/// Input streaming +// ----------------------------------------------------------------------------- +#ifndef __SYNTHESIS__ +template +INLINE std::istream& operator>>( + std::istream& in, + ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& x) { + double d; + in >> d; + x = ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(d); + return in; +} +#endif +#endif // ifndef AP_AUTOCC + +/// Operators mixing Integers with ap_fixed_base +// ----------------------------------------------------------------------------- +#define AF_BIN_OP_WITH_INT_SF(BIN_OP, C_TYPE, _AP_W2, _AP_S2, RTYPE) \ + template \ + INLINE typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::template RType< \ + _AP_W2, _AP_W2, _AP_S2>::RTYPE \ + operator BIN_OP( \ + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op, \ + C_TYPE i_op) { \ + return op.operator BIN_OP(ap_int_base<_AP_W2, _AP_S2>(i_op)); \ + } + +#define AF_BIN_OP_WITH_INT(BIN_OP, C_TYPE, _AP_W2, _AP_S2, RTYPE) \ + template \ + INLINE typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::template RType< \ + _AP_W2, _AP_W2, _AP_S2>::RTYPE \ + operator BIN_OP( \ + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op, \ + C_TYPE i_op) { \ + return op.operator BIN_OP(ap_fixed_base<_AP_W2, _AP_W2, _AP_S2>(i_op)); \ + } \ + template \ + INLINE typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::template RType< \ + _AP_W2, _AP_W2, _AP_S2>::RTYPE \ + operator BIN_OP( \ + C_TYPE i_op, \ + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) { \ + return ap_fixed_base<_AP_W2, _AP_W2, _AP_S2>(i_op).operator BIN_OP(op); \ + } + +#define AF_REL_OP_WITH_INT(REL_OP, C_TYPE, _AP_W2, _AP_S2) \ + template \ + INLINE bool operator REL_OP( \ + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op, \ + C_TYPE i_op) { \ + return op.operator REL_OP(ap_fixed_base<_AP_W2, _AP_W2, _AP_S2>(i_op)); \ + } \ + template \ + INLINE bool operator REL_OP( \ + C_TYPE i_op, \ + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) { \ + return ap_fixed_base<_AP_W2, _AP_W2, _AP_S2>(i_op).operator REL_OP(op); \ + } + +#define AF_ASSIGN_OP_WITH_INT(ASSIGN_OP, C_TYPE, _AP_W2, _AP_S2) \ + template \ + INLINE ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& \ + operator ASSIGN_OP( \ + ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op, \ + C_TYPE i_op) { \ + return op.operator ASSIGN_OP(ap_fixed_base<_AP_W2, _AP_W2, _AP_S2>(i_op)); \ + } + +#define AF_ASSIGN_OP_WITH_INT_SF(ASSIGN_OP, C_TYPE, _AP_W2, _AP_S2) \ + template \ + INLINE ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& \ + operator ASSIGN_OP( \ + ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op, \ + C_TYPE i_op) { \ + return op.operator ASSIGN_OP(ap_int_base<_AP_W2, _AP_S2>(i_op)); \ + } + +#define ALL_AF_OP_WITH_INT(C_TYPE, BITS, SIGN) \ + AF_BIN_OP_WITH_INT(+, C_TYPE, (BITS), (SIGN), plus) \ + AF_BIN_OP_WITH_INT(-, C_TYPE, (BITS), (SIGN), minus) \ + AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ + AF_BIN_OP_WITH_INT(/, C_TYPE, (BITS), (SIGN), div) \ + AF_BIN_OP_WITH_INT(&, C_TYPE, (BITS), (SIGN), logic) \ + AF_BIN_OP_WITH_INT(|, C_TYPE, (BITS), (SIGN), logic) \ + AF_BIN_OP_WITH_INT(^, C_TYPE, (BITS), (SIGN), logic) \ + AF_BIN_OP_WITH_INT_SF(>>, C_TYPE, (BITS), (SIGN), lhs) \ + AF_BIN_OP_WITH_INT_SF(<<, C_TYPE, (BITS), (SIGN), lhs) \ + \ + AF_ASSIGN_OP_WITH_INT(+=, C_TYPE, (BITS), (SIGN)) \ + AF_ASSIGN_OP_WITH_INT(-=, C_TYPE, (BITS), (SIGN)) \ + AF_ASSIGN_OP_WITH_INT(*=, C_TYPE, (BITS), (SIGN)) \ + AF_ASSIGN_OP_WITH_INT(/=, C_TYPE, (BITS), (SIGN)) \ + AF_ASSIGN_OP_WITH_INT(&=, C_TYPE, (BITS), (SIGN)) \ + AF_ASSIGN_OP_WITH_INT(|=, C_TYPE, (BITS), (SIGN)) \ + AF_ASSIGN_OP_WITH_INT(^=, C_TYPE, (BITS), (SIGN)) \ + AF_ASSIGN_OP_WITH_INT_SF(>>=, C_TYPE, (BITS), (SIGN)) \ + AF_ASSIGN_OP_WITH_INT_SF(<<=, C_TYPE, (BITS), (SIGN)) \ + \ + AF_REL_OP_WITH_INT(>, C_TYPE, (BITS), (SIGN)) \ + AF_REL_OP_WITH_INT(<, C_TYPE, (BITS), (SIGN)) \ + AF_REL_OP_WITH_INT(>=, C_TYPE, (BITS), (SIGN)) \ + AF_REL_OP_WITH_INT(<=, C_TYPE, (BITS), (SIGN)) \ + AF_REL_OP_WITH_INT(==, C_TYPE, (BITS), (SIGN)) \ + AF_REL_OP_WITH_INT(!=, C_TYPE, (BITS), (SIGN)) + +ALL_AF_OP_WITH_INT(bool, 1, false) +ALL_AF_OP_WITH_INT(char, 8, CHAR_IS_SIGNED) +ALL_AF_OP_WITH_INT(signed char, 8, true) +ALL_AF_OP_WITH_INT(unsigned char, 8, false) +ALL_AF_OP_WITH_INT(short, _AP_SIZE_short, true) +ALL_AF_OP_WITH_INT(unsigned short, _AP_SIZE_short, false) +ALL_AF_OP_WITH_INT(int, _AP_SIZE_int, true) +ALL_AF_OP_WITH_INT(unsigned int, _AP_SIZE_int, false) +ALL_AF_OP_WITH_INT(long, _AP_SIZE_long, true) +ALL_AF_OP_WITH_INT(unsigned long, _AP_SIZE_long, false) +ALL_AF_OP_WITH_INT(ap_slong, _AP_SIZE_ap_slong, true) +ALL_AF_OP_WITH_INT(ap_ulong, _AP_SIZE_ap_slong, false) + +#undef ALL_AF_OP_WITH_INT +#undef AF_BIN_OP_WITH_INT +#undef AF_BIN_OP_WITH_INT_SF +#undef AF_ASSIGN_OP_WITH_INT +#undef AF_ASSIGN_OP_WITH_INT_SF +#undef AF_REL_OP_WITH_INT + +/* + * ********************************************************************** + * TODO + * There is no operator defined with float/double/long double, so that + * code like + * ap_fixed<8,4> a = 1.5f; + * a += 0.5f; + * will fail in compilation. + * Operator with warning about conversion might be wanted. + * ********************************************************************** + */ + +#define AF_BIN_OP_WITH_AP_INT(BIN_OP, RTYPE) \ + template \ + INLINE typename ap_fixed_base<_AP_W2, _AP_W2, _AP_S2>::template RType< \ + _AP_W, _AP_I, _AP_S>::RTYPE \ + operator BIN_OP( \ + const ap_int_base<_AP_W2, _AP_S2>& i_op, \ + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) { \ + return ap_fixed_base<_AP_W2, _AP_W2, _AP_S2>(i_op).operator BIN_OP(op); \ + } \ + \ + template \ + INLINE typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::template RType< \ + _AP_W2, _AP_W2, _AP_S2>::RTYPE \ + operator BIN_OP( \ + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op, \ + const ap_int_base<_AP_W2, _AP_S2>& i_op) { \ + return op.operator BIN_OP(ap_fixed_base<_AP_W2, _AP_W2, _AP_S2>(i_op)); \ + } + +#define AF_REL_OP_WITH_AP_INT(REL_OP) \ + template \ + INLINE bool operator REL_OP( \ + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op, \ + const ap_int_base<_AP_W2, _AP_S2>& i_op) { \ + return op.operator REL_OP(ap_fixed_base<_AP_W2, _AP_W2, _AP_S2>(i_op)); \ + } \ + \ + template \ + INLINE bool operator REL_OP( \ + const ap_int_base<_AP_W2, _AP_S2>& i_op, \ + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) { \ + return ap_fixed_base<_AP_W2, _AP_W2, _AP_S2>(i_op).operator REL_OP(op); \ + } + +#define AF_ASSIGN_OP_WITH_AP_INT(ASSIGN_OP) \ + template \ + INLINE ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& \ + operator ASSIGN_OP( \ + ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op, \ + const ap_int_base<_AP_W2, _AP_S2>& i_op) { \ + return op.operator ASSIGN_OP(ap_fixed_base<_AP_W2, _AP_W2, _AP_S2>(i_op)); \ + } \ + \ + template \ + INLINE ap_int_base<_AP_W2, _AP_S2>& operator ASSIGN_OP( \ + ap_int_base<_AP_W2, _AP_S2>& i_op, \ + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) { \ + return i_op.operator ASSIGN_OP(op.to_ap_int_base()); \ + } + +AF_BIN_OP_WITH_AP_INT(+, plus) +AF_BIN_OP_WITH_AP_INT(-, minus) +AF_BIN_OP_WITH_AP_INT(*, mult) +AF_BIN_OP_WITH_AP_INT(/, div) +AF_BIN_OP_WITH_AP_INT(&, logic) +AF_BIN_OP_WITH_AP_INT(|, logic) +AF_BIN_OP_WITH_AP_INT(^, logic) + +#undef AF_BIN_OP_WITH_AP_INT + +AF_ASSIGN_OP_WITH_AP_INT(+=) +AF_ASSIGN_OP_WITH_AP_INT(-=) +AF_ASSIGN_OP_WITH_AP_INT(*=) +AF_ASSIGN_OP_WITH_AP_INT(/=) +AF_ASSIGN_OP_WITH_AP_INT(&=) +AF_ASSIGN_OP_WITH_AP_INT(|=) +AF_ASSIGN_OP_WITH_AP_INT(^=) + +#undef AF_ASSIGN_OP_WITH_AP_INT + +AF_REL_OP_WITH_AP_INT(==) +AF_REL_OP_WITH_AP_INT(!=) +AF_REL_OP_WITH_AP_INT(>) +AF_REL_OP_WITH_AP_INT(>=) +AF_REL_OP_WITH_AP_INT(<) +AF_REL_OP_WITH_AP_INT(<=) + +#undef AF_REL_OP_WITH_AP_INT + +// Relational Operators with double +template +INLINE bool operator==( + double op1, + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) { + return op2.operator==(op1); +} + +template +INLINE bool operator!=( + double op1, + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) { + return op2.operator!=(op1); +} + +template +INLINE bool operator>( + double op1, + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) { + return op2.operator<(op1); +} + +template +INLINE bool operator>=( + double op1, + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) { + return op2.operator<=(op1); +} + +template +INLINE bool operator<( + double op1, + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) { + return op2.operator>(op1); +} + +template +INLINE bool operator<=( + double op1, + const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) { + return op2.operator>=(op1); +} + +#endif // ifndef __cplusplus else + +#endif // ifndef __AP_FIXED_BASE_H__ else + +// -*- cpp -*- diff --git a/firmware/ap_types/ap_fixed_ref.h b/firmware/ap_types/ap_fixed_ref.h new file mode 100644 index 0000000000000000000000000000000000000000..aefda0a6767aa0530931b9441dc549ab0e8aa839 --- /dev/null +++ b/firmware/ap_types/ap_fixed_ref.h @@ -0,0 +1,718 @@ +/* + * Copyright 2011-2019 Xilinx, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __AP_FIXED_REF_H__ +#define __AP_FIXED_REF_H__ + +#ifndef __AP_FIXED_H__ +#error "Only ap_fixed.h and ap_int.h can be included directly in user code." +#endif + +#ifndef __cplusplus +#error "C++ is required to include this header file" + +#else +#ifndef __SYNTHESIS__ +#include +#endif +/// Proxy class, which allows bit selection to be used as both rvalue (for +/// reading) and lvalue (for writing) +template +struct af_bit_ref { +#ifdef _MSC_VER +#pragma warning(disable : 4521 4522) +#endif + typedef ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> ref_type; + ref_type& d_bv; + int d_index; + + public: + INLINE af_bit_ref( + const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ref) + : d_bv(ref.d_bv), d_index(ref.d_index) { +#ifndef __SYNTHESIS__ + _AP_WARNING(d_index < 0, "Index of bit vector (%d) cannot be negative.", + d_index); + _AP_WARNING(d_index >= _AP_W, "Index of bit vector (%d) out of range (%d).", + d_index, _AP_W); +#endif + } + + INLINE af_bit_ref(ref_type* bv, int index = 0) : d_bv(*bv), d_index(index) {} + + INLINE af_bit_ref(const ref_type* bv, int index = 0) + : d_bv(*const_cast(bv)), d_index(index) {} + + /// convert operators. + INLINE operator bool() const { return _AP_ROOT_op_get_bit(d_bv.V, d_index); } + + /// @name assign operators + // @{ + INLINE af_bit_ref& operator=(bool val) { + d_bv.V = _AP_ROOT_op_set_bit(d_bv.V, d_index, val); + return *this; + } + + // Be explicit to prevent it from being deleted, as field d_bv + // is of reference type. + INLINE af_bit_ref& operator=(const af_bit_ref& val) { + return operator=(bool(val)); + } + + template + INLINE af_bit_ref& operator=( + const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) { + return operator=(bool(val)); + } + + template + INLINE af_bit_ref& operator=(const ap_bit_ref<_AP_W2, _AP_S2>& val) { + return operator=(bool(val)); + } + + template + INLINE af_bit_ref& operator=(const ap_int_base<_AP_W2, _AP_S2>& val) { + return operator=(val != 0); + } + + template + INLINE af_bit_ref& operator=(const ap_range_ref<_AP_W2, _AP_S2>& val) { + return operator=(ap_int_base<_AP_W2, false>(val)); + } + + template + INLINE af_bit_ref& operator=( + const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) { + return operator=(ap_int_base<_AP_W2, false>(val)); + } + + template + INLINE af_bit_ref& operator=( + const ap_concat_ref<_AP_W2, _AP_T3, _AP_W3, _AP_T3>& val) { + return operator=(ap_int_base<_AP_W2 + _AP_W3, false>(val)); + } + // @} + + /// @name concatenate operators + // @{ + template + INLINE ap_concat_ref<1, af_bit_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> > + operator,(ap_int_base<_AP_W2, _AP_S2> &op) { + return ap_concat_ref<1, af_bit_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >( + *this, op); + } + + template + INLINE ap_concat_ref<1, af_bit_ref, 1, ap_bit_ref<_AP_W2, _AP_S2> > operator,( + const ap_bit_ref<_AP_W2, _AP_S2> &op) { + return ap_concat_ref<1, af_bit_ref, 1, ap_bit_ref<_AP_W2, _AP_S2> >(*this, + op); + } + + template + INLINE ap_concat_ref<1, af_bit_ref, _AP_W2, ap_range_ref<_AP_W2, _AP_S2> > + operator,(const ap_range_ref<_AP_W2, _AP_S2> &op) { + return ap_concat_ref<1, af_bit_ref, _AP_W2, ap_range_ref<_AP_W2, _AP_S2> >( + *this, op); + } + + template + INLINE ap_concat_ref<1, af_bit_ref, _AP_W2 + _AP_W3, + ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> > + operator,(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &op) { + return ap_concat_ref<1, af_bit_ref, _AP_W2 + _AP_W3, + ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >(*this, + op); + } + + template + INLINE ap_concat_ref< + 1, af_bit_ref, _AP_W2, + af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> > + operator,( + const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> &op) { + return ap_concat_ref< + 1, af_bit_ref, _AP_W2, + af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this, + op); + } + + template + INLINE ap_concat_ref<1, af_bit_ref, 1, af_bit_ref<_AP_W2, _AP_I2, _AP_S2, + _AP_Q2, _AP_O2, _AP_N2> > + operator,( + const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> &op) { + return ap_concat_ref<1, af_bit_ref, 1, af_bit_ref<_AP_W2, _AP_I2, _AP_S2, + _AP_Q2, _AP_O2, _AP_N2> >( + *this, + const_cast&>( + op)); + } + // @} + + /// @name comparison + // @{ + template + INLINE bool operator==( + const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) { + return get() == op.get(); + } + + template + INLINE bool operator!=( + const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) { + return get() != op.get(); + } + // @} + + INLINE bool operator~() const { + bool bit = _AP_ROOT_op_get_bit(d_bv.V, d_index); + return bit ? false : true; + } + + INLINE bool get() const { return _AP_ROOT_op_get_bit(d_bv.V, d_index); } + + INLINE int length() const { return 1; } + +#ifndef __SYNTHESIS__ + std::string to_string() const { return get() ? "1" : "0"; } +#else + // XXX HLS will delete this in synthesis + INLINE char* to_string() const { return 0; } +#endif +}; // struct af_bit_ref + +// XXX apcc cannot handle global std::ios_base::Init() brought in by +#ifndef AP_AUTOCC +#ifndef __SYNTHESIS__ +template +INLINE std::ostream& operator<<( + std::ostream& os, + const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& x) { + os << x.to_string(); + return os; +} +#endif // ifndef __SYNTHESIS__ +#endif // ifndef AP_AUTOCC + +/// Range (slice) reference. +template +struct af_range_ref { +#ifdef _MSC_VER +#pragma warning(disable : 4521 4522) +#endif + typedef ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> ref_type; + ref_type& d_bv; + int l_index; + int h_index; + + public: + /// copy ctor + INLINE af_range_ref( + const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ref) + : d_bv(ref.d_bv), l_index(ref.l_index), h_index(ref.h_index) {} + + /// ctor from ap_fixed_base, higher and lower bound. + /** if h is less than l, the bits selected will be returned in reverse order. + */ + INLINE af_range_ref(ref_type* bv, int h, int l) + : d_bv(*bv), l_index(l), h_index(h) { +#ifndef __SYNTHESIS__ + _AP_WARNING(h < 0 || l < 0, + "Higher bound(%d) and lower(%d) bound cannot be negative.", h, + l); + _AP_WARNING(h >= _AP_W || l >= _AP_W, + "Higher bound(%d) or lower(%d) bound out of range.", h, l); + _AP_WARNING(h < l, "The bits selected will be returned in reverse order."); +#endif + } + + INLINE af_range_ref(const ref_type* bv, int h, int l) + : d_bv(*const_cast(bv)), l_index(l), h_index(h) { +#ifndef __SYNTHESIS__ + _AP_WARNING(h < 0 || l < 0, + "Higher bound(%d) and lower(%d) bound cannot be negative.", h, + l); + _AP_WARNING(h >= _AP_W || l >= _AP_W, + "Higher bound(%d) or lower(%d) bound out of range.", h, l); + _AP_WARNING(h < l, "The bits selected will be returned in reverse order."); +#endif + } + + /// @name assign operators + // @{ + +#define ASSIGN_CTYPE_TO_AF_RANGE(DATA_TYPE) \ + INLINE af_range_ref& operator=(const DATA_TYPE val) { \ + ap_int_base<_AP_W, false> loc(val); \ + d_bv.V = _AP_ROOT_op_set_range(d_bv.V, l_index, h_index, loc.V); \ + return *this; \ + } + + ASSIGN_CTYPE_TO_AF_RANGE(bool) + ASSIGN_CTYPE_TO_AF_RANGE(char) + ASSIGN_CTYPE_TO_AF_RANGE(signed char) + ASSIGN_CTYPE_TO_AF_RANGE(unsigned char) + ASSIGN_CTYPE_TO_AF_RANGE(short) + ASSIGN_CTYPE_TO_AF_RANGE(unsigned short) + ASSIGN_CTYPE_TO_AF_RANGE(int) + ASSIGN_CTYPE_TO_AF_RANGE(unsigned int) + ASSIGN_CTYPE_TO_AF_RANGE(long) + ASSIGN_CTYPE_TO_AF_RANGE(unsigned long) + ASSIGN_CTYPE_TO_AF_RANGE(ap_slong) + ASSIGN_CTYPE_TO_AF_RANGE(ap_ulong) +#if _AP_ENABLE_HALF_ == 1 + ASSIGN_CTYPE_TO_AF_RANGE(half) +#endif + ASSIGN_CTYPE_TO_AF_RANGE(float) + ASSIGN_CTYPE_TO_AF_RANGE(double) +#undef ASSIGN_CTYPE_TO_AF_RANGE + + /// assgin using a string. XXX crucial for cosim. + INLINE af_range_ref& operator=(const char* val) { + const ap_int_base<_AP_W, false> tmp(val); // XXX figure out radix + d_bv.V = _AP_ROOT_op_set_range(d_bv.V, l_index, h_index, tmp.V); + return *this; + } + + /// assign from ap_int_base. + // NOTE Base of other assgin operators. + template + INLINE af_range_ref& operator=(const ap_int_base<_AP_W3, _AP_S3>& val) { + d_bv.V = _AP_ROOT_op_set_range(d_bv.V, l_index, h_index, val.V); + return *this; + } + + /// assign from range reference to ap_int_base. + template + INLINE af_range_ref& operator=(const ap_range_ref<_AP_W2, _AP_S2>& val) { + const ap_int_base<_AP_W2, false> tmp(val); + return operator=(tmp); + } + + /// assign from bit reference to ap_int_base.. + template + INLINE af_range_ref& operator=(const ap_bit_ref<_AP_W2, _AP_S2>& val) { + const ap_int_base<1, false> tmp((bool)val); + return operator=(tmp); + } + + /// assgin from ap_fixed_base. + template + INLINE af_range_ref& operator=( + const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& + val) { + d_bv.V = _AP_ROOT_op_set_range(d_bv.V, l_index, h_index, val.V); + return *this; + } + + /// copy assgin. + // XXX This has to be explicit, otherwise it will be deleted, as d_bv is + // of reference type. + INLINE af_range_ref& operator=(const af_range_ref& val) { + ap_int_base<_AP_W, false> tmp(val); + return operator=(tmp); + } + + /// assign from range reference to ap_fixed_base. + template + INLINE af_range_ref& operator=( + const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) { + ap_int_base<_AP_W2, false> tmp(val); + return operator=(tmp); + } + + /// assign from bit reference to ap_fixed_base. + template + INLINE af_range_ref& operator=( + const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) { + ap_int_base<1, false> tmp((bool)val); + return operator=(tmp); + } + + /// assign from compound reference. + template + INLINE af_range_ref& operator=( + const ap_concat_ref<_AP_W2, _AP_T3, _AP_W3, _AP_T3>& val) { + const ap_int_base<_AP_W2 + _AP_W3, false> tmp(val); + return operator=(tmp); + } + // @} + + /// @name comparison operators with ap_range_ref. + // @{ + template + INLINE bool operator==(const ap_range_ref<_AP_W2, _AP_S2>& op2) { + ap_int_base<_AP_W, false> lop(*this); + ap_int_base<_AP_W2, false> rop(op2); + return lop == rop; + } + + template + INLINE bool operator!=(const ap_range_ref<_AP_W2, _AP_S2>& op2) { + return !(operator==(op2)); + } + + template + INLINE bool operator<(const ap_range_ref<_AP_W2, _AP_S2>& op2) { + ap_int_base<_AP_W, false> lop(*this); + ap_int_base<_AP_W2, false> rop(op2); + return lop < rop; + } + + template + INLINE bool operator>(const ap_range_ref<_AP_W2, _AP_S2>& op2) { + ap_int_base<_AP_W, false> lop(*this); + ap_int_base<_AP_W2, false> rop(op2); + return lop > rop; + } + + template + INLINE bool operator<=(const ap_range_ref<_AP_W2, _AP_S2>& op2) { + return !(operator>(op2)); + } + + template + INLINE bool operator>=(const ap_range_ref<_AP_W2, _AP_S2>& op2) { + return !(operator<(op2)); + } + // @} + + /// @name comparison operators with af_range_ref. + // @{ + template + INLINE bool operator==( + const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) { + ap_int_base<_AP_W, false> lop(*this); + ap_int_base<_AP_W2, false> rop(op2); + return lop == rop; + } + + template + INLINE bool operator!=( + const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) { + return !(operator==(op2)); + } + + template + INLINE bool operator<( + const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) { + ap_int_base<_AP_W, false> lop(*this); + ap_int_base<_AP_W2, false> rop(op2); + return lop < rop; + } + + template + INLINE bool operator>( + const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) { + ap_int_base<_AP_W, false> lop(*this); + ap_int_base<_AP_W2, false> rop(op2); + return lop > rop; + } + + template + INLINE bool operator<=( + const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) { + return !(operator>(op2)); + } + + template + INLINE bool operator>=( + const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) { + return !(operator<(op2)); + } + // @} + + /// @name concatenate operators. + /// @{ + /// concatenate with ap_int_base. + template + INLINE + ap_concat_ref<_AP_W, af_range_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> > + operator,(ap_int_base<_AP_W2, _AP_S2> &op) { + return ap_concat_ref<_AP_W, af_range_ref, _AP_W2, + ap_int_base<_AP_W2, _AP_S2> >(*this, op); + } + + /// concatenate with ap_bit_ref. + template + INLINE ap_concat_ref<_AP_W, af_range_ref, 1, ap_bit_ref<_AP_W2, _AP_S2> > + operator,(const ap_bit_ref<_AP_W2, _AP_S2> &op) { + return ap_concat_ref<_AP_W, af_range_ref, 1, ap_bit_ref<_AP_W2, _AP_S2> >( + *this, const_cast&>(op)); + } + + /// concatenate with ap_bit_ref. + template + INLINE ap_concat_ref<_AP_W, af_range_ref, _AP_W2, ap_range_ref<_AP_W2, _AP_S2> > + operator,(const ap_range_ref<_AP_W2, _AP_S2> &op) { + return ap_concat_ref<_AP_W, af_range_ref, _AP_W2, + ap_range_ref<_AP_W2, _AP_S2> >( + *this, const_cast&>(op)); + } + + /// concatenate with ap_concat_ref. + template + INLINE ap_concat_ref<_AP_W, af_range_ref, _AP_W2 + _AP_W3, + ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> > + operator,(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &op) { + return ap_concat_ref<_AP_W, af_range_ref, _AP_W2 + _AP_W3, + ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >( + *this, const_cast&>(op)); + } + + /// concatenate with another af_range_ref. + template + INLINE + ap_concat_ref<_AP_W, af_range_ref, _AP_W2, + af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> > + operator,(const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> + &op) { + return ap_concat_ref< + _AP_W, af_range_ref, _AP_W2, + af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >( + *this, + const_cast&>( + op)); + } + + /// concatenate with another af_bit_ref. + template + INLINE + ap_concat_ref<_AP_W, af_range_ref, 1, + af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> > + operator,( + const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> &op) { + return ap_concat_ref< + _AP_W, af_range_ref, 1, + af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >( + *this, + const_cast&>( + op)); + } + // @} + + INLINE operator ap_ulong() const { + ap_int_base<_AP_W, false> ret; + ret.V = _AP_ROOT_op_get_range(d_bv.V, l_index, h_index); + return ret.to_uint64(); + } + + INLINE operator ap_int_base<_AP_W, false>() const { + ap_int_base<_AP_W, false> ret; + ret.V = _AP_ROOT_op_get_range(d_bv.V, l_index, h_index); + return ret; + } + + INLINE ap_int_base<_AP_W, false> to_ap_int_base() const { + ap_int_base<_AP_W, false> ret; + ret.V = _AP_ROOT_op_get_range(d_bv.V, l_index, h_index); + return ret; + } + + // used in ap_fixed_base::to_string() + INLINE char to_char() const { + return (char)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index)); + } + + INLINE int to_int() const { + return (int)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index)); + } + + INLINE unsigned to_uint() const { + return (unsigned)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index)); + } + + INLINE long to_long() const { + return (long)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index)); + } + + INLINE unsigned long to_ulong() const { + return (unsigned long)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index)); + } + + INLINE ap_slong to_int64() const { + return (ap_slong)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index)); + } + + INLINE ap_ulong to_uint64() const { + return (ap_ulong)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index)); + } + + INLINE ap_int_base<_AP_W, false> get() const { + ap_int_base<_AP_W, false> ret; + ret.V = _AP_ROOT_op_get_range(d_bv.V, l_index, h_index); + return ret; + } + + template + INLINE void set(const ap_int_base<_AP_W2, false>& val) { + d_bv.V = _AP_ROOT_op_set_range(d_bv.V, l_index, h_index, val.V); + } + + INLINE int length() const { + return h_index >= l_index ? h_index - l_index + 1 : l_index - h_index + 1; + } + +#ifndef __SYNTHESIS__ + std::string to_string(signed char rd = 2) const { + ap_int_base<_AP_W, false> ret; + ret.V = _AP_ROOT_op_get_range(d_bv.V, l_index, h_index); + return ret.to_string(rd); + } +#else + // XXX HLS will delete this in synthesis + INLINE char* to_string(signed char rd = 2) const { + return 0; + } +#endif +}; // struct af_range_ref + +// XXX apcc cannot handle global std::ios_base::Init() brought in by +#ifndef AP_AUTOCC +#ifndef __SYNTHESIS__ +template +INLINE std::ostream& operator<<( + std::ostream& os, + const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& x) { + os << x.to_string(); + return os; +} +#endif +#endif // ifndef AP_AUTOCC + +#define AF_REF_REL_OP_WITH_INT(REL_OP, C_TYPE, _AP_W2, _AP_S2) \ + template \ + INLINE bool operator REL_OP( \ + const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op, \ + C_TYPE op2) { \ + return ap_int_base<_AP_W, false>(op) \ + REL_OP ap_int_base<_AP_W2, _AP_S2>(op2); \ + } \ + \ + template \ + INLINE bool operator REL_OP( \ + C_TYPE op2, \ + const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) { \ + return ap_int_base<_AP_W2, _AP_S2>(op2) \ + REL_OP ap_int_base<_AP_W, false>(op); \ + } \ + \ + template \ + INLINE bool operator REL_OP( \ + const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op, \ + C_TYPE op2) { \ + return bool(op) REL_OP op2; \ + } \ + \ + template \ + INLINE bool operator REL_OP( \ + C_TYPE op2, \ + const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) { \ + return op2 REL_OP bool(op); \ + } + +#define AF_REF_REL_OPS_WITH_INT(C_TYPE, _AP_W2, _AP_S2) \ + AF_REF_REL_OP_WITH_INT(>, C_TYPE, (_AP_W2), (_AP_S2)) \ + AF_REF_REL_OP_WITH_INT(<, C_TYPE, (_AP_W2), (_AP_S2)) \ + AF_REF_REL_OP_WITH_INT(>=, C_TYPE, (_AP_W2), (_AP_S2)) \ + AF_REF_REL_OP_WITH_INT(<=, C_TYPE, (_AP_W2), (_AP_S2)) \ + AF_REF_REL_OP_WITH_INT(==, C_TYPE, (_AP_W2), (_AP_S2)) \ + AF_REF_REL_OP_WITH_INT(!=, C_TYPE, (_AP_W2), (_AP_S2)) + +AF_REF_REL_OPS_WITH_INT(bool, 1, false) +AF_REF_REL_OPS_WITH_INT(char, 8, CHAR_IS_SIGNED) +AF_REF_REL_OPS_WITH_INT(signed char, 8, true) +AF_REF_REL_OPS_WITH_INT(unsigned char, 8, false) +AF_REF_REL_OPS_WITH_INT(short, _AP_SIZE_short, true) +AF_REF_REL_OPS_WITH_INT(unsigned short, _AP_SIZE_short, false) +AF_REF_REL_OPS_WITH_INT(int, _AP_SIZE_int, true) +AF_REF_REL_OPS_WITH_INT(unsigned int, _AP_SIZE_int, false) +AF_REF_REL_OPS_WITH_INT(long, _AP_SIZE_long, true) +AF_REF_REL_OPS_WITH_INT(unsigned long, _AP_SIZE_long, false) +AF_REF_REL_OPS_WITH_INT(ap_slong, _AP_SIZE_ap_slong, true) +AF_REF_REL_OPS_WITH_INT(ap_ulong, _AP_SIZE_ap_slong, false) + +#undef AF_REF_REL_OP_INT +#undef AF_REF_REL_OPS_WITH_INT + +#define AF_REF_REL_OP_WITH_AP_INT(REL_OP) \ + template \ + INLINE bool operator REL_OP( \ + const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op, \ + const ap_int_base<_AP_W2, _AP_S>& op2) { \ + return ap_int_base<_AP_W, false>(op) REL_OP op2; \ + } \ + template \ + INLINE bool operator REL_OP( \ + const ap_int_base<_AP_W2, _AP_S2>& op2, \ + const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) { \ + return op2 REL_OP ap_int_base<_AP_W, false>(op); \ + } \ + template \ + INLINE bool operator REL_OP( \ + const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op, \ + const ap_int_base<_AP_W2, _AP_S2>& op2) { \ + return ap_int_base<1, false>(op) REL_OP op2; \ + } \ + template \ + INLINE bool operator REL_OP( \ + const ap_int_base<_AP_W2, _AP_S2>& op2, \ + const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) { \ + return op2 REL_OP ap_int_base<1, false>(op); \ + } + +AF_REF_REL_OP_WITH_AP_INT(>) +AF_REF_REL_OP_WITH_AP_INT(<) +AF_REF_REL_OP_WITH_AP_INT(>=) +AF_REF_REL_OP_WITH_AP_INT(<=) +AF_REF_REL_OP_WITH_AP_INT(==) +AF_REF_REL_OP_WITH_AP_INT(!=) + +#endif // ifndef __cplusplus + +#endif // ifndef __AP_FIXED_REF_H__ + +// -*- cpp -*- diff --git a/firmware/ap_types/ap_fixed_special.h b/firmware/ap_types/ap_fixed_special.h new file mode 100644 index 0000000000000000000000000000000000000000..0f7a9f7eb35605b91ca5d32cd03115a94b554b7a --- /dev/null +++ b/firmware/ap_types/ap_fixed_special.h @@ -0,0 +1,230 @@ +/* + * Copyright 2011-2019 Xilinx, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __AP_FIXED_SPECIAL_H__ +#define __AP_FIXED_SPECIAL_H__ + +#ifndef __AP_FIXED_H__ +#error "Only ap_fixed.h and ap_int.h can be included directly in user code." +#endif + +#ifndef __SYNTHESIS__ +#include +#include +#endif +// FIXME AP_AUTOCC cannot handle many standard headers, so declare instead of +// include. +// #include +namespace std { +template class complex; +} + +/* + TODO: Modernize the code using C++11/C++14 + 1. constexpr http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2016/p0415r0.html + 2. move constructor +*/ + +namespace std { +/* + Specialize std::complex to zero initialization ap_fixed. + + To reduce the area cost, ap_fixed is not zero initialized, just like basic + types float or double. However, libstdc++ provides specialization for float, + double and long double, initializing image part to 0 when not specified. + + This has become a difficulty in switching legacy code from these C types to + ap_fixed. To ease the tranform of legacy code, we have to implement + specialization of std::complex<> for our type. + + As ap_fixed is a template, it is impossible to specialize only the methods + that causes default initialization of value type in std::complex<>. An + explicit full specialization of the template class has to be done, covering + all the member functions and operators of std::complex<> as specified + in standard 26.2.4 and 26.2.5. +*/ +template +class complex > { + public: + typedef ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N> _Tp; + typedef _Tp value_type; + + // 26.2.4/1 + // Constructor without argument + // Default initialize, so that in dataflow, the variable is only written once. + complex() : _M_real(_Tp()), _M_imag(_Tp()) {} + // Constructor with ap_fixed. + // Zero initialize image part when not specified, so that `C(1) == C(1,0)` + complex(const _Tp &__r, const _Tp &__i = _Tp(0)) + : _M_real(__r), _M_imag(__i) {} + + // Constructor with another complex number + template + complex(const complex<_Up> &__z) : _M_real(__z.real()), _M_imag(__z.imag()) {} + +#if __cplusplus >= 201103L + const _Tp& real() const { return _M_real; } + const _Tp& imag() const { return _M_imag; } +#else + _Tp& real() { return _M_real; } + const _Tp& real() const { return _M_real; } + _Tp& imag() { return _M_imag; } + const _Tp& imag() const { return _M_imag; } +#endif + + void real(_Tp __val) { _M_real = __val; } + + void imag(_Tp __val) { _M_imag = __val; } + + // Assign this complex number with ap_fixed. + // Zero initialize image poarrt, so that `C c; c = 1; c == C(1,0);` + complex<_Tp> &operator=(const _Tp __t) { + _M_real = __t; + _M_imag = _Tp(0); + return *this; + } + + // 26.2.5/1 + // Add ap_fixed to this complex number. + complex<_Tp> &operator+=(const _Tp &__t) { + _M_real += __t; + return *this; + } + + // 26.2.5/3 + // Subtract ap_fixed from this complex number. + complex<_Tp> &operator-=(const _Tp &__t) { + _M_real -= __t; + return *this; + } + + // 26.2.5/5 + // Multiply this complex number by ap_fixed. + complex<_Tp> &operator*=(const _Tp &__t) { + _M_real *= __t; + _M_imag *= __t; + return *this; + } + + // 26.2.5/7 + // Divide this complex number by ap_fixed. + complex<_Tp> &operator/=(const _Tp &__t) { + _M_real /= __t; + _M_imag /= __t; + return *this; + } + + // Assign complex number to this complex number. + template + complex<_Tp> &operator=(const complex<_Up> &__z) { + _M_real = __z.real(); + _M_imag = __z.imag(); + return *this; + } + + // 26.2.5/9 + // Add complex number to this. + template + complex<_Tp> &operator+=(const complex<_Up> &__z) { + _M_real += __z.real(); + _M_imag += __z.imag(); + return *this; + } + + // 26.2.5/11 + // Subtract complex number from this. + template + complex<_Tp> &operator-=(const complex<_Up> &__z) { + _M_real -= __z.real(); + _M_imag -= __z.imag(); + return *this; + } + + // 26.2.5/13 + // Multiply this by complex number. + template + complex<_Tp> &operator*=(const complex<_Up> &__z) { + const _Tp __r = _M_real * __z.real() - _M_imag * __z.imag(); + _M_imag = _M_real * __z.imag() + _M_imag * __z.real(); + _M_real = __r; + return *this; + } + + // 26.2.5/15 + // Divide this by complex number. + template + complex<_Tp> &operator/=(const complex<_Up> &__z) { + complex<_Tp> cj (__z.real(), -__z.imag()); + complex<_Tp> a = (*this) * cj; + complex<_Tp> b = cj * __z; + _M_real = a.real() / b.real(); + _M_imag = a.imag() / b.real(); + return *this; + } + + private: + _Tp _M_real; + _Tp _M_imag; + +}; // class complex > + +/* + Non-member operations + These operations are not required by standard in 26.2.6, but libstdc++ + defines them for + float, double or long double's specialization. +*/ +// Compare complex number with ap_fixed. +template +inline bool operator==( + const complex > &__x, + const ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N> &__y) { + return __x.real() == __y && + __x.imag() == 0; +} + +// Compare ap_fixed with complex number. +template +inline bool operator==( + const ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N> &__x, + const complex > &__y) { + return __x == __y.real() && + 0 == __y.imag(); +} + +// Compare complex number with ap_fixed. +template +inline bool operator!=( + const complex > &__x, + const ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N> &__y) { + return __x.real() != __y || + __x.imag() != 0; +} + +// Compare ap_fixed with complex number. +template +inline bool operator!=( + const ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N> &__x, + const complex > &__y) { + return __x != __y.real() || + 0 != __y.imag(); +} + +} // namespace std + +#endif // ifndef __AP_FIXED_SPECIAL_H__ + +// -*- cpp -*- diff --git a/firmware/ap_types/ap_float.h b/firmware/ap_types/ap_float.h new file mode 100644 index 0000000000000000000000000000000000000000..b91d38d9fc02218f0be8da3c53f689ff53789733 --- /dev/null +++ b/firmware/ap_types/ap_float.h @@ -0,0 +1,186 @@ +#ifndef __AP_FLOAT_H__ +#define __AP_FLOAT_H__ + +#define __AP_FLOAT_H_MAX(a, b) ((a) > (b) ? (a) : (b)) + +constexpr int ceillog2(int x) { return (x <= 2) ? 1 : 1 + ceillog2((x + 1) / 2); } + +#include "ap_fixed.h" +#include +#include + +template +INLINE ap_fixed_base<_AP_W, _AP_I, false, _AP_Q, _AP_O, _AP_N> +abs(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> value) { + if (value > 0) { + return value; + } else { + return -value; + } +} + +template +INLINE ap_uint msb_loc(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> value) { + auto buf = abs(value); + ap_uint msb = 0; + for (int i = 0; i < _AP_W; i++) { +#pragma HLS UNROLL + if (buf[i] && msb < i) { + msb = i; + } + } + return msb; +} + +template +INLINE auto rt_floorlog2(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> value) + -> ap_int_base 0), (_AP_W - _AP_I > 0)> { + // Runtime floorlog2 for fixed point numbers + auto msb = msb_loc(value); + ap_int_base<6, 1> r = msb; + return r - (_AP_W - _AP_I); +} + +template +INLINE auto rt_ceillog2(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> value) -> decltype(rt_floorlog2(value)) { + // Runtime ceillog2 for fixed point numbers + auto msb = msb_loc(value); + ap_ufixed<_AP_W, _AP_I> buf; + if (value > 0) { + buf = value; + } else { + buf = -value; + } + bool is_pow2 = buf << (_AP_W - msb) == 0; + return msb + !is_pow2 - (_AP_W - _AP_I); +} + +template INLINE bool cond_minimal_normal(ap_ufixed abs_value) { + bool is_normal = true; + for (int i = 0; i < M + 1; ++i) { +#pragma HLS UNROLL + is_normal &= abs_value[W - I - (1 << (E - 1)) + E0 - i]; + } + return is_normal; +} + +template struct ap_float { + + bool is_negative; + typedef ap_ufixed mantissa_t; + typedef ap_fixed exponent_t; + typedef ap_ufixed opr_mantissa_t; + typedef ap_ufixed opr_mantissa2_t; + mantissa_t mantissa; + exponent_t exponent; + INLINE ap_float() {} + INLINE ap_float(mantissa_t mantissa, exponent_t exponent) : mantissa(mantissa), exponent(exponent) {} + + template INLINE ap_float(T value) { *this = ap_fixed<32, 16>(value); } + + template + INLINE int operator=(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> value) { + is_negative = value < 0; + ap_ufixed _mantissa; + ap_ufixed<_AP_W - _AP_S, _AP_I - _AP_S> abs_value = abs(value); + exponent = rt_floorlog2(abs_value) - E0; // E0 is the offset + + // std::cout << "cond=" << (abs_value >> (-(1 << (E - 1)) + E0)).to_float() << std::endl; + if (exponent != -(1 << (E - 1))) { + // Normal + _mantissa = (abs_value >> (ap_int(exponent) + E0)) - 1; + } else { + // Subnormal + _mantissa = (abs_value >> (ap_int(exponent + 1) + E0)); + } + if (_mantissa >= 1 && exponent != (1 << (E - 1)) - 1) { + exponent = exponent + 1; + _mantissa = 0; + } + mantissa = _mantissa; + + return 0; + } + + INLINE ap_fixed to_ap_fixed() const { + + ap_ufixed _result; + int shift = exponent; + if (exponent == -(1 << (E - 1))) { + shift += 1; + _result = mantissa; + } else { + _result = mantissa + 1; + } + + ap_ufixed result; + + _result = _result << shift; + result.range() = _result.range(); + if (is_negative) + return -result; + else + return result; + } + + INLINE double to_float() const { return to_ap_fixed().to_float(); } + INLINE operator float() const { return to_float(); } + INLINE operator double() const { return to_float(); } + + template + auto operator*(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> other) + -> ap_fixed { + + int shift = exponent; + opr_mantissa_t mantissa; + if (exponent == -(1 << (E - 1))) { + shift += 1; + mantissa = this->mantissa; + } else { + mantissa = this->mantissa + 1; + } + opr_mantissa2_t mantissa2; + mantissa2.range() = mantissa.range(); + + constexpr int E_max = (1 << (E - 1)) - 1 + E0; + constexpr int E_min = -(1 << (E - 1)) + E0; + constexpr int I = 1 + E_max + _AP_I + (!_AP_S); + constexpr int W = M + 1 + _AP_W + E_max - E_min + 1 + (!_AP_S); + // std::cout << "W=" << W << std::endl; + // std::cout << "I=" << I << std::endl; + // std::cout << "E_max=" << E_max << std::endl; + // std::cout << "E_min=" << E_min << std::endl; + ap_fixed result_fixed = mantissa2 * other; + + if (is_negative) { + result_fixed = -result_fixed; + } + result_fixed <<= shift; + return result_fixed; + } + + template ap_float<_M, _E, _E0> operator*(ap_float<_M, _E, _E0> other) { + assert(0); // ap_float can only be multiplied by ap_fixed + } +}; + +template +auto operator*(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> a, ap_float b) -> decltype(b * a) { + return b * a; +} + +#ifndef __SYNTHESIS__ +template int operator>>(std::istringstream s, ap_float &b) { + std::string str; + s >> str; + b = std::stof(str); + return 0; +} + +template std::ostream &operator<<(std::ostream &os, const ap_float &b) { + os << b.to_float(); + return os; +} +#endif + +#endif diff --git a/firmware/ap_types/ap_int.h b/firmware/ap_types/ap_int.h new file mode 100644 index 0000000000000000000000000000000000000000..db3044d48ce8b19696aac46b97512da8efa5a5a7 --- /dev/null +++ b/firmware/ap_types/ap_int.h @@ -0,0 +1,330 @@ +/* + * Copyright 2011-2019 Xilinx, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __AP_INT_H__ +#define __AP_INT_H__ + +#include +#include +#include + +//--------------------------------------------------------------- + +/// Sign Arbitrary Precision Type. +template +struct ap_int : ap_int_base<_AP_W, true> { + typedef ap_int_base<_AP_W, true> Base; + // Constructor + INLINE ap_int() : Base() {} + + // Copy ctor + INLINE ap_int(const ap_int& op) { Base::V = op.V; } + + template + INLINE ap_int(const ap_int<_AP_W2>& op) { + Base::V = op.V; + } + + template + INLINE ap_int(const volatile ap_int<_AP_W2>& op) { + Base::V = op.V; + } + + template + INLINE ap_int(const ap_uint<_AP_W2>& op) { + Base::V = op.V; + } + + template + INLINE ap_int(const volatile ap_uint<_AP_W2>& op) { + Base::V = op.V; + } + + template + INLINE ap_int(const ap_range_ref<_AP_W2, _AP_S2>& ref) : Base(ref) {} + + template + INLINE ap_int(const ap_bit_ref<_AP_W2, _AP_S2>& ref) : Base(ref) {} + + template + INLINE ap_int(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& ref) + : Base(ref) {} + + template + INLINE ap_int(const ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op) + : Base((ap_fixed_base<_AP_W2, _AP_I2, true, _AP_Q2, _AP_O2, _AP_N2>)op) {} + + template + INLINE ap_int(const ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op) + : Base((ap_fixed_base<_AP_W2, _AP_I2, false, _AP_Q2, _AP_O2, _AP_N2>)op) { + } + + template + INLINE ap_int( + const volatile ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op) + : Base((ap_fixed_base<_AP_W2, _AP_I2, true, _AP_Q2, _AP_O2, _AP_N2>)op) {} + + template + INLINE ap_int( + const volatile ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op) + : Base((ap_fixed_base<_AP_W2, _AP_I2, false, _AP_Q2, _AP_O2, _AP_N2>)op) { + } + + template + INLINE ap_int(const ap_int_base<_AP_W2, _AP_S2>& op) { + Base::V = op.V; + } + + template + INLINE ap_int( + const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) + : Base(op) {} + + template + INLINE ap_int( + const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) + : Base(op) {} + + template + INLINE ap_int( + const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) + : Base(op) {} + +#define CTOR(TYPE) \ + INLINE ap_int(TYPE val) { Base::V = val; } + CTOR(bool) + CTOR(char) + CTOR(signed char) + CTOR(unsigned char) + CTOR(short) + CTOR(unsigned short) + CTOR(int) + CTOR(unsigned int) + CTOR(long) + CTOR(unsigned long) + CTOR(ap_slong) + CTOR(ap_ulong) +#undef CTOR + ap_int(double val) : Base(val) {} + ap_int(float val) : Base(val) {} +#if _AP_ENABLE_HALF_ == 1 + ap_int(half val) : Base(val) {} +#endif + + // ap_int_base will guess radix if radix is not provided. + INLINE ap_int(const char* s) : Base(s) {} + + INLINE ap_int(const char* s, signed char rd) : Base(s, rd) {} + + // Assignment + /* ctor will be used when right is not of proper type. */ + + INLINE ap_int& operator=(const ap_int<_AP_W>& op2) { + Base::V = op2.V; + return *this; + } + + /* cannot bind volatile reference to non-volatile type. */ + INLINE ap_int& operator=(const volatile ap_int<_AP_W>& op2) { + Base::V = op2.V; + return *this; + } + + /* cannot return volatile *this. */ + INLINE void operator=(const ap_int<_AP_W>& op2) volatile { Base::V = op2.V; } + + INLINE void operator=(const volatile ap_int<_AP_W>& op2) volatile { + Base::V = op2.V; + } + +}; // struct ap_int. + +//--------------------------------------------------------------- + +/// Unsigned Arbitrary Precision Type. +template +struct ap_uint : ap_int_base<_AP_W, false> { + typedef ap_int_base<_AP_W, false> Base; + // Constructor + INLINE ap_uint() : Base() {} + + // Copy ctor + INLINE ap_uint(const ap_uint& op) { Base::V = op.V; } + + template + INLINE ap_uint(const ap_uint<_AP_W2>& op) { + Base::V = op.V; + } + + template + INLINE ap_uint(const ap_int<_AP_W2>& op) { + Base::V = op.V; + } + + template + INLINE ap_uint(const volatile ap_uint<_AP_W2>& op) { + Base::V = op.V; + } + + template + INLINE ap_uint(const volatile ap_int<_AP_W2>& op) { + Base::V = op.V; + } + + template + INLINE ap_uint(const ap_range_ref<_AP_W2, _AP_S2>& ref) : Base(ref) {} + + template + INLINE ap_uint(const ap_bit_ref<_AP_W2, _AP_S2>& ref) : Base(ref) {} + + template + INLINE ap_uint(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& ref) + : Base(ref) {} + + template + INLINE ap_uint(const ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op) + : Base((ap_fixed_base<_AP_W2, _AP_I2, true, _AP_Q2, _AP_O2, _AP_N2>)op) {} + + template + INLINE ap_uint(const ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op) + : Base((ap_fixed_base<_AP_W2, _AP_I2, false, _AP_Q2, _AP_O2, _AP_N2>)op) { + } + + template + INLINE ap_uint( + const volatile ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op) + : Base((ap_fixed_base<_AP_W2, _AP_I2, true, _AP_Q2, _AP_O2, _AP_N2>)op) {} + + template + INLINE ap_uint( + const volatile ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op) + : Base((ap_fixed_base<_AP_W2, _AP_I2, false, _AP_Q2, _AP_O2, _AP_N2>)op) { + } + + template + INLINE ap_uint(const ap_int_base<_AP_W2, _AP_S2>& op) { + Base::V = op.V; + } + + template + INLINE ap_uint( + const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) + : Base(op) {} + + template + INLINE ap_uint( + const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) + : Base(op) {} + + template + INLINE ap_uint( + const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) + : Base(op) {} + +#define CTOR(TYPE) \ + INLINE ap_uint(TYPE val) { Base::V = val; } + CTOR(bool) + CTOR(char) + CTOR(signed char) + CTOR(unsigned char) + CTOR(short) + CTOR(unsigned short) + CTOR(int) + CTOR(unsigned int) + CTOR(long) + CTOR(unsigned long) + CTOR(ap_slong) + CTOR(ap_ulong) +#undef CTOR + ap_uint(double val) : Base(val) {} + ap_uint(float val) : Base(val) {} +#if _AP_ENABLE_HALF_ == 1 + ap_uint(half val) : Base(val) {} +#endif + + // ap_int_base will guess radix if radix is not provided. + INLINE ap_uint(const char* s) : Base(s) {} + + INLINE ap_uint(const char* s, signed char rd) : Base(s, rd) {} + + // Assignment + /* XXX ctor will be used when right is not of proper type. */ + + INLINE ap_uint& operator=(const ap_uint<_AP_W>& op2) { + Base::V = op2.V; + return *this; + } + + /* cannot bind volatile reference to non-volatile type. */ + INLINE ap_uint& operator=(const volatile ap_uint<_AP_W>& op2) { + Base::V = op2.V; + return *this; + } + + /* cannot return volatile *this. */ + INLINE void operator=(const ap_uint<_AP_W>& op2) volatile { Base::V = op2.V; } + + INLINE void operator=(const volatile ap_uint<_AP_W>& op2) volatile { + Base::V = op2.V; + } + +}; // struct ap_uint. + +#define ap_bigint ap_int +#define ap_biguint ap_uint + +#if !defined(__SYNTHESIS__) && (defined(SYSTEMC_H) || defined(SYSTEMC_INCLUDED)) +// XXX sc_trace overload for ap_fixed is already included in +// "ap_sysc/ap_sc_extras.h", so do not define in synthesis. +template +INLINE void sc_trace(sc_core::sc_trace_file* tf, const ap_int<_AP_W>& op, + const std::string& name) { + if (tf) tf->trace(sc_dt::sc_lv<_AP_W>(op.to_string(2).c_str()), name); +} + +template +INLINE void sc_trace(sc_core::sc_trace_file* tf, const ap_uint<_AP_W>& op, + const std::string& name) { + if (tf) tf->trace(sc_dt::sc_lv<_AP_W>(op.to_string(2).c_str()), name); +} +#endif // System C sim + +#include + +#endif // ifndef __AP_INT_H__ else + +// FIXME user should include ap_fixed.h when using ap_fixed. +// to avoid circular inclusion, must check whether this is required by +// ap_fixed.h +#ifndef __AP_FIXED_H__ +#include +#endif + +// -*- cpp -*- diff --git a/firmware/ap_types/ap_int_base.h b/firmware/ap_types/ap_int_base.h new file mode 100644 index 0000000000000000000000000000000000000000..091552a88186d221c87d871200d8bd85339145f6 --- /dev/null +++ b/firmware/ap_types/ap_int_base.h @@ -0,0 +1,1885 @@ +/* + * Copyright 2011-2019 Xilinx, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __AP_INT_BASE_H__ +#define __AP_INT_BASE_H__ + +#ifndef __AP_INT_H__ +#error "Only ap_fixed.h and ap_int.h can be included directly in user code." +#endif + +#ifndef __cplusplus +#error "C++ is required to include this header file" +#else + +#include +#ifndef __SYNTHESIS__ +#if _AP_ENABLE_HALF_ == 1 +#include +#endif +#include +#include +#endif + +/* ---------------------------------------------------------------- + * ap_int_base: AutoPilot integer/Arbitrary precision integer. + * ---------------------------------------------------------------- + */ + +/* helper trait. Selecting the smallest C type that can hold the value, + * return 64 bit C type if not possible. + */ +template +struct retval; + +// at least 64 bit +template +struct retval<_AP_N, true> { + typedef ap_slong Type; +}; + +template +struct retval<_AP_N, false> { + typedef ap_ulong Type; +}; + +// at least 8 bit +template <> +struct retval<1, true> { + typedef signed char Type; +}; + +template <> +struct retval<1, false> { + typedef unsigned char Type; +}; + +// at least 16 bit +template <> +struct retval<2, true> { + typedef short Type; +}; + +template <> +struct retval<2, false> { + typedef unsigned short Type; +}; + +// at least 32 bit +template <> +struct retval<3, true> { + typedef long Type; +}; + +template <> +struct retval<3, false> { + typedef unsigned long Type; +}; + +template <> +struct retval<4, true> { + typedef long Type; +}; + +template <> +struct retval<4, false> { + typedef unsigned long Type; +}; + +// trait for letting base class to return derived class. +// Notice that derived class template is incomplete, and we cannot use +// the member of the derived class. +template +struct _ap_int_factory; +template +struct _ap_int_factory<_AP_W2,true> { typedef ap_int<_AP_W2> type; }; +template +struct _ap_int_factory<_AP_W2,false> { typedef ap_uint<_AP_W2> type; }; + +template +struct ap_int_base : public _AP_ROOT_TYPE<_AP_W, _AP_S> { + public: + typedef _AP_ROOT_TYPE<_AP_W, _AP_S> Base; + + /* ap_int_base<_AP_W, _AP_S, true> + * typedef typename retval<(_AP_W + 7) / 8, _AP_S>::Type RetType; + * + * ap_int_base<_AP_W, _AP_S, false> + * typedef typename retval<8, _AP_S>::Type RetType; + */ + typedef typename retval::Type RetType; + + static const int width = _AP_W; + + template + struct RType { + enum { + mult_w = _AP_W + _AP_W2, + mult_s = _AP_S || _AP_S2, + plus_w = + AP_MAX(_AP_W + (_AP_S2 && !_AP_S), _AP_W2 + (_AP_S && !_AP_S2)) + 1, + plus_s = _AP_S || _AP_S2, + minus_w = + AP_MAX(_AP_W + (_AP_S2 && !_AP_S), _AP_W2 + (_AP_S && !_AP_S2)) + 1, + minus_s = true, + div_w = _AP_W + _AP_S2, + div_s = _AP_S || _AP_S2, + mod_w = AP_MIN(_AP_W, _AP_W2 + (!_AP_S2 && _AP_S)), + mod_s = _AP_S, + logic_w = AP_MAX(_AP_W + (_AP_S2 && !_AP_S), _AP_W2 + (_AP_S && !_AP_S2)), + logic_s = _AP_S || _AP_S2 + }; + + + typedef ap_int_base mult_base; + typedef ap_int_base plus_base; + typedef ap_int_base minus_base; + typedef ap_int_base logic_base; + typedef ap_int_base div_base; + typedef ap_int_base mod_base; + typedef ap_int_base<_AP_W, _AP_S> arg1_base; + + typedef typename _ap_int_factory::type mult; + typedef typename _ap_int_factory::type plus; + typedef typename _ap_int_factory::type minus; + typedef typename _ap_int_factory::type logic; + typedef typename _ap_int_factory::type div; + typedef typename _ap_int_factory::type mod; + typedef typename _ap_int_factory<_AP_W, _AP_S>::type arg1; + typedef bool reduce; + }; + + /* Constructors. + * ---------------------------------------------------------------- + */ + /// default ctor + INLINE ap_int_base() { + /* + #ifdef __SC_COMPATIBLE__ + Base::V = 0; + #endif + */ + } + + /// copy ctor + template + INLINE ap_int_base(const ap_int_base<_AP_W2, _AP_S2>& op) { + Base::V = op.V; + } + + /// volatile copy ctor + template + INLINE ap_int_base(const volatile ap_int_base<_AP_W2, _AP_S2>& op) { + Base::V = op.V; + } + +// XXX C++11 feature. +// The explicit specifier specifies that a constructor or conversion function +// (since C++11) doesn't allow implicit conversions or copy-initialization. +// ap_int_base x = 1; +// ap_int_base foo() { return 1; } +// but allows +// ap_int_base x(1); +// ap_int_base y {1}; + +/// from all c types. +#define CTOR_FROM_INT(Type, Size, Signed) \ + INLINE ap_int_base(const Type op) { Base::V = op; } + + CTOR_FROM_INT(bool, 1, false) + CTOR_FROM_INT(char, 8, CHAR_IS_SIGNED) + CTOR_FROM_INT(signed char, 8, true) + CTOR_FROM_INT(unsigned char, 8, false) + CTOR_FROM_INT(short, _AP_SIZE_short, true) + CTOR_FROM_INT(unsigned short, _AP_SIZE_short, false) + CTOR_FROM_INT(int, _AP_SIZE_int, true) + CTOR_FROM_INT(unsigned int, _AP_SIZE_int, false) + CTOR_FROM_INT(long, _AP_SIZE_long, true) + CTOR_FROM_INT(unsigned long, _AP_SIZE_long, false) + CTOR_FROM_INT(ap_slong, _AP_SIZE_ap_slong, true) + CTOR_FROM_INT(ap_ulong, _AP_SIZE_ap_slong, false) +#undef CTOR_FROM_INT + +#if _AP_ENABLE_HALF_ == 1 + /// ctor from half. + // TODO optimize + INLINE ap_int_base(half op) { + ap_int_base<_AP_W, _AP_S> t((float)op); + Base::V = t.V; + } +#endif + + /// ctor from float. + INLINE ap_int_base(float op) { + const int BITS = FLOAT_MAN + FLOAT_EXP + 1; + ap_int_base reg; + reg.V = floatToRawBits(op); + bool is_neg = _AP_ROOT_op_get_bit(reg.V, BITS - 1); + + ap_int_base exp = 0; + exp.V = _AP_ROOT_op_get_range(reg.V, FLOAT_MAN, BITS - 2); + exp = exp - FLOAT_BIAS; + + ap_int_base man; + man.V = _AP_ROOT_op_get_range(reg.V, 0, FLOAT_MAN - 1); + // check for NaN + _AP_WARNING(exp == ((unsigned char)(FLOAT_BIAS + 1)) && man.V != 0, + "assign NaN to ap integer value"); + // set leading 1. + man.V = _AP_ROOT_op_set_bit(man.V, FLOAT_MAN, 1); + //if (is_neg) man = -man; + + if ((reg.V & 0x7ffffffful) == 0) { + Base::V = 0; + } else { + int sh_amt = FLOAT_MAN - exp.V; + if (sh_amt == 0) { + Base::V = man.V; + } else if (sh_amt > 0) { + if (sh_amt < FLOAT_MAN + 2) { + Base::V = man.V >> sh_amt; + } else { + if (is_neg) + Base::V = -1; + else + Base::V = 0; + } + } else { + sh_amt = -sh_amt; + if (sh_amt < _AP_W) { + Base::V = man.V; + Base::V <<= sh_amt; + } else { + Base::V = 0; + } + } + } + if (is_neg) *this = -(*this); + } + + /// ctor from double. + INLINE ap_int_base(double op) { + const int BITS = DOUBLE_MAN + DOUBLE_EXP + 1; + ap_int_base reg; + reg.V = doubleToRawBits(op); + bool is_neg = _AP_ROOT_op_get_bit(reg.V, BITS - 1); + + ap_int_base exp = 0; + exp.V = _AP_ROOT_op_get_range(reg.V, DOUBLE_MAN, BITS - 2); + exp = exp - DOUBLE_BIAS; + + ap_int_base man; + man.V = _AP_ROOT_op_get_range(reg.V, 0, DOUBLE_MAN - 1); + // check for NaN + _AP_WARNING(exp == ((unsigned char)(DOUBLE_BIAS + 1)) && man.V != 0, + "assign NaN to ap integer value"); + // set leading 1. + man.V = _AP_ROOT_op_set_bit(man.V, DOUBLE_MAN, 1); + //if (is_neg) man = -man; + + if ((reg.V & 0x7fffffffffffffffull) == 0) { + Base::V = 0; + } else { + int sh_amt = DOUBLE_MAN - exp.V; + if (sh_amt == 0) { + Base::V = man.V; + } else if (sh_amt > 0) { + if (sh_amt < DOUBLE_MAN + 2) { + Base::V = man.V >> sh_amt; + } else { + if (is_neg) + Base::V = -1; + else + Base::V = 0; + } + } else { + sh_amt = -sh_amt; + if (sh_amt < _AP_W) { + Base::V = man.V; + Base::V <<= sh_amt; + } else { + Base::V = 0; + } + } + } + if (is_neg) *this = -(*this); + } + + /// from higer rank type. + template + INLINE ap_int_base( + const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) { + Base::V = op.to_ap_int_base().V; + } + + template + INLINE ap_int_base(const ap_range_ref<_AP_W2, _AP_S2>& ref) { + Base::V = (ref.get()).V; + } + + template + INLINE ap_int_base(const ap_bit_ref<_AP_W2, _AP_S2>& ref) { + Base::V = ref.operator bool(); + } + + template + INLINE ap_int_base(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& ref) { + const ap_int_base::_AP_WR, + false> + tmp = ref.get(); + Base::V = tmp.V; + } + + /* radix has default value in set */ + +#ifndef __SYNTHESIS__ + INLINE ap_int_base(const char* s, signed char rd = 0) { + if (rd == 0) + rd = guess_radix(s); + unsigned int length = strlen(s); + Base::V.fromString(s, length, rd); + } +#else + // XXX __builtin_bit_from_string(...) requires const C string and radix. + INLINE ap_int_base(const char* s) { + typeof(Base::V) t; + _ssdm_string2bits((void*)(&t), (const char*)(s), 10, _AP_W, _AP_S, + AP_TRN, AP_WRAP, 0, _AP_C99); + Base::V = t; + } + INLINE ap_int_base(const char* s, signed char rd) { + typeof(Base::V) t; + _ssdm_string2bits((void*)(&t), (const char*)(s), rd, _AP_W, _AP_S, + AP_TRN, AP_WRAP, 0, _AP_C99); + Base::V = t; + } +#endif + + template + INLINE ap_int_base( + const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) { + Base::V = (val.get()).V; + } + + template + INLINE ap_int_base( + const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) { + Base::V = val.operator bool(); + } + + INLINE ap_int_base read() volatile { + /*AP_DEBUG(printf("call read %d\n", Base::V););*/ + ap_int_base ret; + ret.V = Base::V; + return ret; + } + + INLINE void write(const ap_int_base<_AP_W, _AP_S>& op2) volatile { + /*AP_DEBUG(printf("call write %d\n", op2.V););*/ + Base::V = op2.V; + } + + /* Another form of "write".*/ + template + INLINE void operator=( + const volatile ap_int_base<_AP_W2, _AP_S2>& op2) volatile { + Base::V = op2.V; + } + + INLINE void operator=( + const volatile ap_int_base<_AP_W, _AP_S>& op2) volatile { + Base::V = op2.V; + } + + template + INLINE void operator=(const ap_int_base<_AP_W2, _AP_S2>& op2) volatile { + Base::V = op2.V; + } + + INLINE void operator=(const ap_int_base<_AP_W, _AP_S>& op2) volatile { + Base::V = op2.V; + } + + template + INLINE ap_int_base& operator=( + const volatile ap_int_base<_AP_W2, _AP_S2>& op2) { + Base::V = op2.V; + return *this; + } + + template + INLINE ap_int_base& operator=(const ap_int_base<_AP_W2, _AP_S2>& op2) { + Base::V = op2.V; + return *this; + } + + INLINE ap_int_base& operator=(const volatile ap_int_base<_AP_W, _AP_S>& op2) { + Base::V = op2.V; + return *this; + } + + INLINE ap_int_base& operator=(const ap_int_base<_AP_W, _AP_S>& op2) { + Base::V = op2.V; + return *this; + } + + +#define ASSIGN_OP_FROM_INT(Type, Size, Signed) \ + INLINE ap_int_base& operator=(Type op) { \ + Base::V = op; \ + return *this; \ + } + + ASSIGN_OP_FROM_INT(bool, 1, false) + ASSIGN_OP_FROM_INT(char, 8, CHAR_IS_SIGNED) + ASSIGN_OP_FROM_INT(signed char, 8, true) + ASSIGN_OP_FROM_INT(unsigned char, 8, false) + ASSIGN_OP_FROM_INT(short, _AP_SIZE_short, true) + ASSIGN_OP_FROM_INT(unsigned short, _AP_SIZE_short, false) + ASSIGN_OP_FROM_INT(int, _AP_SIZE_int, true) + ASSIGN_OP_FROM_INT(unsigned int, _AP_SIZE_int, false) + ASSIGN_OP_FROM_INT(long, _AP_SIZE_long, true) + ASSIGN_OP_FROM_INT(unsigned long, _AP_SIZE_long, false) + ASSIGN_OP_FROM_INT(ap_slong, _AP_SIZE_ap_slong, true) + ASSIGN_OP_FROM_INT(ap_ulong, _AP_SIZE_ap_slong, false) + +#undef ASSIGN_OP_FROM_INT + + template + INLINE ap_int_base& operator=(const ap_bit_ref<_AP_W2, _AP_S2>& op2) { + Base::V = (bool)op2; + return *this; + } + + template + INLINE ap_int_base& operator=(const ap_range_ref<_AP_W2, _AP_S2>& op2) { + Base::V = (ap_int_base<_AP_W2, false>(op2)).V; + return *this; + } + + template + INLINE ap_int_base& operator=( + const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& op2) { + Base::V = op2.get().V; + return *this; + } + + template + INLINE ap_int_base& operator=( + const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) { + Base::V = op.to_ap_int_base().V; + return *this; + } + + template + INLINE ap_int_base& operator=( + const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) { + Base::V = (bool)op; + return *this; + } + + template + INLINE ap_int_base& operator=( + const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) { + Base::V = ((const ap_int_base<_AP_W2, false>)(op)).V; + return *this; + } + + // FIXME: UG902 has clearly required user to use to_int() to convert to built-in + // types, but this implicit conversion is relied on in hls_cordic.h and hls_rsr.h. + // For example: + // int d_exp = fps_x.exp - fps_y.exp; + INLINE operator RetType() const { return (RetType)(Base::V); } + + /* Explicit conversions to C types. + * ---------------------------------------------------------------- + */ + INLINE bool to_bool() const { return (bool)(Base::V); } + INLINE char to_char() const { return (char)(Base::V); } + INLINE signed char to_schar() const { return (signed char)(Base::V); } + INLINE unsigned char to_uchar() const { return (unsigned char)(Base::V); } + INLINE short to_short() const { return (short)(Base::V); } + INLINE unsigned short to_ushort() const { return (unsigned short)(Base::V); } + INLINE int to_int() const { return (int)(Base::V); } + INLINE unsigned to_uint() const { return (unsigned)(Base::V); } + INLINE long to_long() const { return (long)(Base::V); } + INLINE unsigned long to_ulong() const { return (unsigned long)(Base::V); } + INLINE ap_slong to_int64() const { return (ap_slong)(Base::V); } + INLINE ap_ulong to_uint64() const { return (ap_ulong)(Base::V); } + INLINE float to_float() const { return (float)(Base::V); } + INLINE double to_double() const { return (double)(Base::V); } + + // TODO decide if user-defined conversion should be provided. +#if 0 + INLINE operator char() const { return (char)(Base::V); } + INLINE operator signed char() const { return (signed char)(Base::V); } + INLINE operator unsigned char() const { return (unsigned char)(Base::V); } + INLINE operator short() const { return (short)(Base::V); } + INLINE operator unsigned short() const { return (unsigned short)(Base::V); } + INLINE operator int() const { return (int)(Base::V); } + INLINE operator unsigned int () const { return (unsigned)(Base::V); } + INLINE operator long () const { return (long)(Base::V); } + INLINE operator unsigned long () const { return (unsigned long)(Base::V); } + INLINE operator ap_slong () { return (ap_slong)(Base::V); } + INLINE operator ap_ulong () { return (ap_ulong)(Base::V); } +#endif + + /* Helper methods. + ---------------------------------------------------------------- + */ + /* we cannot call a non-volatile function on a volatile instance. + * but calling a volatile function is ok. + * XXX deleted non-volatile version. + */ + INLINE int length() const volatile { return _AP_W; } + + /*Return true if the value of ap_int_base instance is zero*/ + INLINE bool iszero() const { return Base::V == 0; } + + /*Return true if the value of ap_int_base instance is zero*/ + INLINE bool is_zero() const { return Base::V == 0; } + + /* x < 0 */ + INLINE bool sign() const { + if (_AP_S && + _AP_ROOT_op_get_bit(Base::V, _AP_W - 1)) + return true; + else + return false; + } + + /* x[i] = 0 */ + INLINE void clear(int i) { + AP_ASSERT(i >= 0 && i < _AP_W, "position out of range"); + Base::V = _AP_ROOT_op_set_bit(Base::V, i, 0); + } + + /* x[i] = !x[i]*/ + INLINE void invert(int i) { + AP_ASSERT(i >= 0 && i < _AP_W, "position out of range"); + bool val = _AP_ROOT_op_get_bit(Base::V, i); + if (val) + Base::V = _AP_ROOT_op_set_bit(Base::V, i, 0); + else + Base::V = _AP_ROOT_op_set_bit(Base::V, i, 1); + } + + INLINE bool test(int i) const { + AP_ASSERT(i >= 0 && i < _AP_W, "position out of range"); + return _AP_ROOT_op_get_bit(Base::V, i); + } + + // Get self. For ap_concat_ref expansion. + INLINE ap_int_base& get() { return *this; } + + // Set the ith bit into 1 + INLINE void set(int i) { + AP_ASSERT(i >= 0 && i < _AP_W, "position out of range"); + Base::V = _AP_ROOT_op_set_bit(Base::V, i, 1); + } + + // Set the ith bit into v + INLINE void set(int i, bool v) { + AP_ASSERT(i >= 0 && i < _AP_W, "position out of range"); + Base::V = _AP_ROOT_op_set_bit(Base::V, i, v); + } + + // This is used for sc_lv and sc_bv, which is implemented by sc_uint + // Rotate an ap_int_base object n places to the left + INLINE ap_int_base& lrotate(int n) { + AP_ASSERT(n >= 0 && n < _AP_W, "shift value out of range"); + // TODO unify this. +#ifdef __SYNTHESIS__ + typeof(Base::V) l_p = Base::V << n; + typeof(Base::V) r_p = Base::V >> (_AP_W - n); + Base::V = l_p | r_p; +#else + Base::V.lrotate(n); +#endif + return *this; + } + + // This is used for sc_lv and sc_bv, which is implemented by sc_uint + // Rotate an ap_int_base object n places to the right + INLINE ap_int_base& rrotate(int n) { + AP_ASSERT(n >= 0 && n < _AP_W, "shift value out of range"); + // TODO unify this. +#ifdef __SYNTHESIS__ + typeof(Base::V) l_p = Base::V << (_AP_W - n); + typeof(Base::V) r_p = Base::V >> n; + Base::V = l_p | r_p; +#else + Base::V.rrotate(n); +#endif + return *this; + } + + // Reverse the contents of ap_int_base instance. + // I.e. LSB becomes MSB and vise versa. + INLINE ap_int_base& reverse() { + Base::V = _AP_ROOT_op_get_range(Base::V, _AP_W - 1, 0); + return *this; + } + + // Set the ith bit into v + INLINE void set_bit(int i, bool v) { + Base::V = _AP_ROOT_op_set_bit(Base::V, i, v); + } + + // Get the value of ith bit + INLINE bool get_bit(int i) const { + return (bool)_AP_ROOT_op_get_bit(Base::V, i); + } + + // complements every bit + INLINE void b_not() { Base::V = ~Base::V; } + +#define OP_ASSIGN_AP(Sym) \ + template \ + INLINE ap_int_base& operator Sym(const ap_int_base<_AP_W2, _AP_S2>& op2) { \ + Base::V Sym op2.V; \ + return *this; \ + } + + /* Arithmetic assign. + * ---------------------------------------------------------------- + */ + OP_ASSIGN_AP(*=) + OP_ASSIGN_AP(+=) + OP_ASSIGN_AP(-=) + OP_ASSIGN_AP(/=) + OP_ASSIGN_AP(%=) +#undef OP_ASSIGN_AP + + /* Bitwise assign: and, or, xor. + * ---------------------------------------------------------------- + */ +#define OP_ASSIGN_AP_CHK(Sym) \ + template \ + INLINE ap_int_base& operator Sym(const ap_int_base<_AP_W2, _AP_S2>& op2) { \ + _AP_WARNING((_AP_W != _AP_W2), \ + "Bitsize mismatch for ap_[u]int" #Sym "ap_[u]int."); \ + Base::V Sym op2.V; \ + return *this; \ + } + OP_ASSIGN_AP_CHK(&=) + OP_ASSIGN_AP_CHK(|=) + OP_ASSIGN_AP_CHK(^=) +#undef OP_ASSIGN_AP_CHK + + /* Prefix increment, decrement. + * ---------------------------------------------------------------- + */ + INLINE ap_int_base& operator++() { + operator+=((ap_int_base<1, false>)1); + return *this; + } + INLINE ap_int_base& operator--() { + operator-=((ap_int_base<1, false>)1); + return *this; + } + + /* Postfix increment, decrement + * ---------------------------------------------------------------- + */ + INLINE const typename RType<_AP_W,_AP_S>::arg1 operator++(int) { + ap_int_base t = *this; + operator+=((ap_int_base<1, false>)1); + return t; + } + INLINE const typename RType<_AP_W,_AP_S>::arg1 operator--(int) { + ap_int_base t = *this; + operator-=((ap_int_base<1, false>)1); + return t; + } + + /* Unary arithmetic. + * ---------------------------------------------------------------- + */ + INLINE typename RType<_AP_W,_AP_S>::arg1 operator+() const { return *this; } + + // TODO used to be W>64 only... need check. + INLINE typename RType<1, false>::minus operator-() const { + return ap_int_base<1, false>(0) - *this; + } + + /* Not (!) + * ---------------------------------------------------------------- + */ + INLINE bool operator!() const { return Base::V == 0; } + + /* Bitwise (arithmetic) unary: complement + ---------------------------------------------------------------- + */ + // XXX different from Mentor's ac_int! + INLINE typename RType<_AP_W,_AP_S>::arg1 operator~() const { + ap_int_base<_AP_W, _AP_S> r; + r.V = ~Base::V; + return r; + } + + /* Shift (result constrained by left operand). + * ---------------------------------------------------------------- + */ + template + INLINE typename RType<_AP_W,_AP_S>::arg1 operator<<(const ap_int_base<_AP_W2, true>& op2) const { + bool isNeg = _AP_ROOT_op_get_bit(op2.V, _AP_W2 - 1); + ap_int_base<_AP_W2, false> sh = op2; + if (isNeg) { + sh = -op2; + return operator>>(sh); + } else + return operator<<(sh); + } + + template + INLINE typename RType<_AP_W,_AP_S>::arg1 operator<<(const ap_int_base<_AP_W2, false>& op2) const { + ap_int_base r; + r.V = Base::V << op2.to_uint(); + return r; + } + + template + INLINE typename RType<_AP_W,_AP_S>::arg1 operator>>(const ap_int_base<_AP_W2, true>& op2) const { + bool isNeg = _AP_ROOT_op_get_bit(op2.V, _AP_W2 - 1); + ap_int_base<_AP_W2, false> sh = op2; + if (isNeg) { + sh = -op2; + return operator<<(sh); + } + return operator>>(sh); + } + + template + INLINE typename RType<_AP_W,_AP_S>::arg1 operator>>(const ap_int_base<_AP_W2, false>& op2) const { + ap_int_base r; + r.V = Base::V >> op2.to_uint(); + return r; + } + + // FIXME we standalone operator>> for ap_int_base and ap_range_ref. +#if 0 + template + INLINE ap_int_base operator<<(const ap_range_ref<_AP_W2, _AP_S2>& op2) const { + return *this << (op2.operator ap_int_base<_AP_W2, false>()); + } + + template + INLINE ap_int_base operator>>(const ap_range_ref<_AP_W2, _AP_S2>& op2) const { + return *this >> (op2.operator ap_int_base<_AP_W2, false>()); + } +#endif + + /* Shift assign + * ---------------------------------------------------------------- + */ + template + INLINE ap_int_base& operator<<=(const ap_int_base<_AP_W2, true>& op2) { + bool isNeg = _AP_ROOT_op_get_bit(op2.V, _AP_W2 - 1); + ap_int_base<_AP_W2, false> sh = op2; + if (isNeg) { + sh = -op2; + return operator>>=(sh); + } else + return operator<<=(sh); + } + + template + INLINE ap_int_base& operator<<=(const ap_int_base<_AP_W2, false>& op2) { + Base::V <<= op2.to_uint(); + return *this; + } + + template + INLINE ap_int_base& operator>>=(const ap_int_base<_AP_W2, true>& op2) { + bool isNeg = _AP_ROOT_op_get_bit(op2.V, _AP_W2 - 1); + ap_int_base<_AP_W2, false> sh = op2; + if (isNeg) { + sh = -op2; + return operator<<=(sh); + } + return operator>>=(sh); + } + + template + INLINE ap_int_base& operator>>=(const ap_int_base<_AP_W2, false>& op2) { + Base::V >>= op2.to_uint(); + return *this; + } + + // FIXME we standalone operator>> for ap_int_base and ap_range_ref. +#if 0 + template + INLINE ap_int_base& operator<<=(const ap_range_ref<_AP_W2, _AP_S2>& op2) { + return *this <<= (op2.operator ap_int_base<_AP_W2, false>()); + } + template + INLINE ap_int_base& operator>>=(const ap_range_ref<_AP_W2, _AP_S2>& op2) { + return *this >>= (op2.operator ap_int_base<_AP_W2, false>()); + } +#endif + + /* Equality and Relational. + * ---------------------------------------------------------------- + */ + template + INLINE bool operator==(const ap_int_base<_AP_W2, _AP_S2>& op2) const { + return Base::V == op2.V; + } + template + INLINE bool operator!=(const ap_int_base<_AP_W2, _AP_S2>& op2) const { + return !(Base::V == op2.V); + } + template + INLINE bool operator<(const ap_int_base<_AP_W2, _AP_S2>& op2) const { + return Base::V < op2.V; + } + template + INLINE bool operator>=(const ap_int_base<_AP_W2, _AP_S2>& op2) const { + return Base::V >= op2.V; + } + template + INLINE bool operator>(const ap_int_base<_AP_W2, _AP_S2>& op2) const { + return Base::V > op2.V; + } + template + INLINE bool operator<=(const ap_int_base<_AP_W2, _AP_S2>& op2) const { + return Base::V <= op2.V; + } + + /* Bit and Part Select + * ---------------------------------------------------------------- + */ + INLINE ap_range_ref<_AP_W, _AP_S> range(int Hi, int Lo) { + _AP_ERROR(Hi >= _AP_W, "Hi(%d)out of bound(%d) in range()", Hi, _AP_W); + _AP_ERROR(Lo >= _AP_W, "Lo(%d)out of bound(%d) in range()", Lo, _AP_W); + return ap_range_ref<_AP_W, _AP_S>(this, Hi, Lo); + } + + // This is a must to strip constness to produce reference type. + INLINE ap_range_ref<_AP_W, _AP_S> range(int Hi, int Lo) const { + _AP_ERROR(Hi >= _AP_W, "Hi(%d)out of bound(%d) in range()", Hi, _AP_W); + _AP_ERROR(Lo >= _AP_W, "Lo(%d)out of bound(%d) in range()", Lo, _AP_W); + return ap_range_ref<_AP_W, _AP_S>(const_cast(this), Hi, Lo); + } + + template + INLINE ap_range_ref<_AP_W, _AP_S> range( + const ap_int_base<_AP_W2, _AP_S2>& HiIdx, + const ap_int_base<_AP_W3, _AP_S3>& LoIdx) { + int Hi = HiIdx.to_int(); + int Lo = LoIdx.to_int(); + return this->range(Hi, Lo); + } + + template + INLINE ap_range_ref<_AP_W, _AP_S> range( + const ap_int_base<_AP_W2, _AP_S2>& HiIdx, + const ap_int_base<_AP_W3, _AP_S3>& LoIdx) const { + int Hi = HiIdx.to_int(); + int Lo = LoIdx.to_int(); + return this->range(Hi, Lo); + } + + INLINE ap_range_ref<_AP_W, _AP_S> range() { + return this->range(_AP_W - 1, 0); + } + + INLINE ap_range_ref<_AP_W, _AP_S> range() const { + return this->range(_AP_W - 1, 0); + } + + INLINE ap_range_ref<_AP_W, _AP_S> operator()(int Hi, int Lo) { + return this->range(Hi, Lo); + } + + INLINE ap_range_ref<_AP_W, _AP_S> operator()(int Hi, int Lo) const { + return this->range(Hi, Lo); + } + + template + INLINE ap_range_ref<_AP_W, _AP_S> operator()( + const ap_int_base<_AP_W2, _AP_S2>& HiIdx, + const ap_int_base<_AP_W3, _AP_S3>& LoIdx) { + int Hi = HiIdx.to_int(); + int Lo = LoIdx.to_int(); + return this->range(Hi, Lo); + } + + template + INLINE ap_range_ref<_AP_W, _AP_S> operator()( + const ap_int_base<_AP_W2, _AP_S2>& HiIdx, + const ap_int_base<_AP_W3, _AP_S3>& LoIdx) const { + int Hi = HiIdx.to_int(); + int Lo = LoIdx.to_int(); + return this->range(Hi, Lo); + } + +#if 0 + template + INLINE ap_int_base slice() const { + AP_ASSERT(Hi >= Lo && Hi < _AP_W && Lo < _AP_W, "Out of bounds in slice()"); + ap_int_base tmp ; + tmp.V = _AP_ROOT_op_get_range(Base::V, Lo, Hi); + return tmp; + } + + INLINE ap_bit_ref<_AP_W,_AP_S> operator [] ( unsigned int uindex) { + AP_ASSERT(uindex < _AP_W, "Attempting to read bit beyond MSB"); + ap_bit_ref<_AP_W,_AP_S> bvh( this, uindex ); + return bvh; + } +#endif + + INLINE ap_bit_ref<_AP_W, _AP_S> operator[](int index) { + AP_ASSERT(index >= 0, "Attempting to read bit with negative index"); + AP_ASSERT(index < _AP_W, "Attempting to read bit beyond MSB"); + ap_bit_ref<_AP_W, _AP_S> bvh(this, index); + return bvh; + } + + template + INLINE ap_bit_ref<_AP_W, _AP_S> operator[]( + const ap_int_base<_AP_W2, _AP_S2>& index) { + AP_ASSERT(index >= 0, "Attempting to read bit with negative index"); + AP_ASSERT(index < _AP_W, "Attempting to read bit beyond MSB"); + ap_bit_ref<_AP_W, _AP_S> bvh(this, index.to_int()); + return bvh; + } + + INLINE bool operator[](int index) const { + AP_ASSERT(index >= 0, "Attempting to read bit with negative index"); + AP_ASSERT(index < _AP_W, "Attempting to read bit beyond MSB"); + ap_bit_ref<_AP_W, _AP_S> br(this, index); + return br.to_bool(); + } + template + INLINE bool operator[](const ap_int_base<_AP_W2, _AP_S2>& index) const { + AP_ASSERT(index < _AP_W, "Attempting to read bit beyond MSB"); + ap_bit_ref<_AP_W, _AP_S> br(this, index.to_int()); + return br.to_bool(); + } + + INLINE ap_bit_ref<_AP_W, _AP_S> bit(int index) { + AP_ASSERT(index >= 0, "Attempting to read bit with negative index"); + AP_ASSERT(index < _AP_W, "Attempting to read bit beyond MSB"); + ap_bit_ref<_AP_W, _AP_S> bvh(this, index); + return bvh; + } + template + INLINE ap_bit_ref<_AP_W, _AP_S> bit( + const ap_int_base<_AP_W2, _AP_S2>& index) { + AP_ASSERT(index >= 0, "Attempting to read bit with negative index"); + AP_ASSERT(index < _AP_W, "Attempting to read bit beyond MSB"); + ap_bit_ref<_AP_W, _AP_S> bvh(this, index.to_int()); + return bvh; + } + + INLINE bool bit(int index) const { + AP_ASSERT(index >= 0, "Attempting to read bit with negative index"); + AP_ASSERT(index < _AP_W, "Attempting to read bit beyond MSB"); + ap_bit_ref<_AP_W, _AP_S> br(this, index); + return br.to_bool(); + } + + template + INLINE bool bit(const ap_int_base<_AP_W2, _AP_S2>& index) const { + return bit(index.to_int()); + } + +#if 0 + template + INLINE bool operator[](_AP_T index) const { + AP_ASSERT(index < _AP_W, "Attempting to read bit beyond MSB"); + ap_bit_ref<_AP_W,_AP_S> br = operator[](index); + return br.to_bool(); + } +#endif + + // Count the number of zeros from the most significant bit + // to the first one bit. + INLINE int countLeadingZeros() { +#ifdef __SYNTHESIS__ + if (_AP_W <= 32) { + ap_int_base<32, false> t(-1UL), x; + x.V = _AP_ROOT_op_get_range(this->V, _AP_W - 1, 0); // reverse + t.V = _AP_ROOT_op_set_range(t.V, 0, _AP_W - 1, x.V); + return __builtin_ctz(t.V); // count trailing zeros. + } else if (_AP_W <= 64) { + ap_int_base<64, false> t(-1ULL); + ap_int_base<64, false> x; + x.V = _AP_ROOT_op_get_range(this->V, _AP_W - 1, 0); // reverse + t.V = _AP_ROOT_op_set_range(t.V, 0, _AP_W - 1, x.V); + return __builtin_ctzll(t.V); // count trailing zeros. + } else { + enum { __N = (_AP_W + 63) / 64 }; + int NZeros = 0; + int i = 0; + bool hitNonZero = false; + for (i = 0; i < __N - 1; ++i) { + ap_int_base<64, false> t; + t.V = _AP_ROOT_op_get_range(this->V, _AP_W - i * 64 - 64, _AP_W - i * 64 - 1); + NZeros += hitNonZero ? 0 : __builtin_clzll(t.V); // count leading zeros. + hitNonZero |= (t.V != 0); + } + if (!hitNonZero) { + ap_int_base<64, false> t(-1ULL); + enum { REST = (_AP_W - 1) % 64 }; + ap_int_base<64, false> x; + x.V = _AP_ROOT_op_get_range(this->V, 0, REST); + t.V = _AP_ROOT_op_set_range(t.V, 63 - REST, 63, x.V); + NZeros += __builtin_clzll(t.V); + } + return NZeros; + } +#else + return (Base::V).countLeadingZeros(); +#endif + } // countLeadingZeros + + template + INLINE ap_concat_ref<_AP_W, ap_int_base, _AP_W2, ap_int_base<_AP_W2, _AP_S2> > + concat(const ap_int_base<_AP_W2, _AP_S2>& a2) const { + return ap_concat_ref<_AP_W, ap_int_base, _AP_W2, + ap_int_base<_AP_W2, _AP_S2> >( + const_cast&>(*this), + const_cast&>(a2)); + } + + template + INLINE ap_concat_ref<_AP_W, ap_int_base, _AP_W2, ap_int_base<_AP_W2, _AP_S2> > + concat(ap_int_base<_AP_W2, _AP_S2>& a2) { + return ap_concat_ref<_AP_W, ap_int_base, _AP_W2, + ap_int_base<_AP_W2, _AP_S2> >(*this, a2); + } + + template + INLINE + ap_concat_ref<_AP_W, ap_int_base, _AP_W2, ap_range_ref<_AP_W2, _AP_S2> > + operator,(const ap_range_ref<_AP_W2, _AP_S2> &a2) const { + return ap_concat_ref<_AP_W, ap_int_base, _AP_W2, + ap_range_ref<_AP_W2, _AP_S2> >( + const_cast&>(*this), + const_cast&>(a2)); + } + + template + INLINE + ap_concat_ref<_AP_W, ap_int_base, _AP_W2, ap_range_ref<_AP_W2, _AP_S2> > + operator,(ap_range_ref<_AP_W2, _AP_S2> &a2) { + return ap_concat_ref<_AP_W, ap_int_base, _AP_W2, + ap_range_ref<_AP_W2, _AP_S2> >(*this, a2); + } + + template + INLINE ap_concat_ref<_AP_W, ap_int_base, _AP_W2, ap_int_base<_AP_W2, _AP_S2> > + operator,(const ap_int_base<_AP_W2, _AP_S2> &a2) { + return ap_concat_ref<_AP_W, ap_int_base, _AP_W2, + ap_int_base<_AP_W2, _AP_S2> >( + *this, const_cast&>(a2)); + } + + template + INLINE ap_concat_ref<_AP_W, ap_int_base, _AP_W2, ap_int_base<_AP_W2, _AP_S2> > + operator,(ap_int_base<_AP_W2, _AP_S2> &a2) const { + return ap_concat_ref<_AP_W, ap_int_base, _AP_W2, + ap_int_base<_AP_W2, _AP_S2> >( + const_cast&>(*this), a2); + } + + template + INLINE ap_concat_ref<_AP_W, ap_int_base, _AP_W2, ap_int_base<_AP_W2, _AP_S2> > + operator,(const ap_int_base<_AP_W2, _AP_S2> &a2) const { + return ap_concat_ref<_AP_W, ap_int_base, _AP_W2, + ap_int_base<_AP_W2, _AP_S2> >( + const_cast&>(*this), + const_cast&>(a2)); + } + + template + INLINE ap_concat_ref<_AP_W, ap_int_base, _AP_W2, ap_int_base<_AP_W2, _AP_S2> > + operator,(ap_int_base<_AP_W2, _AP_S2> &a2) { + return ap_concat_ref<_AP_W, ap_int_base, _AP_W2, + ap_int_base<_AP_W2, _AP_S2> >(*this, a2); + } + + template + INLINE ap_concat_ref<_AP_W, ap_int_base, 1, ap_bit_ref<_AP_W2, _AP_S2> > + operator,(const ap_bit_ref<_AP_W2, _AP_S2> &a2) const { + return ap_concat_ref<_AP_W, ap_int_base, 1, ap_bit_ref<_AP_W2, _AP_S2> >( + const_cast&>(*this), + const_cast&>(a2)); + } + + template + INLINE ap_concat_ref<_AP_W, ap_int_base, 1, ap_bit_ref<_AP_W2, _AP_S2> > + operator,(ap_bit_ref<_AP_W2, _AP_S2> &a2) { + return ap_concat_ref<_AP_W, ap_int_base, 1, ap_bit_ref<_AP_W2, _AP_S2> >( + *this, a2); + } + + template + INLINE ap_concat_ref<_AP_W, ap_int_base, _AP_W2 + _AP_W3, + ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> > + operator,(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &a2) { + return ap_concat_ref<_AP_W, ap_int_base, _AP_W2 + _AP_W3, + ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >( + const_cast&>(*this), + const_cast&>(a2)); + } + + template + INLINE ap_concat_ref<_AP_W, ap_int_base, _AP_W2 + _AP_W3, + ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> > + operator,(ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &a2) { + return ap_concat_ref<_AP_W, ap_int_base, _AP_W2 + _AP_W3, + ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >(*this, + a2); + } + + template + INLINE ap_concat_ref< + _AP_W, ap_int_base, _AP_W2, + af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> > + operator,(const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> + &a2) const { + return ap_concat_ref< + _AP_W, ap_int_base, _AP_W2, + af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >( + const_cast&>(*this), + const_cast< + af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>&>(a2)); + } + + template + INLINE ap_concat_ref< + _AP_W, ap_int_base, _AP_W2, + af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> > + operator,(af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> &a2) { + return ap_concat_ref< + _AP_W, ap_int_base, _AP_W2, + af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this, + a2); + } + + template + INLINE + ap_concat_ref<_AP_W, ap_int_base, 1, + af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> > + operator,(const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> + &a2) const { + return ap_concat_ref< + _AP_W, ap_int_base, 1, + af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >( + const_cast&>(*this), + const_cast&>( + a2)); + } + + template + INLINE + ap_concat_ref<_AP_W, ap_int_base, 1, + af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> > + operator,( + af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> &a2) { + return ap_concat_ref< + _AP_W, ap_int_base, 1, + af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this, a2); + } + + template + INLINE ap_int_base operator&( + const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& a2) { + return *this & a2.get(); + } + + template + INLINE ap_int_base operator|( + const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& a2) { + return *this | a2.get(); + } + + template + INLINE ap_int_base operator^( + const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& a2) { + return *this ^ a2.get(); + } + + template + INLINE void set(const ap_int_base<_AP_W3, false>& val) { + Base::V = val.V; + } + + /* Reduce operations. + * ---------------------------------------------------------------- + */ + // XXX non-const version deleted. + INLINE bool and_reduce() const { return _AP_ROOT_op_reduce(and, Base::V); } + INLINE bool nand_reduce() const { return _AP_ROOT_op_reduce(nand, Base::V); } + INLINE bool or_reduce() const { return _AP_ROOT_op_reduce(or, Base::V); } + INLINE bool nor_reduce() const { return !(_AP_ROOT_op_reduce(or, Base::V)); } + INLINE bool xor_reduce() const { return _AP_ROOT_op_reduce (xor, Base::V); } + INLINE bool xnor_reduce() const { + return !(_AP_ROOT_op_reduce (xor, Base::V)); + } + + /* Output as a string. + * ---------------------------------------------------------------- + */ +#ifndef __SYNTHESIS__ + std::string to_string(signed char rd = 2, bool sign = _AP_S) const { + // XXX in autosim/autowrap.tcl "(${name}).to_string(2).c_str()" is used to + // initialize sc_lv, which seems incapable of handling format "-0b". + if (rd == 2) sign = false; + return (Base::V).to_string(rd, sign); + } +#else + INLINE char* to_string(signed char rd = 2, bool sign = _AP_S) const { + return 0; + } +#endif +}; // struct ap_int_base + +// XXX apcc cannot handle global std::ios_base::Init() brought in by +#ifndef AP_AUTOCC +#ifndef __SYNTHESIS__ +template +INLINE std::ostream& operator<<(std::ostream& os, + const ap_int_base<_AP_W, _AP_S>& x) { + std::ios_base::fmtflags ff = std::cout.flags(); + if (ff & std::cout.hex) { + os << x.to_string(16); // don't print sign + } else if (ff & std::cout.oct) { + os << x.to_string(8); // don't print sign + } else { + os << x.to_string(10); + } + return os; +} +#endif // ifndef __SYNTHESIS__ + +#ifndef __SYNTHESIS__ +template +INLINE std::istream& operator>>(std::istream& in, + ap_int_base<_AP_W, _AP_S>& op) { + std::string str; + in >> str; + const std::ios_base::fmtflags basefield = in.flags() & std::ios_base::basefield; + unsigned radix = (basefield == std::ios_base::dec) ? 0 : ( + (basefield == std::ios_base::oct) ? 8 : ( + (basefield == std::ios_base::hex) ? 16 : 0)); + op = ap_int_base<_AP_W, _AP_S>(str.c_str(), radix); + return in; +} +#endif // ifndef __SYNTHESIS__ +#endif // ifndef AP_AUTOCC + +/* Operators with another ap_int_base. + * ---------------------------------------------------------------- + */ +#define OP_BIN_AP(Sym, Rty) \ + template \ + INLINE \ + typename ap_int_base<_AP_W, _AP_S>::template RType<_AP_W2, _AP_S2>::Rty \ + operator Sym(const ap_int_base<_AP_W, _AP_S>& op, \ + const ap_int_base<_AP_W2, _AP_S2>& op2) { \ + typename ap_int_base<_AP_W, _AP_S>::template RType< \ + _AP_W2, _AP_S2>::Rty##_base lhs(op); \ + typename ap_int_base<_AP_W, _AP_S>::template RType< \ + _AP_W2, _AP_S2>::Rty##_base rhs(op2); \ + typename ap_int_base<_AP_W, _AP_S>::template RType< \ + _AP_W2, _AP_S2>::Rty##_base ret; \ + ret.V = lhs.V Sym rhs.V; \ + return ret; \ + } + +OP_BIN_AP(*, mult) +OP_BIN_AP(+, plus) +OP_BIN_AP(-, minus) +OP_BIN_AP(&, logic) +OP_BIN_AP(|, logic) +OP_BIN_AP(^, logic) + +#define OP_BIN_AP2(Sym, Rty) \ + template \ + INLINE \ + typename ap_int_base<_AP_W, _AP_S>::template RType<_AP_W2, _AP_S2>::Rty \ + operator Sym(const ap_int_base<_AP_W, _AP_S>& op, \ + const ap_int_base<_AP_W2, _AP_S2>& op2) { \ + typename ap_int_base<_AP_W, _AP_S>::template RType< \ + _AP_W2, _AP_S2>::Rty##_base ret; \ + ret.V = op.V Sym op2.V; \ + return ret; \ + } + +OP_BIN_AP2(/, div) +OP_BIN_AP2(%, mod) + +// shift operators are defined inside class. +// compound assignment operators are defined inside class. + +/* Operators with a pointer type. + * ---------------------------------------------------------------- + * char a[100]; + * char* ptr = a; + * ap_int<2> n = 3; + * char* ptr2 = ptr + n*2; + * avoid ambiguous errors. + */ +#define OP_BIN_WITH_PTR(BIN_OP) \ + template \ + INLINE PTR_TYPE* operator BIN_OP(PTR_TYPE* i_op, \ + const ap_int_base<_AP_W, _AP_S>& op) { \ + ap_slong op2 = op.to_int64(); /* Not all implementation */ \ + return i_op BIN_OP op2; \ + } \ + template \ + INLINE PTR_TYPE* operator BIN_OP(const ap_int_base<_AP_W, _AP_S>& op, \ + PTR_TYPE* i_op) { \ + ap_slong op2 = op.to_int64(); /* Not all implementation */ \ + return op2 BIN_OP i_op; \ + } + +OP_BIN_WITH_PTR(+) +OP_BIN_WITH_PTR(-) + +/* Operators with a native floating point types. + * ---------------------------------------------------------------- + */ +// float OP ap_int +// when ap_int's width > 64, then trunc ap_int to ap_int<64> +#define OP_BIN_WITH_FLOAT(BIN_OP, C_TYPE) \ + template \ + INLINE C_TYPE operator BIN_OP(C_TYPE i_op, \ + const ap_int_base<_AP_W, _AP_S>& op) { \ + typename ap_int_base<_AP_W, _AP_S>::RetType op2 = op; \ + return i_op BIN_OP op2; \ + } \ + template \ + INLINE C_TYPE operator BIN_OP(const ap_int_base<_AP_W, _AP_S>& op, \ + C_TYPE i_op) { \ + typename ap_int_base<_AP_W, _AP_S>::RetType op2 = op; \ + return op2 BIN_OP i_op; \ + } + +#define ALL_OP_WITH_FLOAT(C_TYPE) \ + OP_BIN_WITH_FLOAT(*, C_TYPE) \ + OP_BIN_WITH_FLOAT(/, C_TYPE) \ + OP_BIN_WITH_FLOAT(+, C_TYPE) \ + OP_BIN_WITH_FLOAT(-, C_TYPE) + +#if _AP_ENABLE_HALF_ == 1 +ALL_OP_WITH_FLOAT(half) +#endif +ALL_OP_WITH_FLOAT(float) +ALL_OP_WITH_FLOAT(double) + +// TODO no shift? + +/* Operators with a native integral types. + * ---------------------------------------------------------------- + */ +// arithmetic and bitwise operators. +#define OP_BIN_WITH_INT(BIN_OP, C_TYPE, _AP_W2, _AP_S2, RTYPE) \ + template \ + INLINE typename ap_int_base<_AP_W, _AP_S>::template RType<_AP_W2, \ + _AP_S2>::RTYPE \ + operator BIN_OP(C_TYPE i_op, const ap_int_base<_AP_W, _AP_S>& op) { \ + return ap_int_base<_AP_W2, _AP_S2>(i_op) BIN_OP(op); \ + } \ + template \ + INLINE typename ap_int_base<_AP_W, _AP_S>::template RType<_AP_W2, \ + _AP_S2>::RTYPE \ + operator BIN_OP(const ap_int_base<_AP_W, _AP_S>& op, C_TYPE i_op) { \ + return op BIN_OP ap_int_base<_AP_W2, _AP_S2>(i_op); \ + } + +#define ALL_OP_BIN_WITH_INT(C_TYPE, _AP_W2, _AP_S2) \ + OP_BIN_WITH_INT(*, C_TYPE, _AP_W2, _AP_S2, mult) \ + OP_BIN_WITH_INT(+, C_TYPE, _AP_W2, _AP_S2, plus) \ + OP_BIN_WITH_INT(-, C_TYPE, _AP_W2, _AP_S2, minus) \ + OP_BIN_WITH_INT(/, C_TYPE, _AP_W2, _AP_S2, div) \ + OP_BIN_WITH_INT(%, C_TYPE, _AP_W2, _AP_S2, mod) \ + OP_BIN_WITH_INT(&, C_TYPE, _AP_W2, _AP_S2, logic) \ + OP_BIN_WITH_INT(|, C_TYPE, _AP_W2, _AP_S2, logic) \ + OP_BIN_WITH_INT(^, C_TYPE, _AP_W2, _AP_S2, logic) + +ALL_OP_BIN_WITH_INT(bool, 1, false) +ALL_OP_BIN_WITH_INT(char, 8, CHAR_IS_SIGNED) +ALL_OP_BIN_WITH_INT(signed char, 8, true) +ALL_OP_BIN_WITH_INT(unsigned char, 8, false) +ALL_OP_BIN_WITH_INT(short, _AP_SIZE_short, true) +ALL_OP_BIN_WITH_INT(unsigned short, _AP_SIZE_short, false) +ALL_OP_BIN_WITH_INT(int, _AP_SIZE_int, true) +ALL_OP_BIN_WITH_INT(unsigned int, _AP_SIZE_int, false) +ALL_OP_BIN_WITH_INT(long, _AP_SIZE_long, true) +ALL_OP_BIN_WITH_INT(unsigned long, _AP_SIZE_long, false) +ALL_OP_BIN_WITH_INT(ap_slong, _AP_SIZE_ap_slong, true) +ALL_OP_BIN_WITH_INT(ap_ulong, _AP_SIZE_ap_slong, false) + +#undef OP_BIN_WITH_INT +#undef ALL_OP_BIN_WITH_INT + +// shift operators. +#define ALL_OP_SHIFT_WITH_INT(C_TYPE, _AP_W2, _AP_S2) \ + template \ + INLINE typename ap_int_base<_AP_W, _AP_S>::template RType<_AP_W,_AP_S>::arg1 operator<<( \ + const ap_int_base<_AP_W, _AP_S>& op, C_TYPE op2) { \ + ap_int_base<_AP_W, _AP_S> r; \ + if (_AP_S2) \ + r.V = op2 >= 0 ? (op.V << op2) : (op.V >> (-op2)); \ + else \ + r.V = op.V << op2; \ + return r; \ + } \ + template \ + INLINE typename ap_int_base<_AP_W, _AP_S>::template RType<_AP_W,_AP_S>::arg1 operator>>( \ + const ap_int_base<_AP_W, _AP_S>& op, C_TYPE op2) { \ + ap_int_base<_AP_W, _AP_S> r; \ + if (_AP_S2) \ + r.V = op2 >= 0 ? (op.V >> op2) : (op.V << (-op2)); \ + else \ + r.V = op.V >> op2; \ + return r; \ + } + +ALL_OP_SHIFT_WITH_INT(char, 8, CHAR_IS_SIGNED) +ALL_OP_SHIFT_WITH_INT(signed char, 8, true) +ALL_OP_SHIFT_WITH_INT(short, _AP_SIZE_short, true) +ALL_OP_SHIFT_WITH_INT(int, _AP_SIZE_int, true) +ALL_OP_SHIFT_WITH_INT(long, _AP_SIZE_long, true) +ALL_OP_SHIFT_WITH_INT(ap_slong, _AP_SIZE_ap_slong, true) + +#undef ALL_OP_SHIFT_WITH_INT + +#define ALL_OP_SHIFT_WITH_INT(C_TYPE, _AP_W2, _AP_S2) \ + template \ + INLINE typename ap_int_base<_AP_W, _AP_S>::template RType<_AP_W,_AP_S>::arg1 operator<<( \ + const ap_int_base<_AP_W, _AP_S>& op, C_TYPE op2) { \ + ap_int_base<_AP_W, _AP_S> r; \ + r.V = op.V << op2; \ + return r; \ + } \ + template \ + INLINE typename ap_int_base<_AP_W, _AP_S>::template RType<_AP_W,_AP_S>::arg1 operator>>( \ + const ap_int_base<_AP_W, _AP_S>& op, C_TYPE op2) { \ + ap_int_base<_AP_W, _AP_S> r; \ + r.V = op.V >> op2; \ + return r; \ + } +ALL_OP_SHIFT_WITH_INT(bool, 1, false) +ALL_OP_SHIFT_WITH_INT(unsigned char, 8, false) +ALL_OP_SHIFT_WITH_INT(unsigned short, _AP_SIZE_short, false) +ALL_OP_SHIFT_WITH_INT(unsigned int, _AP_SIZE_int, false) +ALL_OP_SHIFT_WITH_INT(unsigned long, _AP_SIZE_long, false) +ALL_OP_SHIFT_WITH_INT(ap_ulong, _AP_SIZE_ap_slong, false) + +#undef ALL_OP_SHIFT_WITH_INT + +// compound assign operators. +#define OP_ASSIGN_WITH_INT(ASSIGN_OP, C_TYPE, _AP_W2, _AP_S2) \ + template \ + INLINE ap_int_base<_AP_W, _AP_S>& operator ASSIGN_OP( \ + ap_int_base<_AP_W, _AP_S>& op, C_TYPE op2) { \ + return op ASSIGN_OP ap_int_base<_AP_W2, _AP_S2>(op2); \ + } + +// TODO int a; ap_int<16> b; a += b; + +#define ALL_OP_ASSIGN_WITH_INT(C_TYPE, _AP_W2, _AP_S2) \ + OP_ASSIGN_WITH_INT(+=, C_TYPE, _AP_W2, _AP_S2) \ + OP_ASSIGN_WITH_INT(-=, C_TYPE, _AP_W2, _AP_S2) \ + OP_ASSIGN_WITH_INT(*=, C_TYPE, _AP_W2, _AP_S2) \ + OP_ASSIGN_WITH_INT(/=, C_TYPE, _AP_W2, _AP_S2) \ + OP_ASSIGN_WITH_INT(%=, C_TYPE, _AP_W2, _AP_S2) \ + OP_ASSIGN_WITH_INT(&=, C_TYPE, _AP_W2, _AP_S2) \ + OP_ASSIGN_WITH_INT(|=, C_TYPE, _AP_W2, _AP_S2) \ + OP_ASSIGN_WITH_INT(^=, C_TYPE, _AP_W2, _AP_S2) \ + OP_ASSIGN_WITH_INT(>>=, C_TYPE, _AP_W2, _AP_S2) \ + OP_ASSIGN_WITH_INT(<<=, C_TYPE, _AP_W2, _AP_S2) + +ALL_OP_ASSIGN_WITH_INT(bool, 1, false) +ALL_OP_ASSIGN_WITH_INT(char, 8, CHAR_IS_SIGNED) +ALL_OP_ASSIGN_WITH_INT(signed char, 8, true) +ALL_OP_ASSIGN_WITH_INT(unsigned char, 8, false) +ALL_OP_ASSIGN_WITH_INT(short, _AP_SIZE_short, true) +ALL_OP_ASSIGN_WITH_INT(unsigned short, _AP_SIZE_short, false) +ALL_OP_ASSIGN_WITH_INT(int, _AP_SIZE_int, true) +ALL_OP_ASSIGN_WITH_INT(unsigned int, _AP_SIZE_int, false) +ALL_OP_ASSIGN_WITH_INT(long, _AP_SIZE_long, true) +ALL_OP_ASSIGN_WITH_INT(unsigned long, _AP_SIZE_long, false) +ALL_OP_ASSIGN_WITH_INT(ap_slong, _AP_SIZE_ap_slong, true) +ALL_OP_ASSIGN_WITH_INT(ap_ulong, _AP_SIZE_ap_slong, false) + +#undef OP_ASSIGN_WITH_INT +#undef ALL_OP_ASSIGN_WITH_INT + +// equality and relational operators. +#define OP_REL_WITH_INT(REL_OP, C_TYPE, _AP_W2, _AP_S2) \ + template \ + INLINE bool operator REL_OP(C_TYPE i_op, \ + const ap_int_base<_AP_W, _AP_S>& op) { \ + return ap_int_base<_AP_W2, _AP_S2>(i_op) REL_OP op; \ + } \ + template \ + INLINE bool operator REL_OP(const ap_int_base<_AP_W, _AP_S>& op, \ + C_TYPE op2) { \ + return op REL_OP ap_int_base<_AP_W2, _AP_S2>(op2); \ + } + +#define ALL_OP_REL_WITH_INT(C_TYPE, _AP_W2, _AP_S2) \ + OP_REL_WITH_INT(>, C_TYPE, _AP_W2, _AP_S2) \ + OP_REL_WITH_INT(<, C_TYPE, _AP_W2, _AP_S2) \ + OP_REL_WITH_INT(>=, C_TYPE, _AP_W2, _AP_S2) \ + OP_REL_WITH_INT(<=, C_TYPE, _AP_W2, _AP_S2) \ + OP_REL_WITH_INT(==, C_TYPE, _AP_W2, _AP_S2) \ + OP_REL_WITH_INT(!=, C_TYPE, _AP_W2, _AP_S2) + +ALL_OP_REL_WITH_INT(bool, 1, false) +ALL_OP_REL_WITH_INT(char, 8, CHAR_IS_SIGNED) +ALL_OP_REL_WITH_INT(signed char, 8, true) +ALL_OP_REL_WITH_INT(unsigned char, 8, false) +ALL_OP_REL_WITH_INT(short, _AP_SIZE_short, true) +ALL_OP_REL_WITH_INT(unsigned short, _AP_SIZE_short, false) +ALL_OP_REL_WITH_INT(int, _AP_SIZE_int, true) +ALL_OP_REL_WITH_INT(unsigned int, _AP_SIZE_int, false) +ALL_OP_REL_WITH_INT(long, _AP_SIZE_long, true) +ALL_OP_REL_WITH_INT(unsigned long, _AP_SIZE_long, false) +ALL_OP_REL_WITH_INT(ap_slong, _AP_SIZE_ap_slong, true) +ALL_OP_REL_WITH_INT(ap_ulong, _AP_SIZE_ap_slong, false) + +#undef OP_REL_WITH_INT +#undef ALL_OP_BIN_WITH_INT + +#define OP_REL_WITH_DOUBLE_OR_FLOAT(Sym) \ + template \ + INLINE bool operator Sym(const ap_int_base<_AP_W, _AP_S>& op1, \ + double op2) { \ + return op1.to_double() Sym op2 ; \ + } \ + template \ + INLINE bool operator Sym(double op1, \ + const ap_int_base<_AP_W, _AP_S>& op2) { \ + return op1 Sym op2.to_double() ; \ + } \ + template \ + INLINE bool operator Sym(const ap_int_base<_AP_W, _AP_S>& op1, \ + float op2) { \ + return op1.to_double() Sym op2 ; \ + } \ + template \ + INLINE bool operator Sym(float op1, \ + const ap_int_base<_AP_W, _AP_S>& op2) { \ + return op1 Sym op2.to_double() ; \ + } + OP_REL_WITH_DOUBLE_OR_FLOAT(>) + OP_REL_WITH_DOUBLE_OR_FLOAT(<) + OP_REL_WITH_DOUBLE_OR_FLOAT(>=) + OP_REL_WITH_DOUBLE_OR_FLOAT(<=) + OP_REL_WITH_DOUBLE_OR_FLOAT(==) + OP_REL_WITH_DOUBLE_OR_FLOAT(!=) + +#undef OP_REL_WITH_DOUBLE_OR_FLOAT + + +/* Operators with ap_bit_ref. + * ------------------------------------------------------------ + */ +// arithmetic, bitwise and shift operators. +#define OP_BIN_WITH_RANGE(BIN_OP, RTYPE) \ + template \ + INLINE typename ap_int_base<_AP_W1, _AP_S1>::template RType<_AP_W2, \ + _AP_S2>::RTYPE \ + operator BIN_OP(const ap_range_ref<_AP_W1, _AP_S1>& op1, \ + const ap_int_base<_AP_W2, _AP_S2>& op2) { \ + return ap_int_base<_AP_W1, false>(op1) BIN_OP op2; \ + } \ + template \ + INLINE typename ap_int_base<_AP_W1, _AP_S1>::template RType<_AP_W2, \ + _AP_S2>::RTYPE \ + operator BIN_OP(const ap_int_base<_AP_W1, _AP_S1>& op1, \ + const ap_range_ref<_AP_W2, _AP_S2>& op2) { \ + return op1 BIN_OP ap_int_base<_AP_W2, false>(op2); \ + } + +OP_BIN_WITH_RANGE(+, plus) +OP_BIN_WITH_RANGE(-, minus) +OP_BIN_WITH_RANGE(*, mult) +OP_BIN_WITH_RANGE(/, div) +OP_BIN_WITH_RANGE(%, mod) +OP_BIN_WITH_RANGE(&, logic) +OP_BIN_WITH_RANGE(|, logic) +OP_BIN_WITH_RANGE(^, logic) +OP_BIN_WITH_RANGE(>>, arg1) +OP_BIN_WITH_RANGE(<<, arg1) + +#undef OP_BIN_WITH_RANGE + +// compound assignment operators. +#define OP_ASSIGN_WITH_RANGE(ASSIGN_OP) \ + template \ + INLINE ap_int_base<_AP_W1, _AP_S1>& operator ASSIGN_OP( \ + ap_int_base<_AP_W1, _AP_S1>& op1, ap_range_ref<_AP_W2, _AP_S2>& op2) { \ + return op1 ASSIGN_OP ap_int_base<_AP_W2, false>(op2); \ + } \ + template \ + INLINE ap_range_ref<_AP_W1, _AP_S1>& operator ASSIGN_OP( \ + ap_range_ref<_AP_W1, _AP_S1>& op1, ap_int_base<_AP_W2, _AP_S2>& op2) { \ + ap_int_base<_AP_W1, false> tmp(op1); \ + tmp ASSIGN_OP op2; \ + op1 = tmp; \ + return op1; \ + } + +OP_ASSIGN_WITH_RANGE(+=) +OP_ASSIGN_WITH_RANGE(-=) +OP_ASSIGN_WITH_RANGE(*=) +OP_ASSIGN_WITH_RANGE(/=) +OP_ASSIGN_WITH_RANGE(%=) +OP_ASSIGN_WITH_RANGE(&=) +OP_ASSIGN_WITH_RANGE(|=) +OP_ASSIGN_WITH_RANGE(^=) +OP_ASSIGN_WITH_RANGE(>>=) +OP_ASSIGN_WITH_RANGE(<<=) + +#undef OP_ASSIGN_WITH_RANGE + +// equality and relational operators +#define OP_REL_WITH_RANGE(REL_OP) \ + template \ + INLINE bool operator REL_OP(const ap_range_ref<_AP_W1, _AP_S1>& op1, \ + const ap_int_base<_AP_W2, _AP_S2>& op2) { \ + return ap_int_base<_AP_W1, false>(op1).operator REL_OP(op2); \ + } \ + template \ + INLINE bool operator REL_OP(const ap_int_base<_AP_W1, _AP_S1>& op1, \ + const ap_range_ref<_AP_W2, _AP_S2>& op2) { \ + return op1.operator REL_OP(op2.operator ap_int_base<_AP_W2, false>()); \ + } + +OP_REL_WITH_RANGE(==) +OP_REL_WITH_RANGE(!=) +OP_REL_WITH_RANGE(>) +OP_REL_WITH_RANGE(>=) +OP_REL_WITH_RANGE(<) +OP_REL_WITH_RANGE(<=) + +#undef OP_REL_WITH_RANGE + +/* Operators with ap_bit_ref. + * ------------------------------------------------------------ + */ +// arithmetic, bitwise and shift operators. +#define OP_BIN_WITH_BIT(BIN_OP, RTYPE) \ + template \ + INLINE typename ap_int_base<_AP_W1, _AP_S1>::template RType<1, false>::RTYPE \ + operator BIN_OP(const ap_int_base<_AP_W1, _AP_S1>& op1, \ + const ap_bit_ref<_AP_W2, _AP_S2>& op2) { \ + return op1 BIN_OP ap_int_base<1, false>(op2); \ + } \ + template \ + INLINE typename ap_int_base<1, false>::template RType<_AP_W2, _AP_S2>::RTYPE \ + operator BIN_OP(const ap_bit_ref<_AP_W1, _AP_S1>& op1, \ + const ap_int_base<_AP_W2, _AP_S2>& op2) { \ + return ap_int_base<1, false>(op1) BIN_OP op2; \ + } + +OP_BIN_WITH_BIT(+, plus) +OP_BIN_WITH_BIT(-, minus) +OP_BIN_WITH_BIT(*, mult) +OP_BIN_WITH_BIT(/, div) +OP_BIN_WITH_BIT(%, mod) +OP_BIN_WITH_BIT(&, logic) +OP_BIN_WITH_BIT(|, logic) +OP_BIN_WITH_BIT(^, logic) +OP_BIN_WITH_BIT(>>, arg1) +OP_BIN_WITH_BIT(<<, arg1) + +#undef OP_BIN_WITH_BIT + +// compound assignment operators. +#define OP_ASSIGN_WITH_BIT(ASSIGN_OP) \ + template \ + INLINE ap_int_base<_AP_W1, _AP_S1>& operator ASSIGN_OP( \ + ap_int_base<_AP_W1, _AP_S1>& op1, ap_bit_ref<_AP_W2, _AP_S2>& op2) { \ + return op1 ASSIGN_OP ap_int_base<1, false>(op2); \ + } \ + template \ + INLINE ap_bit_ref<_AP_W1, _AP_S1>& operator ASSIGN_OP( \ + ap_bit_ref<_AP_W1, _AP_S1>& op1, ap_int_base<_AP_W2, _AP_S2>& op2) { \ + ap_int_base<1, false> tmp(op1); \ + tmp ASSIGN_OP op2; \ + op1 = tmp; \ + return op1; \ + } + +OP_ASSIGN_WITH_BIT(+=) +OP_ASSIGN_WITH_BIT(-=) +OP_ASSIGN_WITH_BIT(*=) +OP_ASSIGN_WITH_BIT(/=) +OP_ASSIGN_WITH_BIT(%=) +OP_ASSIGN_WITH_BIT(&=) +OP_ASSIGN_WITH_BIT(|=) +OP_ASSIGN_WITH_BIT(^=) +OP_ASSIGN_WITH_BIT(>>=) +OP_ASSIGN_WITH_BIT(<<=) + +#undef OP_ASSIGN_WITH_BIT + +// equality and relational operators. +#define OP_REL_WITH_BIT(REL_OP) \ + template \ + INLINE bool operator REL_OP(const ap_int_base<_AP_W1, _AP_S1>& op1, \ + const ap_bit_ref<_AP_W2, _AP_S2>& op2) { \ + return op1 REL_OP ap_int_base<1, false>(op2); \ + } \ + template \ + INLINE bool operator REL_OP(const ap_bit_ref<_AP_W1, _AP_S1>& op1, \ + const ap_int_base<_AP_W2, _AP_S2>& op2) { \ + return ap_int_base<1, false>(op1) REL_OP op2; \ + } + +OP_REL_WITH_BIT(==) +OP_REL_WITH_BIT(!=) +OP_REL_WITH_BIT(>) +OP_REL_WITH_BIT(>=) +OP_REL_WITH_BIT(<) +OP_REL_WITH_BIT(<=) + +#undef OP_REL_WITH_BIT + + +/* Operators with ap_concat_ref. + * ------------------------------------------------------------ + */ +// arithmetic, bitwise and shift operators. +// bitwise operators are defined in struct. +// TODO specify whether to define arithmetic and bitwise operators. +#if 0 +#define OP_BIN_WITH_CONCAT(BIN_OP, RTYPE) \ + template \ + INLINE typename ap_int_base<_AP_W3, _AP_S3>::template RType<_AP_W1 + _AP_W2, \ + false>::RTYPE \ + operator BIN_OP(const ap_int_base<_AP_W3, _AP_S3>& op1, \ + const ap_concat_ref<_AP_W1, _AP_T1, _AP_W2, _AP_T2>& op2) { \ + /* convert ap_concat_ref to ap_int_base */ \ + return op1 BIN_OP op2.get(); \ + } \ + template \ + INLINE typename ap_int_base<_AP_W1 + _AP_W2, \ + false>::template RType<_AP_W3, _AP_S3>::RTYPE \ + operator BIN_OP(const ap_concat_ref<_AP_W1, _AP_T1, _AP_W2, _AP_T2>& op1, \ + const ap_int_base<_AP_W3, _AP_S3>& op2) { \ + /* convert ap_concat_ref to ap_int_base */ \ + return op1.get() BIN_OP op2; \ + } + +OP_BIN_WITH_CONCAT(+, plus) +OP_BIN_WITH_CONCAT(-, minus) +OP_BIN_WITH_CONCAT(*, mult) +OP_BIN_WITH_CONCAT(/, div) +OP_BIN_WITH_CONCAT(%, mod) +OP_BIN_WITH_CONCAT(&, logic) +OP_BIN_WITH_CONCAT(|, logic) +OP_BIN_WITH_CONCAT(^, logic) +OP_BIN_WITH_CONCAT(>>, arg1) +OP_BIN_WITH_CONCAT(<<, arg1) + +#undef OP_BIN_WITH_CONCAT + +// compound assignment operators. +#define OP_ASSIGN_WITH_CONCAT(ASSIGN_OP) \ + template \ + INLINE typename ap_int_base<_AP_W3, _AP_S3>::template RType<_AP_W1 + _AP_W2, \ + false>::RTYPE \ + operator ASSIGN_OP( \ + const ap_int_base<_AP_W3, _AP_S3>& op1, \ + const ap_concat_ref<_AP_W1, _AP_T1, _AP_W2, _AP_T2>& op2) { \ + /* convert ap_concat_ref to ap_int_base */ \ + return op1 ASSIGN_OP op2.get(); \ + } \ + template \ + INLINE typename ap_int_base<_AP_W1 + _AP_W2, \ + false>::template RType<_AP_W3, _AP_S3>::RTYPE \ + operator ASSIGN_OP(const ap_concat_ref<_AP_W1, _AP_T1, _AP_W2, _AP_T2>& op1, \ + const ap_int_base<_AP_W3, _AP_S3>& op2) { \ + /* convert ap_concat_ref to ap_int_base */ \ + ap_int_base<_AP_W1 + _AP_W2, false> tmp = op1.get(); \ + tmp ASSIGN_OP op2; \ + op1 = tmp; \ + return op1; \ + } + +OP_ASSIGN_WITH_CONCAT(+=) +OP_ASSIGN_WITH_CONCAT(-=) +OP_ASSIGN_WITH_CONCAT(*=) +OP_ASSIGN_WITH_CONCAT(/=) +OP_ASSIGN_WITH_CONCAT(%=) +OP_ASSIGN_WITH_CONCAT(&=) +OP_ASSIGN_WITH_CONCAT(|=) +OP_ASSIGN_WITH_CONCAT(^=) +OP_ASSIGN_WITH_CONCAT(>>=) +OP_ASSIGN_WITH_CONCAT(<<=) + +#undef OP_ASSIGN_WITH_CONCAT +#endif + +// equality and relational operators. +#define OP_REL_WITH_CONCAT(REL_OP) \ + template \ + INLINE bool operator REL_OP( \ + const ap_int_base<_AP_W3, _AP_S3>& op1, \ + const ap_concat_ref<_AP_W1, _AP_T1, _AP_W2, _AP_T2>& op2) { \ + /* convert ap_concat_ref to ap_int_base */ \ + return op1 REL_OP op2.get(); \ + } \ + template \ + INLINE bool operator REL_OP( \ + const ap_concat_ref<_AP_W1, _AP_T1, _AP_W2, _AP_T2>& op1, \ + const ap_int_base<_AP_W3, _AP_S3>& op2) { \ + /* convert ap_concat_ref to ap_int_base */ \ + return op1.get() REL_OP op2; \ + } + +OP_REL_WITH_CONCAT(==) +OP_REL_WITH_CONCAT(!=) +OP_REL_WITH_CONCAT(>) +OP_REL_WITH_CONCAT(>=) +OP_REL_WITH_CONCAT(<) +OP_REL_WITH_CONCAT(<=) + +#undef OP_REL_WITH_CONCAT + +#endif // ifndef __cplusplus +#endif // ifndef __AP_INT_BASE_H__ + +// -*- cpp -*- diff --git a/firmware/ap_types/ap_int_ref.h b/firmware/ap_types/ap_int_ref.h new file mode 100644 index 0000000000000000000000000000000000000000..421f09fda6c7f194e7192fbb5a77ab984fb0e435 --- /dev/null +++ b/firmware/ap_types/ap_int_ref.h @@ -0,0 +1,1346 @@ +/* + * Copyright 2011-2019 Xilinx, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __AP_INT_REF_H__ +#define __AP_INT_REF_H__ + +#ifndef __AP_INT_H__ +#error "Only ap_fixed.h and ap_int.h can be included directly in user code." +#endif + +#ifndef __cplusplus +#error "C++ is required to include this header file" + +#else + +#ifndef __SYNTHESIS__ +#include +#endif + +/* Concatination reference. + ---------------------------------------------------------------- +*/ +template +struct ap_concat_ref { + enum { + _AP_WR = _AP_W1 + _AP_W2, + }; + + _AP_T1& mbv1; + _AP_T2& mbv2; + + INLINE ap_concat_ref(const ap_concat_ref<_AP_W1, _AP_T1, _AP_W2, _AP_T2>& ref) + : mbv1(ref.mbv1), mbv2(ref.mbv2) {} + + INLINE ap_concat_ref(_AP_T1& bv1, _AP_T2& bv2) : mbv1(bv1), mbv2(bv2) {} + + template + INLINE ap_concat_ref& operator=(const ap_int_base<_AP_W3, _AP_S3>& val) { + ap_int_base<_AP_W1 + _AP_W2, false> vval(val); + int W_ref1 = mbv1.length(); + int W_ref2 = mbv2.length(); + ap_int_base<_AP_W1, false> Part1; + Part1.V = _AP_ROOT_op_get_range(vval.V, W_ref2, W_ref1 + W_ref2 - 1); + mbv1.set(Part1); + ap_int_base<_AP_W2, false> Part2; + Part2.V = _AP_ROOT_op_get_range(vval.V, 0, W_ref2 - 1); + mbv2.set(Part2); + return *this; + } + + // assign op from hls supported C integral types. + // FIXME disabled to support legacy code directly assign from sc_signal + //template + //INLINE typename _ap_type::enable_if<_ap_type::is_integral::value, + // ap_concat_ref&>::type + //operator=(T val) { + // ap_int_base<_AP_W1 + _AP_W2, false> tmpVal(val); + // return operator=(tmpVal); + //} +#define ASSIGN_WITH_CTYPE(_Tp) \ + INLINE ap_concat_ref& operator=(_Tp val) { \ + ap_int_base<_AP_W1 + _AP_W2, false> tmpVal(val); \ + return operator=(tmpVal); \ + } + + ASSIGN_WITH_CTYPE(bool) + ASSIGN_WITH_CTYPE(char) + ASSIGN_WITH_CTYPE(signed char) + ASSIGN_WITH_CTYPE(unsigned char) + ASSIGN_WITH_CTYPE(short) + ASSIGN_WITH_CTYPE(unsigned short) + ASSIGN_WITH_CTYPE(int) + ASSIGN_WITH_CTYPE(unsigned int) + ASSIGN_WITH_CTYPE(long) + ASSIGN_WITH_CTYPE(unsigned long) + ASSIGN_WITH_CTYPE(ap_slong) + ASSIGN_WITH_CTYPE(ap_ulong) +#if _AP_ENABLE_HALF_ == 1 + ASSIGN_WITH_CTYPE(half) +#endif + ASSIGN_WITH_CTYPE(float) + ASSIGN_WITH_CTYPE(double) + +#undef ASSIGN_WITH_CTYPE + + // Be explicit to prevent it from being deleted, as field d_bv + // is of reference type. + INLINE ap_concat_ref& operator=( + const ap_concat_ref<_AP_W1, _AP_T1, _AP_W2, _AP_T2>& val) { + ap_int_base<_AP_W1 + _AP_W2, false> tmpVal(val); + return operator=(tmpVal); + } + + template + INLINE ap_concat_ref& operator=( + const ap_concat_ref<_AP_W3, _AP_T3, _AP_W4, _AP_T4>& val) { + ap_int_base<_AP_W1 + _AP_W2, false> tmpVal(val); + return operator=(tmpVal); + } + + template + INLINE ap_concat_ref& operator=(const ap_bit_ref<_AP_W3, _AP_S3>& val) { + ap_int_base<_AP_W1 + _AP_W2, false> tmpVal(val); + return operator=(tmpVal); + } + template + INLINE ap_concat_ref& operator=(const ap_range_ref<_AP_W3, _AP_S3>& val) { + ap_int_base<_AP_W1 + _AP_W2, false> tmpVal(val); + return operator=(tmpVal); + } + + template + INLINE ap_concat_ref& operator=( + const af_range_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3>& val) { + return operator=((const ap_int_base<_AP_W3, false>)(val)); + } + + template + INLINE ap_concat_ref& operator=( + const ap_fixed_base<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3>& + val) { + return operator=(val.to_ap_int_base()); + } + + template + INLINE ap_concat_ref& operator=( + const af_bit_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3>& val) { + return operator=((ap_ulong)(bool)(val)); + } + + INLINE operator ap_int_base<_AP_WR, false>() const { return get(); } + + INLINE operator ap_ulong() const { return get().to_uint64(); } + + template + INLINE ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, + ap_range_ref<_AP_W3, _AP_S3> > + operator,(const ap_range_ref<_AP_W3, _AP_S3> &a2) { + return ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, + ap_range_ref<_AP_W3, _AP_S3> >( + *this, const_cast&>(a2)); + } + + template + INLINE + ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, ap_int_base<_AP_W3, _AP_S3> > + operator,(ap_int_base<_AP_W3, _AP_S3> &a2) { + return ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, + ap_int_base<_AP_W3, _AP_S3> >(*this, a2); + } + + template + INLINE + ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, ap_int_base<_AP_W3, _AP_S3> > + operator,(volatile ap_int_base<_AP_W3, _AP_S3> &a2) { + return ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, + ap_int_base<_AP_W3, _AP_S3> >( + *this, const_cast&>(a2)); + } + + template + INLINE + ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, ap_int_base<_AP_W3, _AP_S3> > + operator,(const ap_int_base<_AP_W3, _AP_S3> &a2) { + return ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, + ap_int_base<_AP_W3, _AP_S3> >( + *this, const_cast&>(a2)); + } + + template + INLINE + ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, ap_int_base<_AP_W3, _AP_S3> > + operator,(const volatile ap_int_base<_AP_W3, _AP_S3> &a2) { + // FIXME op's life does not seem long enough + ap_int_base<_AP_W3, _AP_S3> op(a2); + return ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, + ap_int_base<_AP_W3, _AP_S3> >( + *this, const_cast&>(op)); + } + + template + INLINE ap_concat_ref<_AP_WR, ap_concat_ref, 1, ap_bit_ref<_AP_W3, _AP_S3> > + operator,(const ap_bit_ref<_AP_W3, _AP_S3> &a2) { + return ap_concat_ref<_AP_WR, ap_concat_ref, 1, ap_bit_ref<_AP_W3, _AP_S3> >( + *this, const_cast&>(a2)); + } + + template + INLINE ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3 + _AP_W4, + ap_concat_ref<_AP_W3, _AP_T3, _AP_W4, _AP_T4> > + operator,(const ap_concat_ref<_AP_W3, _AP_T3, _AP_W4, _AP_T4> &a2) { + return ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3 + _AP_W4, + ap_concat_ref<_AP_W3, _AP_T3, _AP_W4, _AP_T4> >( + *this, const_cast&>(a2)); + } + + template + INLINE ap_concat_ref< + _AP_WR, ap_concat_ref, _AP_W3, + af_range_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> > + operator,( + const af_range_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> &a2) { + return ap_concat_ref< + _AP_WR, ap_concat_ref, _AP_W3, + af_range_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> >( + *this, + const_cast< + af_range_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3>&>(a2)); + } + + template + INLINE + ap_concat_ref<_AP_WR, ap_concat_ref, 1, + af_bit_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> > + operator,(const af_bit_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> + &a2) { + return ap_concat_ref< + _AP_WR, ap_concat_ref, 1, + af_bit_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> >( + *this, + const_cast&>( + a2)); + } + + template + INLINE ap_int_base operator&( + const ap_int_base<_AP_W3, _AP_S3>& a2) { + return get() & a2; + } + + template + INLINE ap_int_base operator|( + const ap_int_base<_AP_W3, _AP_S3>& a2) { + return get() | a2; + } + + template + INLINE ap_int_base operator^( + const ap_int_base<_AP_W3, _AP_S3>& a2) { + return get() ^ a2; + } + +#if 0 + template + INLINE ap_int_base slice() { + ap_int_base<_AP_WR, false> bv = get(); + return bv.slice(); + } +#endif + + INLINE ap_int_base<_AP_WR, false> get() const { + ap_int_base<_AP_WR, false> tmpVal(0); + int W_ref1 = mbv1.length(); + int W_ref2 = mbv2.length(); + ap_int_base<_AP_W2, false> v2(mbv2); + ap_int_base<_AP_W1, false> v1(mbv1); + tmpVal.V = _AP_ROOT_op_set_range(tmpVal.V, 0, W_ref2 - 1, v2.V); + tmpVal.V = + _AP_ROOT_op_set_range(tmpVal.V, W_ref2, W_ref1 + W_ref2 - 1, v1.V); + return tmpVal; + } + + template + INLINE void set(const ap_int_base<_AP_W3, false>& val) { + ap_int_base<_AP_W1 + _AP_W2, false> vval(val); + int W_ref1 = mbv1.length(); + int W_ref2 = mbv2.length(); + ap_int_base<_AP_W1, false> tmpVal1; + tmpVal1.V = _AP_ROOT_op_get_range(vval.V, W_ref2, W_ref1 + W_ref2 - 1); + mbv1.set(tmpVal1); + ap_int_base<_AP_W2, false> tmpVal2; + tmpVal2.V = _AP_ROOT_op_get_range(vval.V, 0, W_ref2 - 1); + mbv2.set(tmpVal2); + } + + INLINE int length() const { return mbv1.length() + mbv2.length(); } +}; // struct ap_concat_ref + +/* Range (slice) reference. + ---------------------------------------------------------------- +*/ +template +struct ap_range_ref { + // struct ssdm_int or its sim model. + // TODO make it possible to reference to ap_fixed_base/ap_fixed/ap_ufixed + // and then we can retire af_range_ref. + typedef ap_int_base<_AP_W, _AP_S> ref_type; + ref_type& d_bv; + int l_index; + int h_index; + + public: + INLINE ap_range_ref(const ap_range_ref<_AP_W, _AP_S>& ref) + : d_bv(ref.d_bv), l_index(ref.l_index), h_index(ref.h_index) {} + + INLINE ap_range_ref(ref_type* bv, int h, int l) + : d_bv(*bv), l_index(l), h_index(h) {} + + INLINE ap_range_ref(const ref_type* bv, int h, int l) + : d_bv(*const_cast(bv)), l_index(l), h_index(h) {} + + INLINE operator ap_int_base<_AP_W, false>() const { + ap_int_base<_AP_W, false> ret; + ret.V = _AP_ROOT_op_get_range(d_bv.V, l_index, h_index); + return ret; + } + + INLINE operator ap_ulong() const { return to_uint64(); } + + /// @name assign operators + // @{ + + // FIXME disabled to work-around lagacy code assigning from sc_signal, + // which dependes on implicit type conversion. + // + // /// assign from hls supported C integral types. + // template + // INLINE typename _ap_type::enable_if<_ap_type::is_integral::value, + // ap_range_ref&>::type + // operator=(T val) { + // ap_int_base<_AP_W, false> tmp(val); + // d_bv.V = _AP_ROOT_op_set_range(d_bv.V, l_index, h_index, tmp.V); + // return *this; + // } +#define ASSIGN_WITH_CTYPE(_Tp) \ + INLINE ap_range_ref& operator=(_Tp val) { \ + ap_int_base<_AP_W, false> tmp(val); \ + d_bv.V = _AP_ROOT_op_set_range(d_bv.V, l_index, h_index, tmp.V); \ + return *this; \ + } + + ASSIGN_WITH_CTYPE(bool) + ASSIGN_WITH_CTYPE(char) + ASSIGN_WITH_CTYPE(signed char) + ASSIGN_WITH_CTYPE(unsigned char) + ASSIGN_WITH_CTYPE(short) + ASSIGN_WITH_CTYPE(unsigned short) + ASSIGN_WITH_CTYPE(int) + ASSIGN_WITH_CTYPE(unsigned int) + ASSIGN_WITH_CTYPE(long) + ASSIGN_WITH_CTYPE(unsigned long) + ASSIGN_WITH_CTYPE(ap_slong) + ASSIGN_WITH_CTYPE(ap_ulong) +#if _AP_ENABLE_HALF_ == 1 + ASSIGN_WITH_CTYPE(half) +#endif + ASSIGN_WITH_CTYPE(float) + ASSIGN_WITH_CTYPE(double) + +#undef ASSIGN_WITH_CTYPE + + /// assign using string. XXX crucial for cosim. + INLINE ap_range_ref& operator=(const char* val) { + const ap_int_base<_AP_W, false> tmp(val); // XXX figure out radix + d_bv.V = _AP_ROOT_op_set_range(d_bv.V, l_index, h_index, tmp.V); + return *this; + } + + /// assign from ap_int_base. + template + INLINE ap_range_ref& operator=(const ap_int_base<_AP_W2, _AP_S2>& val) { + ap_int_base<_AP_W, false> tmp(val); + d_bv.V = _AP_ROOT_op_set_range(d_bv.V, l_index, h_index, tmp.V); + return *this; + } + + /// copy assign operator + // XXX Be explicit to prevent it from being deleted, as field d_bv + // is of reference type. + INLINE ap_range_ref& operator=(const ap_range_ref& val) { + return operator=((const ap_int_base<_AP_W, false>)val); + } + + /// assign from range reference to ap_int_base. + template + INLINE ap_range_ref& operator=(const ap_range_ref<_AP_W2, _AP_S2>& val) { + return operator=((const ap_int_base<_AP_W2, false>)val); + } + + /// assign from bit reference to ap_int_base. + template + INLINE ap_range_ref& operator=(const ap_bit_ref<_AP_W2, _AP_S2>& val) { + return operator=((ap_ulong)(bool)(val)); + } + + /// assign from ap_fixed_base. + template + INLINE ap_range_ref& operator=( + const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& + val) { + return operator=(val.to_ap_int_base()); + } + + /// assign from range reference to ap_fixed_base. + template + INLINE ap_range_ref& operator=( + const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) { + return operator=((const ap_int_base<_AP_W2, false>)val); + } + + /// assign from bit reference to ap_fixed_base. + template + INLINE ap_range_ref& operator=( + const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) { + return operator=((ap_ulong)(bool)(val)); + } + + /// assign from compound reference. + template + INLINE ap_range_ref& operator=( + const ap_concat_ref<_AP_W2, _AP_T3, _AP_W3, _AP_T3>& val) { + return operator=((const ap_int_base<_AP_W2 + _AP_W3, false>)(val)); + } + // @} + + template + INLINE + ap_concat_ref<_AP_W, ap_range_ref, _AP_W2, ap_range_ref<_AP_W2, _AP_S2> > + operator,(const ap_range_ref<_AP_W2, _AP_S2> &a2) { + return ap_concat_ref<_AP_W, ap_range_ref, _AP_W2, + ap_range_ref<_AP_W2, _AP_S2> >( + *this, const_cast&>(a2)); + } + + template + INLINE + ap_concat_ref<_AP_W, ap_range_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> > + operator,(ap_int_base<_AP_W2, _AP_S2> &a2) { + return ap_concat_ref<_AP_W, ap_range_ref, _AP_W2, + ap_int_base<_AP_W2, _AP_S2> >(*this, a2); + } + + INLINE + ap_concat_ref<_AP_W, ap_range_ref, _AP_W, ap_int_base<_AP_W, _AP_S> > + operator,(ap_int_base<_AP_W, _AP_S>& a2) { + return ap_concat_ref<_AP_W, ap_range_ref, _AP_W, + ap_int_base<_AP_W, _AP_S> >(*this, a2); + } + + template + INLINE + ap_concat_ref<_AP_W, ap_range_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> > + operator,(volatile ap_int_base<_AP_W2, _AP_S2> &a2) { + return ap_concat_ref<_AP_W, ap_range_ref, _AP_W2, + ap_int_base<_AP_W2, _AP_S2> >( + *this, const_cast&>(a2)); + } + + template + INLINE + ap_concat_ref<_AP_W, ap_range_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> > + operator,(const ap_int_base<_AP_W2, _AP_S2> &a2) { + return ap_concat_ref<_AP_W, ap_range_ref, _AP_W2, + ap_int_base<_AP_W2, _AP_S2> >( + *this, const_cast&>(a2)); + } + + template + INLINE + ap_concat_ref<_AP_W, ap_range_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> > + operator,(const volatile ap_int_base<_AP_W2, _AP_S2> &a2) { + return ap_concat_ref<_AP_W, ap_range_ref, _AP_W2, + ap_int_base<_AP_W2, _AP_S2> >( + *this, const_cast&>(a2)); + } + + template + INLINE ap_concat_ref<_AP_W, ap_range_ref, 1, ap_bit_ref<_AP_W2, _AP_S2> > + operator,(const ap_bit_ref<_AP_W2, _AP_S2> &a2) { + return ap_concat_ref<_AP_W, ap_range_ref, 1, ap_bit_ref<_AP_W2, _AP_S2> >( + *this, const_cast&>(a2)); + } + + template + INLINE ap_concat_ref<_AP_W, ap_range_ref, _AP_W2 + _AP_W3, + ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> > + operator,(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &a2) { + return ap_concat_ref<_AP_W, ap_range_ref, _AP_W2 + _AP_W3, + ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >( + *this, const_cast&>(a2)); + } + + template + INLINE ap_concat_ref< + _AP_W, ap_range_ref, _AP_W2, + af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> > + operator,( + const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> a2) { + return ap_concat_ref< + _AP_W, ap_range_ref, _AP_W2, + af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >( + *this, + const_cast< + af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>&>(a2)); + } + + template + INLINE + ap_concat_ref<_AP_W, ap_range_ref, 1, + af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> > + operator,(const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> + &a2) { + return ap_concat_ref< + _AP_W, ap_range_ref, 1, + af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >( + *this, + const_cast&>( + a2)); + } + + template + INLINE bool operator==(const ap_range_ref<_AP_W2, _AP_S2>& op2) { + ap_int_base<_AP_W, false> lop(*this); + ap_int_base<_AP_W2, false> hop(op2); + return lop == hop; + } + + template + INLINE bool operator!=(const ap_range_ref<_AP_W2, _AP_S2>& op2) { + return !(operator==(op2)); + } + + template + INLINE bool operator<(const ap_range_ref<_AP_W2, _AP_S2>& op2) { + ap_int_base<_AP_W, false> lop(*this); + ap_int_base<_AP_W2, false> hop(op2); + return lop < hop; + } + + template + INLINE bool operator<=(const ap_range_ref<_AP_W2, _AP_S2>& op2) { + ap_int_base<_AP_W, false> lop(*this); + ap_int_base<_AP_W2, false> hop(op2); + return lop <= hop; + } + + template + INLINE bool operator>(const ap_range_ref<_AP_W2, _AP_S2>& op2) { + return !(operator<=(op2)); + } + + template + INLINE bool operator>=(const ap_range_ref<_AP_W2, _AP_S2>& op2) { + return !(operator<(op2)); + } + + template + INLINE ap_range_ref<_AP_W, _AP_S>& operator|=( + const ap_range_ref<_AP_W2, _AP_S2>& op2) { + (this->d_bv).V |= (op2.d_bv).V; + return *this; + }; + + template + INLINE ap_range_ref<_AP_W, _AP_S>& operator|=( + const ap_int_base<_AP_W2, _AP_S2>& op2) { + (this->d_bv).V |= op2.V; + return *this; + }; + + template + INLINE ap_range_ref<_AP_W, _AP_S>& operator&=( + const ap_range_ref<_AP_W2, _AP_S2>& op2) { + (this->d_bv).V &= (op2.d_bv).V; + return *this; + }; + + template + INLINE ap_range_ref<_AP_W, _AP_S>& operator&=( + const ap_int_base<_AP_W2, _AP_S2>& op2) { + (this->d_bv).V &= op2.V; + return *this; + }; + + template + INLINE ap_range_ref<_AP_W, _AP_S>& operator^=( + const ap_range_ref<_AP_W2, _AP_S2>& op2) { + (this->d_bv).V ^= (op2.d_bv).V; + return *this; + }; + + template + INLINE ap_range_ref<_AP_W, _AP_S>& operator^=( + const ap_int_base<_AP_W2, _AP_S2>& op2) { + (this->d_bv).V ^= op2.V; + return *this; + }; + + INLINE ap_int_base<_AP_W, false> get() const { + ap_int_base<_AP_W, false> ret; + ret.V = _AP_ROOT_op_get_range(d_bv.V, l_index, h_index); + return ret; + } + + template + INLINE void set(const ap_int_base<_AP_W2, false>& val) { + d_bv.V = _AP_ROOT_op_set_range(d_bv.V, l_index, h_index, val.V); + } + + INLINE int length() const { + return h_index >= l_index ? h_index - l_index + 1 : l_index - h_index + 1; + } + + INLINE int to_int() const { + return (int)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index)); + } + + INLINE unsigned to_uint() const { + return (unsigned)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index)); + } + + INLINE long to_long() const { + return (long)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index)); + } + + INLINE unsigned long to_ulong() const { + return (unsigned long)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index)); + } + + INLINE ap_slong to_int64() const { + return (ap_slong)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index)); + } + + INLINE ap_ulong to_uint64() const { + return (ap_ulong)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index)); + } + + INLINE bool and_reduce() const { + bool ret = true; + bool reverse = l_index > h_index; + unsigned low = reverse ? h_index : l_index; + unsigned high = reverse ? l_index : h_index; + for (unsigned i = low; i != high; ++i) { +#ifdef __SYNTHESIS__ +#pragma HLS unroll +#endif + ret &= _AP_ROOT_op_get_bit(d_bv.V, i); + } + return ret; + } + + INLINE bool or_reduce() const { + bool ret = false; + bool reverse = l_index > h_index; + unsigned low = reverse ? h_index : l_index; + unsigned high = reverse ? l_index : h_index; + for (unsigned i = low; i != high; ++i) { +#ifdef __SYNTHESIS__ +#pragma HLS unroll +#endif + ret |= _AP_ROOT_op_get_bit(d_bv.V, i); + } + return ret; + } + + INLINE bool xor_reduce() const { + bool ret = false; + bool reverse = l_index > h_index; + unsigned low = reverse ? h_index : l_index; + unsigned high = reverse ? l_index : h_index; + for (unsigned i = low; i != high; ++i) { +#ifdef __SYNTHESIS__ +#pragma HLS unroll +#endif + ret ^= _AP_ROOT_op_get_bit(d_bv.V, i); + } + return ret; + } +#ifndef __SYNTHESIS__ + std::string to_string(signed char radix = 2) const { + ap_int_base<_AP_W, false> ret; + ret.V = _AP_ROOT_op_get_range(d_bv.V, l_index, h_index); + return ret.to_string(radix); + } +#else + // XXX HLS will delete this in synthesis + INLINE char* to_string(signed char radix = 2) const { + return 0; + } +#endif +}; // struct ap_range_ref + +// XXX apcc cannot handle global std::ios_base::Init() brought in by +#ifndef AP_AUTOCC +#ifndef __SYNTHESIS__ +template +INLINE std::ostream& operator<<(std::ostream& os, + const ap_range_ref<_AP_W, _AP_S>& x) { + std::ios_base::fmtflags ff = std::cout.flags(); + if (ff & std::cout.hex) { + os << x.to_string(16); // don't print sign + } else if (ff & std::cout.oct) { + os << x.to_string(8); // don't print sign + } else { + os << x.to_string(10); + } + return os; +} +#endif // ifndef __SYNTHESIS__ + +#ifndef __SYNTHESIS__ +template +INLINE std::istream& operator>>(std::istream& in, + ap_range_ref<_AP_W, _AP_S>& op) { + std::string str; + in >> str; + op = ap_int_base<_AP_W, _AP_S>(str.c_str()); + return in; +} +#endif // ifndef __SYNTHESIS__ +#endif // ifndef AP_AUTOCC + +/* Bit reference. + ---------------------------------------------------------------- +*/ +template +struct ap_bit_ref { + // struct ssdm_int or its sim model. + // TODO make it possible to reference to ap_fixed_base/ap_fixed/ap_ufixed + // and then we can retire af_bit_ref. + typedef ap_int_base<_AP_W, _AP_S> ref_type; + ref_type& d_bv; + int d_index; + + public: + // copy ctor + INLINE ap_bit_ref(const ap_bit_ref<_AP_W, _AP_S>& ref) + : d_bv(ref.d_bv), d_index(ref.d_index) {} + + INLINE ap_bit_ref(ref_type* bv, int index = 0) : d_bv(*bv), d_index(index) {} + + INLINE ap_bit_ref(const ref_type* bv, int index = 0) + : d_bv(*const_cast(bv)), d_index(index) {} + + INLINE operator bool() const { return _AP_ROOT_op_get_bit(d_bv.V, d_index); } + INLINE bool to_bool() const { return _AP_ROOT_op_get_bit(d_bv.V, d_index); } + + // assign op from hls supported C integral types. + // FIXME disabled to support sc_signal. + // NOTE this used to be unsigned long long. + //template + //INLINE typename _ap_type::enable_if<_ap_type::is_integral::value, + // ap_bit_ref&>::type + //operator=(T val) { + // d_bv.V = _AP_ROOT_op_set_bit(d_bv.V, d_index, val); + // return *this; + //} +#define ASSIGN_WITH_CTYPE(_Tp) \ + INLINE ap_bit_ref& operator=(_Tp val) { \ + d_bv.V = _AP_ROOT_op_set_bit(d_bv.V, d_index, val); \ + return *this; \ + } + + ASSIGN_WITH_CTYPE(bool) + ASSIGN_WITH_CTYPE(char) + ASSIGN_WITH_CTYPE(signed char) + ASSIGN_WITH_CTYPE(unsigned char) + ASSIGN_WITH_CTYPE(short) + ASSIGN_WITH_CTYPE(unsigned short) + ASSIGN_WITH_CTYPE(int) + ASSIGN_WITH_CTYPE(unsigned int) + ASSIGN_WITH_CTYPE(long) + ASSIGN_WITH_CTYPE(unsigned long) + ASSIGN_WITH_CTYPE(ap_slong) + ASSIGN_WITH_CTYPE(ap_ulong) + +#undef ASSIGN_WITH_CTYPE + +#define ASSIGN_WITH_CTYPE_FP(_Tp) \ + INLINE ap_bit_ref& operator=(_Tp val) { \ + bool tmp_val = val; \ + d_bv.V = _AP_ROOT_op_set_bit(d_bv.V, d_index,tmp_val); \ + return *this; \ + } + +#if _AP_ENABLE_HALF_ == 1 + ASSIGN_WITH_CTYPE_FP(half) +#endif + ASSIGN_WITH_CTYPE_FP(float) + ASSIGN_WITH_CTYPE_FP(double) + +#undef ASSIGN_WITH_CTYPE_FP + + + template + INLINE ap_bit_ref& operator=(const ap_int_base<_AP_W2, _AP_S2>& val) { + return operator=((ap_ulong)(val.V != 0)); + } + + template + INLINE ap_bit_ref& operator=(const ap_range_ref<_AP_W2, _AP_S2>& val) { + return operator=((ap_int_base<_AP_W2, false>)val); + } + + // Be explicit to prevent it from being deleted, as field d_bv + // is of reference type. + INLINE ap_bit_ref& operator=(const ap_bit_ref& val) { + return operator=((ap_ulong)(bool)val); + } + + template + INLINE ap_bit_ref& operator=(const ap_bit_ref<_AP_W2, _AP_S2>& val) { + return operator=((ap_ulong)(bool)val); + } + + template + INLINE ap_bit_ref& operator=( + const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) { + return operator=((const ap_int_base<_AP_W2, false>)val); + } + + template + INLINE ap_bit_ref& operator=( + const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) { + return operator=((ap_ulong)(bool)val); + } + + template + INLINE ap_bit_ref& operator=( + const ap_concat_ref<_AP_W2, _AP_T3, _AP_W3, _AP_T3>& val) { + return operator=((const ap_int_base<_AP_W2 + _AP_W3, false>)val); + } + + template + INLINE ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> > + operator,(ap_int_base<_AP_W2, _AP_S2> &a2) { + return ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >( + *this, a2); + } + + template + INLINE ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> > + operator,(volatile ap_int_base<_AP_W2, _AP_S2> &a2) { + return ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >( + *this, const_cast&>(a2)); + } + + template + INLINE ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> > + operator,(const ap_int_base<_AP_W2, _AP_S2> &a2) { + ap_int_base<_AP_W2, _AP_S2> op(a2); + return ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >( + *this, const_cast&>(op)); + } + + template + INLINE ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> > + operator,(const volatile ap_int_base<_AP_W2, _AP_S2> &a2) { + ap_int_base<_AP_W2, _AP_S2> op(a2); + return ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >( + *this, const_cast&>(op)); + } + + template + INLINE ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_range_ref<_AP_W2, _AP_S2> > + operator,(const ap_range_ref<_AP_W2, _AP_S2> &a2) { + return ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_range_ref<_AP_W2, _AP_S2> >( + *this, const_cast&>(a2)); + } + + template + INLINE ap_concat_ref<1, ap_bit_ref, 1, ap_bit_ref<_AP_W2, _AP_S2> > operator,( + const ap_bit_ref<_AP_W2, _AP_S2> &a2) { + return ap_concat_ref<1, ap_bit_ref, 1, ap_bit_ref<_AP_W2, _AP_S2> >( + *this, const_cast&>(a2)); + } + + template + INLINE ap_concat_ref<1, ap_bit_ref, _AP_W2 + _AP_W3, + ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> > + operator,(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &a2) { + return ap_concat_ref<1, ap_bit_ref, _AP_W2 + _AP_W3, + ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >( + *this, const_cast&>(a2)); + } + + template + INLINE ap_concat_ref< + 1, ap_bit_ref, _AP_W2, + af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> > + operator,( + const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> &a2) { + return ap_concat_ref< + 1, ap_bit_ref, _AP_W2, + af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >( + *this, + const_cast< + af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>&>(a2)); + } + + template + INLINE ap_concat_ref<1, ap_bit_ref, 1, af_bit_ref<_AP_W2, _AP_I2, _AP_S2, + _AP_Q2, _AP_O2, _AP_N2> > + operator,( + const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> &a2) { + return ap_concat_ref<1, ap_bit_ref, 1, af_bit_ref<_AP_W2, _AP_I2, _AP_S2, + _AP_Q2, _AP_O2, _AP_N2> >( + *this, + const_cast&>( + a2)); + } + + template + INLINE bool operator==(const ap_bit_ref<_AP_W2, _AP_S2>& op) { + return get() == op.get(); + } + + template + INLINE bool operator!=(const ap_bit_ref<_AP_W2, _AP_S2>& op) { + return get() != op.get(); + } + + INLINE bool get() const { return _AP_ROOT_op_get_bit(d_bv.V, d_index); } + + INLINE bool get() { return _AP_ROOT_op_get_bit(d_bv.V, d_index); } + + template + INLINE void set(const ap_int_base<_AP_W3, false>& val) { + operator=(val); + } + + INLINE bool operator~() const { + bool bit = _AP_ROOT_op_get_bit(d_bv.V, d_index); + return bit ? false : true; + } + + INLINE int length() const { return 1; } + +#ifndef __SYNTHESIS__ + std::string to_string() const { return get() ? "1" : "0"; } +#else + // XXX HLS will delete this in synthesis + INLINE char* to_string() const { return 0; } +#endif +}; // struct ap_bit_ref + +/* ap_range_ref with int. + * ------------------------------------------------------------ + */ +// equality and relational operators. +#define REF_REL_OP_WITH_INT(REL_OP, C_TYPE, _AP_W2, _AP_S2) \ + template \ + INLINE bool operator REL_OP(const ap_range_ref<_AP_W, _AP_S>& op, \ + C_TYPE op2) { \ + return ap_int_base<_AP_W, false>(op) \ + REL_OP ap_int_base<_AP_W2, _AP_S2>(op2); \ + } \ + template \ + INLINE bool operator REL_OP(const ap_bit_ref<_AP_W, _AP_S>& op, \ + C_TYPE op2) { \ + return bool(op) REL_OP op2; \ + } \ + template \ + INLINE bool operator REL_OP(C_TYPE op2, \ + const ap_bit_ref<_AP_W, _AP_S>& op) { \ + return op2 REL_OP bool(op); \ + } \ + template \ + INLINE bool operator REL_OP( \ + const ap_concat_ref<_AP_W, _AP_T, _AP_W1, _AP_T1>& op, C_TYPE op2) { \ + return ap_int_base<_AP_W + _AP_W1, false>(op) \ + REL_OP ap_int_base<_AP_W2, _AP_S2>(op2); \ + } + +// Make the line shorter than 5000 chars +#define REF_REL_WITH_INT_1(C_TYPE, _AP_WI, _AP_SI) \ + REF_REL_OP_WITH_INT(>, C_TYPE, _AP_WI, _AP_SI) \ + REF_REL_OP_WITH_INT(<, C_TYPE, _AP_WI, _AP_SI) \ + REF_REL_OP_WITH_INT(>=, C_TYPE, _AP_WI, _AP_SI) \ + REF_REL_OP_WITH_INT(<=, C_TYPE, _AP_WI, _AP_SI) + +REF_REL_WITH_INT_1(bool, 1, false) +REF_REL_WITH_INT_1(char, 8, CHAR_IS_SIGNED) +REF_REL_WITH_INT_1(signed char, 8, true) +REF_REL_WITH_INT_1(unsigned char, 8, false) +REF_REL_WITH_INT_1(short, _AP_SIZE_short, true) +REF_REL_WITH_INT_1(unsigned short, _AP_SIZE_short, false) +REF_REL_WITH_INT_1(int, _AP_SIZE_int, true) +REF_REL_WITH_INT_1(unsigned int, _AP_SIZE_int, false) +REF_REL_WITH_INT_1(long, _AP_SIZE_long, true) +REF_REL_WITH_INT_1(unsigned long, _AP_SIZE_long, false) +REF_REL_WITH_INT_1(ap_slong, _AP_SIZE_ap_slong, true) +REF_REL_WITH_INT_1(ap_ulong, _AP_SIZE_ap_slong, false) + +// Make the line shorter than 5000 chars +#define REF_REL_WITH_INT_2(C_TYPE, _AP_WI, _AP_SI) \ + REF_REL_OP_WITH_INT(==, C_TYPE, _AP_WI, _AP_SI) \ + REF_REL_OP_WITH_INT(!=, C_TYPE, _AP_WI, _AP_SI) + +REF_REL_WITH_INT_2(bool, 1, false) +REF_REL_WITH_INT_2(char, 8, CHAR_IS_SIGNED) +REF_REL_WITH_INT_2(signed char, 8, true) +REF_REL_WITH_INT_2(unsigned char, 8, false) +REF_REL_WITH_INT_2(short, _AP_SIZE_short, true) +REF_REL_WITH_INT_2(unsigned short, _AP_SIZE_short, false) +REF_REL_WITH_INT_2(int, _AP_SIZE_int, true) +REF_REL_WITH_INT_2(unsigned int, _AP_SIZE_int, false) +REF_REL_WITH_INT_2(long, _AP_SIZE_long, true) +REF_REL_WITH_INT_2(unsigned long, _AP_SIZE_long, false) +REF_REL_WITH_INT_2(ap_slong, _AP_SIZE_ap_slong, true) +REF_REL_WITH_INT_2(ap_ulong, _AP_SIZE_ap_slong, false) + +#undef REF_REL_OP_WITH_INT +#undef REF_REL_WITH_INT_1 +#undef REF_REL_WITH_INT_2 + +#define REF_BIN_OP_WITH_INT(BIN_OP, RTYPE, C_TYPE, _AP_W2, _AP_S2) \ + template \ + INLINE typename ap_int_base<_AP_W, false>::template RType<_AP_W2, \ + _AP_S2>::RTYPE \ + operator BIN_OP(const ap_range_ref<_AP_W, _AP_S>& op, C_TYPE op2) { \ + return ap_int_base<_AP_W, false>(op) \ + BIN_OP ap_int_base<_AP_W2, _AP_S2>(op2); \ + } \ + template \ + INLINE typename ap_int_base<_AP_W2, _AP_S2>::template RType<_AP_W, \ + false>::RTYPE \ + operator BIN_OP(C_TYPE op2, const ap_range_ref<_AP_W, _AP_S>& op) { \ + return ap_int_base<_AP_W2, _AP_S2>(op2) \ + BIN_OP ap_int_base<_AP_W, false>(op); \ + } + +// arithmetic operators. +#define REF_BIN_OP_WITH_INT_ARITH(C_TYPE, _AP_W2, _AP_S2) \ + REF_BIN_OP_WITH_INT(+, plus, C_TYPE, (_AP_W2), (_AP_S2)) \ + REF_BIN_OP_WITH_INT(-, minus, C_TYPE, (_AP_W2), (_AP_S2)) \ + REF_BIN_OP_WITH_INT(*, mult, C_TYPE, (_AP_W2), (_AP_S2)) \ + REF_BIN_OP_WITH_INT(/, div, C_TYPE, (_AP_W2), (_AP_S2)) \ + REF_BIN_OP_WITH_INT(%, mod, C_TYPE, (_AP_W2), (_AP_S2)) + +REF_BIN_OP_WITH_INT_ARITH(bool, 1, false) +REF_BIN_OP_WITH_INT_ARITH(char, 8, CHAR_IS_SIGNED) +REF_BIN_OP_WITH_INT_ARITH(signed char, 8, true) +REF_BIN_OP_WITH_INT_ARITH(unsigned char, 8, false) +REF_BIN_OP_WITH_INT_ARITH(short, _AP_SIZE_short, true) +REF_BIN_OP_WITH_INT_ARITH(unsigned short, _AP_SIZE_short, false) +REF_BIN_OP_WITH_INT_ARITH(int, _AP_SIZE_int, true) +REF_BIN_OP_WITH_INT_ARITH(unsigned int, _AP_SIZE_int, false) +REF_BIN_OP_WITH_INT_ARITH(long, _AP_SIZE_long, true) +REF_BIN_OP_WITH_INT_ARITH(unsigned long, _AP_SIZE_long, false) +REF_BIN_OP_WITH_INT_ARITH(ap_slong, _AP_SIZE_ap_slong, true) +REF_BIN_OP_WITH_INT_ARITH(ap_ulong, _AP_SIZE_ap_slong, false) + +#undef REF_BIN_OP_WITH_INT_ARITH + +// bitwise and shift operators +#define REF_BIN_OP_WITH_INT_BITS(C_TYPE, _AP_W2, _AP_S2) \ + REF_BIN_OP_WITH_INT(&, logic, C_TYPE, (_AP_W2), (_AP_S2)) \ + REF_BIN_OP_WITH_INT(|, logic, C_TYPE, (_AP_W2), (_AP_S2)) \ + REF_BIN_OP_WITH_INT(^, logic, C_TYPE, (_AP_W2), (_AP_S2)) \ + REF_BIN_OP_WITH_INT(>>, arg1, C_TYPE, (_AP_W2), (_AP_S2)) \ + REF_BIN_OP_WITH_INT(<<, arg1, C_TYPE, (_AP_W2), (_AP_S2)) + +REF_BIN_OP_WITH_INT_BITS(bool, 1, false) +REF_BIN_OP_WITH_INT_BITS(char, 8, CHAR_IS_SIGNED) +REF_BIN_OP_WITH_INT_BITS(signed char, 8, true) +REF_BIN_OP_WITH_INT_BITS(unsigned char, 8, false) +REF_BIN_OP_WITH_INT_BITS(short, _AP_SIZE_short, true) +REF_BIN_OP_WITH_INT_BITS(unsigned short, _AP_SIZE_short, false) +REF_BIN_OP_WITH_INT_BITS(int, _AP_SIZE_int, true) +REF_BIN_OP_WITH_INT_BITS(unsigned int, _AP_SIZE_int, false) +REF_BIN_OP_WITH_INT_BITS(long, _AP_SIZE_long, true) +REF_BIN_OP_WITH_INT_BITS(unsigned long, _AP_SIZE_long, false) +REF_BIN_OP_WITH_INT_BITS(ap_slong, _AP_SIZE_ap_slong, true) +REF_BIN_OP_WITH_INT_BITS(ap_ulong, _AP_SIZE_ap_slong, false) + +#undef REF_BIN_OP_WITH_INT_BITS + +/* ap_range_ref with ap_range_ref + * ------------------------------------------------------------ + */ +#define REF_BIN_OP(BIN_OP, RTYPE) \ + template \ + INLINE \ + typename ap_int_base<_AP_W, false>::template RType<_AP_W2, false>::RTYPE \ + operator BIN_OP(const ap_range_ref<_AP_W, _AP_S>& lhs, \ + const ap_range_ref<_AP_W2, _AP_S2>& rhs) { \ + return (lhs.operator ap_int_base<_AP_W, false>())BIN_OP( \ + rhs.operator ap_int_base<_AP_W2, false>()); \ + } + +REF_BIN_OP(+, plus) +REF_BIN_OP(-, minus) +REF_BIN_OP(*, mult) +REF_BIN_OP(/, div) +REF_BIN_OP(%, mod) +REF_BIN_OP(&, logic) +REF_BIN_OP(|, logic) +REF_BIN_OP(^, logic) +REF_BIN_OP(>>, arg1) +REF_BIN_OP(<<, arg1) + +/* ap_concat_ref with ap_concat_ref. + * ------------------------------------------------------------ + */ + +//************************************************************************ +// Implement +// ap_int_base = ap_concat_ref OP ap_concat_ref +// for operators +, -, *, /, %, >>, <<, &, |, ^ +// Without these operators the operands are converted to int64 and +// larger results lose informations (higher order bits). +// +// operand OP +// / | +// left-concat right-concat +// / | / | +// +// +// _AP_LW1, _AP_LT1 (width and type of left-concat's left side) +// _AP_LW2, _AP_LT2 (width and type of left-concat's right side) +// Similarly for RHS of operand OP: _AP_RW1, AP_RW2, _AP_RT1, _AP_RT2 +// +// In Verilog 2001 result of concatenation is always unsigned even +// when both sides are signed. +//************************************************************************ + +#undef SYN_CONCAT_REF_BIN_OP + +#define SYN_CONCAT_REF_BIN_OP(BIN_OP, RTYPE) \ + template \ + INLINE typename ap_int_base<_AP_LW1 + _AP_LW2, false>::template RType< \ + _AP_RW1 + _AP_RW2, false>::RTYPE \ + operator BIN_OP( \ + const ap_concat_ref<_AP_LW1, _AP_LT1, _AP_LW2, _AP_LT2>& lhs, \ + const ap_concat_ref<_AP_RW1, _AP_RT1, _AP_RW2, _AP_RT2>& rhs) { \ + return lhs.get() BIN_OP rhs.get(); \ + } + +SYN_CONCAT_REF_BIN_OP(+, plus) +SYN_CONCAT_REF_BIN_OP(-, minus) +SYN_CONCAT_REF_BIN_OP(*, mult) +SYN_CONCAT_REF_BIN_OP(/, div) +SYN_CONCAT_REF_BIN_OP(%, mod) +SYN_CONCAT_REF_BIN_OP(&, logic) +SYN_CONCAT_REF_BIN_OP(|, logic) +SYN_CONCAT_REF_BIN_OP(^, logic) +SYN_CONCAT_REF_BIN_OP(>>, arg1) +SYN_CONCAT_REF_BIN_OP(<<, arg1) + +#undef SYN_CONCAT_REF_BIN_OP + +#define CONCAT_OP_WITH_INT(C_TYPE, _AP_WI, _AP_SI) \ + template \ + INLINE ap_int_base<_AP_W + _AP_WI, false> operator,( \ + const ap_int_base<_AP_W, _AP_S> &op1, C_TYPE op2) { \ + ap_int_base<_AP_WI + _AP_W, false> val(op2); \ + ap_int_base<_AP_WI + _AP_W, false> ret(op1); \ + ret <<= _AP_WI; \ + if (_AP_SI) { \ + val <<= _AP_W; \ + val >>= _AP_W; \ + } \ + ret |= val; \ + return ret; \ + } \ + template \ + INLINE ap_int_base<_AP_W + _AP_WI, false> operator,( \ + C_TYPE op1, const ap_int_base<_AP_W, _AP_S> &op2) { \ + ap_int_base<_AP_WI + _AP_W, false> val(op1); \ + ap_int_base<_AP_WI + _AP_W, false> ret(op2); \ + if (_AP_S) { \ + ret <<= _AP_WI; \ + ret >>= _AP_WI; \ + } \ + ret |= val << _AP_W; \ + return ret; \ + } \ + template \ + INLINE ap_int_base<_AP_W + _AP_WI, false> operator,( \ + const ap_range_ref<_AP_W, _AP_S> &op1, C_TYPE op2) { \ + ap_int_base<_AP_WI + _AP_W, false> val(op2); \ + ap_int_base<_AP_WI + _AP_W, false> ret(op1); \ + ret <<= _AP_WI; \ + if (_AP_SI) { \ + val <<= _AP_W; \ + val >>= _AP_W; \ + } \ + ret |= val; \ + return ret; \ + } \ + template \ + INLINE ap_int_base<_AP_W + _AP_WI, false> operator,( \ + C_TYPE op1, const ap_range_ref<_AP_W, _AP_S> &op2) { \ + ap_int_base<_AP_WI + _AP_W, false> val(op1); \ + ap_int_base<_AP_WI + _AP_W, false> ret(op2); \ + int len = op2.length(); \ + val <<= len; \ + ret |= val; \ + return ret; \ + } \ + template \ + INLINE ap_int_base<_AP_WI + 1, false> operator,( \ + const ap_bit_ref<_AP_W, _AP_S> &op1, C_TYPE op2) { \ + ap_int_base<_AP_WI + 1, false> val(op2); \ + val[_AP_WI] = op1; \ + return val; \ + } \ + template \ + INLINE ap_int_base<_AP_WI + 1, false> operator,( \ + C_TYPE op1, const ap_bit_ref<_AP_W, _AP_S> &op2) { \ + ap_int_base<_AP_WI + 1, false> val(op1); \ + val <<= 1; \ + val[0] = op2; \ + return val; \ + } \ + template \ + INLINE ap_int_base<_AP_W + _AP_W2 + _AP_WI, false> operator,( \ + const ap_concat_ref<_AP_W, _AP_T, _AP_W2, _AP_T2> &op1, C_TYPE op2) { \ + ap_int_base<_AP_WI + _AP_W + _AP_W2, _AP_SI> val(op2); \ + ap_int_base<_AP_WI + _AP_W + _AP_W2, _AP_SI> ret(op1); \ + if (_AP_SI) { \ + val <<= _AP_W + _AP_W2; \ + val >>= _AP_W + _AP_W2; \ + } \ + ret <<= _AP_WI; \ + ret |= val; \ + return ret; \ + } \ + template \ + INLINE ap_int_base<_AP_W + _AP_W2 + _AP_WI, false> operator,( \ + C_TYPE op1, const ap_concat_ref<_AP_W, _AP_T, _AP_W2, _AP_T2> &op2) { \ + ap_int_base<_AP_WI + _AP_W + _AP_W2, _AP_SI> val(op1); \ + ap_int_base<_AP_WI + _AP_W + _AP_W2, _AP_SI> ret(op2); \ + int len = op2.length(); \ + val <<= len; \ + ret |= val; \ + return ret; \ + } \ + template \ + INLINE ap_int_base<_AP_W + _AP_WI, false> operator,( \ + const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op1, \ + C_TYPE op2) { \ + ap_int_base<_AP_WI + _AP_W, false> val(op2); \ + ap_int_base<_AP_WI + _AP_W, false> ret(op1); \ + if (_AP_SI) { \ + val <<= _AP_W; \ + val >>= _AP_W; \ + } \ + ret <<= _AP_WI; \ + ret |= val; \ + return ret; \ + } \ + template \ + INLINE ap_int_base<_AP_W + _AP_WI, false> operator,( \ + C_TYPE op1, \ + const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op2) { \ + ap_int_base<_AP_WI + _AP_W, false> val(op1); \ + ap_int_base<_AP_WI + _AP_W, false> ret(op2); \ + int len = op2.length(); \ + val <<= len; \ + ret |= val; \ + return ret; \ + } \ + template \ + INLINE ap_int_base<1 + _AP_WI, false> operator,( \ + const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op1, \ + C_TYPE op2) { \ + ap_int_base<_AP_WI + 1, _AP_SI> val(op2); \ + val[_AP_WI] = op1; \ + return val; \ + } \ + template \ + INLINE ap_int_base<1 + _AP_WI, false> operator,( \ + C_TYPE op1, \ + const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op2) { \ + ap_int_base<_AP_WI + 1, _AP_SI> val(op1); \ + val <<= 1; \ + val[0] = op2; \ + return val; \ + } + +CONCAT_OP_WITH_INT(bool, 1, false) +CONCAT_OP_WITH_INT(char, 8, CHAR_IS_SIGNED) +CONCAT_OP_WITH_INT(signed char, 8, true) +CONCAT_OP_WITH_INT(unsigned char, 8, false) +CONCAT_OP_WITH_INT(short, _AP_SIZE_short, true) +CONCAT_OP_WITH_INT(unsigned short, _AP_SIZE_short, false) +CONCAT_OP_WITH_INT(int, _AP_SIZE_int, true) +CONCAT_OP_WITH_INT(unsigned int, _AP_SIZE_int, false) +CONCAT_OP_WITH_INT(long, _AP_SIZE_long, true) +CONCAT_OP_WITH_INT(unsigned long, _AP_SIZE_long, false) +CONCAT_OP_WITH_INT(ap_slong, _AP_SIZE_ap_slong, true) +CONCAT_OP_WITH_INT(ap_ulong, _AP_SIZE_ap_slong, false) + +#undef CONCAT_OP_WITH_INT + +#define CONCAT_SHIFT_WITH_INT(C_TYPE, OP) \ + template \ + INLINE ap_uint<_AP_W + _AP_W1> operator OP( \ + const ap_concat_ref<_AP_W, _AP_T, _AP_W1, _AP_T1> lhs, C_TYPE rhs) { \ + return ap_uint<_AP_W + _AP_W1>(lhs).get() OP int(rhs); \ + } + +// FIXME int(rhs) may loose precision. + +CONCAT_SHIFT_WITH_INT(int, <<) +CONCAT_SHIFT_WITH_INT(unsigned int, <<) +CONCAT_SHIFT_WITH_INT(long, <<) +CONCAT_SHIFT_WITH_INT(unsigned long, <<) +CONCAT_SHIFT_WITH_INT(ap_slong, <<) +CONCAT_SHIFT_WITH_INT(ap_ulong, <<) + +CONCAT_SHIFT_WITH_INT(int, >>) +CONCAT_SHIFT_WITH_INT(unsigned int, >>) +CONCAT_SHIFT_WITH_INT(long, >>) +CONCAT_SHIFT_WITH_INT(unsigned long, >>) +CONCAT_SHIFT_WITH_INT(ap_slong, >>) +CONCAT_SHIFT_WITH_INT(ap_ulong, >>) + +#endif // ifndef __cplusplus +#endif // ifndef __AP_INT_REF_H__ + +// -*- cpp -*- diff --git a/firmware/ap_types/ap_int_special.h b/firmware/ap_types/ap_int_special.h new file mode 100644 index 0000000000000000000000000000000000000000..3afc6192bae84676443f0375a9caf42ffadd3c7e --- /dev/null +++ b/firmware/ap_types/ap_int_special.h @@ -0,0 +1,223 @@ +/* + * Copyright 2011-2019 Xilinx, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __AP_INT_SPECIAL_H__ +#define __AP_INT_SPECIAL_H__ + +#ifndef __AP_INT_H__ +#error "Only ap_fixed.h and ap_int.h can be included directly in user code." +#endif + +#ifndef __SYNTHESIS__ +#include +#include +#endif +// FIXME AP_AUTOCC cannot handle many standard headers, so declare instead of +// include. +// #include +namespace std { +template class complex; +} + +/* + TODO: Modernize the code using C++11/C++14 + 1. constexpr http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2016/p0415r0.html + 2. move constructor +*/ + +namespace std { +/* + Specialize std::complex to zero initialization ap_int. + + To reduce the area cost, ap_int is not zero initialized, just like basic + types float or double. However, libstdc++ provides specialization for float, + double and long double, initializing image part to 0 when not specified. + + This has become a difficulty in switching legacy code from these C types to + ap_int. To ease the tranform of legacy code, we have to implement + specialization of std::complex<> for our type. + + As ap_int is a template, it is impossible to specialize only the methods + that causes default initialization of value type in std::complex<>. An + explicit full specialization of the template class has to be done, covering + all the member functions and operators of std::complex<> as specified + in standard 26.2.4 and 26.2.5. +*/ +template +class complex > { + public: + typedef ap_int<_AP_W> _Tp; + typedef _Tp value_type; + + // 26.2.4/1 + // Constructor without argument + // Default initialize, so that in dataflow, the variable is only written once. + complex() : _M_real(_Tp()), _M_imag(_Tp()) {} + // Constructor with ap_int. + // Zero initialize image part when not specified, so that `C(1) == C(1,0)` + complex(const _Tp &__r, const _Tp &__i = _Tp(0)) + : _M_real(__r), _M_imag(__i) {} + + // Constructor with another complex number + template + complex(const complex<_Up> &__z) : _M_real(__z.real()), _M_imag(__z.imag()) {} + +#if __cplusplus >= 201103L + const _Tp& real() const { return _M_real; } + const _Tp& imag() const { return _M_imag; } +#else + _Tp& real() { return _M_real; } + const _Tp& real() const { return _M_real; } + _Tp& imag() { return _M_imag; } + const _Tp& imag() const { return _M_imag; } +#endif + + void real(_Tp __val) { _M_real = __val; } + + void imag(_Tp __val) { _M_imag = __val; } + + // Assign this complex number with ap_int. + // Zero initialize image poarrt, so that `C c; c = 1; c == C(1,0);` + complex<_Tp> &operator=(const _Tp __t) { + _M_real = __t; + _M_imag = _Tp(0); + return *this; + } + + // 26.2.5/1 + // Add ap_int to this complex number. + complex<_Tp> &operator+=(const _Tp &__t) { + _M_real += __t; + return *this; + } + + // 26.2.5/3 + // Subtract ap_int from this complex number. + complex<_Tp> &operator-=(const _Tp &__t) { + _M_real -= __t; + return *this; + } + + // 26.2.5/5 + // Multiply this complex number by ap_int. + complex<_Tp> &operator*=(const _Tp &__t) { + _M_real *= __t; + _M_imag *= __t; + return *this; + } + + // 26.2.5/7 + // Divide this complex number by ap_int. + complex<_Tp> &operator/=(const _Tp &__t) { + _M_real /= __t; + _M_imag /= __t; + return *this; + } + + // Assign complex number to this complex number. + template + complex<_Tp> &operator=(const complex<_Up> &__z) { + _M_real = __z.real(); + _M_imag = __z.imag(); + return *this; + } + + // 26.2.5/9 + // Add complex number to this. + template + complex<_Tp> &operator+=(const complex<_Up> &__z) { + _M_real += __z.real(); + _M_imag += __z.imag(); + return *this; + } + + // 26.2.5/11 + // Subtract complex number from this. + template + complex<_Tp> &operator-=(const complex<_Up> &__z) { + _M_real -= __z.real(); + _M_imag -= __z.imag(); + return *this; + } + + // 26.2.5/13 + // Multiply this by complex number. + template + complex<_Tp> &operator*=(const complex<_Up> &__z) { + const _Tp __r = _M_real * __z.real() - _M_imag * __z.imag(); + _M_imag = _M_real * __z.imag() + _M_imag * __z.real(); + _M_real = __r; + return *this; + } + + // 26.2.5/15 + // Divide this by complex number. + template + complex<_Tp> &operator/=(const complex<_Up> &__z) { + complex<_Tp> cj (__z.real(), -__z.imag()); + complex<_Tp> a = (*this) * cj; + complex<_Tp> b = cj * __z; + _M_real = a.real() / b.real(); + _M_imag = a.imag() / b.real(); + return *this; + } + + private: + _Tp _M_real; + _Tp _M_imag; + +}; // class complex > + + +/* + Non-member operations + These operations are not required by standard in 26.2.6, but libstdc++ + defines them for + float, double or long double's specialization. +*/ +// Compare complex number with ap_int. +template +inline bool operator==(const complex > &__x, const ap_int<_AP_W> &__y) { + return __x.real() == __y && + __x.imag() == 0; +} + +// Compare ap_int with complex number. +template +inline bool operator==(const ap_int<_AP_W> &__x, const complex > &__y) { + return __x == __y.real() && + 0 == __y.imag(); +} + +// Compare complex number with ap_int. +template +inline bool operator!=(const complex > &__x, const ap_int<_AP_W> &__y) { + return __x.real() != __y || + __x.imag() != 0; +} + +// Compare ap_int with complex number. +template +inline bool operator!=(const ap_int<_AP_W> &__x, const complex > &__y) { + return __x != __y.real() || + 0 != __y.imag(); +} + +} // namespace std + +#endif // ifndef __AP_INT_SPECIAL_H__ + +// -*- cpp -*- diff --git a/firmware/ap_types/ap_shift_reg.h b/firmware/ap_types/ap_shift_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..94dba51e469c07ecca4655de84683062577c834f --- /dev/null +++ b/firmware/ap_types/ap_shift_reg.h @@ -0,0 +1,138 @@ +/* +#- (c) Copyright 2011-2019 Xilinx, Inc. All rights reserved. +#- +#- This file contains confidential and proprietary information +#- of Xilinx, Inc. and is protected under U.S. and +#- international copyright and other intellectual property +#- laws. +#- +#- DISCLAIMER +#- This disclaimer is not a license and does not grant any +#- rights to the materials distributed herewith. Except as +#- otherwise provided in a valid license issued to you by +#- Xilinx, and to the maximum extent permitted by applicable +#- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +#- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +#- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +#- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +#- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +#- (2) Xilinx shall not be liable (whether in contract or tort, +#- including negligence, or under any other theory of +#- liability) for any loss or damage of any kind or nature +#- related to, arising under or in connection with these +#- materials, including for any direct, or any indirect, +#- special, incidental, or consequential loss or damage +#- (including loss of data, profits, goodwill, or any type of +#- loss or damage suffered as a result of any action brought +#- by a third party) even if such damage or loss was +#- reasonably foreseeable or Xilinx had been advised of the +#- possibility of the same. +#- +#- CRITICAL APPLICATIONS +#- Xilinx products are not designed or intended to be fail- +#- safe, or for use in any application requiring fail-safe +#- performance, such as life-support or safety devices or +#- systems, Class III medical devices, nuclear facilities, +#- applications related to the deployment of airbags, or any +#- other applications that could lead to death, personal +#- injury, or severe property or environmental damage +#- (individually and collectively, "Critical +#- Applications"). Customer assumes the sole risk and +#- liability of any use of Xilinx products in Critical +#- Applications, subject only to applicable laws and +#- regulations governing limitations on product liability. +#- +#- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +#- PART OF THIS FILE AT ALL TIMES. +#- ************************************************************************ + + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef __SIM_AP_SHIFT_REG_H__ +#define __SIM_AP_SHIFT_REG_H__ + + +/* + * This file contains a C++ model of shift register. + * It defines C level simulation model. + */ +#ifndef __cplusplus +#error C++ is required to include this header file +#else + +#include + +////////////////////////////////////////////// +// C level simulation model for ap_shift_reg +////////////////////////////////////////////// +template +class ap_shift_reg +{ + public: + /// Constructors + ap_shift_reg() { } + ap_shift_reg(const char* name) { } + /// Destructor + virtual ~ap_shift_reg() { } + + private: + /// Make copy constructor and assignment operator private + ap_shift_reg(const ap_shift_reg< __SHIFT_T__, __SHIFT_DEPTH__ >& shreg) + { + for (unsigned i = 0; i < __SHIFT_DEPTH__; ++i) + Array[i] = shreg.Array[i]; + } + + ap_shift_reg& operator = (const ap_shift_reg< __SHIFT_T__, + __SHIFT_DEPTH__ >& shreg) + { + for (unsigned i = 0; i < __SHIFT_DEPTH__; ++i) + Array[i] = shreg.Array[i]; + return *this; + } + + public: + // Shift the queue, push to back and read from a given address. + __SHIFT_T__ shift(__SHIFT_T__ DataIn, + unsigned int Addr = __SHIFT_DEPTH__ - 1, bool Enable = true) + { + assert(Addr < __SHIFT_DEPTH__ && + "Out-of-bound shift is found in ap_shift_reg."); + __SHIFT_T__ ret = Array[Addr]; + if (Enable) { + for (unsigned int i = __SHIFT_DEPTH__ - 1; i > 0; --i) + Array[i] = Array[i-1]; + Array[0] = DataIn; + } + return ret; + } + + // Read from a given address. + __SHIFT_T__ read(unsigned int Addr = __SHIFT_DEPTH__ - 1) const + { + assert(Addr < __SHIFT_DEPTH__ && + "Out-of-bound read is found in ap_shift_reg."); + return Array[Addr]; + } + + protected: + __SHIFT_T__ Array[__SHIFT_DEPTH__]; +}; + +#endif //__cplusplus + +#endif //__SIM_AP_SHIFT_REG_H__ + + diff --git a/firmware/ap_types/etc/ap_private.h b/firmware/ap_types/etc/ap_private.h new file mode 100644 index 0000000000000000000000000000000000000000..0c29a0ac1a65e671bf7b4509f58d452c83855e28 --- /dev/null +++ b/firmware/ap_types/etc/ap_private.h @@ -0,0 +1,7199 @@ +/* + * Copyright 2011-2019 Xilinx, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __AP_PRIVATE_H__ +#define __AP_PRIVATE_H__ + +// common macros and type declarations are now defined in ap_common.h, and +// ap_private becomes part of it. +#ifndef __AP_COMMON_H__ +#error "etc/ap_private.h cannot be included directly." +#endif + +// forward declarations +//template +//class ap_private; // moved to ap_common.h +template +struct _private_range_ref; +template +struct _private_bit_ref; + +// TODO clean up this part. +#ifndef LLVM_SUPPORT_MATHEXTRAS_H +#define LLVM_SUPPORT_MATHEXTRAS_H + +#ifdef _MSC_VER +#if _MSC_VER <= 1500 +typedef __int8 int8_t; +typedef unsigned __int8 uint8_t; +typedef __int16 int16_t; +typedef unsigned __int16 uint16_t; +typedef __int32 int32_t; +typedef unsigned __int32 uint32_t; +typedef __int64 int64_t; +typedef unsigned __int64 uint64_t; +#else +#include +#endif +#else +#include +#endif + +#ifndef INLINE +#define INLINE inline +// Enable to debug ap_int/ap_fixed +// #define INLINE __attribute__((weak)) +#endif + +// NOTE: The following support functions use the _32/_64 extensions instead of +// type overloading so that signed and unsigned integers can be used without +// ambiguity. +namespace AESL_std { +template +DataType INLINE min(DataType a, DataType b) { + return (a >= b) ? b : a; +} + +template +DataType INLINE max(DataType a, DataType b) { + return (a >= b) ? a : b; +} +} // namespace AESL_std + +// TODO clean up included headers. +#include +#include +#include +#include +#include +#include +#include +#include +#include + +namespace ap_private_ops { +/// Hi_32 - This function returns the high 32 bits of a 64 bit value. +static INLINE uint32_t Hi_32(uint64_t Value) { + return static_cast(Value >> 32); +} + +/// Lo_32 - This function returns the low 32 bits of a 64 bit value. +static INLINE uint32_t Lo_32(uint64_t Value) { + return static_cast(Value); +} + +template +INLINE bool isNegative(const ap_private<_AP_W, false>& a) { + return false; +} + +template +INLINE bool isNegative(const ap_private<_AP_W, true>& a) { + enum { + APINT_BITS_PER_WORD = 64, + _AP_N = (_AP_W + APINT_BITS_PER_WORD - 1) / APINT_BITS_PER_WORD + }; + static const uint64_t sign_mask = 1ULL << ((_AP_W - 1) % APINT_BITS_PER_WORD); + return (sign_mask & a.get_pVal(_AP_N - 1)) != 0; +} + +/// CountLeadingZeros_32 - this function performs the platform optimal form of +/// counting the number of zeros from the most significant bit to the first one +/// bit. Ex. CountLeadingZeros_32(0x00F000FF) == 8. +/// Returns 32 if the word is zero. +static INLINE unsigned CountLeadingZeros_32(uint32_t Value) { + unsigned Count; // result +#if __GNUC__ >= 4 +// PowerPC is defined for __builtin_clz(0) +#if !defined(__ppc__) && !defined(__ppc64__) + if (Value == 0) return 32; +#endif + Count = __builtin_clz(Value); +#else + if (Value == 0) return 32; + Count = 0; + // bisecton method for count leading zeros + for (unsigned Shift = 32 >> 1; Shift; Shift >>= 1) { + uint32_t Tmp = (Value) >> (Shift); + if (Tmp) { + Value = Tmp; + } else { + Count |= Shift; + } + } +#endif + return Count; +} + +/// CountLeadingZeros_64 - This function performs the platform optimal form +/// of counting the number of zeros from the most significant bit to the first +/// one bit (64 bit edition.) +/// Returns 64 if the word is zero. +static INLINE unsigned CountLeadingZeros_64(uint64_t Value) { + unsigned Count; // result +#if __GNUC__ >= 4 +// PowerPC is defined for __builtin_clzll(0) +#if !defined(__ppc__) && !defined(__ppc64__) + if (!Value) return 64; +#endif + Count = __builtin_clzll(Value); +#else + if (sizeof(long) == sizeof(int64_t)) { + if (!Value) return 64; + Count = 0; + // bisecton method for count leading zeros + for (unsigned Shift = 64 >> 1; Shift; Shift >>= 1) { + uint64_t Tmp = (Value) >> (Shift); + if (Tmp) { + Value = Tmp; + } else { + Count |= Shift; + } + } + } else { + // get hi portion + uint32_t Hi = Hi_32(Value); + + // if some bits in hi portion + if (Hi) { + // leading zeros in hi portion plus all bits in lo portion + Count = CountLeadingZeros_32(Hi); + } else { + // get lo portion + uint32_t Lo = Lo_32(Value); + // same as 32 bit value + Count = CountLeadingZeros_32(Lo) + 32; + } + } +#endif + return Count; +} + +/// CountTrailingZeros_64 - This function performs the platform optimal form +/// of counting the number of zeros from the least significant bit to the first +/// one bit (64 bit edition.) +/// Returns 64 if the word is zero. +static INLINE unsigned CountTrailingZeros_64(uint64_t Value) { +#if __GNUC__ >= 4 + return (Value != 0) ? __builtin_ctzll(Value) : 64; +#else + static const unsigned Mod67Position[] = { + 64, 0, 1, 39, 2, 15, 40, 23, 3, 12, 16, 59, 41, 19, 24, 54, 4, + 64, 13, 10, 17, 62, 60, 28, 42, 30, 20, 51, 25, 44, 55, 47, 5, 32, + 65, 38, 14, 22, 11, 58, 18, 53, 63, 9, 61, 27, 29, 50, 43, 46, 31, + 37, 21, 57, 52, 8, 26, 49, 45, 36, 56, 7, 48, 35, 6, 34, 33, 0}; + return Mod67Position[(uint64_t)(-(int64_t)Value & (int64_t)Value) % 67]; +#endif +} + +/// CountPopulation_64 - this function counts the number of set bits in a value, +/// (64 bit edition.) +static INLINE unsigned CountPopulation_64(uint64_t Value) { +#if __GNUC__ >= 4 + return __builtin_popcountll(Value); +#else + uint64_t v = Value - (((Value) >> 1) & 0x5555555555555555ULL); + v = (v & 0x3333333333333333ULL) + (((v) >> 2) & 0x3333333333333333ULL); + v = (v + ((v) >> 4)) & 0x0F0F0F0F0F0F0F0FULL; + return unsigned((uint64_t)(v * 0x0101010101010101ULL) >> 56); +#endif +} + +static INLINE uint32_t countLeadingOnes_64(uint64_t __V, uint32_t skip) { + uint32_t Count = 0; + if (skip) (__V) <<= (skip); + while (__V && (__V & (1ULL << 63))) { + Count++; + (__V) <<= 1; + } + return Count; +} + +static INLINE std::string oct2Bin(char oct) { + switch (oct) { + case '\0': { + return ""; + } + case '.': { + return "."; + } + case '0': { + return "000"; + } + case '1': { + return "001"; + } + case '2': { + return "010"; + } + case '3': { + return "011"; + } + case '4': { + return "100"; + } + case '5': { + return "101"; + } + case '6': { + return "110"; + } + case '7': { + return "111"; + } + } + assert(0 && "Invalid character in digit string"); + return ""; +} + +static INLINE std::string hex2Bin(char hex) { + switch (hex) { + case '\0': { + return ""; + } + case '.': { + return "."; + } + case '0': { + return "0000"; + } + case '1': { + return "0001"; + } + case '2': { + return "0010"; + } + case '3': { + return "0011"; + } + case '4': { + return "0100"; + } + case '5': { + return "0101"; + } + case '6': { + return "0110"; + } + case '7': { + return "0111"; + } + case '8': { + return "1000"; + } + case '9': { + return "1001"; + } + case 'A': + case 'a': { + return "1010"; + } + case 'B': + case 'b': { + return "1011"; + } + case 'C': + case 'c': { + return "1100"; + } + case 'D': + case 'd': { + return "1101"; + } + case 'E': + case 'e': { + return "1110"; + } + case 'F': + case 'f': { + return "1111"; + } + } + assert(0 && "Invalid character in digit string"); + return ""; +} + +static INLINE uint32_t decode_digit(char cdigit, int radix) { + uint32_t digit = 0; + if (radix == 16) { +#define isxdigit(c) \ + (((c) >= '0' && (c) <= '9') || ((c) >= 'a' && (c) <= 'f') || \ + ((c) >= 'A' && (c) <= 'F')) +#define isdigit(c) ((c) >= '0' && (c) <= '9') + if (!isxdigit(cdigit)) assert(0 && "Invalid hex digit in string"); + if (isdigit(cdigit)) + digit = cdigit - '0'; + else if (cdigit >= 'a') + digit = cdigit - 'a' + 10; + else if (cdigit >= 'A') + digit = cdigit - 'A' + 10; + else + assert(0 && "huh? we shouldn't get here"); + } else if (isdigit(cdigit)) { + digit = cdigit - '0'; + } else { + assert(0 && "Invalid character in digit string"); + } +#undef isxdigit +#undef isdigit + return digit; +} + +// Determine the radix of "val". +static INLINE std::string parseString(const std::string& input, unsigned char& radix) { + size_t len = input.length(); + if (len == 0) { + if (radix == 0) radix = 10; + return input; + } + + size_t startPos = 0; + // Trim whitespace + while (input[startPos] == ' ' && startPos < len) startPos++; + while (input[len - 1] == ' ' && startPos < len) len--; + + std::string val = input.substr(startPos, len - startPos); + // std::cout << "val = " << val << "\n"; + len = val.length(); + startPos = 0; + + // If the length of the string is less than 2, then radix + // is decimal and there is no exponent. + if (len < 2) { + if (radix == 0) radix = 10; + return val; + } + + bool isNegative = false; + std::string ans; + + // First check to see if we start with a sign indicator + if (val[0] == '-') { + ans = "-"; + ++startPos; + isNegative = true; + } else if (val[0] == '+') + ++startPos; + + if (len - startPos < 2) { + if (radix == 0) radix = 10; + return val; + } + + if (val.substr(startPos, 2) == "0x" || val.substr(startPos, 2) == "0X") { + // If we start with "0x", then the radix is hex. + radix = 16; + startPos += 2; + } else if (val.substr(startPos, 2) == "0b" || + val.substr(startPos, 2) == "0B") { + // If we start with "0b", then the radix is binary. + radix = 2; + startPos += 2; + } else if (val.substr(startPos, 2) == "0o" || + val.substr(startPos, 2) == "0O") { + // If we start with "0o", then the radix is octal. + radix = 8; + startPos += 2; + } else if (radix == 0) { + radix = 10; + } + + int exp = 0; + if (radix == 10) { + // If radix is decimal, then see if there is an + // exponent indicator. + size_t expPos = val.find('e'); + bool has_exponent = true; + if (expPos == std::string::npos) expPos = val.find('E'); + if (expPos == std::string::npos) { + // No exponent indicator, so the mantissa goes to the end. + expPos = len; + has_exponent = false; + } + // std::cout << "startPos = " << startPos << " " << expPos << "\n"; + + ans += val.substr(startPos, expPos - startPos); + if (has_exponent) { + // Parse the exponent. + std::istringstream iss(val.substr(expPos + 1, len - expPos - 1)); + iss >> exp; + } + } else { + // Check for a binary exponent indicator. + size_t expPos = val.find('p'); + bool has_exponent = true; + if (expPos == std::string::npos) expPos = val.find('P'); + if (expPos == std::string::npos) { + // No exponent indicator, so the mantissa goes to the end. + expPos = len; + has_exponent = false; + } + + // std::cout << "startPos = " << startPos << " " << expPos << "\n"; + + assert(startPos <= expPos); + // Convert to binary as we go. + for (size_t i = startPos; i < expPos; ++i) { + if (radix == 16) { + ans += hex2Bin(val[i]); + } else if (radix == 8) { + ans += oct2Bin(val[i]); + } else { // radix == 2 + ans += val[i]; + } + } + // End in binary + radix = 2; + if (has_exponent) { + // Parse the exponent. + std::istringstream iss(val.substr(expPos + 1, len - expPos - 1)); + iss >> exp; + } + } + if (exp == 0) return ans; + + size_t decPos = ans.find('.'); + if (decPos == std::string::npos) decPos = ans.length(); + if ((int)decPos + exp >= (int)ans.length()) { + int i = decPos; + for (; i < (int)ans.length() - 1; ++i) ans[i] = ans[i + 1]; + for (; i < (int)ans.length(); ++i) ans[i] = '0'; + for (; i < (int)decPos + exp; ++i) ans += '0'; + return ans; + } else if ((int)decPos + exp < (int)isNegative) { + std::string dupAns = "0."; + if (ans[0] == '-') dupAns = "-0."; + for (int i = 0; i < isNegative - (int)decPos - exp; ++i) dupAns += '0'; + for (size_t i = isNegative; i < ans.length(); ++i) + if (ans[i] != '.') dupAns += ans[i]; + return dupAns; + } + + if (exp > 0) + for (size_t i = decPos; i < decPos + exp; ++i) ans[i] = ans[i + 1]; + else { + if (decPos == ans.length()) ans += ' '; + for (int i = decPos; i > (int)decPos + exp; --i) ans[i] = ans[i - 1]; + } + ans[decPos + exp] = '.'; + return ans; +} + +/// sub_1 - This function subtracts a single "digit" (64-bit word), y, from +/// the multi-digit integer array, x[], propagating the borrowed 1 value until +/// no further borrowing is neeeded or it runs out of "digits" in x. The result +/// is 1 if "borrowing" exhausted the digits in x, or 0 if x was not exhausted. +/// In other words, if y > x then this function returns 1, otherwise 0. +/// @returns the borrow out of the subtraction +static INLINE bool sub_1(uint64_t x[], uint32_t len, uint64_t y) { + for (uint32_t i = 0; i < len; ++i) { + uint64_t __X = x[i]; + x[i] -= y; + if (y > __X) + y = 1; // We have to "borrow 1" from next "digit" + else { + y = 0; // No need to borrow + break; // Remaining digits are unchanged so exit early + } + } + return (y != 0); +} + +/// add_1 - This function adds a single "digit" integer, y, to the multiple +/// "digit" integer array, x[]. x[] is modified to reflect the addition and +/// 1 is returned if there is a carry out, otherwise 0 is returned. +/// @returns the carry of the addition. +static INLINE bool add_1(uint64_t dest[], uint64_t x[], uint32_t len, + uint64_t y) { + for (uint32_t i = 0; i < len; ++i) { + dest[i] = y + x[i]; + if (dest[i] < y) + y = 1; // Carry one to next digit. + else { + y = 0; // No need to carry so exit early + break; + } + } + return (y != 0); +} + +/// add - This function adds the integer array x to the integer array Y and +/// places the result in dest. +/// @returns the carry out from the addition +/// @brief General addition of 64-bit integer arrays +static INLINE bool add(uint64_t* dest, const uint64_t* x, const uint64_t* y, + uint32_t destlen, uint32_t xlen, uint32_t ylen, + bool xsigned, bool ysigned) { + bool carry = false; + uint32_t len = AESL_std::min(xlen, ylen); + uint32_t i; + for (i = 0; i < len && i < destlen; ++i) { + uint64_t limit = + AESL_std::min(x[i], y[i]); // must come first in case dest == x + dest[i] = x[i] + y[i] + carry; + carry = dest[i] < limit || (carry && dest[i] == limit); + } + if (xlen > ylen) { + const uint64_t yext = ysigned && int64_t(y[ylen - 1]) < 0 ? -1 : 0; + for (i = ylen; i < xlen && i < destlen; i++) { + uint64_t limit = AESL_std::min(x[i], yext); + dest[i] = x[i] + yext + carry; + carry = (dest[i] < limit) || (carry && dest[i] == limit); + } + } else if (ylen > xlen) { + const uint64_t xext = xsigned && int64_t(x[xlen - 1]) < 0 ? -1 : 0; + for (i = xlen; i < ylen && i < destlen; i++) { + uint64_t limit = AESL_std::min(xext, y[i]); + dest[i] = xext + y[i] + carry; + carry = (dest[i] < limit) || (carry && dest[i] == limit); + } + } + return carry; +} + +/// @returns returns the borrow out. +/// @brief Generalized subtraction of 64-bit integer arrays. +static INLINE bool sub(uint64_t* dest, const uint64_t* x, const uint64_t* y, + uint32_t destlen, uint32_t xlen, uint32_t ylen, + bool xsigned, bool ysigned) { + bool borrow = false; + uint32_t i; + uint32_t len = AESL_std::min(xlen, ylen); + for (i = 0; i < len && i < destlen; ++i) { + uint64_t x_tmp = borrow ? x[i] - 1 : x[i]; + borrow = y[i] > x_tmp || (borrow && x[i] == 0); + dest[i] = x_tmp - y[i]; + } + if (xlen > ylen) { + const uint64_t yext = ysigned && int64_t(y[ylen - 1]) < 0 ? -1 : 0; + for (i = ylen; i < xlen && i < destlen; i++) { + uint64_t x_tmp = borrow ? x[i] - 1 : x[i]; + borrow = yext > x_tmp || (borrow && x[i] == 0); + dest[i] = x_tmp - yext; + } + } else if (ylen > xlen) { + const uint64_t xext = xsigned && int64_t(x[xlen - 1]) < 0 ? -1 : 0; + for (i = xlen; i < ylen && i < destlen; i++) { + uint64_t x_tmp = borrow ? xext - 1 : xext; + borrow = y[i] > x_tmp || (borrow && xext == 0); + dest[i] = x_tmp - y[i]; + } + } + return borrow; +} + +/// Subtracts the RHS ap_private from this ap_private +/// @returns this, after subtraction +/// @brief Subtraction assignment operator. + +/// Multiplies an integer array, x by a a uint64_t integer and places the result +/// into dest. +/// @returns the carry out of the multiplication. +/// @brief Multiply a multi-digit ap_private by a single digit (64-bit) integer. +static INLINE uint64_t mul_1(uint64_t dest[], const uint64_t x[], uint32_t len, + uint64_t y) { + // Split y into high 32-bit part (hy) and low 32-bit part (ly) + uint64_t ly = y & 0xffffffffULL, hy = (y) >> 32; + uint64_t carry = 0; + static const uint64_t two_power_32 = 1ULL << 32; + // For each digit of x. + for (uint32_t i = 0; i < len; ++i) { + // Split x into high and low words + uint64_t lx = x[i] & 0xffffffffULL; + uint64_t hx = (x[i]) >> 32; + // hasCarry - A flag to indicate if there is a carry to the next digit. + // hasCarry == 0, no carry + // hasCarry == 1, has carry + // hasCarry == 2, no carry and the calculation result == 0. + uint8_t hasCarry = 0; + dest[i] = carry + lx * ly; + // Determine if the add above introduces carry. + hasCarry = (dest[i] < carry) ? 1 : 0; + carry = hx * ly + ((dest[i]) >> 32) + (hasCarry ? two_power_32 : 0); + // The upper limit of carry can be (2^32 - 1)(2^32 - 1) + + // (2^32 - 1) + 2^32 = 2^64. + hasCarry = (!carry && hasCarry) ? 1 : (!carry ? 2 : 0); + + carry += (lx * hy) & 0xffffffffULL; + dest[i] = ((carry) << 32) | (dest[i] & 0xffffffffULL); + carry = (((!carry && hasCarry != 2) || hasCarry == 1) ? two_power_32 : 0) + + ((carry) >> 32) + ((lx * hy) >> 32) + hx * hy; + } + return carry; +} + +/// Multiplies integer array x by integer array y and stores the result into +/// the integer array dest. Note that dest's size must be >= xlen + ylen in +/// order to +/// do a full precision computation. If it is not, then only the low-order words +/// are returned. +/// @brief Generalized multiplicate of integer arrays. +static INLINE void mul(uint64_t dest[], const uint64_t x[], uint32_t xlen, + const uint64_t y[], uint32_t ylen, uint32_t destlen) { + assert(xlen > 0); + assert(ylen > 0); + assert(destlen >= xlen + ylen); + if (xlen < destlen) dest[xlen] = mul_1(dest, x, xlen, y[0]); + for (uint32_t i = 1; i < ylen; ++i) { + uint64_t ly = y[i] & 0xffffffffULL, hy = (y[i]) >> 32; + uint64_t carry = 0, lx = 0, hx = 0; + for (uint32_t j = 0; j < xlen; ++j) { + lx = x[j] & 0xffffffffULL; + hx = (x[j]) >> 32; + // hasCarry - A flag to indicate if has carry. + // hasCarry == 0, no carry + // hasCarry == 1, has carry + // hasCarry == 2, no carry and the calculation result == 0. + uint8_t hasCarry = 0; + uint64_t resul = carry + lx * ly; + hasCarry = (resul < carry) ? 1 : 0; + carry = (hasCarry ? (1ULL << 32) : 0) + hx * ly + ((resul) >> 32); + hasCarry = (!carry && hasCarry) ? 1 : (!carry ? 2 : 0); + carry += (lx * hy) & 0xffffffffULL; + resul = ((carry) << 32) | (resul & 0xffffffffULL); + if (i + j < destlen) dest[i + j] += resul; + carry = + (((!carry && hasCarry != 2) || hasCarry == 1) ? (1ULL << 32) : 0) + + ((carry) >> 32) + (dest[i + j] < resul ? 1 : 0) + ((lx * hy) >> 32) + + hx * hy; + } + if (i + xlen < destlen) dest[i + xlen] = carry; + } +} + +/// Implementation of Knuth's Algorithm D (Division of nonnegative integers) +/// from "Art of Computer Programming, Volume 2", section 4.3.1, p. 272. The +/// variables here have the same names as in the algorithm. Comments explain +/// the algorithm and any deviation from it. +static INLINE void KnuthDiv(uint32_t* u, uint32_t* v, uint32_t* q, uint32_t* r, + uint32_t m, uint32_t n) { + assert(u && "Must provide dividend"); + assert(v && "Must provide divisor"); + assert(q && "Must provide quotient"); + assert(u != v && u != q && v != q && "Must us different memory"); + assert(n > 1 && "n must be > 1"); + + // Knuth uses the value b as the base of the number system. In our case b + // is 2^31 so we just set it to -1u. + uint64_t b = uint64_t(1) << 32; + + // DEBUG(cerr << "KnuthDiv: m=" << m << " n=" << n << '\n'); + // DEBUG(cerr << "KnuthDiv: original:"); + // DEBUG(for (int i = m+n; i >=0; i--) cerr << " " << std::setbase(16) << + // u[i]); + // DEBUG(cerr << " by"); + // DEBUG(for (int i = n; i >0; i--) cerr << " " << std::setbase(16) << + // v[i-1]); + // DEBUG(cerr << '\n'); + // D1. [Normalize.] Set d = b / (v[n-1] + 1) and multiply all the digits of + // u and v by d. Note that we have taken Knuth's advice here to use a power + // of 2 value for d such that d * v[n-1] >= b/2 (b is the base). A power of + // 2 allows us to shift instead of multiply and it is easy to determine the + // shift amount from the leading zeros. We are basically normalizing the u + // and v so that its high bits are shifted to the top of v's range without + // overflow. Note that this can require an extra word in u so that u must + // be of length m+n+1. + uint32_t shift = CountLeadingZeros_32(v[n - 1]); + uint32_t v_carry = 0; + uint32_t u_carry = 0; + if (shift) { + for (uint32_t i = 0; i < m + n; ++i) { + uint32_t u_tmp = (u[i]) >> (32 - shift); + u[i] = ((u[i]) << (shift)) | u_carry; + u_carry = u_tmp; + } + for (uint32_t i = 0; i < n; ++i) { + uint32_t v_tmp = (v[i]) >> (32 - shift); + v[i] = ((v[i]) << (shift)) | v_carry; + v_carry = v_tmp; + } + } + u[m + n] = u_carry; + // DEBUG(cerr << "KnuthDiv: normal:"); + // DEBUG(for (int i = m+n; i >=0; i--) cerr << " " << std::setbase(16) << + // u[i]); + // DEBUG(cerr << " by"); + // DEBUG(for (int i = n; i >0; i--) cerr << " " << std::setbase(16) << + // v[i-1]); + // DEBUG(cerr << '\n'); + + // D2. [Initialize j.] Set j to m. This is the loop counter over the places. + int j = m; + do { + // DEBUG(cerr << "KnuthDiv: quotient digit #" << j << '\n'); + // D3. [Calculate q'.]. + // Set qp = (u[j+n]*b + u[j+n-1]) / v[n-1]. (qp=qprime=q') + // Set rp = (u[j+n]*b + u[j+n-1]) % v[n-1]. (rp=rprime=r') + // Now test if qp == b or qp*v[n-2] > b*rp + u[j+n-2]; if so, decrease + // qp by 1, inrease rp by v[n-1], and repeat this test if rp < b. The test + // on v[n-2] determines at high speed most of the cases in which the trial + // value qp is one too large, and it eliminates all cases where qp is two + // too large. + uint64_t dividend = ((uint64_t(u[j + n]) << 32) + u[j + n - 1]); + // DEBUG(cerr << "KnuthDiv: dividend == " << dividend << '\n'); + uint64_t qp = dividend / v[n - 1]; + uint64_t rp = dividend % v[n - 1]; + if (qp == b || qp * v[n - 2] > b * rp + u[j + n - 2]) { + qp--; + rp += v[n - 1]; + if (rp < b && (qp == b || qp * v[n - 2] > b * rp + u[j + n - 2])) qp--; + } + // DEBUG(cerr << "KnuthDiv: qp == " << qp << ", rp == " << rp << '\n'); + + // D4. [Multiply and subtract.] Replace (u[j+n]u[j+n-1]...u[j]) with + // (u[j+n]u[j+n-1]..u[j]) - qp * (v[n-1]...v[1]v[0]). This computation + // consists of a simple multiplication by a one-place number, combined with + // a subtraction. + bool isNeg = false; + for (uint32_t i = 0; i < n; ++i) { + uint64_t u_tmp = uint64_t(u[j + i]) | ((uint64_t(u[j + i + 1])) << 32); + uint64_t subtrahend = uint64_t(qp) * uint64_t(v[i]); + bool borrow = subtrahend > u_tmp; + /*DEBUG(cerr << "KnuthDiv: u_tmp == " << u_tmp + << ", subtrahend == " << subtrahend + << ", borrow = " << borrow << '\n');*/ + + uint64_t result = u_tmp - subtrahend; + uint32_t k = j + i; + u[k++] = (uint32_t)(result & (b - 1)); // subtract low word + u[k++] = (uint32_t)((result) >> 32); // subtract high word + while (borrow && k <= m + n) { // deal with borrow to the left + borrow = u[k] == 0; + u[k]--; + k++; + } + isNeg |= borrow; + /*DEBUG(cerr << "KnuthDiv: u[j+i] == " << u[j+i] << ", u[j+i+1] == " << + u[j+i+1] << '\n');*/ + } + /*DEBUG(cerr << "KnuthDiv: after subtraction:"); + DEBUG(for (int i = m+n; i >=0; i--) cerr << " " << u[i]); + DEBUG(cerr << '\n');*/ + // The digits (u[j+n]...u[j]) should be kept positive; if the result of + // this step is actually negative, (u[j+n]...u[j]) should be left as the + // true value plus b**(n+1), namely as the b's complement of + // the true value, and a "borrow" to the left should be remembered. + // + if (isNeg) { + bool carry = true; // true because b's complement is "complement + 1" + for (uint32_t i = 0; i <= m + n; ++i) { + u[i] = ~u[i] + carry; // b's complement + carry = carry && u[i] == 0; + } + } + /*DEBUG(cerr << "KnuthDiv: after complement:"); + DEBUG(for (int i = m+n; i >=0; i--) cerr << " " << u[i]); + DEBUG(cerr << '\n');*/ + + // D5. [Test remainder.] Set q[j] = qp. If the result of step D4 was + // negative, go to step D6; otherwise go on to step D7. + q[j] = (uint32_t)qp; + if (isNeg) { + // D6. [Add back]. The probability that this step is necessary is very + // small, on the order of only 2/b. Make sure that test data accounts for + // this possibility. Decrease q[j] by 1 + q[j]--; + // and add (0v[n-1]...v[1]v[0]) to (u[j+n]u[j+n-1]...u[j+1]u[j]). + // A carry will occur to the left of u[j+n], and it should be ignored + // since it cancels with the borrow that occurred in D4. + bool carry = false; + for (uint32_t i = 0; i < n; i++) { + uint32_t limit = AESL_std::min(u[j + i], v[i]); + u[j + i] += v[i] + carry; + carry = u[j + i] < limit || (carry && u[j + i] == limit); + } + u[j + n] += carry; + } + /*DEBUG(cerr << "KnuthDiv: after correction:"); + DEBUG(for (int i = m+n; i >=0; i--) cerr <<" " << u[i]); + DEBUG(cerr << "\nKnuthDiv: digit result = " << q[j] << '\n');*/ + + // D7. [Loop on j.] Decrease j by one. Now if j >= 0, go back to D3. + } while (--j >= 0); + + /*DEBUG(cerr << "KnuthDiv: quotient:"); + DEBUG(for (int i = m; i >=0; i--) cerr <<" " << q[i]); + DEBUG(cerr << '\n');*/ + + // D8. [Unnormalize]. Now q[...] is the desired quotient, and the desired + // remainder may be obtained by dividing u[...] by d. If r is non-null we + // compute the remainder (urem uses this). + if (r) { + // The value d is expressed by the "shift" value above since we avoided + // multiplication by d by using a shift left. So, all we have to do is + // shift right here. In order to mak + if (shift) { + uint32_t carry = 0; + // DEBUG(cerr << "KnuthDiv: remainder:"); + for (int i = n - 1; i >= 0; i--) { + r[i] = ((u[i]) >> (shift)) | carry; + carry = (u[i]) << (32 - shift); + // DEBUG(cerr << " " << r[i]); + } + } else { + for (int i = n - 1; i >= 0; i--) { + r[i] = u[i]; + // DEBUG(cerr << " " << r[i]); + } + } + // DEBUG(cerr << '\n'); + } + // DEBUG(cerr << std::setbase(10) << '\n'); +} + +template +void divide(const ap_private<_AP_W, _AP_S>& LHS, uint32_t lhsWords, + const ap_private<_AP_W, _AP_S>& RHS, uint32_t rhsWords, + ap_private<_AP_W, _AP_S>* Quotient, + ap_private<_AP_W, _AP_S>* Remainder) { + assert(lhsWords >= rhsWords && "Fractional result"); + enum { APINT_BITS_PER_WORD = 64 }; + // First, compose the values into an array of 32-bit words instead of + // 64-bit words. This is a necessity of both the "short division" algorithm + // and the the Knuth "classical algorithm" which requires there to be native + // operations for +, -, and * on an m bit value with an m*2 bit result. We + // can't use 64-bit operands here because we don't have native results of + // 128-bits. Furthremore, casting the 64-bit values to 32-bit values won't + // work on large-endian machines. + uint64_t mask = ~0ull >> (sizeof(uint32_t) * 8); + uint32_t n = rhsWords * 2; + uint32_t m = (lhsWords * 2) - n; + + // Allocate space for the temporary values we need either on the stack, if + // it will fit, or on the heap if it won't. + uint32_t SPACE[128]; + uint32_t* __U = 0; + uint32_t* __V = 0; + uint32_t* __Q = 0; + uint32_t* __R = 0; + if ((Remainder ? 4 : 3) * n + 2 * m + 1 <= 128) { + __U = &SPACE[0]; + __V = &SPACE[m + n + 1]; + __Q = &SPACE[(m + n + 1) + n]; + if (Remainder) __R = &SPACE[(m + n + 1) + n + (m + n)]; + } else { + __U = new uint32_t[m + n + 1]; + __V = new uint32_t[n]; + __Q = new uint32_t[m + n]; + if (Remainder) __R = new uint32_t[n]; + } + + // Initialize the dividend + memset(__U, 0, (m + n + 1) * sizeof(uint32_t)); + for (unsigned i = 0; i < lhsWords; ++i) { + uint64_t tmp = LHS.get_pVal(i); + __U[i * 2] = (uint32_t)(tmp & mask); + __U[i * 2 + 1] = (tmp) >> (sizeof(uint32_t) * 8); + } + __U[m + n] = 0; // this extra word is for "spill" in the Knuth algorithm. + + // Initialize the divisor + memset(__V, 0, (n) * sizeof(uint32_t)); + for (unsigned i = 0; i < rhsWords; ++i) { + uint64_t tmp = RHS.get_pVal(i); + __V[i * 2] = (uint32_t)(tmp & mask); + __V[i * 2 + 1] = (tmp) >> (sizeof(uint32_t) * 8); + } + + // initialize the quotient and remainder + memset(__Q, 0, (m + n) * sizeof(uint32_t)); + if (Remainder) memset(__R, 0, n * sizeof(uint32_t)); + + // Now, adjust m and n for the Knuth division. n is the number of words in + // the divisor. m is the number of words by which the dividend exceeds the + // divisor (i.e. m+n is the length of the dividend). These sizes must not + // contain any zero words or the Knuth algorithm fails. + for (unsigned i = n; i > 0 && __V[i - 1] == 0; i--) { + n--; + m++; + } + for (unsigned i = m + n; i > 0 && __U[i - 1] == 0; i--) m--; + + // If we're left with only a single word for the divisor, Knuth doesn't work + // so we implement the short division algorithm here. This is much simpler + // and faster because we are certain that we can divide a 64-bit quantity + // by a 32-bit quantity at hardware speed and short division is simply a + // series of such operations. This is just like doing short division but we + // are using base 2^32 instead of base 10. + assert(n != 0 && "Divide by zero?"); + if (n == 1) { + uint32_t divisor = __V[0]; + uint32_t remainder = 0; + for (int i = m + n - 1; i >= 0; i--) { + uint64_t partial_dividend = (uint64_t(remainder)) << 32 | __U[i]; + if (partial_dividend == 0) { + __Q[i] = 0; + remainder = 0; + } else if (partial_dividend < divisor) { + __Q[i] = 0; + remainder = (uint32_t)partial_dividend; + } else if (partial_dividend == divisor) { + __Q[i] = 1; + remainder = 0; + } else { + __Q[i] = (uint32_t)(partial_dividend / divisor); + remainder = (uint32_t)(partial_dividend - (__Q[i] * divisor)); + } + } + if (__R) __R[0] = remainder; + } else { + // Now we're ready to invoke the Knuth classical divide algorithm. In this + // case n > 1. + KnuthDiv(__U, __V, __Q, __R, m, n); + } + + // If the caller wants the quotient + if (Quotient) { + // Set up the Quotient value's memory. + if (Quotient->BitWidth != LHS.BitWidth) { + if (Quotient->isSingleWord()) Quotient->set_VAL(0); + } else + Quotient->clear(); + + // The quotient is in Q. Reconstitute the quotient into Quotient's low + // order words. + if (lhsWords == 1) { + uint64_t tmp = + uint64_t(__Q[0]) | ((uint64_t(__Q[1])) << (APINT_BITS_PER_WORD / 2)); + Quotient->set_VAL(tmp); + } else { + assert(!Quotient->isSingleWord() && + "Quotient ap_private not large enough"); + for (unsigned i = 0; i < lhsWords; ++i) + Quotient->set_pVal( + i, uint64_t(__Q[i * 2]) | + ((uint64_t(__Q[i * 2 + 1])) << (APINT_BITS_PER_WORD / 2))); + } + Quotient->clearUnusedBits(); + } + + // If the caller wants the remainder + if (Remainder) { + // Set up the Remainder value's memory. + if (Remainder->BitWidth != RHS.BitWidth) { + if (Remainder->isSingleWord()) Remainder->set_VAL(0); + } else + Remainder->clear(); + + // The remainder is in R. Reconstitute the remainder into Remainder's low + // order words. + if (rhsWords == 1) { + uint64_t tmp = + uint64_t(__R[0]) | ((uint64_t(__R[1])) << (APINT_BITS_PER_WORD / 2)); + Remainder->set_VAL(tmp); + } else { + assert(!Remainder->isSingleWord() && + "Remainder ap_private not large enough"); + for (unsigned i = 0; i < rhsWords; ++i) + Remainder->set_pVal( + i, uint64_t(__R[i * 2]) | + ((uint64_t(__R[i * 2 + 1])) << (APINT_BITS_PER_WORD / 2))); + } + Remainder->clearUnusedBits(); + } + + // Clean up the memory we allocated. + if (__U != &SPACE[0]) { + delete[] __U; + delete[] __V; + delete[] __Q; + delete[] __R; + } +} + +template +void divide(const ap_private<_AP_W, _AP_S>& LHS, uint32_t lhsWords, + uint64_t RHS, ap_private<_AP_W, _AP_S>* Quotient, + ap_private<_AP_W, _AP_S>* Remainder) { + uint32_t rhsWords = 1; + assert(lhsWords >= rhsWords && "Fractional result"); + enum { APINT_BITS_PER_WORD = 64 }; + // First, compose the values into an array of 32-bit words instead of + // 64-bit words. This is a necessity of both the "short division" algorithm + // and the the Knuth "classical algorithm" which requires there to be native + // operations for +, -, and * on an m bit value with an m*2 bit result. We + // can't use 64-bit operands here because we don't have native results of + // 128-bits. Furthremore, casting the 64-bit values to 32-bit values won't + // work on large-endian machines. + uint64_t mask = ~0ull >> (sizeof(uint32_t) * 8); + uint32_t n = 2; + uint32_t m = (lhsWords * 2) - n; + + // Allocate space for the temporary values we need either on the stack, if + // it will fit, or on the heap if it won't. + uint32_t SPACE[128]; + uint32_t* __U = 0; + uint32_t* __V = 0; + uint32_t* __Q = 0; + uint32_t* __R = 0; + if ((Remainder ? 4 : 3) * n + 2 * m + 1 <= 128) { + __U = &SPACE[0]; + __V = &SPACE[m + n + 1]; + __Q = &SPACE[(m + n + 1) + n]; + if (Remainder) __R = &SPACE[(m + n + 1) + n + (m + n)]; + } else { + __U = new uint32_t[m + n + 1]; + __V = new uint32_t[n]; + __Q = new uint32_t[m + n]; + if (Remainder) __R = new uint32_t[n]; + } + + // Initialize the dividend + memset(__U, 0, (m + n + 1) * sizeof(uint32_t)); + for (unsigned i = 0; i < lhsWords; ++i) { + uint64_t tmp = LHS.get_pVal(i); + __U[i * 2] = tmp & mask; + __U[i * 2 + 1] = (tmp) >> (sizeof(uint32_t) * 8); + } + __U[m + n] = 0; // this extra word is for "spill" in the Knuth algorithm. + + // Initialize the divisor + memset(__V, 0, (n) * sizeof(uint32_t)); + __V[0] = RHS & mask; + __V[1] = (RHS) >> (sizeof(uint32_t) * 8); + + // initialize the quotient and remainder + memset(__Q, 0, (m + n) * sizeof(uint32_t)); + if (Remainder) memset(__R, 0, n * sizeof(uint32_t)); + + // Now, adjust m and n for the Knuth division. n is the number of words in + // the divisor. m is the number of words by which the dividend exceeds the + // divisor (i.e. m+n is the length of the dividend). These sizes must not + // contain any zero words or the Knuth algorithm fails. + for (unsigned i = n; i > 0 && __V[i - 1] == 0; i--) { + n--; + m++; + } + for (unsigned i = m + n; i > 0 && __U[i - 1] == 0; i--) m--; + + // If we're left with only a single word for the divisor, Knuth doesn't work + // so we implement the short division algorithm here. This is much simpler + // and faster because we are certain that we can divide a 64-bit quantity + // by a 32-bit quantity at hardware speed and short division is simply a + // series of such operations. This is just like doing short division but we + // are using base 2^32 instead of base 10. + assert(n != 0 && "Divide by zero?"); + if (n == 1) { + uint32_t divisor = __V[0]; + uint32_t remainder = 0; + for (int i = m + n - 1; i >= 0; i--) { + uint64_t partial_dividend = (uint64_t(remainder)) << 32 | __U[i]; + if (partial_dividend == 0) { + __Q[i] = 0; + remainder = 0; + } else if (partial_dividend < divisor) { + __Q[i] = 0; + remainder = partial_dividend; + } else if (partial_dividend == divisor) { + __Q[i] = 1; + remainder = 0; + } else { + __Q[i] = partial_dividend / divisor; + remainder = partial_dividend - (__Q[i] * divisor); + } + } + if (__R) __R[0] = remainder; + } else { + // Now we're ready to invoke the Knuth classical divide algorithm. In this + // case n > 1. + KnuthDiv(__U, __V, __Q, __R, m, n); + } + + // If the caller wants the quotient + if (Quotient) { + // Set up the Quotient value's memory. + if (Quotient->BitWidth != LHS.BitWidth) { + if (Quotient->isSingleWord()) Quotient->set_VAL(0); + } else + Quotient->clear(); + + // The quotient is in Q. Reconstitute the quotient into Quotient's low + // order words. + if (lhsWords == 1) { + uint64_t tmp = + uint64_t(__Q[0]) | ((uint64_t(__Q[1])) << (APINT_BITS_PER_WORD / 2)); + Quotient->set_VAL(tmp); + } else { + assert(!Quotient->isSingleWord() && + "Quotient ap_private not large enough"); + for (unsigned i = 0; i < lhsWords; ++i) + Quotient->set_pVal( + i, uint64_t(__Q[i * 2]) | + ((uint64_t(__Q[i * 2 + 1])) << (APINT_BITS_PER_WORD / 2))); + } + Quotient->clearUnusedBits(); + } + + // If the caller wants the remainder + if (Remainder) { + // Set up the Remainder value's memory. + if (Remainder->BitWidth != 64 /* RHS.BitWidth */) { + if (Remainder->isSingleWord()) Remainder->set_VAL(0); + } else + Remainder->clear(); + + // The remainder is in __R. Reconstitute the remainder into Remainder's low + // order words. + if (rhsWords == 1) { + uint64_t tmp = + uint64_t(__R[0]) | ((uint64_t(__R[1])) << (APINT_BITS_PER_WORD / 2)); + Remainder->set_VAL(tmp); + } else { + assert(!Remainder->isSingleWord() && + "Remainder ap_private not large enough"); + for (unsigned i = 0; i < rhsWords; ++i) + Remainder->set_pVal( + i, uint64_t(__R[i * 2]) | + ((uint64_t(__R[i * 2 + 1])) << (APINT_BITS_PER_WORD / 2))); + } + Remainder->clearUnusedBits(); + } + + // Clean up the memory we allocated. + if (__U != &SPACE[0]) { + delete[] __U; + delete[] __V; + delete[] __Q; + delete[] __R; + } +} + +/// @brief Logical right-shift function. +template +INLINE ap_private<_AP_W, _AP_S, _AP_C> lshr( + const ap_private<_AP_W, _AP_S, _AP_C>& LHS, uint32_t shiftAmt) { + return LHS.lshr(shiftAmt); +} + +/// Left-shift the ap_private by shiftAmt. +/// @brief Left-shift function. +template +INLINE ap_private<_AP_W, _AP_S, _AP_C> shl( + const ap_private<_AP_W, _AP_S, _AP_C>& LHS, uint32_t shiftAmt) { + return LHS.shl(shiftAmt); +} + +} // namespace ap_private_ops + +#endif // LLVM_SUPPORT_MATHEXTRAS_H + +/// This enumeration just provides for internal constants used in this +/// translation unit. +enum { + MIN_INT_BITS = 1, ///< Minimum number of bits that can be specified + ///< Note that this must remain synchronized with IntegerType::MIN_INT_BITS + MAX_INT_BITS = (1 << 23) - 1 ///< Maximum number of bits that can be specified + ///< Note that this must remain synchronized with IntegerType::MAX_INT_BITS +}; + +//===----------------------------------------------------------------------===// +// ap_private Class +//===----------------------------------------------------------------------===// + +/// ap_private - This class represents arbitrary precision constant integral +/// values. +/// It is a functional replacement for common case unsigned integer type like +/// "unsigned", "unsigned long" or "uint64_t", but also allows non-byte-width +/// integer sizes and large integer value types such as 3-bits, 15-bits, or more +/// than 64-bits of precision. ap_private provides a variety of arithmetic +/// operators +/// and methods to manipulate integer values of any bit-width. It supports both +/// the typical integer arithmetic and comparison operations as well as bitwise +/// manipulation. +/// +/// The class has several invariants worth noting: +/// * All bit, byte, and word positions are zero-based. +/// * Once the bit width is set, it doesn't change except by the Truncate, +/// SignExtend, or ZeroExtend operations. +/// * All binary operators must be on ap_private instances of the same bit +/// width. +/// Attempting to use these operators on instances with different bit +/// widths will yield an assertion. +/// * The value is stored canonically as an unsigned value. For operations +/// where it makes a difference, there are both signed and unsigned variants +/// of the operation. For example, sdiv and udiv. However, because the bit +/// widths must be the same, operations such as Mul and Add produce the same +/// results regardless of whether the values are interpreted as signed or +/// not. +/// * In general, the class tries to follow the style of computation that LLVM +/// uses in its IR. This simplifies its use for LLVM. +/// +/// @brief Class for arbitrary precision integers. + +#if defined(_MSC_VER) +#if _MSC_VER < 1400 && !defined(for) +#define for if (0); else for +#endif +typedef unsigned __int64 ap_ulong; +typedef signed __int64 ap_slong; +#else +typedef unsigned long long ap_ulong; +typedef signed long long ap_slong; +#endif +template +struct valtype; + +template +struct valtype<_AP_N8, false> { + typedef uint64_t Type; +}; + +template +struct valtype<_AP_N8, true> { + typedef int64_t Type; +}; + +template <> +struct valtype<1, false> { + typedef unsigned char Type; +}; +template <> +struct valtype<2, false> { + typedef unsigned short Type; +}; +template <> +struct valtype<3, false> { + typedef unsigned int Type; +}; +template <> +struct valtype<4, false> { + typedef unsigned int Type; +}; +template <> +struct valtype<1, true> { + typedef signed char Type; +}; +template <> +struct valtype<2, true> { + typedef short Type; +}; +template <> +struct valtype<3, true> { + typedef int Type; +}; +template <> +struct valtype<4, true> { + typedef int Type; +}; + +template +struct ap_private_enable_if {}; +template <> +struct ap_private_enable_if { + static const bool isValid = true; +}; + +// When bitwidth < 64 +template +class ap_private<_AP_W, _AP_S, true> { + // SFINAE pattern. Only consider this class when _AP_W <= 64 + const static bool valid = ap_private_enable_if<_AP_W <= 64>::isValid; + +#ifdef _MSC_VER +#pragma warning(disable : 4521 4522) +#endif + public: + typedef typename valtype<(_AP_W + 7) / 8, _AP_S>::Type ValType; + typedef ap_private<_AP_W, _AP_S> Type; + template + struct RType { + enum { + mult_w = _AP_W + _AP_W2, + mult_s = _AP_S || _AP_S2, + plus_w = + AP_MAX(_AP_W + (_AP_S2 && !_AP_S), _AP_W2 + (_AP_S && !_AP_S2)) + 1, + plus_s = _AP_S || _AP_S2, + minus_w = + AP_MAX(_AP_W + (_AP_S2 && !_AP_S), _AP_W2 + (_AP_S && !_AP_S2)) + 1, + minus_s = true, + div_w = _AP_W + _AP_S2, + div_s = _AP_S || _AP_S2, + mod_w = AP_MIN(_AP_W, _AP_W2 + (!_AP_S2 && _AP_S)), + mod_s = _AP_S, + logic_w = AP_MAX(_AP_W + (_AP_S2 && !_AP_S), _AP_W2 + (_AP_S && !_AP_S2)), + logic_s = _AP_S || _AP_S2 + }; + typedef ap_private mult; + typedef ap_private plus; + typedef ap_private minus; + typedef ap_private logic; + typedef ap_private div; + typedef ap_private mod; + typedef ap_private<_AP_W, _AP_S> arg1; + typedef bool reduce; + }; + enum { APINT_BITS_PER_WORD = sizeof(uint64_t) * 8 }; + enum { + excess_bits = (_AP_W % APINT_BITS_PER_WORD) + ? APINT_BITS_PER_WORD - (_AP_W % APINT_BITS_PER_WORD) + : 0 + }; + static const uint64_t mask = ((uint64_t)~0ULL >> (excess_bits)); + static const uint64_t not_mask = ~mask; + static const uint64_t sign_bit_mask = 1ULL << (APINT_BITS_PER_WORD - 1); + template + struct sign_ext_mask { + static const uint64_t mask = ~0ULL << _AP_W1; + }; + static const int width = _AP_W; + + enum { + BitWidth = _AP_W, + _AP_N = 1, + }; + ValType VAL; ///< Used to store the <= 64 bits integer value. +#ifdef AP_CANARY + ValType CANARY; + void check_canary() { assert(CANARY == (ValType)0xDEADBEEFDEADBEEF); } + void set_canary() { CANARY = (ValType)0xDEADBEEFDEADBEEF; } +#else + void check_canary() {} + void set_canary() {} +#endif + + INLINE ValType& get_VAL(void) { return VAL; } + INLINE ValType get_VAL(void) const { return VAL; } + INLINE ValType get_VAL(void) const volatile { return VAL; } + INLINE void set_VAL(uint64_t value) { VAL = (ValType)value; } + INLINE ValType& get_pVal(int i) { return VAL; } + INLINE ValType get_pVal(int i) const { return VAL; } + INLINE const uint64_t* get_pVal() const { + assert(0 && "invalid usage"); + return 0; + } + INLINE ValType get_pVal(int i) const volatile { return VAL; } + INLINE uint64_t* get_pVal() const volatile { + assert(0 && "invalid usage"); + return 0; + } + INLINE void set_pVal(int i, uint64_t value) { VAL = (ValType)value; } + + INLINE uint32_t getBitWidth() const { return BitWidth; } + + template + ap_private<_AP_W, _AP_S>& operator=(const ap_private<_AP_W1, _AP_S1>& RHS) { + VAL = (ValType)(RHS.get_VAL()); + clearUnusedBits(); + return *this; + } + + template + ap_private<_AP_W, _AP_S>& operator=( + const volatile ap_private<_AP_W1, _AP_S1>& RHS) { + VAL = (ValType)(RHS.get_VAL()); // TODO check here about ap_private + clearUnusedBits(); + return *this; + } + + void operator=(const ap_private& RHS) volatile { + // Don't do anything for X = X + VAL = RHS.get_VAL(); // No need to check because no harm done by copying. + clearUnusedBits(); + } + + ap_private& operator=(const ap_private& RHS) { + // Don't do anything for X = X + VAL = RHS.get_VAL(); // No need to check because no harm done by copying. + clearUnusedBits(); + return *this; + } + + void operator=(const volatile ap_private& RHS) volatile { + // Don't do anything for X = X + VAL = RHS.get_VAL(); // No need to check because no harm done by copying. + clearUnusedBits(); + } + + ap_private& operator=(const volatile ap_private& RHS) { + // Don't do anything for X = X + VAL = RHS.get_VAL(); // No need to check because no harm done by copying. + clearUnusedBits(); + return *this; + } + + template + INLINE ap_private& operator=(const _private_range_ref<_AP_W2, _AP_S2>& op2) { + *this = ap_private<_AP_W2, false>(op2); + return *this; + } + +#define ASSIGN_OP_FROM_INT(C_TYPE) \ + INLINE ap_private& operator=(const C_TYPE v) { \ + set_canary(); \ + this->VAL = (ValType)v; \ + clearUnusedBits(); \ + check_canary(); \ + return *this; \ + } + +ASSIGN_OP_FROM_INT(bool) +ASSIGN_OP_FROM_INT(char) +ASSIGN_OP_FROM_INT(signed char) +ASSIGN_OP_FROM_INT(unsigned char) +ASSIGN_OP_FROM_INT(short) +ASSIGN_OP_FROM_INT(unsigned short) +ASSIGN_OP_FROM_INT(int) +ASSIGN_OP_FROM_INT(unsigned int) +ASSIGN_OP_FROM_INT(long) +ASSIGN_OP_FROM_INT(unsigned long) +ASSIGN_OP_FROM_INT(ap_slong) +ASSIGN_OP_FROM_INT(ap_ulong) +#if 0 +ASSIGN_OP_FROM_INT(half) +ASSIGN_OP_FROM_INT(float) +ASSIGN_OP_FROM_INT(double) +#endif +#undef ASSIGN_OP_FROM_INT + + // XXX This is a must to prevent pointer being converted to bool. + INLINE ap_private& operator=(const char* s) { + ap_private tmp(s); // XXX direct-initialization, as ctor is explicit. + operator=(tmp); + return *this; + } + + private: + explicit INLINE ap_private(uint64_t* val) : VAL(val[0]) { + set_canary(); + clearUnusedBits(); + check_canary(); + } + + INLINE bool isSingleWord() const { return true; } + + public: + INLINE void fromString(const char* strStart, uint32_t slen, uint8_t radix) { + bool isNeg = strStart[0] == '-'; + if (isNeg) { + strStart++; + slen--; + } + + if (strStart[0] == '0' && (strStart[1] == 'b' || strStart[1] == 'B')) { + //if(radix == 0) radix = 2; + _AP_WARNING(radix != 2, "%s seems to have base %d, but %d given.", strStart, 2, radix); + strStart += 2; + slen -=2; + } else if (strStart[0] == '0' && (strStart[1] == 'o' || strStart[1] == 'O')) { + //if (radix == 0) radix = 8; + _AP_WARNING(radix != 8, "%s seems to have base %d, but %d given.", strStart, 8, radix); + strStart += 2; + slen -=2; + } else if (strStart[0] == '0' && (strStart[1] == 'x' || strStart[1] == 'X')) { + //if (radix == 0) radix = 16; + _AP_WARNING(radix != 16, "%s seems to have base %d, but %d given.", strStart, 16, radix); + strStart += 2; + slen -=2; + } else if (strStart[0] == '0' && (strStart[1] == 'd' || strStart[1] == 'D')) { + //if (radix == 0) radix = 10; + _AP_WARNING(radix != 10, "%s seems to have base %d, but %d given.", strStart, 10, radix); + strStart += 2; + slen -=2; + } else if (radix == 0) { + //radix = 2; // XXX default value + } + + // Check our assumptions here + assert((radix == 10 || radix == 8 || radix == 16 || radix == 2) && + "Radix should be 2, 8, 10, or 16!"); + assert(strStart && "String is null?"); + + // Clear bits. + uint64_t tmpVAL = VAL = 0; + + switch (radix) { + case 2: + // sscanf(strStart,"%b",&VAL); + // tmpVAL = *strStart =='1' ? ~0ULL : 0; + for (; *strStart; ++strStart) { + assert((*strStart == '0' || *strStart == '1') && + ("Wrong binary number")); + tmpVAL <<= 1; + tmpVAL |= (*strStart - '0'); + } + break; + case 8: +#ifdef _MSC_VER + sscanf_s(strStart, "%llo", &tmpVAL, slen + 1); +#else +#if defined(__x86_64__) && !defined(__MINGW32__) && !defined(__WIN32__) + sscanf(strStart, "%lo", &tmpVAL); +#else + sscanf(strStart, "%llo", &tmpVAL); +#endif //__x86_64__ +#endif //_MSC_VER + break; + case 10: +#ifdef _MSC_VER + sscanf_s(strStart, "%llu", &tmpVAL, slen + 1); +#else +#if defined(__x86_64__) && !defined(__MINGW32__) && !defined(__WIN32__) + sscanf(strStart, "%lu", &tmpVAL); +#else + sscanf(strStart, "%llu", &tmpVAL); +#endif //__x86_64__ +#endif //_MSC_VER + break; + case 16: +#ifdef _MSC_VER + sscanf_s(strStart, "%llx", &tmpVAL, slen + 1); +#else +#if defined(__x86_64__) && !defined(__MINGW32__) && !defined(__WIN32__) + sscanf(strStart, "%lx", &tmpVAL); +#else + sscanf(strStart, "%llx", &tmpVAL); +#endif //__x86_64__ +#endif //_MSC_VER + break; + default: + assert(true && "Unknown radix"); + // error + } + VAL = isNeg ? (ValType)(-tmpVAL) : (ValType)(tmpVAL); + + clearUnusedBits(); + } + + private: + INLINE ap_private(const std::string& val, uint8_t radix = 2) : VAL(0) { + assert(!val.empty() && "String empty?"); + set_canary(); + fromString(val.c_str(), val.size(), radix); + check_canary(); + } + + INLINE ap_private(const char strStart[], uint32_t slen, uint8_t radix) + : VAL(0) { + set_canary(); + fromString(strStart, slen, radix); + check_canary(); + } + + INLINE ap_private(uint32_t numWords, const uint64_t bigVal[]) + : VAL(bigVal[0]) { + set_canary(); + clearUnusedBits(); + check_canary(); + } + + public: + INLINE ap_private() { + set_canary(); + clearUnusedBits(); + check_canary(); + } + +#define CTOR(TYPE) \ + INLINE ap_private(TYPE v) : VAL((ValType)v) { \ + set_canary(); \ + clearUnusedBits(); \ + check_canary(); \ + } + CTOR(bool) + CTOR(char) + CTOR(signed char) + CTOR(unsigned char) + CTOR(short) + CTOR(unsigned short) + CTOR(int) + CTOR(unsigned int) + CTOR(long) + CTOR(unsigned long) + CTOR(ap_slong) + CTOR(ap_ulong) +#if 0 + CTOR(half) + CTOR(float) + CTOR(double) +#endif +#undef CTOR + + template + INLINE ap_private(const ap_private<_AP_W1, _AP_S1, _AP_OPT>& that) + : VAL((ValType)that.get_VAL()) { + set_canary(); + clearUnusedBits(); + check_canary(); + } + + template + INLINE ap_private(const volatile ap_private<_AP_W1, _AP_S1, _AP_OPT>& that) + : VAL((ValType)that.get_VAL()) { + set_canary(); + clearUnusedBits(); + check_canary(); + } + + explicit INLINE ap_private(const char* val) { + set_canary(); + unsigned char radix = 10; + std::string str = ap_private_ops::parseString(val, radix); // will set radix. + std::string::size_type pos = str.find('.'); + // trunc all fraction part + if (pos != std::string::npos) str = str.substr(pos); + + ap_private<_AP_W, _AP_S> ap_private_val(str, radix); + operator=(ap_private_val); + check_canary(); + } + + INLINE ap_private(const char* val, signed char rd) { + set_canary(); + unsigned char radix = rd; + std::string str = ap_private_ops::parseString(val, radix); // will set radix. + std::string::size_type pos = str.find('.'); + // trunc all fraction part + if (pos != std::string::npos) str = str.substr(pos); + + ap_private<_AP_W, _AP_S> ap_private_val(str, radix); + operator=(ap_private_val); + check_canary(); + } + + INLINE ~ap_private() { check_canary(); } + + INLINE bool isNegative() const { + static const uint64_t sign_mask = 1ULL << (_AP_W - 1); + return _AP_S && (sign_mask & VAL); + } + + INLINE bool isPositive() const { return !isNegative(); } + + INLINE bool isStrictlyPositive() const { return !isNegative() && VAL != 0; } + + INLINE bool isAllOnesValue() const { return (mask & VAL) == mask; } + + INLINE bool operator==(const ap_private<_AP_W, _AP_S>& RHS) const { + return VAL == RHS.get_VAL(); + } + INLINE bool operator==(const ap_private<_AP_W, !_AP_S>& RHS) const { + return (uint64_t)VAL == (uint64_t)RHS.get_VAL(); + } + + INLINE bool operator==(uint64_t Val) const { return ((uint64_t)VAL == Val); } + INLINE bool operator!=(uint64_t Val) const { return ((uint64_t)VAL != Val); } + INLINE bool operator!=(const ap_private<_AP_W, _AP_S>& RHS) const { + return VAL != RHS.get_VAL(); + } + INLINE bool operator!=(const ap_private<_AP_W, !_AP_S>& RHS) const { + return (uint64_t)VAL != (uint64_t)RHS.get_VAL(); + } + + /// postfix increment. + const ap_private operator++(int) { + ap_private orig(*this); + VAL++; + clearUnusedBits(); + return orig; + } + + /// prefix increment. + const ap_private operator++() { + ++VAL; + clearUnusedBits(); + return *this; + } + + /// postfix decrement. + const ap_private operator--(int) { + ap_private orig(*this); + --VAL; + clearUnusedBits(); + return orig; + } + + /// prefix decrement. + const ap_private operator--() { + --VAL; + clearUnusedBits(); + return *this; + } + + /// one's complement. + INLINE ap_private<_AP_W + !_AP_S, true> operator~() const { + ap_private<_AP_W + !_AP_S, true> Result(*this); + Result.flip(); + return Result; + } + + /// two's complement. + INLINE typename RType<1, false>::minus operator-() const { + return ap_private<1, false>(0) - (*this); + } + + /// logic negation. + INLINE bool operator!() const { return !VAL; } + + INLINE std::string toString(uint8_t radix, bool wantSigned) const; + INLINE std::string toStringUnsigned(uint8_t radix = 10) const { + return toString(radix, false); + } + INLINE std::string toStringSigned(uint8_t radix = 10) const { + return toString(radix, true); + } + INLINE void clear() { VAL = 0; } + INLINE ap_private& clear(uint32_t bitPosition) { + VAL &= ~(1ULL << (bitPosition)); + clearUnusedBits(); + return *this; + } + + INLINE ap_private ashr(uint32_t shiftAmt) const { + if (_AP_S) + return ap_private((shiftAmt == BitWidth) ? 0 + : ((int64_t)VAL) >> (shiftAmt)); + else + return ap_private((shiftAmt == BitWidth) ? 0 + : ((uint64_t)VAL) >> (shiftAmt)); + } + + INLINE ap_private lshr(uint32_t shiftAmt) const { + return ap_private((shiftAmt == BitWidth) + ? ap_private(0) + : ap_private((VAL & mask) >> (shiftAmt))); + } + + INLINE ap_private shl(uint32_t shiftAmt) const +// just for clang compiler +#if defined(__clang__) && !defined(__CLANG_3_1__) + __attribute__((no_sanitize("undefined"))) +#endif + { + if (shiftAmt > BitWidth) { + if (!isNegative()) + return ap_private(0); + else + return ap_private(-1); + } + if (shiftAmt == BitWidth) + return ap_private(0); + else + return ap_private((VAL) << (shiftAmt)); + // return ap_private((shiftAmt == BitWidth) ? ap_private(0ULL) : + // ap_private(VAL << shiftAmt)); + } + + INLINE int64_t getSExtValue() const { return VAL; } + + // XXX XXX this function is used in CBE + INLINE uint64_t getZExtValue() const { return VAL & mask; } + + template + INLINE ap_private(const _private_range_ref<_AP_W2, _AP_S2>& ref) { + set_canary(); + *this = ref.get(); + check_canary(); + } + + template + INLINE ap_private(const _private_bit_ref<_AP_W2, _AP_S2>& ref) { + set_canary(); + *this = ((uint64_t)(bool)ref); + check_canary(); + } + +// template +// INLINE ap_private(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& ref) { +// set_canary(); +// *this = ref.get(); +// check_canary(); +// } +// +// template +// INLINE ap_private( +// const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) { +// set_canary(); +// *this = ((val.operator ap_private<_AP_W2, false>())); +// check_canary(); +// } +// +// template +// INLINE ap_private( +// const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) { +// set_canary(); +// *this = (uint64_t)(bool)val; +// check_canary(); +// } + + INLINE void write(const ap_private<_AP_W, _AP_S>& op2) volatile { + *this = (op2); + } + + // Explicit conversions to C interger types + //----------------------------------------------------------- + INLINE operator ValType() const { return get_VAL(); } + + INLINE int to_uchar() const { return (unsigned char)get_VAL(); } + + INLINE int to_char() const { return (signed char)get_VAL(); } + + INLINE int to_ushort() const { return (unsigned short)get_VAL(); } + + INLINE int to_short() const { return (short)get_VAL(); } + + INLINE int to_int() const { + // ap_private<64 /* _AP_W */, _AP_S> res(V); + return (int)get_VAL(); + } + + INLINE unsigned to_uint() const { return (unsigned)get_VAL(); } + + INLINE long to_long() const { return (long)get_VAL(); } + + INLINE unsigned long to_ulong() const { return (unsigned long)get_VAL(); } + + INLINE ap_slong to_int64() const { return (ap_slong)get_VAL(); } + + INLINE ap_ulong to_uint64() const { return (ap_ulong)get_VAL(); } + + INLINE double to_double() const { + if (isNegative()) + return roundToDouble(true); + else + return roundToDouble(false); + } + + INLINE unsigned length() const { return _AP_W; } + + INLINE bool isMinValue() const { return VAL == 0; } + template + INLINE ap_private& operator&=(const ap_private<_AP_W1, _AP_S1>& RHS) { + VAL = (ValType)(((uint64_t)VAL) & RHS.get_VAL()); + clearUnusedBits(); + return *this; + } + + template + INLINE ap_private& operator|=(const ap_private<_AP_W1, _AP_S1>& RHS) { + VAL = (ValType)(((uint64_t)VAL) | RHS.get_VAL()); + clearUnusedBits(); + return *this; + } + + template + INLINE ap_private& operator^=(const ap_private<_AP_W1, _AP_S1>& RHS) { + VAL = (ValType)(((uint64_t)VAL) ^ RHS.get_VAL()); + clearUnusedBits(); + return *this; + } + + template + INLINE ap_private& operator*=(const ap_private<_AP_W1, _AP_S1>& RHS) { + VAL = (ValType)(((uint64_t)VAL) * RHS.get_VAL()); + clearUnusedBits(); + return *this; + } + + template + INLINE ap_private& operator+=(const ap_private<_AP_W1, _AP_S1>& RHS) { + VAL = (ValType)(((uint64_t)VAL) + RHS.get_VAL()); + clearUnusedBits(); + return *this; + } + + template + INLINE ap_private& operator-=(const ap_private<_AP_W1, _AP_S1>& RHS) { + VAL = (ValType)(((uint64_t)VAL) - RHS.get_VAL()); + clearUnusedBits(); + return *this; + } + + template + INLINE typename RType<_AP_W1, _AP_S1>::logic operator&( + const ap_private<_AP_W1, _AP_S1>& RHS) const { + if (RType<_AP_W1, _AP_S1>::logic_w <= 64) { + typename RType<_AP_W1, _AP_S1>::logic Ret(((uint64_t)VAL) & + RHS.get_VAL()); + return Ret; + } else { + typename RType<_AP_W1, _AP_S1>::logic Ret = *this; + return Ret & RHS; + } + } + + template + INLINE typename RType<_AP_W1, _AP_S1>::logic operator^( + const ap_private<_AP_W1, _AP_S1>& RHS) const { + if (RType<_AP_W1, _AP_S1>::logic_w <= 64) { + typename RType<_AP_W1, _AP_S1>::logic Ret(((uint64_t)VAL) ^ + RHS.get_VAL()); + return Ret; + } else { + typename RType<_AP_W1, _AP_S1>::logic Ret = *this; + return Ret ^ RHS; + } + } + + template + INLINE typename RType<_AP_W1, _AP_S1>::logic operator|( + const ap_private<_AP_W1, _AP_S1>& RHS) const { + if (RType<_AP_W1, _AP_S1>::logic_w <= 64) { + typename RType<_AP_W1, _AP_S1>::logic Ret(((uint64_t)VAL) | + RHS.get_VAL()); + return Ret; + } else { + typename RType<_AP_W1, _AP_S1>::logic Ret = *this; + return Ret | RHS; + } + } + + INLINE ap_private And(const ap_private& RHS) const { + return ap_private(VAL & RHS.get_VAL()); + } + + INLINE ap_private Or(const ap_private& RHS) const { + return ap_private(VAL | RHS.get_VAL()); + } + + INLINE ap_private Xor(const ap_private& RHS) const { + return ap_private(VAL ^ RHS.get_VAL()); + } +#if 1 + template + INLINE typename RType<_AP_W1, _AP_S1>::mult operator*( + const ap_private<_AP_W1, _AP_S1>& RHS) const { + if (RType<_AP_W1, _AP_S1>::mult_w <= 64) { + typename RType<_AP_W1, _AP_S1>::mult Result(((uint64_t)VAL) * + RHS.get_VAL()); + return Result; + } else { + typename RType<_AP_W1, _AP_S1>::mult Result(*this); + Result *= RHS; + return Result; + } + } +#endif + INLINE ap_private Mul(const ap_private& RHS) const { + return ap_private(VAL * RHS.get_VAL()); + } + + INLINE ap_private Add(const ap_private& RHS) const { + return ap_private(VAL + RHS.get_VAL()); + } + + INLINE ap_private Sub(const ap_private& RHS) const { + return ap_private(VAL - RHS.get_VAL()); + } + + INLINE ap_private& operator&=(uint64_t RHS) { + VAL &= (ValType)RHS; + clearUnusedBits(); + return *this; + } + INLINE ap_private& operator|=(uint64_t RHS) { + VAL |= (ValType)RHS; + clearUnusedBits(); + return *this; + } + INLINE ap_private& operator^=(uint64_t RHS) { + VAL ^= (ValType)RHS; + clearUnusedBits(); + return *this; + } + INLINE ap_private& operator*=(uint64_t RHS) { + VAL *= (ValType)RHS; + clearUnusedBits(); + return *this; + } + INLINE ap_private& operator+=(uint64_t RHS) { + VAL += (ValType)RHS; + clearUnusedBits(); + return *this; + } + INLINE ap_private& operator-=(uint64_t RHS) { + VAL -= (ValType)RHS; + clearUnusedBits(); + return *this; + } + + INLINE bool isMinSignedValue() const { + static const uint64_t min_mask = ~(~0ULL << (_AP_W - 1)); + return BitWidth == 1 ? VAL == 1 + : (ap_private_ops::isNegative<_AP_W>(*this) && + ((min_mask & VAL) == 0)); + } + + template + INLINE typename RType<_AP_W1, _AP_S1>::plus operator+( + const ap_private<_AP_W1, _AP_S1>& RHS) const { + if (RType<_AP_W1, _AP_S1>::plus_w <= 64) + return typename RType<_AP_W1, _AP_S1>::plus( + RType<_AP_W1, _AP_S1>::plus_s + ? int64_t(((uint64_t)VAL) + RHS.get_VAL()) + : uint64_t(((uint64_t)VAL) + RHS.get_VAL())); + typename RType<_AP_W1, _AP_S1>::plus Result = RHS; + Result += VAL; + return Result; + } + + template + INLINE typename RType<_AP_W1, _AP_S1>::minus operator-( + const ap_private<_AP_W1, _AP_S1>& RHS) const { + if (RType<_AP_W1, _AP_S1>::minus_w <= 64) + return typename RType<_AP_W1, _AP_S1>::minus( + int64_t(((uint64_t)VAL) - RHS.get_VAL())); + typename RType<_AP_W1, _AP_S1>::minus Result = *this; + Result -= RHS; + return Result; + } + + INLINE uint32_t countPopulation() const { + return ap_private_ops::CountPopulation_64(VAL); + } + INLINE uint32_t countLeadingZeros() const { + int remainder = BitWidth % 64; + int excessBits = (64 - remainder) % 64; + uint32_t Count = ap_private_ops::CountLeadingZeros_64(VAL); + if (Count) Count -= excessBits; + return AESL_std::min(Count, (uint32_t)_AP_W); + } + + /// HiBits - This function returns the high "numBits" bits of this ap_private. + INLINE ap_private<_AP_W, _AP_S> getHiBits(uint32_t numBits) const { + ap_private<_AP_W, _AP_S> ret(*this); + ret = (ret) >> (BitWidth - numBits); + return ret; + } + + /// LoBits - This function returns the low "numBits" bits of this ap_private. + INLINE ap_private<_AP_W, _AP_S> getLoBits(uint32_t numBits) const { + ap_private<_AP_W, _AP_S> ret(((uint64_t)VAL) << (BitWidth - numBits)); + ret = (ret) >> (BitWidth - numBits); + return ret; + // return ap_private(numBits, (VAL << (BitWidth - numBits))>> (BitWidth - + // numBits)); + } + + INLINE ap_private<_AP_W, _AP_S>& set(uint32_t bitPosition) { + VAL |= (1ULL << (bitPosition)); + clearUnusedBits(); + return *this; // clearUnusedBits(); + } + + INLINE void set() { + VAL = (ValType)~0ULL; + clearUnusedBits(); + } + + template + INLINE void set(const ap_private<_AP_W3, false>& val) { + operator=(ap_private<_AP_W3, _AP_S>(val)); + } + + INLINE void set(const ap_private& val) { operator=(val); } + + INLINE void clearUnusedBits(void) volatile +// just for clang compiler +#if defined(__clang__) && !defined(__CLANG_3_1__) + __attribute__((no_sanitize("undefined"))) +#endif + { + enum { excess_bits = (_AP_W % 64) ? 64 - _AP_W % 64 : 0 }; + VAL = (ValType)( + _AP_S + ? ((((int64_t)VAL) << (excess_bits)) >> (excess_bits)) + : (excess_bits ? (((uint64_t)VAL) << (excess_bits)) >> (excess_bits) + : (uint64_t)VAL)); + } + + INLINE void clearUnusedBitsToZero(void) { + enum { excess_bits = (_AP_W % 64) ? 64 - _AP_W % 64 : 0 }; + static uint64_t mask = ~0ULL >> (excess_bits); + VAL &= mask; + } + + INLINE ap_private udiv(const ap_private& RHS) const { + return ap_private((uint64_t)VAL / RHS.get_VAL()); + } + + /// Signed divide this ap_private by ap_private RHS. + /// @brief Signed division function for ap_private. + INLINE ap_private sdiv(const ap_private& RHS) const { + if (isNegative()) + if (RHS.isNegative()) + return ((uint64_t)(0 - (*this))) / (uint64_t)(0 - RHS); + else + return 0 - ((uint64_t)(0 - (*this)) / (uint64_t)(RHS)); + else if (RHS.isNegative()) + return 0 - (this->udiv((ap_private)(0 - RHS))); + return this->udiv(RHS); + } + + template + INLINE ap_private urem(const ap_private<_AP_W, _AP_S2>& RHS) const { + assert(RHS.get_VAL() != 0 && "Divide by 0"); + return ap_private(((uint64_t)VAL) % ((uint64_t)RHS.get_VAL())); + } + + /// Signed remainder operation on ap_private. + /// @brief Function for signed remainder operation. + template + INLINE ap_private srem(const ap_private<_AP_W, _AP_S2>& RHS) const { + if (isNegative()) { + ap_private lhs = 0 - (*this); + if (RHS.isNegative()) { + ap_private rhs = 0 - RHS; + return 0 - (lhs.urem(rhs)); + } else + return 0 - (lhs.urem(RHS)); + } else if (RHS.isNegative()) { + ap_private rhs = 0 - RHS; + return this->urem(rhs); + } + return this->urem(RHS); + } + + template + INLINE bool eq(const ap_private<_AP_W1, _AP_S1>& RHS) const { + return (*this) == RHS; + } + + template + INLINE bool ne(const ap_private<_AP_W1, _AP_S1>& RHS) const { + return !((*this) == RHS); + } + + /// Regards both *this and RHS as unsigned quantities and compares them for + /// the validity of the less-than relationship. + /// @returns true if *this < RHS when both are considered unsigned. + /// @brief Unsigned less than comparison + template + INLINE bool ult(const ap_private<_AP_W1, _AP_S1>& RHS) const { + if (_AP_W1 <= 64) { + uint64_t lhsZext = ((uint64_t(VAL)) << (64 - _AP_W)) >> (64 - _AP_W); + uint64_t rhsZext = + ((uint64_t(RHS.get_VAL())) << (64 - _AP_W1)) >> (64 - _AP_W1); + return lhsZext < rhsZext; + } else + return RHS.uge(*this); + } + + /// Regards both *this and RHS as signed quantities and compares them for + /// validity of the less-than relationship. + /// @returns true if *this < RHS when both are considered signed. + /// @brief Signed less than comparison + template + INLINE bool slt(const ap_private<_AP_W1, _AP_S1>& RHS) const +// just for clang compiler +#if defined(__clang__) && !defined(__CLANG_3_1__) + __attribute__((no_sanitize("undefined"))) +#endif + { + if (_AP_W1 <= 64) { + int64_t lhsSext = ((int64_t(VAL)) << (64 - _AP_W)) >> (64 - _AP_W); + int64_t rhsSext = + ((int64_t(RHS.get_VAL())) << (64 - _AP_W1)) >> (64 - _AP_W1); + return lhsSext < rhsSext; + } else + return RHS.sge(*this); + } + + /// Regards both *this and RHS as unsigned quantities and compares them for + /// validity of the less-or-equal relationship. + /// @returns true if *this <= RHS when both are considered unsigned. + /// @brief Unsigned less or equal comparison + template + INLINE bool ule(const ap_private<_AP_W1, _AP_S1>& RHS) const { + return ult(RHS) || eq(RHS); + } + + /// Regards both *this and RHS as signed quantities and compares them for + /// validity of the less-or-equal relationship. + /// @returns true if *this <= RHS when both are considered signed. + /// @brief Signed less or equal comparison + template + INLINE bool sle(const ap_private<_AP_W1, _AP_S1>& RHS) const { + return slt(RHS) || eq(RHS); + } + + /// Regards both *this and RHS as unsigned quantities and compares them for + /// the validity of the greater-than relationship. + /// @returns true if *this > RHS when both are considered unsigned. + /// @brief Unsigned greather than comparison + template + INLINE bool ugt(const ap_private<_AP_W1, _AP_S1>& RHS) const { + return !ult(RHS) && !eq(RHS); + } + + /// Regards both *this and RHS as signed quantities and compares them for + /// the validity of the greater-than relationship. + /// @returns true if *this > RHS when both are considered signed. + /// @brief Signed greather than comparison + template + INLINE bool sgt(const ap_private<_AP_W1, _AP_S1>& RHS) const { + return !slt(RHS) && !eq(RHS); + } + + /// Regards both *this and RHS as unsigned quantities and compares them for + /// validity of the greater-or-equal relationship. + /// @returns true if *this >= RHS when both are considered unsigned. + /// @brief Unsigned greater or equal comparison + template + INLINE bool uge(const ap_private<_AP_W1, _AP_S1>& RHS) const { + return !ult(RHS); + } + + /// Regards both *this and RHS as signed quantities and compares them for + /// validity of the greater-or-equal relationship. + /// @returns true if *this >= RHS when both are considered signed. + /// @brief Signed greather or equal comparison + template + INLINE bool sge(const ap_private<_AP_W1, _AP_S1>& RHS) const { + return !slt(RHS); + } + + INLINE ap_private abs() const { + if (isNegative()) return -(*this); + return *this; + } + + INLINE ap_private<_AP_W, false> get() const { + ap_private<_AP_W, false> ret(*this); + return ret; + } + + INLINE static uint32_t getBitsNeeded(const char* str, uint32_t slen, + uint8_t radix) { + return _AP_W; + } + + INLINE uint32_t getActiveBits() const { + uint32_t bits = _AP_W - countLeadingZeros(); + return bits ? bits : 1; + } + + INLINE double roundToDouble(bool isSigned = false) const { + return isSigned ? double((int64_t)VAL) : double((uint64_t)VAL); + } + + /*Reverse the contents of ap_private instance. I.e. LSB becomes MSB and vise + * versa*/ + INLINE ap_private& reverse() { + for (int i = 0; i < _AP_W / 2; ++i) { + bool tmp = operator[](i); + if (operator[](_AP_W - 1 - i)) + set(i); + else + clear(i); + if (tmp) + set(_AP_W - 1 - i); + else + clear(_AP_W - 1 - i); + } + clearUnusedBits(); + return *this; + } + + /*Return true if the value of ap_private instance is zero*/ + INLINE bool iszero() const { return isMinValue(); } + + INLINE bool to_bool() const { return !iszero(); } + + /* x < 0 */ + INLINE bool sign() const { + if (isNegative()) return true; + return false; + } + + /* x[i] = !x[i] */ + INLINE void invert(int i) { + assert(i >= 0 && "Attempting to read bit with negative index"); + assert(i < _AP_W && "Attempting to read bit beyond MSB"); + flip(i); + } + + /* x[i] */ + INLINE bool test(int i) const { + assert(i >= 0 && "Attempting to read bit with negative index"); + assert(i < _AP_W && "Attempting to read bit beyond MSB"); + return operator[](i); + } + + // This is used for sc_lv and sc_bv, which is implemented by sc_uint + // Rotate an ap_private object n places to the left + INLINE void lrotate(int n) { + assert(n >= 0 && "Attempting to shift negative index"); + assert(n < _AP_W && "Shift value larger than bit width"); + operator=(shl(n) | lshr(_AP_W - n)); + } + + // This is used for sc_lv and sc_bv, which is implemented by sc_uint + // Rotate an ap_private object n places to the right + INLINE void rrotate(int n) { + assert(n >= 0 && "Attempting to shift negative index"); + assert(n < _AP_W && "Shift value larger than bit width"); + operator=(lshr(n) | shl(_AP_W - n)); + } + + // Set the ith bit into v + INLINE void set(int i, bool v) { + assert(i >= 0 && "Attempting to write bit with negative index"); + assert(i < _AP_W && "Attempting to write bit beyond MSB"); + v ? set(i) : clear(i); + } + + // Set the ith bit into v + INLINE void set_bit(int i, bool v) { + assert(i >= 0 && "Attempting to write bit with negative index"); + assert(i < _AP_W && "Attempting to write bit beyond MSB"); + v ? set(i) : clear(i); + } + + // Get the value of ith bit + INLINE bool get_bit(int i) const { + assert(i >= 0 && "Attempting to read bit with negative index"); + assert(i < _AP_W && "Attempting to read bit beyond MSB"); + return (((1ULL << i) & VAL) != 0); + } + + /// Toggle all bits. + INLINE ap_private& flip() { + VAL = (ValType)((~0ULL ^ VAL) & mask); + clearUnusedBits(); + return *this; + } + + /// Toggles a given bit to its opposite value. + INLINE ap_private& flip(uint32_t bitPosition) { + assert(bitPosition < BitWidth && "Out of the bit-width range!"); + set_bit(bitPosition, !get_bit(bitPosition)); + return *this; + } + + // complements every bit + INLINE void b_not() { flip(); } + +// Binary Arithmetic +//----------------------------------------------------------- +#define OP_BIN_AP(Sym, Rty, Fun) \ + template \ + INLINE typename RType<_AP_W2, _AP_S2>::Rty operator Sym( \ + const ap_private<_AP_W2, _AP_S2>& op) const { \ + typename RType<_AP_W2, _AP_S2>::Rty lhs(*this); \ + typename RType<_AP_W2, _AP_S2>::Rty rhs(op); \ + return lhs.Fun(rhs); \ + } + +/// Bitwise and, or, xor +// OP_BIN_AP(&,logic, And) +// OP_BIN_AP(|,logic, Or) +// OP_BIN_AP(^,logic, Xor) +#undef OP_BIN_AP + + template + INLINE typename RType<_AP_W2, _AP_S2>::div operator/( + const ap_private<_AP_W2, _AP_S2>& op) const { + ap_private _AP_W2 ? _AP_S + : (_AP_W2 > _AP_W ? _AP_S2 : _AP_S || _AP_S2))> + lhs = *this; + ap_private _AP_W2 ? _AP_S + : (_AP_W2 > _AP_W ? _AP_S2 : _AP_S || _AP_S2))> + rhs = op; + return typename RType<_AP_W2, _AP_S2>::div( + (_AP_S || _AP_S2) ? lhs.sdiv(rhs) : lhs.udiv(rhs)); + } + + template + INLINE typename RType<_AP_W2, _AP_S2>::mod operator%( + const ap_private<_AP_W2, _AP_S2>& op) const { + ap_private _AP_W2 ? _AP_S + : (_AP_W2 > _AP_W ? _AP_S2 : _AP_S || _AP_S2))> + lhs = *this; + ap_private _AP_W2 ? _AP_S + : (_AP_W2 > _AP_W ? _AP_S2 : _AP_S || _AP_S2))> + rhs = op; + typename RType<_AP_W2, _AP_S2>::mod res = + typename RType<_AP_W2, _AP_S2>::mod(_AP_S ? lhs.srem(rhs) + : lhs.urem(rhs)); + return res; + } + +#define OP_ASSIGN_AP_2(Sym) \ + template \ + INLINE ap_private<_AP_W, _AP_S>& operator Sym##=( \ + const ap_private<_AP_W2, _AP_S2>& op) { \ + *this = operator Sym(op); \ + return *this; \ + } + + OP_ASSIGN_AP_2(/) + OP_ASSIGN_AP_2(%) +#undef OP_ASSIGN_AP_2 + +/// Bitwise assign: and, or, xor +//------------------------------------------------------------- +// OP_ASSIGN_AP(&) +// OP_ASSIGN_AP(^) +// OP_ASSIGN_AP(|) + +#define OP_LEFT_SHIFT_CTYPE(TYPE, SIGNED) \ + INLINE ap_private operator<<(const TYPE op) const { \ + if (op >= _AP_W) return ap_private(0); \ + if (SIGNED && op < 0) return *this >> (0 - op); \ + return shl(op); \ + } + + // OP_LEFT_SHIFT_CTYPE(bool, false) + OP_LEFT_SHIFT_CTYPE(char, CHAR_IS_SIGNED) + OP_LEFT_SHIFT_CTYPE(signed char, true) + OP_LEFT_SHIFT_CTYPE(unsigned char, false) + OP_LEFT_SHIFT_CTYPE(short, true) + OP_LEFT_SHIFT_CTYPE(unsigned short, false) + OP_LEFT_SHIFT_CTYPE(int, true) + OP_LEFT_SHIFT_CTYPE(unsigned int, false) + OP_LEFT_SHIFT_CTYPE(long, true) + OP_LEFT_SHIFT_CTYPE(unsigned long, false) + OP_LEFT_SHIFT_CTYPE(long long, true) + OP_LEFT_SHIFT_CTYPE(unsigned long long, false) +#if 0 + OP_LEFT_SHIFT_CTYPE(half, false) + OP_LEFT_SHIFT_CTYPE(float, false) + OP_LEFT_SHIFT_CTYPE(double, false) +#endif + +#undef OP_LEFT_SHIFT_CTYPE + + template + INLINE ap_private operator<<(const ap_private<_AP_W2, _AP_S2>& op2) const { + if (_AP_S2 == false) { + uint32_t sh = op2.to_uint(); + return *this << sh; + } else { + int sh = op2.to_int(); + return *this << sh; + } + } + +#define OP_RIGHT_SHIFT_CTYPE(TYPE, SIGNED) \ + INLINE ap_private operator>>(const TYPE op) const { \ + if (op >= _AP_W) { \ + if (isNegative()) \ + return ap_private(-1); \ + else \ + return ap_private(0); \ + } \ + if ((SIGNED) && op < 0) return *this << (0 - op); \ + if (_AP_S) \ + return ashr(op); \ + else \ + return lshr(op); \ + } + + // OP_RIGHT_SHIFT_CTYPE(bool, false) + OP_RIGHT_SHIFT_CTYPE(char, CHAR_IS_SIGNED) + OP_RIGHT_SHIFT_CTYPE(signed char, true) + OP_RIGHT_SHIFT_CTYPE(unsigned char, false) + OP_RIGHT_SHIFT_CTYPE(short, true) + OP_RIGHT_SHIFT_CTYPE(unsigned short, false) + OP_RIGHT_SHIFT_CTYPE(int, true) + OP_RIGHT_SHIFT_CTYPE(unsigned int, false) + OP_RIGHT_SHIFT_CTYPE(long, true) + OP_RIGHT_SHIFT_CTYPE(unsigned long, false) + OP_RIGHT_SHIFT_CTYPE(unsigned long long, false) + OP_RIGHT_SHIFT_CTYPE(long long, true) +#if 0 + OP_RIGHT_SHIFT_CTYPE(half, false) + OP_RIGHT_SHIFT_CTYPE(float, false) + OP_RIGHT_SHIFT_CTYPE(double, false) +#endif + +#undef OP_RIGHT_SHIFT_CTYPE + + template + INLINE ap_private operator>>(const ap_private<_AP_W2, _AP_S2>& op2) const { + if (_AP_S2 == false) { + uint32_t sh = op2.to_uint(); + return *this >> sh; + } else { + int sh = op2.to_int(); + return *this >> sh; + } + } + + /// Shift assign + //----------------------------------------------------------------- + + //INLINE const ap_private& operator<<=(uint32_t shiftAmt) { + // VAL <<= shiftAmt; + // clearUnusedBits(); + // return *this; + //} + +#define OP_ASSIGN_AP(Sym) \ + template \ + INLINE ap_private& operator Sym##=(int op) { \ + *this = operator Sym(op); \ + clearUnusedBits(); \ + return *this; \ + } \ + INLINE ap_private& operator Sym##=(unsigned int op) { \ + *this = operator Sym(op); \ + clearUnusedBits(); \ + return *this; \ + } \ + template \ + INLINE ap_private& operator Sym##=(const ap_private<_AP_W2, _AP_S2>& op) { \ + *this = operator Sym(op); \ + clearUnusedBits(); \ + return *this; \ + } + + OP_ASSIGN_AP(>>) + OP_ASSIGN_AP(<<) +#undef OP_ASSIGN_AP + + /// Comparisons + //----------------------------------------------------------------- + template + INLINE bool operator==(const ap_private<_AP_W1, _AP_S1>& op) const { + enum { _AP_MAX_W = AP_MAX(AP_MAX(_AP_W, _AP_W1), 32) }; + ap_private<_AP_MAX_W, false> lhs(*this); + ap_private<_AP_MAX_W, false> rhs(op); + if (_AP_MAX_W <= 64) { + return (uint64_t)lhs.get_VAL() == (uint64_t)rhs.get_VAL(); + } else + return lhs == rhs; + } + + template + INLINE bool operator!=(const ap_private<_AP_W2, _AP_S2>& op) const { + return !(*this == op); + } + + template + INLINE bool operator>(const ap_private<_AP_W2, _AP_S2>& op) const { + enum { + _AP_MAX_W = AP_MAX(_AP_W + (_AP_S || _AP_S2), _AP_W2 + (_AP_S || _AP_S2)) + }; + ap_private<_AP_MAX_W, _AP_S> lhs(*this); + ap_private<_AP_MAX_W, _AP_S2> rhs(op); + // this will follow gcc rule for comparison + // between different bitwidth and signness + if (_AP_S == _AP_S2) + return _AP_S ? lhs.sgt(rhs) : lhs.ugt(rhs); + else if (_AP_W < 32 && _AP_W2 < 32) + // different signness but both bitwidth is less than 32 + return lhs.sgt(rhs); + else + // different signness but bigger bitwidth + // is greater or equal to 32 + if (_AP_S) + if (_AP_W2 >= _AP_W) + return lhs.ugt(rhs); + else + return lhs.sgt(rhs); + else if (_AP_W >= _AP_W2) + return lhs.ugt(rhs); + else + return lhs.sgt(rhs); + } + + template + INLINE bool operator<=(const ap_private<_AP_W2, _AP_S2>& op) const { + return !(*this > op); + } + + template + INLINE bool operator<(const ap_private<_AP_W2, _AP_S2>& op) const { + enum { + _AP_MAX_W = AP_MAX(_AP_W + (_AP_S || _AP_S2), _AP_W2 + (_AP_S || _AP_S2)) + }; + ap_private<_AP_MAX_W, _AP_S> lhs(*this); + ap_private<_AP_MAX_W, _AP_S2> rhs(op); + if (_AP_S == _AP_S2) + return _AP_S ? lhs.slt(rhs) : lhs.ult(rhs); + else if (_AP_W < 32 && _AP_W2 < 32) + return lhs.slt(rhs); + else if (_AP_S) + if (_AP_W2 >= _AP_W) + return lhs.ult(rhs); + else + return lhs.slt(rhs); + else if (_AP_W >= _AP_W2) + return lhs.ult(rhs); + else + return lhs.slt(rhs); + } + + template + INLINE bool operator>=(const ap_private<_AP_W2, _AP_S2>& op) const { + return !(*this < op); + } + + /// Bit and Part Select + //-------------------------------------------------------------- + // FIXME now _private_range_ref refs to _AP_ROOT_TYPE(struct ssdm_int). + INLINE _private_range_ref<_AP_W, _AP_S> operator()(int Hi, int Lo) { + return _private_range_ref<_AP_W, _AP_S>(this, Hi, Lo); + } + + INLINE _private_range_ref<_AP_W, _AP_S> operator()(int Hi, int Lo) const { + return _private_range_ref<_AP_W, _AP_S>( + const_cast*>(this), Hi, Lo); + } + + INLINE _private_range_ref<_AP_W, _AP_S> range(int Hi, int Lo) const { + return _private_range_ref<_AP_W, _AP_S>( + (const_cast*>(this)), Hi, Lo); + } + + INLINE _private_range_ref<_AP_W, _AP_S> range(int Hi, int Lo) { + return _private_range_ref<_AP_W, _AP_S>(this, Hi, Lo); + } + + INLINE _private_bit_ref<_AP_W, _AP_S> operator[](int index) { + return _private_bit_ref<_AP_W, _AP_S>(*this, index); + } + + template + INLINE _private_bit_ref<_AP_W, _AP_S> operator[]( + const ap_private<_AP_W2, _AP_S2>& index) { + return _private_bit_ref<_AP_W, _AP_S>(*this, index.to_int()); + } + + INLINE const _private_bit_ref<_AP_W, _AP_S> operator[](int index) const { + return _private_bit_ref<_AP_W, _AP_S>( + const_cast&>(*this), index); + } + + template + INLINE const _private_bit_ref<_AP_W, _AP_S> operator[]( + const ap_private<_AP_W2, _AP_S2>& index) const { + return _private_bit_ref<_AP_W, _AP_S>( + const_cast&>(*this), index.to_int()); + } + + INLINE _private_bit_ref<_AP_W, _AP_S> bit(int index) { + return _private_bit_ref<_AP_W, _AP_S>(*this, index); + } + + template + INLINE _private_bit_ref<_AP_W, _AP_S> bit(const ap_private<_AP_W2, _AP_S2>& index) { + return _private_bit_ref<_AP_W, _AP_S>(*this, index.to_int()); + } + + INLINE const _private_bit_ref<_AP_W, _AP_S> bit(int index) const { + return _private_bit_ref<_AP_W, _AP_S>( + const_cast&>(*this), index); + } + + template + INLINE const _private_bit_ref<_AP_W, _AP_S> bit( + const ap_private<_AP_W2, _AP_S2>& index) const { + return _private_bit_ref<_AP_W, _AP_S>( + const_cast&>(*this), index.to_int()); + } + +// template +// INLINE ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2, +// ap_private<_AP_W2, _AP_S2> > +// concat(const ap_private<_AP_W2, _AP_S2>& a2) const { +// return ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2, +// ap_private<_AP_W2, _AP_S2> >( +// const_cast&>(*this), +// const_cast&>(a2)); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2, +// ap_private<_AP_W2, _AP_S2> > +// concat(ap_private<_AP_W2, _AP_S2>& a2) { +// return ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2, +// ap_private<_AP_W2, _AP_S2> >(*this, a2); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, ap_private, _AP_W2, ap_private<_AP_W2, _AP_S2> > +// operator,(const ap_private<_AP_W2, _AP_S2> &a2) const { +// return ap_concat_ref<_AP_W, ap_private, _AP_W2, +// ap_private<_AP_W2, _AP_S2> >( +// const_cast&>(*this), +// const_cast&>(a2)); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, ap_private, _AP_W2, ap_private<_AP_W2, _AP_S2> > +// operator,(const ap_private<_AP_W2, _AP_S2> &a2) { +// return ap_concat_ref<_AP_W, ap_private, _AP_W2, +// ap_private<_AP_W2, _AP_S2> >( +// *this, const_cast&>(a2)); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, ap_private, _AP_W2, ap_private<_AP_W2, _AP_S2> > +// operator,(ap_private<_AP_W2, _AP_S2> &a2) const { +// return ap_concat_ref<_AP_W, ap_private, _AP_W2, +// ap_private<_AP_W2, _AP_S2> >( +// const_cast&>(*this), a2); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, ap_private, _AP_W2, ap_private<_AP_W2, _AP_S2> > +// operator,(ap_private<_AP_W2, _AP_S2> &a2) { +// return ap_concat_ref<_AP_W, ap_private, _AP_W2, +// ap_private<_AP_W2, _AP_S2> >(*this, a2); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2, +// _private_range_ref<_AP_W2, _AP_S2> > +// operator,(const _private_range_ref<_AP_W2, _AP_S2> &a2) const { +// return ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2, +// _private_range_ref<_AP_W2, _AP_S2> >( +// const_cast&>(*this), +// const_cast<_private_range_ref<_AP_W2, _AP_S2>&>(a2)); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2, +// _private_range_ref<_AP_W2, _AP_S2> > +// operator,(_private_range_ref<_AP_W2, _AP_S2> &a2) { +// return ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2, +// _private_range_ref<_AP_W2, _AP_S2> >(*this, a2); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, 1, +// _private_bit_ref<_AP_W2, _AP_S2> > +// operator,(const _private_bit_ref<_AP_W2, _AP_S2> &a2) const { +// return ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, 1, +// _private_bit_ref<_AP_W2, _AP_S2> >( +// const_cast&>(*this), +// const_cast<_private_bit_ref<_AP_W2, _AP_S2>&>(a2)); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, 1, +// _private_bit_ref<_AP_W2, _AP_S2> > +// operator,(_private_bit_ref<_AP_W2, _AP_S2> &a2) { +// return ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, 1, +// _private_bit_ref<_AP_W2, _AP_S2> >(*this, a2); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2 + _AP_W3, +// ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> > +// operator,(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &a2) const { +// return ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2 + _AP_W3, +// ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >( +// const_cast&>(*this), +// const_cast&>(a2)); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2 + _AP_W3, +// ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> > +// operator,(ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &a2) { +// return ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2 + _AP_W3, +// ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >(*this, +// a2); +// } +// +// template +// INLINE ap_concat_ref< +// _AP_W, ap_private, _AP_W2, +// af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> > +// operator,(const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> +// &a2) const { +// return ap_concat_ref< +// _AP_W, ap_private, _AP_W2, +// af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >( +// const_cast&>(*this), +// const_cast< +// af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>&>(a2)); +// } +// +// template +// INLINE ap_concat_ref< +// _AP_W, ap_private, _AP_W2, +// af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> > +// operator,(af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> &a2) { +// return ap_concat_ref< +// _AP_W, ap_private, _AP_W2, +// af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this, +// a2); +// } +// +// template +// INLINE +// ap_concat_ref<_AP_W, ap_private, 1, +// af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> > +// operator,(const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> +// &a2) const { +// return ap_concat_ref< +// _AP_W, ap_private, 1, +// af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >( +// const_cast&>(*this), +// const_cast&>( +// a2)); +// } +// +// template +// INLINE +// ap_concat_ref<_AP_W, ap_private, 1, +// af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> > +// operator,( +// af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> &a2) { +// return ap_concat_ref< +// _AP_W, ap_private, 1, +// af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this, a2); +// } +// +// template +// INLINE ap_private operator&( +// const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& a2) { +// return *this & a2.get(); +// } +// +// template +// INLINE ap_private operator|( +// const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& a2) { +// return *this | a2.get(); +// } +// +// template +// INLINE ap_private operator^( +// const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& a2) { +// return *this ^ a2.get(); +// } + + // Reduce operation + //----------------------------------------------------------- + INLINE bool and_reduce() const { return (VAL & mask) == mask; } + + INLINE bool nand_reduce() const { return (VAL & mask) != mask; } + + INLINE bool or_reduce() const { return (bool)VAL; } + + INLINE bool nor_reduce() const { return VAL == 0; } + + INLINE bool xor_reduce() const { + unsigned int i = countPopulation(); + return (i % 2) ? true : false; + } + + INLINE bool xnor_reduce() const { + unsigned int i = countPopulation(); + return (i % 2) ? false : true; + } + + INLINE std::string to_string(uint8_t radix = 2, bool sign = false) const { + return toString(radix, radix == 10 ? _AP_S : sign); + } +}; // End of class ap_private <_AP_W, _AP_S, true> + +template +std::string ap_private<_AP_W, _AP_S, true>::toString(uint8_t radix, + bool wantSigned) const { + assert((radix == 10 || radix == 8 || radix == 16 || radix == 2) && + "Radix should be 2, 8, 10, or 16!"); + static const char* digits[] = {"0", "1", "2", "3", "4", "5", "6", "7", + "8", "9", "a", "b", "c", "d", "e", "f"}; + std::string result; + if (radix != 10) { + // For the 2, 8 and 16 bit cases, we can just shift instead of divide + // because the number of bits per digit (1,3 and 4 respectively) divides + // equaly. We just shift until there value is zero. + + // First, check for a zero value and just short circuit the logic below. + if (*this == (uint64_t)(0)) { + // Always generate a radix indicator because fixed-point + // formats require it. + switch (radix) { + case 2: + result = "0b0"; + break; + case 8: + result = "0o0"; + break; + case 16: + result = "0x0"; + break; + default: + assert("invalid radix" && 0); + } + } else { + ap_private<_AP_W, false, true> tmp(*this); + size_t insert_at = 0; + bool leading_zero = true; + if (wantSigned && isNegative()) { + // They want to print the signed version and it is a negative value + // Flip the bits and add one to turn it into the equivalent positive + // value and put a '-' in the result. + tmp.flip(); + tmp++; + result = "-"; + insert_at = 1; + leading_zero = false; + } + switch (radix) { + case 2: + result += "0b"; + break; + case 8: + result += "0o"; + break; + case 16: + result += "0x"; + break; + default: + assert("invalid radix" && 0); + } + insert_at += 2; + + // Just shift tmp right for each digit width until it becomes zero + uint32_t shift = (radix == 16 ? 4 : (radix == 8 ? 3 : 1)); + uint64_t mask = radix - 1; + ap_private<_AP_W, false, true> zero(0); + unsigned bits = 0; + bool msb = false; + while (tmp.ne(zero)) { + unsigned digit = (unsigned)(tmp.get_VAL() & mask); + result.insert(insert_at, digits[digit]); + tmp = tmp.lshr(shift); + bits++; + msb = (digit >> (shift - 1)) == 1; + } + bits *= shift; + if (bits < _AP_W && leading_zero && msb) + result.insert(insert_at, digits[0]); + } + return result; + } + + ap_private<_AP_W, false, true> tmp(*this); + ap_private<6, false, true> divisor(radix); + ap_private<_AP_W, _AP_S, true> zero(0); + size_t insert_at = 0; + if (wantSigned && isNegative()) { + // They want to print the signed version and it is a negative value + // Flip the bits and add one to turn it into the equivalent positive + // value and put a '-' in the result. + tmp.flip(); + tmp++; + result = "-"; + insert_at = 1; + } + if (tmp == ap_private<_AP_W, false, true>(0ULL)) + result = "0"; + else + while (tmp.ne(zero)) { + ap_private<_AP_W, false, true> APdigit = tmp % divisor; + ap_private<_AP_W, false, true> tmp2 = tmp / divisor; + uint32_t digit = (uint32_t)(APdigit.getZExtValue()); + assert(digit < radix && "divide failed"); + result.insert(insert_at, digits[digit]); + tmp = tmp2; + } + return result; + +} // End of ap_private<_AP_W, _AP_S, true>::toString() + +// bitwidth > 64 +template +class ap_private<_AP_W, _AP_S, false> { + // SFINAE pattern. Only consider this class when _AP_W > 64 + const static bool valid = ap_private_enable_if<(_AP_W > 64)>::isValid; + +#ifdef _MSC_VER +#pragma warning(disable : 4521 4522) +#endif + public: + enum { BitWidth = _AP_W, _AP_N = (_AP_W + 63) / 64 }; + static const int width = _AP_W; + + private: + /// This constructor is used only internally for speed of construction of + /// temporaries. It is unsafe for general use so it is not public. + + /* Constructors */ + /// Note that numWords can be smaller or larger than the corresponding bit + /// width but any extraneous bits will be dropped. + /// @param numWords the number of words in bigVal + /// @param bigVal a sequence of words to form the initial value of the + /// ap_private + /// @brief Construct an ap_private, initialized as bigVal[]. + INLINE ap_private(uint32_t numWords, const uint64_t bigVal[]) { + set_canary(); + assert(bigVal && "Null pointer detected!"); + { + // Get memory, cleared to 0 + memset(pVal, 0, _AP_N * sizeof(uint64_t)); + + // Calculate the number of words to copy + uint32_t words = AESL_std::min(numWords, _AP_N); + // Copy the words from bigVal to pVal + memcpy(pVal, bigVal, words * APINT_WORD_SIZE); + if (words >= _AP_W) clearUnusedBits(); + // Make sure unused high bits are cleared + } + check_canary(); + } + + /// This constructor interprets Val as a string in the given radix. The + /// interpretation stops when the first charater that is not suitable for the + /// radix is encountered. Acceptable radix values are 2, 8, 10 and 16. It is + /// an error for the value implied by the string to require more bits than + /// numBits. + /// @param val the string to be interpreted + /// @param radix the radix of Val to use for the intepretation + /// @brief Construct an ap_private from a string representation. + INLINE ap_private(const std::string& val, uint8_t radix = 2) { + set_canary(); + assert(!val.empty() && "The input string is empty."); + const char* c_str = val.c_str(); + fromString(c_str, val.size(), radix); + check_canary(); + } + + /// This constructor interprets the slen characters starting at StrStart as + /// a string in the given radix. The interpretation stops when the first + /// character that is not suitable for the radix is encountered. Acceptable + /// radix values are 2, 8, 10 and 16. It is an error for the value implied by + /// the string to require more bits than numBits. + /// @param strStart the start of the string to be interpreted + /// @param slen the maximum number of characters to interpret + /// @param radix the radix to use for the conversion + /// @brief Construct an ap_private from a string representation. + /// This method does not consider whether it is negative or not. + INLINE ap_private(const char strStart[], uint32_t slen, uint8_t radix) { + set_canary(); + fromString(strStart, slen, radix); + check_canary(); + } + + INLINE void report() { + _AP_ERROR(_AP_W > MAX_MODE(AP_INT_MAX_W) * 1024, + "ap_%sint<%d>: Bitwidth exceeds the " + "default max value %d. Please use macro " + "AP_INT_MAX_W to set a larger max value.", + _AP_S ? "" : "u", _AP_W, MAX_MODE(AP_INT_MAX_W) * 1024); + } + /// This union is used to store the integer value. When the + /// integer bit-width <= 64, it uses VAL, otherwise it uses pVal. + + /// This enum is used to hold the constants we needed for ap_private. + // uint64_t VAL; ///< Used to store the <= 64 bits integer value. + uint64_t pVal[_AP_N]; ///< Used to store the >64 bits integer value. +#ifdef AP_CANARY + uint64_t CANARY; + INLINE void check_canary() { assert(CANARY == (uint64_t)0xDEADBEEFDEADBEEF); } + INLINE void set_canary() { CANARY = (uint64_t)0xDEADBEEFDEADBEEF; } +#else + INLINE void check_canary() {} + INLINE void set_canary() {} +#endif + + public: + typedef typename valtype<8, _AP_S>::Type ValType; + typedef ap_private<_AP_W, _AP_S> Type; + // FIXME remove friend type? + template + friend struct ap_fixed_base; + /// return type of variety of operations + //---------------------------------------------------------- + template + struct RType { + enum { + mult_w = _AP_W + _AP_W2, + mult_s = _AP_S || _AP_S2, + plus_w = + AP_MAX(_AP_W + (_AP_S2 && !_AP_S), _AP_W2 + (_AP_S && !_AP_S2)) + 1, + plus_s = _AP_S || _AP_S2, + minus_w = + AP_MAX(_AP_W + (_AP_S2 && !_AP_S), _AP_W2 + (_AP_S && !_AP_S2)) + 1, + minus_s = true, + div_w = _AP_W + _AP_S2, + div_s = _AP_S || _AP_S2, + mod_w = AP_MIN(_AP_W, _AP_W2 + (!_AP_S2 && _AP_S)), + mod_s = _AP_S, + logic_w = AP_MAX(_AP_W + (_AP_S2 && !_AP_S), _AP_W2 + (_AP_S && !_AP_S2)), + logic_s = _AP_S || _AP_S2 + }; + typedef ap_private mult; + typedef ap_private plus; + typedef ap_private minus; + typedef ap_private logic; + typedef ap_private div; + typedef ap_private mod; + typedef ap_private<_AP_W, _AP_S> arg1; + typedef bool reduce; + }; + + INLINE uint64_t& get_VAL(void) { return pVal[0]; } + INLINE uint64_t get_VAL(void) const { return pVal[0]; } + INLINE uint64_t get_VAL(void) const volatile { return pVal[0]; } + INLINE void set_VAL(uint64_t value) { pVal[0] = value; } + INLINE uint64_t& get_pVal(int index) { return pVal[index]; } + INLINE uint64_t* get_pVal() { return pVal; } + INLINE const uint64_t* get_pVal() const { return pVal; } + INLINE uint64_t get_pVal(int index) const { return pVal[index]; } + INLINE uint64_t* get_pVal() const volatile { return pVal; } + INLINE uint64_t get_pVal(int index) const volatile { return pVal[index]; } + INLINE void set_pVal(int i, uint64_t value) { pVal[i] = value; } + + /// This enum is used to hold the constants we needed for ap_private. + enum { + APINT_BITS_PER_WORD = sizeof(uint64_t) * 8, ///< Bits in a word + APINT_WORD_SIZE = sizeof(uint64_t) ///< Byte size of a word + }; + + enum { + excess_bits = (_AP_W % APINT_BITS_PER_WORD) + ? APINT_BITS_PER_WORD - (_AP_W % APINT_BITS_PER_WORD) + : 0 + }; + static const uint64_t mask = ((uint64_t)~0ULL >> (excess_bits)); + + public: + // NOTE changed to explicit to be consistent with ap_private + explicit INLINE ap_private(const char* val) { + set_canary(); + unsigned char radix = 10; + std::string str = ap_private_ops::parseString(val, radix); // determine radix. + std::string::size_type pos = str.find('.'); + if (pos != std::string::npos) str = str.substr(pos); + ap_private ap_private_val(str, radix); + operator=(ap_private_val); + report(); + check_canary(); + } + + INLINE ap_private(const char* val, unsigned char rd) { + set_canary(); + unsigned char radix = rd; + std::string str = ap_private_ops::parseString(val, radix); // determine radix. + std::string::size_type pos = str.find('.'); + if (pos != std::string::npos) str = str.substr(pos); + ap_private ap_private_val(str, radix); + operator=(ap_private_val); + report(); + + report(); + check_canary(); + } + + template + INLINE ap_private(const _private_range_ref<_AP_W2, _AP_S2>& ref) { + set_canary(); + *this = ref.get(); + report(); + check_canary(); + } + + template + INLINE ap_private(const _private_bit_ref<_AP_W2, _AP_S2>& ref) { + set_canary(); + *this = ((uint64_t)(bool)ref); + report(); + check_canary(); + } + +// template +// INLINE ap_private(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& ref) { +// set_canary(); +// *this = ref.get(); +// report(); +// check_canary(); +// } +// +// template +// INLINE ap_private( +// const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) { +// set_canary(); +// *this = ((val.operator ap_private<_AP_W2, false>())); +// report(); +// check_canary(); +// } +// +// template +// INLINE ap_private( +// const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) { +// set_canary(); +// *this = (uint64_t)(bool)val; +// report(); +// check_canary(); +// } + + /// Simply makes *this a copy of that. + /// @brief Copy Constructor. + INLINE ap_private(const ap_private& that) { + set_canary(); + memcpy(pVal, that.get_pVal(), _AP_N * APINT_WORD_SIZE); + clearUnusedBits(); + check_canary(); + } + + template + INLINE ap_private(const ap_private<_AP_W1, _AP_S1, false>& that) { + set_canary(); + operator=(that); + check_canary(); + } + + template + INLINE ap_private(const volatile ap_private<_AP_W1, _AP_S1, false>& that) { + set_canary(); + operator=(const_cast&>(that)); + check_canary(); + } + + template + INLINE ap_private(const ap_private<_AP_W1, _AP_S1, true>& that) { + set_canary(); + static const uint64_t that_sign_ext_mask = + (_AP_W1 == APINT_BITS_PER_WORD) + ? 0 + : ~0ULL >> (_AP_W1 % APINT_BITS_PER_WORD) + << (_AP_W1 % APINT_BITS_PER_WORD); + if (that.isNegative()) { + pVal[0] = that.get_VAL() | that_sign_ext_mask; + memset(pVal + 1, ~0, sizeof(uint64_t) * (_AP_N - 1)); + } else { + pVal[0] = that.get_VAL(); + memset(pVal + 1, 0, sizeof(uint64_t) * (_AP_N - 1)); + } + clearUnusedBits(); + check_canary(); + } + + template + INLINE ap_private(const volatile ap_private<_AP_W1, _AP_S1, true>& that) { + set_canary(); + operator=(const_cast&>(that)); + check_canary(); + } + + /// @brief Destructor. + // virtual ~ap_private() {} + INLINE ~ap_private() { check_canary(); } + + /// @name Constructors + /// @{ + + /// Default constructor that creates an uninitialized ap_private. This is + /// useful + /// for object deserialization (pair this with the static method Read). + INLINE ap_private() { + set_canary(); + clearUnusedBits(); + check_canary(); + } + + INLINE ap_private(uint64_t* val, uint32_t bits = _AP_W) { assert(0); } + INLINE ap_private(const uint64_t* const val, uint32_t bits) { assert(0); } + +/// If isSigned is true then val is treated as if it were a signed value +/// (i.e. as an int64_t) and the appropriate sign extension to the bit width +/// will be done. Otherwise, no sign extension occurs (high order bits beyond +/// the range of val are zero filled). +/// @param numBits the bit width of the constructed ap_private +/// @param val the initial value of the ap_private +/// @param isSigned how to treat signedness of val +/// @brief Create a new ap_private of numBits width, initialized as val. +#define CTOR(TYPE, SIGNED) \ + INLINE ap_private(TYPE val, bool isSigned = SIGNED) { \ + set_canary(); \ + pVal[0] = (ValType)val; \ + if (isSigned && int64_t(pVal[0]) < 0) { \ + memset(pVal + 1, ~0, sizeof(uint64_t) * (_AP_N - 1)); \ + } else { \ + memset(pVal + 1, 0, sizeof(uint64_t) * (_AP_N - 1)); \ + } \ + clearUnusedBits(); \ + check_canary(); \ + } + + CTOR(bool, false) + CTOR(char, CHAR_IS_SIGNED) + CTOR(signed char, true) + CTOR(unsigned char, false) + CTOR(short, true) + CTOR(unsigned short, false) + CTOR(int, true) + CTOR(unsigned int, false) + CTOR(long, true) + CTOR(unsigned long, false) + CTOR(ap_slong, true) + CTOR(ap_ulong, false) +#if 0 + CTOR(half, false) + CTOR(float, false) + CTOR(double, false) +#endif +#undef CTOR + + /// @returns true if the number of bits <= 64, false otherwise. + /// @brief Determine if this ap_private just has one word to store value. + INLINE bool isSingleWord() const { return false; } + + /// @returns the word position for the specified bit position. + /// @brief Determine which word a bit is in. + static INLINE uint32_t whichWord(uint32_t bitPosition) { + // return bitPosition / APINT_BITS_PER_WORD; + return (bitPosition) >> 6; + } + + /// @returns the bit position in a word for the specified bit position + /// in the ap_private. + /// @brief Determine which bit in a word a bit is in. + static INLINE uint32_t whichBit(uint32_t bitPosition) { + // return bitPosition % APINT_BITS_PER_WORD; + return bitPosition & 0x3f; + } + + /// bit at a specific bit position. This is used to mask the bit in the + /// corresponding word. + /// @returns a uint64_t with only bit at "whichBit(bitPosition)" set + /// @brief Get a single bit mask. + static INLINE uint64_t maskBit(uint32_t bitPosition) { + return 1ULL << (whichBit(bitPosition)); + } + + /// @returns the corresponding word for the specified bit position. + /// @brief Get the word corresponding to a bit position + INLINE uint64_t getWord(uint32_t bitPosition) const { + return pVal[whichWord(bitPosition)]; + } + + /// This method is used internally to clear the to "N" bits in the high order + /// word that are not used by the ap_private. This is needed after the most + /// significant word is assigned a value to ensure that those bits are + /// zero'd out. + /// @brief Clear unused high order bits + INLINE void clearUnusedBits(void) volatile +// just for clang compiler +#if defined(__clang__) && !defined(__CLANG_3_1__) + __attribute__((no_sanitize("undefined"))) +#endif + { + pVal[_AP_N - 1] = + _AP_S ? ((((int64_t)pVal[_AP_N - 1]) << (excess_bits)) >> excess_bits) + : (excess_bits + ? ((pVal[_AP_N - 1]) << (excess_bits)) >> (excess_bits) + : pVal[_AP_N - 1]); + } + + INLINE void clearUnusedBitsToZero(void) { pVal[_AP_N - 1] &= mask; } + + INLINE void clearUnusedBitsToOne(void) { pVal[_AP_N - 1] |= mask; } + + /// This is used by the constructors that take string arguments. + /// @brief Convert a char array into an ap_private + INLINE void fromString(const char* str, uint32_t slen, uint8_t radix) { + enum { numbits = _AP_W }; + bool isNeg = str[0] == '-'; + if (isNeg) { + str++; + slen--; + } + + if (str[0] == '0' && (str[1] == 'b' || str[1] == 'B')) { + //if(radix == 0) radix = 2; + _AP_WARNING(radix != 2, "%s seems to have base %d, but %d given.", str, 2, radix); + str += 2; + slen -=2; + } else if (str[0] == '0' && (str[1] == 'o' || str[1] == 'O')) { + //if (radix == 0) radix = 8; + _AP_WARNING(radix != 8, "%s seems to have base %d, but %d given.", str, 8, radix); + str += 2; + slen -=2; + } else if (str[0] == '0' && (str[1] == 'x' || str[1] == 'X')) { + //if (radix == 0) radix = 16; + _AP_WARNING(radix != 16, "%s seems to have base %d, but %d given.", str, 16, radix); + str += 2; + slen -=2; + } else if (str[0] == '0' && (str[1] == 'd' || str[1] == 'D')) { + //if (radix == 0) radix = 10; + _AP_WARNING(radix != 10, "%s seems to have base %d, but %d given.", str, 10, radix); + str += 2; + slen -=2; + } else if (radix == 0) { + //radix = 2; // XXX default value + } + + // Check our assumptions here + assert((radix == 10 || radix == 8 || radix == 16 || radix == 2) && + "Radix should be 2, 8, 10, or 16!"); + assert(str && "String is null?"); + + // skip any leading zero + while (*str == '0' && *(str + 1) != '\0') { + str++; + slen--; + } + assert((slen <= numbits || radix != 2) && "Insufficient bit width"); + assert(((slen - 1) * 3 <= numbits || radix != 8) && + "Insufficient bit width"); + assert(((slen - 1) * 4 <= numbits || radix != 16) && + "Insufficient bit width"); + assert((((slen - 1) * 64) / 22 <= numbits || radix != 10) && + "Insufficient bit width"); + + // clear bits + memset(pVal, 0, _AP_N * sizeof(uint64_t)); + + // Figure out if we can shift instead of multiply + uint32_t shift = (radix == 16 ? 4 : radix == 8 ? 3 : radix == 2 ? 1 : 0); + + // Set up an ap_private for the digit to add outside the loop so we don't + // constantly construct/destruct it. + uint64_t bigVal[_AP_N]; + memset(bigVal, 0, _AP_N * sizeof(uint64_t)); + ap_private<_AP_W, _AP_S> apdigit(getBitWidth(), bigVal); + ap_private<_AP_W, _AP_S> apradix(radix); + + // Enter digit traversal loop + for (unsigned i = 0; i < slen; i++) { + // Get a digit + uint32_t digit = 0; + char cdigit = str[i]; + if (radix == 16) { +#define isxdigit(c) \ + (((c) >= '0' && (c) <= '9') || ((c) >= 'a' && (c) <= 'f') || \ + ((c) >= 'A' && (c) <= 'F')) +#define isdigit(c) ((c) >= '0' && (c) <= '9') + if (!isxdigit(cdigit)) assert(0 && "Invalid hex digit in string"); + if (isdigit(cdigit)) + digit = cdigit - '0'; + else if (cdigit >= 'a') + digit = cdigit - 'a' + 10; + else if (cdigit >= 'A') + digit = cdigit - 'A' + 10; + else + assert(0 && "huh? we shouldn't get here"); + } else if (isdigit(cdigit)) { + digit = cdigit - '0'; + } else if (cdigit != '\0') { + assert(0 && "Invalid character in digit string"); + } +#undef isxdigit +#undef isdigit + // Shift or multiply the value by the radix + if (shift) + *this <<= shift; + else + *this *= apradix; + + // Add in the digit we just interpreted + apdigit.set_VAL(digit); + *this += apdigit; + } + // If its negative, put it in two's complement form + if (isNeg) { + (*this)--; + this->flip(); + } + clearUnusedBits(); + } + + INLINE ap_private read() volatile { return *this; } + + INLINE void write(const ap_private& op2) volatile { *this = (op2); } + + INLINE operator ValType() const { return get_VAL(); } + + INLINE int to_uchar() const { return (unsigned char)get_VAL(); } + + INLINE int to_char() const { return (signed char)get_VAL(); } + + INLINE int to_ushort() const { return (unsigned short)get_VAL(); } + + INLINE int to_short() const { return (short)get_VAL(); } + + INLINE int to_int() const { return (int)get_VAL(); } + + INLINE unsigned to_uint() const { return (unsigned)get_VAL(); } + + INLINE long to_long() const { return (long)get_VAL(); } + + INLINE unsigned long to_ulong() const { return (unsigned long)get_VAL(); } + + INLINE ap_slong to_int64() const { return (ap_slong)get_VAL(); } + + INLINE ap_ulong to_uint64() const { return (ap_ulong)get_VAL(); } + + INLINE double to_double() const { + if (isNegative()) + return roundToDouble(true); + else + return roundToDouble(false); + } + + INLINE unsigned length() const { return _AP_W; } + + /*Reverse the contents of ap_private instance. I.e. LSB becomes MSB and vise + * versa*/ + INLINE ap_private& reverse() { + for (int i = 0; i < _AP_W / 2; ++i) { + bool tmp = operator[](i); + if (operator[](_AP_W - 1 - i)) + set(i); + else + clear(i); + if (tmp) + set(_AP_W - 1 - i); + else + clear(_AP_W - 1 - i); + } + clearUnusedBits(); + return *this; + } + + /*Return true if the value of ap_private instance is zero*/ + INLINE bool iszero() const { return isMinValue(); } + + INLINE bool to_bool() const { return !iszero(); } + + /* x < 0 */ + INLINE bool sign() const { + if (isNegative()) return true; + return false; + } + + /* x[i] = !x[i] */ + INLINE void invert(int i) { + assert(i >= 0 && "Attempting to read bit with negative index"); + assert(i < _AP_W && "Attempting to read bit beyond MSB"); + flip(i); + } + + /* x[i] */ + INLINE bool test(int i) const { + assert(i >= 0 && "Attempting to read bit with negative index"); + assert(i < _AP_W && "Attempting to read bit beyond MSB"); + return operator[](i); + } + + // Set the ith bit into v + INLINE void set(int i, bool v) { + assert(i >= 0 && "Attempting to write bit with negative index"); + assert(i < _AP_W && "Attempting to write bit beyond MSB"); + v ? set(i) : clear(i); + } + + // Set the ith bit into v + INLINE void set_bit(int i, bool v) { + assert(i >= 0 && "Attempting to write bit with negative index"); + assert(i < _AP_W && "Attempting to write bit beyond MSB"); + v ? set(i) : clear(i); + } + + // FIXME different argument for different action? + INLINE ap_private& set(uint32_t bitPosition) { + pVal[whichWord(bitPosition)] |= maskBit(bitPosition); + clearUnusedBits(); + return *this; + } + + INLINE void set() { + for (int i = 0; i < _AP_N; ++i) pVal[i] = ~0ULL; + clearUnusedBits(); + } + + // Get the value of ith bit + INLINE bool get(int i) const { + assert(i >= 0 && "Attempting to read bit with negative index"); + assert(i < _AP_W && "Attempting to read bit beyond MSB"); + return ((maskBit(i) & (pVal[whichWord(i)])) != 0); + } + + // Get the value of ith bit + INLINE bool get_bit(int i) const { + assert(i >= 0 && "Attempting to read bit with negative index"); + assert(i < _AP_W && "Attempting to read bit beyond MSB"); + return ((maskBit(i) & (pVal[whichWord(i)])) != 0); + } + + // This is used for sc_lv and sc_bv, which is implemented by sc_uint + // Rotate an ap_private object n places to the left + INLINE void lrotate(int n) { + assert(n >= 0 && "Attempting to shift negative index"); + assert(n < _AP_W && "Shift value larger than bit width"); + operator=(shl(n) | lshr(_AP_W - n)); + } + + // This is used for sc_lv and sc_bv, which is implemented by sc_uint + // Rotate an ap_private object n places to the right + INLINE void rrotate(int n) { + assert(n >= 0 && "Attempting to shift negative index"); + assert(n < _AP_W && "Shift value larger than bit width"); + operator=(lshr(n) | shl(_AP_W - n)); + } + + /// Set the given bit to 0 whose position is given as "bitPosition". + /// @brief Set a given bit to 0. + INLINE ap_private& clear(uint32_t bitPosition) { + pVal[whichWord(bitPosition)] &= ~maskBit(bitPosition); + clearUnusedBits(); + return *this; + } + + /// @brief Set every bit to 0. + INLINE void clear() { memset(pVal, 0, _AP_N * APINT_WORD_SIZE); } + + /// @brief Toggle every bit to its opposite value. + ap_private& flip() { + for (int i = 0; i < _AP_N; ++i) pVal[i] ^= ~0ULL; + clearUnusedBits(); + return *this; + } + + /// @brief Toggles a given bit to its opposite value. + INLINE ap_private& flip(uint32_t bitPosition) { + assert(bitPosition < BitWidth && "Out of the bit-width range!"); + set_bit(bitPosition, !get_bit(bitPosition)); + return *this; + } + + // complements every bit + INLINE void b_not() { flip(); } + + INLINE ap_private getLoBits(uint32_t numBits) const { + return ap_private_ops::lshr(ap_private_ops::shl(*this, _AP_W - numBits), + _AP_W - numBits); + } + + INLINE ap_private getHiBits(uint32_t numBits) const { + return ap_private_ops::lshr(*this, _AP_W - numBits); + } + + // Binary Arithmetic + //----------------------------------------------------------- + +// template +// INLINE ap_private operator&( +// const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& a2) { +// return *this & a2.get(); +// } +// +// template +// INLINE ap_private operator|( +// const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& a2) { +// return *this | a2.get(); +// } +// +// template +// INLINE ap_private operator^( +// const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& a2) { +// return *this ^ a2.get(); +// } + +/// Arithmetic assign +//------------------------------------------------------------- + +#define OP_BIN_LOGIC_ASSIGN_AP(Sym) \ + template \ + INLINE ap_private& operator Sym(const ap_private<_AP_W1, _AP_S1>& RHS) { \ + const int _AP_N1 = ap_private<_AP_W1, _AP_S1>::_AP_N; \ + uint32_t numWords = AESL_std::min((int)_AP_N, _AP_N1); \ + uint32_t i; \ + if (_AP_W != _AP_W1) \ + fprintf(stderr, \ + "Warning! Bitsize mismach for ap_[u]int " #Sym " ap_[u]int.\n"); \ + for (i = 0; i < numWords; ++i) pVal[i] Sym RHS.get_pVal(i); \ + if (_AP_N1 < _AP_N) { \ + uint64_t ext = RHS.isNegative() ? ~0ULL : 0; \ + for (; i < _AP_N; i++) pVal[i] Sym ext; \ + } \ + clearUnusedBits(); \ + return *this; \ + } + + OP_BIN_LOGIC_ASSIGN_AP(&=); + OP_BIN_LOGIC_ASSIGN_AP(|=); + OP_BIN_LOGIC_ASSIGN_AP(^=); +#undef OP_BIN_LOGIC_ASSIGN_AP + + /// Adds the RHS APint to this ap_private. + /// @returns this, after addition of RHS. + /// @brief Addition assignment operator. + template + INLINE ap_private& operator+=(const ap_private<_AP_W1, _AP_S1>& RHS) { + const int _AP_N1 = ap_private<_AP_W1, _AP_S1>::_AP_N; + uint64_t RHSpVal[_AP_N1]; + for (int i = 0; i < _AP_N1; ++i) RHSpVal[i] = RHS.get_pVal(i); + ap_private_ops::add(pVal, pVal, RHSpVal, _AP_N, _AP_N, _AP_N1, _AP_S, + _AP_S1); + clearUnusedBits(); + return *this; + } + + template + INLINE ap_private& operator-=(const ap_private<_AP_W1, _AP_S1>& RHS) { + const int _AP_N1 = ap_private<_AP_W1, _AP_S1>::_AP_N; + uint64_t RHSpVal[_AP_N1]; + for (int i = 0; i < _AP_N1; ++i) RHSpVal[i] = RHS.get_pVal(i); + ap_private_ops::sub(pVal, pVal, RHSpVal, _AP_N, _AP_N, _AP_N1, _AP_S, + _AP_S1); + clearUnusedBits(); + return *this; + } + + template + INLINE ap_private& operator*=(const ap_private<_AP_W1, _AP_S1>& RHS) { + // Get some bit facts about LHS and check for zero + uint32_t lhsBits = getActiveBits(); + uint32_t lhsWords = !lhsBits ? 0 : whichWord(lhsBits - 1) + 1; + if (!lhsWords) { + // 0 * X ===> 0 + return *this; + } + + ap_private dupRHS = RHS; + // Get some bit facts about RHS and check for zero + uint32_t rhsBits = dupRHS.getActiveBits(); + uint32_t rhsWords = !rhsBits ? 0 : whichWord(rhsBits - 1) + 1; + if (!rhsWords) { + // X * 0 ===> 0 + clear(); + return *this; + } + + // Allocate space for the result + uint32_t destWords = rhsWords + lhsWords; + uint64_t* dest = (uint64_t*)malloc(destWords * sizeof(uint64_t)); + + // Perform the long multiply + ap_private_ops::mul(dest, pVal, lhsWords, dupRHS.get_pVal(), rhsWords, + destWords); + + // Copy result back into *this + clear(); + uint32_t wordsToCopy = destWords >= _AP_N ? _AP_N : destWords; + + memcpy(pVal, dest, wordsToCopy * APINT_WORD_SIZE); + + uint64_t ext = (isNegative() ^ RHS.isNegative()) ? ~0ULL : 0ULL; + for (int i = wordsToCopy; i < _AP_N; i++) pVal[i] = ext; + clearUnusedBits(); + // delete dest array and return + free(dest); + return *this; + } + +#define OP_ASSIGN_AP(Sym) \ + template \ + INLINE ap_private& operator Sym##=(const ap_private<_AP_W2, _AP_S2>& op) { \ + *this = operator Sym(op); \ + return *this; \ + } + + OP_ASSIGN_AP(/) + OP_ASSIGN_AP(%) +#undef OP_ASSIGN_AP + +#define OP_BIN_LOGIC_AP(Sym) \ + template \ + INLINE typename RType<_AP_W1, _AP_S1>::logic operator Sym( \ + const ap_private<_AP_W1, _AP_S1>& RHS) const { \ + enum { \ + numWords = (RType<_AP_W1, _AP_S1>::logic_w + APINT_BITS_PER_WORD - 1) / \ + APINT_BITS_PER_WORD \ + }; \ + typename RType<_AP_W1, _AP_S1>::logic Result; \ + uint32_t i; \ + const int _AP_N1 = ap_private<_AP_W1, _AP_S1>::_AP_N; \ + uint32_t min_N = std::min((int)_AP_N, _AP_N1); \ + uint32_t max_N = std::max((int)_AP_N, _AP_N1); \ + for (i = 0; i < min_N; ++i) \ + Result.set_pVal(i, pVal[i] Sym RHS.get_pVal(i)); \ + if (numWords > i) { \ + uint64_t ext = ((_AP_N < _AP_N1 && isNegative()) || \ + (_AP_N1 < _AP_N && RHS.isNegative())) \ + ? ~0ULL \ + : 0; \ + if (_AP_N > _AP_N1) \ + for (; i < max_N; i++) Result.set_pVal(i, pVal[i] Sym ext); \ + else \ + for (; i < max_N; i++) Result.set_pVal(i, RHS.get_pVal(i) Sym ext); \ + if (numWords > i) { \ + uint64_t ext2 = ((_AP_N > _AP_N1 && isNegative()) || \ + (_AP_N1 > _AP_N && RHS.isNegative())) \ + ? ~0ULL \ + : 0; \ + Result.set_pVal(i, ext Sym ext2); \ + } \ + } \ + Result.clearUnusedBits(); \ + return Result; \ + } + + OP_BIN_LOGIC_AP(|); + OP_BIN_LOGIC_AP(&); + OP_BIN_LOGIC_AP(^); + +#undef OP_BIN_LOGIC_AP + + template + INLINE typename RType<_AP_W1, _AP_S1>::plus operator+( + const ap_private<_AP_W1, _AP_S1>& RHS) const { + typename RType<_AP_W1, _AP_S1>::plus Result, lhs(*this), rhs(RHS); + const int Result_AP_N = (RType<_AP_W1, _AP_S1>::plus_w + 63) / 64; + ap_private_ops::add(Result.get_pVal(), lhs.get_pVal(), rhs.get_pVal(), + Result_AP_N, Result_AP_N, Result_AP_N, _AP_S, _AP_S1); + Result.clearUnusedBits(); + return Result; + } + + template + INLINE typename RType<_AP_W1, _AP_S1>::minus operator-( + const ap_private<_AP_W1, _AP_S1>& RHS) const { + typename RType<_AP_W1, _AP_S1>::minus Result, lhs(*this), rhs(RHS); + const int Result_AP_N = (RType<_AP_W1, _AP_S1>::minus_w + 63) / 64; + ap_private_ops::sub(Result.get_pVal(), lhs.get_pVal(), rhs.get_pVal(), + Result_AP_N, Result_AP_N, Result_AP_N, _AP_S, _AP_S1); + Result.clearUnusedBits(); + return Result; + } + + template + INLINE typename RType<_AP_W1, _AP_S1>::mult operator*( + const ap_private<_AP_W1, _AP_S1>& RHS) const { + typename RType<_AP_W1, _AP_S1>::mult temp = *this; + temp *= RHS; + return temp; + } + + template + INLINE typename RType<_AP_W2, _AP_S2>::div operator/( + const ap_private<_AP_W2, _AP_S2>& op) const { + ap_private _AP_W2 ? _AP_S + : (_AP_W2 > _AP_W ? _AP_S2 : _AP_S || _AP_S2))> + lhs = *this; + ap_private _AP_W2 ? _AP_S + : (_AP_W2 > _AP_W ? _AP_S2 : _AP_S || _AP_S2))> + rhs = op; + return typename RType<_AP_W2, _AP_S2>::div( + (_AP_S || _AP_S2) ? lhs.sdiv(rhs) : lhs.udiv(rhs)); + } + + template + INLINE typename RType<_AP_W2, _AP_S2>::mod operator%( + const ap_private<_AP_W2, _AP_S2>& op) const { + ap_private _AP_W2 ? _AP_S + : (_AP_W2 > _AP_W ? _AP_S2 : _AP_S || _AP_S2))> + lhs = *this; + ap_private _AP_W2 ? _AP_S + : (_AP_W2 > _AP_W ? _AP_S2 : _AP_S || _AP_S2))> + rhs = op; + typename RType<_AP_W2, _AP_S2>::mod res = + typename RType<_AP_W2, _AP_S2>::mod(_AP_S ? lhs.srem(rhs) + : lhs.urem(rhs)); + return res; + } + +#define OP_LEFT_SHIFT_CTYPE(TYPE, SIGNED) \ + INLINE ap_private operator<<(const TYPE op) const { \ + if (op >= _AP_W) return ap_private(0); \ + if (SIGNED && op < 0) return *this >> (0 - op); \ + return shl(op); \ + } + + OP_LEFT_SHIFT_CTYPE(int, true) + // OP_LEFT_SHIFT_CTYPE(bool, false) + OP_LEFT_SHIFT_CTYPE(signed char, true) + OP_LEFT_SHIFT_CTYPE(unsigned char, false) + OP_LEFT_SHIFT_CTYPE(short, true) + OP_LEFT_SHIFT_CTYPE(unsigned short, false) + OP_LEFT_SHIFT_CTYPE(unsigned int, false) + OP_LEFT_SHIFT_CTYPE(long, true) + OP_LEFT_SHIFT_CTYPE(unsigned long, false) + OP_LEFT_SHIFT_CTYPE(unsigned long long, false) + OP_LEFT_SHIFT_CTYPE(long long, true) +#if 0 + OP_LEFT_SHIFT_CTYPE(half, false) + OP_LEFT_SHIFT_CTYPE(float, false) + OP_LEFT_SHIFT_CTYPE(double, false) +#endif +#undef OP_LEFT_SHIFT_CTYPE + + template + INLINE ap_private operator<<(const ap_private<_AP_W2, _AP_S2>& op2) const { + if (_AP_S2 == false) { + uint32_t sh = op2.to_uint(); + return *this << sh; + } else { + int sh = op2.to_int(); + return *this << sh; + } + } + +#define OP_RIGHT_SHIFT_CTYPE(TYPE, SIGNED) \ + INLINE ap_private operator>>(const TYPE op) const { \ + if (op >= _AP_W) { \ + if (isNegative()) \ + return ap_private(-1); \ + else \ + return ap_private(0); \ + } \ + if ((SIGNED) && op < 0) return *this << (0 - op); \ + if (_AP_S) \ + return ashr(op); \ + else \ + return lshr(op); \ + } + + // OP_RIGHT_SHIFT_CTYPE(bool, false) + OP_RIGHT_SHIFT_CTYPE(char, CHAR_IS_SIGNED) + OP_RIGHT_SHIFT_CTYPE(signed char, true) + OP_RIGHT_SHIFT_CTYPE(unsigned char, false) + OP_RIGHT_SHIFT_CTYPE(short, true) + OP_RIGHT_SHIFT_CTYPE(unsigned short, false) + OP_RIGHT_SHIFT_CTYPE(int, true) + OP_RIGHT_SHIFT_CTYPE(unsigned int, false) + OP_RIGHT_SHIFT_CTYPE(long, true) + OP_RIGHT_SHIFT_CTYPE(unsigned long, false) + OP_RIGHT_SHIFT_CTYPE(unsigned long long, false) + OP_RIGHT_SHIFT_CTYPE(long long, true) +#if 0 + OP_RIGHT_SHIFT_CTYPE(half, false) + OP_RIGHT_SHIFT_CTYPE(float, false) + OP_RIGHT_SHIFT_CTYPE(double, false) +#endif +#undef OP_RIGHT_SHIFT_CTYPE + + template + INLINE ap_private operator>>(const ap_private<_AP_W2, _AP_S2>& op2) const { + if (_AP_S2 == false) { + uint32_t sh = op2.to_uint(); + return *this >> sh; + } else { + int sh = op2.to_int(); + return *this >> sh; + } + } + + /// Shift assign + //------------------------------------------------------------------ + // TODO call clearUnusedBits ? +#define OP_ASSIGN_AP(Sym) \ + template \ + INLINE ap_private& operator Sym##=(int op) { \ + *this = operator Sym(op); \ + return *this; \ + } \ + INLINE ap_private& operator Sym##=(unsigned int op) { \ + *this = operator Sym(op); \ + return *this; \ + } \ + template \ + INLINE ap_private& operator Sym##=(const ap_private<_AP_W2, _AP_S2>& op) { \ + *this = operator Sym(op); \ + return *this; \ + } + OP_ASSIGN_AP(>>) + OP_ASSIGN_AP(<<) +#undef OP_ASSIGN_AP + + /// Comparisons + //----------------------------------------------------------------- + INLINE bool operator==(const ap_private& RHS) const { + // Get some facts about the number of bits used in the two operands. + uint32_t n1 = getActiveBits(); + uint32_t n2 = RHS.getActiveBits(); + + // If the number of bits isn't the same, they aren't equal + if (n1 != n2) return false; + + // If the number of bits fits in a word, we only need to compare the low + // word. + if (n1 <= APINT_BITS_PER_WORD) return pVal[0] == RHS.get_pVal(0); + + // Otherwise, compare everything + for (int i = whichWord(n1 - 1); i >= 0; --i) + if (pVal[i] != RHS.get_pVal(i)) return false; + return true; + } + + template + INLINE bool operator==(const ap_private<_AP_W2, _AP_S2>& op) const { + enum { + _AP_MAX_W = AP_MAX(_AP_W, _AP_W2), + }; + ap_private<_AP_MAX_W, false> lhs(*this); + ap_private<_AP_MAX_W, false> rhs(op); + return lhs == rhs; + } + + INLINE bool operator==(uint64_t Val) const { + uint32_t n = getActiveBits(); + if (n <= APINT_BITS_PER_WORD) + return pVal[0] == Val; + else + return false; + } + + template + INLINE bool operator!=(const ap_private<_AP_W2, _AP_S2>& op) const { + return !(*this == op); + } + + template + INLINE bool operator!=(const ap_private<_AP_W, _AP_S1>& RHS) const { + return !((*this) == RHS); + } + + INLINE bool operator!=(uint64_t Val) const { return !((*this) == Val); } + + template + INLINE bool operator<=(const ap_private<_AP_W2, _AP_S2>& op) const { + return !(*this > op); + } + + INLINE bool operator<(const ap_private& op) const { + return _AP_S ? slt(op) : ult(op); + } + + template + INLINE bool operator<(const ap_private<_AP_W2, _AP_S2>& op) const { + enum { + _AP_MAX_W = AP_MAX(_AP_W + (_AP_S || _AP_S2), _AP_W2 + (_AP_S || _AP_S2)) + }; + ap_private<_AP_MAX_W, _AP_S> lhs(*this); + ap_private<_AP_MAX_W, _AP_S2> rhs(op); + if (_AP_S == _AP_S2) + return _AP_S ? lhs.slt(rhs) : lhs.ult(rhs); + else if (_AP_S) + if (_AP_W2 >= _AP_W) + return lhs.ult(rhs); + else + return lhs.slt(rhs); + else if (_AP_W >= _AP_W2) + return lhs.ult(rhs); + else + return lhs.slt(rhs); + } + + template + INLINE bool operator>=(const ap_private<_AP_W2, _AP_S2>& op) const { + return !(*this < op); + } + + INLINE bool operator>(const ap_private& op) const { + return _AP_S ? sgt(op) : ugt(op); + } + + template + INLINE bool operator>(const ap_private<_AP_W2, _AP_S2>& op) const { + enum { + _AP_MAX_W = AP_MAX(_AP_W + (_AP_S || _AP_S2), _AP_W2 + (_AP_S || _AP_S2)) + }; + ap_private<_AP_MAX_W, _AP_S> lhs(*this); + ap_private<_AP_MAX_W, _AP_S2> rhs(op); + if (_AP_S == _AP_S2) + return _AP_S ? lhs.sgt(rhs) : lhs.ugt(rhs); + else if (_AP_S) + if (_AP_W2 >= _AP_W) + return lhs.ugt(rhs); + else + return lhs.sgt(rhs); + else if (_AP_W >= _AP_W2) + return lhs.ugt(rhs); + else + return lhs.sgt(rhs); + } + + /// Bit and Part Select + //-------------------------------------------------------------- + INLINE _private_range_ref<_AP_W, _AP_S> operator()(int Hi, int Lo) { + return _private_range_ref<_AP_W, _AP_S>(this, Hi, Lo); + } + + INLINE _private_range_ref<_AP_W, _AP_S> operator()(int Hi, int Lo) const { + return _private_range_ref<_AP_W, _AP_S>( + const_cast*>(this), Hi, Lo); + } + + INLINE _private_range_ref<_AP_W, _AP_S> range(int Hi, int Lo) const { + return _private_range_ref<_AP_W, _AP_S>( + (const_cast*>(this)), Hi, Lo); + } + + INLINE _private_range_ref<_AP_W, _AP_S> range(int Hi, int Lo) { + return _private_range_ref<_AP_W, _AP_S>(this, Hi, Lo); + } + + template + INLINE _private_range_ref<_AP_W, _AP_S> range( + const ap_private<_AP_W2, _AP_S2>& HiIdx, + const ap_private<_AP_W3, _AP_S3>& LoIdx) { + int Hi = HiIdx.to_int(); + int Lo = LoIdx.to_int(); + return _private_range_ref<_AP_W, _AP_S>(this, Hi, Lo); + } + + template + INLINE _private_range_ref<_AP_W, _AP_S> operator()( + const ap_private<_AP_W2, _AP_S2>& HiIdx, + const ap_private<_AP_W3, _AP_S3>& LoIdx) { + int Hi = HiIdx.to_int(); + int Lo = LoIdx.to_int(); + return _private_range_ref<_AP_W, _AP_S>(this, Hi, Lo); + } + + template + INLINE _private_range_ref<_AP_W, _AP_S> range( + const ap_private<_AP_W2, _AP_S2>& HiIdx, + const ap_private<_AP_W3, _AP_S3>& LoIdx) const { + int Hi = HiIdx.to_int(); + int Lo = LoIdx.to_int(); + return _private_range_ref<_AP_W, _AP_S>(const_cast(this), Hi, Lo); + } + + template + INLINE _private_range_ref<_AP_W, _AP_S> operator()( + const ap_private<_AP_W2, _AP_S2>& HiIdx, + const ap_private<_AP_W3, _AP_S3>& LoIdx) const { + int Hi = HiIdx.to_int(); + int Lo = LoIdx.to_int(); + return this->range(Hi, Lo); + } + + INLINE _private_bit_ref<_AP_W, _AP_S> operator[](int index) { + return _private_bit_ref<_AP_W, _AP_S>(*this, index); + } + + template + INLINE _private_bit_ref<_AP_W, _AP_S> operator[]( + const ap_private<_AP_W2, _AP_S2>& index) { + return _private_bit_ref<_AP_W, _AP_S>(*this, index.to_int()); + } + + template + INLINE const _private_bit_ref<_AP_W, _AP_S> operator[]( + const ap_private<_AP_W2, _AP_S2>& index) const { + return _private_bit_ref<_AP_W, _AP_S>( + const_cast&>(*this), index.to_int()); + } + + INLINE const _private_bit_ref<_AP_W, _AP_S> operator[](int index) const { + return _private_bit_ref<_AP_W, _AP_S>( + const_cast&>(*this), index); + } + + INLINE _private_bit_ref<_AP_W, _AP_S> bit(int index) { + return _private_bit_ref<_AP_W, _AP_S>(*this, index); + } + + template + INLINE _private_bit_ref<_AP_W, _AP_S> bit(const ap_private<_AP_W2, _AP_S2>& index) { + return _private_bit_ref<_AP_W, _AP_S>(*this, index.to_int()); + } + + INLINE const _private_bit_ref<_AP_W, _AP_S> bit(int index) const { + return _private_bit_ref<_AP_W, _AP_S>( + const_cast&>(*this), index); + } + + template + INLINE const _private_bit_ref<_AP_W, _AP_S> bit( + const ap_private<_AP_W2, _AP_S2>& index) const { + return _private_bit_ref<_AP_W, _AP_S>( + const_cast&>(*this), index.to_int()); + } + +// template +// INLINE ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2, +// ap_private<_AP_W2, _AP_S2> > +// concat(ap_private<_AP_W2, _AP_S2>& a2) { +// return ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2, +// ap_private<_AP_W2, _AP_S2> >(*this, a2); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2, +// ap_private<_AP_W2, _AP_S2> > +// concat(const ap_private<_AP_W2, _AP_S2>& a2) const { +// return ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2, +// ap_private<_AP_W2, _AP_S2> >( +// const_cast&>(*this), +// const_cast&>(a2)); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, ap_private, _AP_W2, ap_private<_AP_W2, _AP_S2> > +// operator,(ap_private<_AP_W2, _AP_S2> &a2) { +// return ap_concat_ref<_AP_W, ap_private, _AP_W2, +// ap_private<_AP_W2, _AP_S2> >(*this, a2); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, ap_private, _AP_W2, ap_private<_AP_W2, _AP_S2> > +// operator,(ap_private<_AP_W2, _AP_S2> &a2) const { +// return ap_concat_ref<_AP_W, ap_private, _AP_W2, +// ap_private<_AP_W2, _AP_S2> >( +// const_cast&>(*this), a2); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, ap_private, _AP_W2, ap_private<_AP_W2, _AP_S2> > +// operator,(const ap_private<_AP_W2, _AP_S2> &a2) { +// return ap_concat_ref<_AP_W, ap_private, _AP_W2, +// ap_private<_AP_W2, _AP_S2> >( +// *this, const_cast&>(a2)); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, ap_private, _AP_W2, ap_private<_AP_W2, _AP_S2> > +// operator,(const ap_private<_AP_W2, _AP_S2> &a2) const { +// return ap_concat_ref<_AP_W, ap_private, _AP_W2, +// ap_private<_AP_W2, _AP_S2> >( +// const_cast&>(*this), +// const_cast&>(a2)); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2, +// _private_range_ref<_AP_W2, _AP_S2> > +// operator,(const _private_range_ref<_AP_W2, _AP_S2> &a2) const { +// return ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2, +// _private_range_ref<_AP_W2, _AP_S2> >( +// const_cast&>(*this), +// const_cast<_private_range_ref<_AP_W2, _AP_S2>&>(a2)); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2, +// _private_range_ref<_AP_W2, _AP_S2> > +// operator,(_private_range_ref<_AP_W2, _AP_S2> &a2) { +// return ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2, +// _private_range_ref<_AP_W2, _AP_S2> >(*this, a2); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, 1, +// _private_bit_ref<_AP_W2, _AP_S2> > +// operator,(const _private_bit_ref<_AP_W2, _AP_S2> &a2) const { +// return ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, 1, +// _private_bit_ref<_AP_W2, _AP_S2> >( +// const_cast&>(*this), +// const_cast<_private_bit_ref<_AP_W2, _AP_S2>&>(a2)); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, 1, +// _private_bit_ref<_AP_W2, _AP_S2> > +// operator,(_private_bit_ref<_AP_W2, _AP_S2> &a2) { +// return ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, 1, +// _private_bit_ref<_AP_W2, _AP_S2> >(*this, a2); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2 + _AP_W3, +// ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> > +// operator,(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &a2) const { +// return ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2 + _AP_W3, +// ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >( +// const_cast&>(*this), +// const_cast&>(a2)); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2 + _AP_W3, +// ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> > +// operator,(ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &a2) { +// return ap_concat_ref<_AP_W, ap_private<_AP_W, _AP_S>, _AP_W2 + _AP_W3, +// ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >(*this, +// a2); +// } +// +// template +// INLINE ap_concat_ref< +// _AP_W, ap_private, _AP_W2, +// af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> > +// operator,(const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> +// &a2) const { +// return ap_concat_ref< +// _AP_W, ap_private, _AP_W2, +// af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >( +// const_cast&>(*this), +// const_cast< +// af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>&>(a2)); +// } +// +// template +// INLINE ap_concat_ref< +// _AP_W, ap_private, _AP_W2, +// af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> > +// operator,(af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> &a2) { +// return ap_concat_ref< +// _AP_W, ap_private, _AP_W2, +// af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this, +// a2); +// } +// +// template +// INLINE +// ap_concat_ref<_AP_W, ap_private, 1, +// af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> > +// operator,(const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> +// &a2) const { +// return ap_concat_ref< +// _AP_W, ap_private, 1, +// af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >( +// const_cast&>(*this), +// const_cast&>( +// a2)); +// } +// +// template +// INLINE +// ap_concat_ref<_AP_W, ap_private, 1, +// af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> > +// operator,( +// af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> &a2) { +// return ap_concat_ref< +// _AP_W, ap_private, 1, +// af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this, a2); +// } + + INLINE ap_private<_AP_W, false> get() const { + ap_private<_AP_W, false> ret(*this); + return ret; + } + + template + INLINE void set(const ap_private<_AP_W3, false>& val) { + operator=(ap_private<_AP_W3, _AP_S>(val)); + } + + /// + /// @name Value Tests + /// + /// This tests the high bit of this ap_private to determine if it is set. + /// @returns true if this ap_private is negative, false otherwise + /// @brief Determine sign of this ap_private. + INLINE bool isNegative() const { + // just for get rid of warnings + enum { shift = (_AP_W - APINT_BITS_PER_WORD * (_AP_N - 1) - 1) }; + static const uint64_t mask = 1ULL << (shift); + return _AP_S && (pVal[_AP_N - 1] & mask); + } + + /// This tests the high bit of the ap_private to determine if it is unset. + /// @brief Determine if this ap_private Value is positive (not negative). + INLINE bool isPositive() const { return !isNegative(); } + + /// This tests if the value of this ap_private is strictly positive (> 0). + /// @returns true if this ap_private is Positive and not zero. + /// @brief Determine if this ap_private Value is strictly positive. + INLINE bool isStrictlyPositive() const { + return isPositive() && (*this) != 0; + } + + /// This checks to see if the value has all bits of the ap_private are set or + /// not. + /// @brief Determine if all bits are set + INLINE bool isAllOnesValue() const { return countPopulation() == _AP_W; } + + /// This checks to see if the value of this ap_private is the maximum unsigned + /// value for the ap_private's bit width. + /// @brief Determine if this is the largest unsigned value. + INLINE bool isMaxValue() const { return countPopulation() == _AP_W; } + + /// This checks to see if the value of this ap_private is the maximum signed + /// value for the ap_private's bit width. + /// @brief Determine if this is the largest signed value. + INLINE bool isMaxSignedValue() const { + return !isNegative() && countPopulation() == _AP_W - 1; + } + + /// This checks to see if the value of this ap_private is the minimum unsigned + /// value for the ap_private's bit width. + /// @brief Determine if this is the smallest unsigned value. + INLINE bool isMinValue() const { return countPopulation() == 0; } + + /// This checks to see if the value of this ap_private is the minimum signed + /// value for the ap_private's bit width. + /// @brief Determine if this is the smallest signed value. + INLINE bool isMinSignedValue() const { + return isNegative() && countPopulation() == 1; + } + + /// This function returns a pointer to the internal storage of the ap_private. + /// This is useful for writing out the ap_private in binary form without any + /// conversions. + INLINE const uint64_t* getRawData() const { return &pVal[0]; } + + // Square Root - this method computes and returns the square root of "this". + // Three mechanisms are used for computation. For small values (<= 5 bits), + // a table lookup is done. This gets some performance for common cases. For + // values using less than 52 bits, the value is converted to double and then + // the libc sqrt function is called. The result is rounded and then converted + // back to a uint64_t which is then used to construct the result. Finally, + // the Babylonian method for computing square roots is used. + INLINE ap_private sqrt() const { + // Determine the magnitude of the value. + uint32_t magnitude = getActiveBits(); + + // Use a fast table for some small values. This also gets rid of some + // rounding errors in libc sqrt for small values. + if (magnitude <= 5) { + static const uint8_t results[32] = { + /* 0 */ 0, + /* 1- 2 */ 1, 1, + /* 3- 6 */ 2, 2, 2, 2, + /* 7-12 */ 3, 3, 3, 3, 3, 3, + /* 13-20 */ 4, 4, 4, 4, 4, 4, 4, 4, + /* 21-30 */ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, + /* 31 */ 6}; + return ap_private<_AP_W, _AP_S>(/*BitWidth,*/ results[get_VAL()]); + } + + // If the magnitude of the value fits in less than 52 bits (the precision of + // an IEEE double precision floating point value), then we can use the + // libc sqrt function which will probably use a hardware sqrt computation. + // This should be faster than the algorithm below. + if (magnitude < 52) { +#ifdef _MSC_VER + // Amazingly, VC++ doesn't have round(). + return ap_private<_AP_W, _AP_S>(/*BitWidth,*/ + uint64_t(::sqrt(double(get_VAL()))) + + 0.5); +#else + return ap_private<_AP_W, _AP_S>(/*BitWidth,*/ + uint64_t( + ::round(::sqrt(double(get_VAL()))))); +#endif + } + + // Okay, all the short cuts are exhausted. We must compute it. The following + // is a classical Babylonian method for computing the square root. This code + // was adapted to APINt from a wikipedia article on such computations. + // See http://www.wikipedia.org/ and go to the page named + // Calculate_an_integer_square_root. + uint32_t nbits = BitWidth, i = 4; + ap_private<_AP_W, _AP_S> testy(16); + ap_private<_AP_W, _AP_S> x_old(/*BitWidth,*/ 1); + ap_private<_AP_W, _AP_S> x_new(0); + ap_private<_AP_W, _AP_S> two(/*BitWidth,*/ 2); + + // Select a good starting value using binary logarithms. + for (;; i += 2, testy = testy.shl(2)) + if (i >= nbits || this->ule(testy)) { + x_old = x_old.shl(i / 2); + break; + } + + // Use the Babylonian method to arrive at the integer square root: + for (;;) { + x_new = (this->udiv(x_old) + x_old).udiv(two); + if (x_old.ule(x_new)) break; + x_old = x_new; + } + + // Make sure we return the closest approximation + // NOTE: The rounding calculation below is correct. It will produce an + // off-by-one discrepancy with results from pari/gp. That discrepancy has + // been + // determined to be a rounding issue with pari/gp as it begins to use a + // floating point representation after 192 bits. There are no discrepancies + // between this algorithm and pari/gp for bit widths < 192 bits. + ap_private<_AP_W, _AP_S> square(x_old * x_old); + ap_private<_AP_W, _AP_S> nextSquare((x_old + 1) * (x_old + 1)); + if (this->ult(square)) + return x_old; + else if (this->ule(nextSquare)) { + ap_private<_AP_W, _AP_S> midpoint((nextSquare - square).udiv(two)); + ap_private<_AP_W, _AP_S> offset(*this - square); + if (offset.ult(midpoint)) + return x_old; + else + return x_old + 1; + } else + assert(0 && "Error in ap_private<_AP_W, _AP_S>::sqrt computation"); + return x_old + 1; + } + + /// + /// @Assignment Operators + /// + /// @returns *this after assignment of RHS. + /// @brief Copy assignment operator. + INLINE ap_private& operator=(const ap_private& RHS) { + if (this != &RHS) memcpy(pVal, RHS.get_pVal(), _AP_N * APINT_WORD_SIZE); + clearUnusedBits(); + return *this; + } + INLINE ap_private& operator=(const volatile ap_private& RHS) { + if (this != &RHS) + for (int i = 0; i < _AP_N; ++i) pVal[i] = RHS.get_pVal(i); + clearUnusedBits(); + return *this; + } + INLINE void operator=(const ap_private& RHS) volatile { + if (this != &RHS) + for (int i = 0; i < _AP_N; ++i) pVal[i] = RHS.get_pVal(i); + clearUnusedBits(); + } + INLINE void operator=(const volatile ap_private& RHS) volatile { + if (this != &RHS) + for (int i = 0; i < _AP_N; ++i) pVal[i] = RHS.get_pVal(i); + clearUnusedBits(); + } + + template + INLINE ap_private& operator=(const ap_private<_AP_W1, _AP_S1>& RHS) { + if (_AP_S1) + cpSextOrTrunc(RHS); + else + cpZextOrTrunc(RHS); + clearUnusedBits(); + return *this; + } + + template + INLINE ap_private& operator=(const volatile ap_private<_AP_W1, _AP_S1>& RHS) { + if (_AP_S1) + cpSextOrTrunc(RHS); + else + cpZextOrTrunc(RHS); + clearUnusedBits(); + return *this; + } + + template + INLINE ap_private& operator=(const _private_range_ref<_AP_W2, _AP_S2>& op2) { + *this = ap_private<_AP_W2, false>(op2); + return *this; + } + +#if 0 + template + INLINE ap_private& operator=(const ap_private<_AP_W1, _AP_S1, true>& RHS) { + static const uint64_t that_sign_ext_mask = (_AP_W1==APINT_BITS_PER_WORD)?0:~0ULL>>(_AP_W1%APINT_BITS_PER_WORD)<<(_AP_W1%APINT_BITS_PER_WORD); + if (RHS.isNegative()) { + pVal[0] = RHS.get_VAL() | that_sign_ext_mask; + memset(pVal+1,~0, APINT_WORD_SIZE*(_AP_N-1)); + } else { + pVal[0] = RHS.get_VAL(); + memset(pVal+1, 0, APINT_WORD_SIZE*(_AP_N-1)); + } + clearUnusedBits(); + return *this; + } + + template + INLINE ap_private& operator=(const volatile ap_private<_AP_W1, _AP_S1, true>& RHS) { + static const uint64_t that_sign_ext_mask = (_AP_W1==APINT_BITS_PER_WORD)?0:~0ULL>>(_AP_W1%APINT_BITS_PER_WORD)<<(_AP_W1%APINT_BITS_PER_WORD); + if (RHS.isNegative()) { + pVal[0] = RHS.get_VAL() | that_sign_ext_mask; + memset(pVal+1,~0, APINT_WORD_SIZE*(_AP_N-1)); + } else { + pVal[0] = RHS.get_VAL(); + memset(pVal+1, 0, APINT_WORD_SIZE*(_AP_N-1)); + } + clearUnusedBits(); + return *this; + } +#endif + +/// from all c types. +#define ASSIGN_OP_FROM_INT(C_TYPE, _AP_W2, _AP_S2) \ + INLINE ap_private& operator=(const C_TYPE rhs) { \ + ap_private<(_AP_W2), (_AP_S2)> tmp = rhs; \ + operator=(tmp); \ + return *this; \ + } + + ASSIGN_OP_FROM_INT(bool, 1, false) + ASSIGN_OP_FROM_INT(char, 8, CHAR_IS_SIGNED) + ASSIGN_OP_FROM_INT(signed char, 8, true) + ASSIGN_OP_FROM_INT(unsigned char, 8, false) + ASSIGN_OP_FROM_INT(short, sizeof(short) * 8, true) + ASSIGN_OP_FROM_INT(unsigned short, sizeof(unsigned short) * 8, false) + ASSIGN_OP_FROM_INT(int, sizeof(int) * 8, true) + ASSIGN_OP_FROM_INT(unsigned int, sizeof(unsigned int) * 8, false) + ASSIGN_OP_FROM_INT(long, sizeof(long) * 8, true) + ASSIGN_OP_FROM_INT(unsigned long, sizeof(unsigned long) * 8, false) + ASSIGN_OP_FROM_INT(ap_slong, sizeof(ap_slong) * 8, true) + ASSIGN_OP_FROM_INT(ap_ulong, sizeof(ap_ulong) * 8, false) +#undef ASSIGN_OP_FROM_INT + + /// from c string. + // XXX this is a must, to prevent pointer being converted to bool. + INLINE ap_private& operator=(const char* s) { + ap_private tmp(s); // XXX direct initialization, as ctor is explicit. + operator=(tmp); + return *this; + } + + /// + /// @name Unary Operators + /// + /// @returns a new ap_private value representing *this incremented by one + /// @brief Postfix increment operator. + INLINE const ap_private operator++(int) { + ap_private API(*this); + ++(*this); + return API; + } + + /// @returns *this incremented by one + /// @brief Prefix increment operator. + INLINE ap_private& operator++() { + ap_private_ops::add_1(pVal, pVal, _AP_N, 1); + clearUnusedBits(); + return *this; + } + + /// @returns a new ap_private representing *this decremented by one. + /// @brief Postfix decrement operator. + INLINE const ap_private operator--(int) { + ap_private API(*this); + --(*this); + return API; + } + + /// @returns *this decremented by one. + /// @brief Prefix decrement operator. + INLINE ap_private& operator--() { + ap_private_ops::sub_1(pVal, _AP_N, 1); + clearUnusedBits(); + return *this; + } + + /// Performs a bitwise complement operation on this ap_private. + /// @returns an ap_private that is the bitwise complement of *this + /// @brief Unary bitwise complement operator. + INLINE ap_private<_AP_W + !_AP_S, true> operator~() const { + ap_private<_AP_W + !_AP_S, true> Result(*this); + Result.flip(); + return Result; + } + + /// Negates *this using two's complement logic. + /// @returns An ap_private value representing the negation of *this. + /// @brief Unary negation operator + INLINE typename RType<1, false>::minus operator-() const { + return ap_private<1, false>(0) - (*this); + } + + /// Performs logical negation operation on this ap_private. + /// @returns true if *this is zero, false otherwise. + /// @brief Logical negation operator. + INLINE bool operator!() const { + for (int i = 0; i < _AP_N; ++i) + if (pVal[i]) return false; + return true; + } + + template + INLINE ap_private<_AP_W, _AP_S || _AP_S1> And( + const ap_private<_AP_W, _AP_S1>& RHS) const { + return this->operator&(RHS); + } + template + INLINE ap_private Or(const ap_private<_AP_W, _AP_S1>& RHS) const { + return this->operator|(RHS); + } + template + INLINE ap_private Xor(const ap_private<_AP_W, _AP_S1>& RHS) const { + return this->operator^(RHS); + } + + INLINE ap_private Mul(const ap_private& RHS) const { + ap_private Result(*this); + Result *= RHS; + return Result; + } + + INLINE ap_private Add(const ap_private& RHS) const { + ap_private Result(0); + ap_private_ops::add(Result.get_pVal(), pVal, RHS.get_pVal(), _AP_N, _AP_N, + _AP_N, _AP_S, _AP_S); + Result.clearUnusedBits(); + return Result; + } + + INLINE ap_private Sub(const ap_private& RHS) const { + ap_private Result(0); + ap_private_ops::sub(Result.get_pVal(), pVal, RHS.get_pVal(), _AP_N, _AP_N, + _AP_N, _AP_S, _AP_S); + Result.clearUnusedBits(); + return Result; + } + + /// Arithmetic right-shift this ap_private by shiftAmt. + /// @brief Arithmetic right-shift function. + INLINE ap_private ashr(uint32_t shiftAmt) const { + assert(shiftAmt <= BitWidth && "Invalid shift amount, too big"); + // Handle a degenerate case + if (shiftAmt == 0) return ap_private(*this); + + // If all the bits were shifted out, the result is, technically, undefined. + // We return -1 if it was negative, 0 otherwise. We check this early to + // avoid + // issues in the algorithm below. + if (shiftAmt == BitWidth) { + if (isNegative()) + return ap_private(-1); + else + return ap_private(0); + } + + // Create some space for the result. + ap_private Retval(0); + uint64_t* val = Retval.get_pVal(); + + // Compute some values needed by the following shift algorithms + uint32_t wordShift = + shiftAmt % APINT_BITS_PER_WORD; // bits to shift per word + uint32_t offset = shiftAmt / APINT_BITS_PER_WORD; // word offset for shift + uint32_t breakWord = _AP_N - 1 - offset; // last word affected + uint32_t bitsInWord = whichBit(BitWidth); // how many bits in last word? + if (bitsInWord == 0) bitsInWord = APINT_BITS_PER_WORD; + + // If we are shifting whole words, just move whole words + if (wordShift == 0) { + // Move the words containing significant bits + for (uint32_t i = 0; i <= breakWord; ++i) + val[i] = pVal[i + offset]; // move whole word + + // Adjust the top significant word for sign bit fill, if negative + if (isNegative()) + if (bitsInWord < APINT_BITS_PER_WORD) + val[breakWord] |= ~0ULL << (bitsInWord); // set high bits + } else { + // Shift the low order words + for (uint32_t i = 0; i < breakWord; ++i) { + // This combines the shifted corresponding word with the low bits from + // the next word (shifted into this word's high bits). + val[i] = ((pVal[i + offset]) >> (wordShift)); + val[i] |= ((pVal[i + offset + 1]) << (APINT_BITS_PER_WORD - wordShift)); + } + + // Shift the break word. In this case there are no bits from the next word + // to include in this word. + val[breakWord] = (pVal[breakWord + offset]) >> (wordShift); + + // Deal with sign extenstion in the break word, and possibly the word + // before + // it. + if (isNegative()) { + if (wordShift > bitsInWord) { + if (breakWord > 0) + val[breakWord - 1] |= + ~0ULL << (APINT_BITS_PER_WORD - (wordShift - bitsInWord)); + val[breakWord] |= ~0ULL; + } else + val[breakWord] |= (~0ULL << (bitsInWord - wordShift)); + } + } + + // Remaining words are 0 or -1, just assign them. + uint64_t fillValue = (isNegative() ? ~0ULL : 0); + for (int i = breakWord + 1; i < _AP_N; ++i) val[i] = fillValue; + Retval.clearUnusedBits(); + return Retval; + } + + /// Logical right-shift this ap_private by shiftAmt. + /// @brief Logical right-shift function. + INLINE ap_private lshr(uint32_t shiftAmt) const { + // If all the bits were shifted out, the result is 0. This avoids issues + // with shifting by the size of the integer type, which produces undefined + // results. We define these "undefined results" to always be 0. + if (shiftAmt == BitWidth) return ap_private(0); + + // If none of the bits are shifted out, the result is *this. This avoids + // issues with shifting byt he size of the integer type, which produces + // undefined results in the code below. This is also an optimization. + if (shiftAmt == 0) return ap_private(*this); + + // Create some space for the result. + ap_private Retval(0); + uint64_t* val = Retval.get_pVal(); + + // If we are shifting less than a word, compute the shift with a simple + // carry + if (shiftAmt < APINT_BITS_PER_WORD) { + uint64_t carry = 0; + for (int i = _AP_N - 1; i >= 0; --i) { + val[i] = ((pVal[i]) >> (shiftAmt)) | carry; + carry = (pVal[i]) << (APINT_BITS_PER_WORD - shiftAmt); + } + Retval.clearUnusedBits(); + return Retval; + } + + // Compute some values needed by the remaining shift algorithms + uint32_t wordShift = shiftAmt % APINT_BITS_PER_WORD; + uint32_t offset = shiftAmt / APINT_BITS_PER_WORD; + + // If we are shifting whole words, just move whole words + if (wordShift == 0) { + for (uint32_t i = 0; i < _AP_N - offset; ++i) val[i] = pVal[i + offset]; + for (uint32_t i = _AP_N - offset; i < _AP_N; i++) val[i] = 0; + Retval.clearUnusedBits(); + return Retval; + } + + // Shift the low order words + uint32_t breakWord = _AP_N - offset - 1; + for (uint32_t i = 0; i < breakWord; ++i) + val[i] = ((pVal[i + offset]) >> (wordShift)) | + ((pVal[i + offset + 1]) << (APINT_BITS_PER_WORD - wordShift)); + // Shift the break word. + val[breakWord] = (pVal[breakWord + offset]) >> (wordShift); + + // Remaining words are 0 + for (int i = breakWord + 1; i < _AP_N; ++i) val[i] = 0; + Retval.clearUnusedBits(); + return Retval; + } + + /// Left-shift this ap_private by shiftAmt. + /// @brief Left-shift function. + INLINE ap_private shl(uint32_t shiftAmt) const { + assert(shiftAmt <= BitWidth && "Invalid shift amount, too big"); + // If all the bits were shifted out, the result is 0. This avoids issues + // with shifting by the size of the integer type, which produces undefined + // results. We define these "undefined results" to always be 0. + if (shiftAmt == BitWidth) return ap_private(0); + + // If none of the bits are shifted out, the result is *this. This avoids a + // lshr by the words size in the loop below which can produce incorrect + // results. It also avoids the expensive computation below for a common + // case. + if (shiftAmt == 0) return ap_private(*this); + + // Create some space for the result. + ap_private Retval(0); + uint64_t* val = Retval.get_pVal(); + // If we are shifting less than a word, do it the easy way + if (shiftAmt < APINT_BITS_PER_WORD) { + uint64_t carry = 0; + for (int i = 0; i < _AP_N; i++) { + val[i] = ((pVal[i]) << (shiftAmt)) | carry; + carry = (pVal[i]) >> (APINT_BITS_PER_WORD - shiftAmt); + } + Retval.clearUnusedBits(); + return Retval; + } + + // Compute some values needed by the remaining shift algorithms + uint32_t wordShift = shiftAmt % APINT_BITS_PER_WORD; + uint32_t offset = shiftAmt / APINT_BITS_PER_WORD; + + // If we are shifting whole words, just move whole words + if (wordShift == 0) { + for (uint32_t i = 0; i < offset; i++) val[i] = 0; + for (int i = offset; i < _AP_N; i++) val[i] = pVal[i - offset]; + Retval.clearUnusedBits(); + return Retval; + } + + // Copy whole words from this to Result. + uint32_t i = _AP_N - 1; + for (; i > offset; --i) + val[i] = (pVal[i - offset]) << (wordShift) | + (pVal[i - offset - 1]) >> (APINT_BITS_PER_WORD - wordShift); + val[offset] = (pVal[0]) << (wordShift); + for (i = 0; i < offset; ++i) val[i] = 0; + Retval.clearUnusedBits(); + return Retval; + } + + INLINE ap_private rotl(uint32_t rotateAmt) const { + if (rotateAmt == 0) return ap_private(*this); + // Don't get too fancy, just use existing shift/or facilities + ap_private hi(*this); + ap_private lo(*this); + hi.shl(rotateAmt); + lo.lshr(BitWidth - rotateAmt); + return hi | lo; + } + + INLINE ap_private rotr(uint32_t rotateAmt) const { + if (rotateAmt == 0) return ap_private(*this); + // Don't get too fancy, just use existing shift/or facilities + ap_private hi(*this); + ap_private lo(*this); + lo.lshr(rotateAmt); + hi.shl(BitWidth - rotateAmt); + return hi | lo; + } + + /// Perform an unsigned divide operation on this ap_private by RHS. Both this + /// and + /// RHS are treated as unsigned quantities for purposes of this division. + /// @returns a new ap_private value containing the division result + /// @brief Unsigned division operation. + INLINE ap_private udiv(const ap_private& RHS) const { + // Get some facts about the LHS and RHS number of bits and words + uint32_t rhsBits = RHS.getActiveBits(); + uint32_t rhsWords = !rhsBits ? 0 : (whichWord(rhsBits - 1) + 1); + assert(rhsWords && "Divided by zero???"); + uint32_t lhsBits = this->getActiveBits(); + uint32_t lhsWords = !lhsBits ? 0 : (whichWord(lhsBits - 1) + 1); + + // Deal with some degenerate cases + if (!lhsWords) + // 0 / X ===> 0 + return ap_private(0); + else if (lhsWords < rhsWords || this->ult(RHS)) { + // X / Y ===> 0, iff X < Y + return ap_private(0); + } else if (*this == RHS) { + // X / X ===> 1 + return ap_private(1); + } else if (lhsWords == 1 && rhsWords == 1) { + // All high words are zero, just use native divide + return ap_private(this->pVal[0] / RHS.get_pVal(0)); + } + + // We have to compute it the hard way. Invoke the Knuth divide algorithm. + ap_private Quotient(0); // to hold result. + ap_private_ops::divide(*this, lhsWords, RHS, rhsWords, &Quotient, + (ap_private*)0); + return Quotient; + } + + /// Signed divide this ap_private by ap_private RHS. + /// @brief Signed division function for ap_private. + INLINE ap_private sdiv(const ap_private& RHS) const { + if (isNegative()) + if (RHS.isNegative()) + return (-(*this)).udiv(-RHS); + else + return -((-(*this)).udiv(RHS)); + else if (RHS.isNegative()) + return -(this->udiv((ap_private)(-RHS))); + return this->udiv(RHS); + } + + /// Perform an unsigned remainder operation on this ap_private with RHS being + /// the + /// divisor. Both this and RHS are treated as unsigned quantities for purposes + /// of this operation. Note that this is a true remainder operation and not + /// a modulo operation because the sign follows the sign of the dividend + /// which is *this. + /// @returns a new ap_private value containing the remainder result + /// @brief Unsigned remainder operation. + INLINE ap_private urem(const ap_private& RHS) const { + // Get some facts about the LHS + uint32_t lhsBits = getActiveBits(); + uint32_t lhsWords = !lhsBits ? 0 : (whichWord(lhsBits - 1) + 1); + + // Get some facts about the RHS + uint32_t rhsBits = RHS.getActiveBits(); + uint32_t rhsWords = !rhsBits ? 0 : (whichWord(rhsBits - 1) + 1); + assert(rhsWords && "Performing remainder operation by zero ???"); + + // Check the degenerate cases + if (lhsWords == 0) { + // 0 % Y ===> 0 + return ap_private(0); + } else if (lhsWords < rhsWords || this->ult(RHS)) { + // X % Y ===> X, iff X < Y + return *this; + } else if (*this == RHS) { + // X % X == 0; + return ap_private(0); + } else if (lhsWords == 1) { + // All high words are zero, just use native remainder + return ap_private(pVal[0] % RHS.get_pVal(0)); + } + + // We have to compute it the hard way. Invoke the Knuth divide algorithm. + ap_private Remainder(0); + ap_private_ops::divide(*this, lhsWords, RHS, rhsWords, (ap_private*)(0), + &Remainder); + return Remainder; + } + + INLINE ap_private urem(uint64_t RHS) const { + // Get some facts about the LHS + uint32_t lhsBits = getActiveBits(); + uint32_t lhsWords = !lhsBits ? 0 : (whichWord(lhsBits - 1) + 1); + // Get some facts about the RHS + uint32_t rhsWords = 1; //! rhsBits ? 0 : (ap_private<_AP_W, + //! _AP_S>::whichWord(rhsBits - 1) + 1); + assert(rhsWords && "Performing remainder operation by zero ???"); + // Check the degenerate cases + if (lhsWords == 0) { + // 0 % Y ===> 0 + return ap_private(0); + } else if (lhsWords < rhsWords || this->ult(RHS)) { + // X % Y ===> X, iff X < Y + return *this; + } else if (*this == RHS) { + // X % X == 0; + return ap_private(0); + } else if (lhsWords == 1) { + // All high words are zero, just use native remainder + return ap_private(pVal[0] % RHS); + } + + // We have to compute it the hard way. Invoke the Knuth divide algorithm. + ap_private Remainder(0); + divide(*this, lhsWords, RHS, (ap_private*)(0), &Remainder); + return Remainder; + } + + /// Signed remainder operation on ap_private. + /// @brief Function for signed remainder operation. + INLINE ap_private srem(const ap_private& RHS) const { + if (isNegative()) { + ap_private lhs = -(*this); + if (RHS.isNegative()) { + ap_private rhs = -RHS; + return -(lhs.urem(rhs)); + } else + return -(lhs.urem(RHS)); + } else if (RHS.isNegative()) { + ap_private rhs = -RHS; + return this->urem(rhs); + } + return this->urem(RHS); + } + + /// Signed remainder operation on ap_private. + /// @brief Function for signed remainder operation. + INLINE ap_private srem(int64_t RHS) const { + if (isNegative()) + if (RHS < 0) + return -((-(*this)).urem(-RHS)); + else + return -((-(*this)).urem(RHS)); + else if (RHS < 0) + return this->urem(-RHS); + return this->urem(RHS); + } + + /// Compares this ap_private with RHS for the validity of the equality + /// relationship. + /// @returns true if *this == Val + /// @brief Equality comparison. + template + INLINE bool eq(const ap_private<_AP_W, _AP_S1>& RHS) const { + return (*this) == RHS; + } + + /// Compares this ap_private with RHS for the validity of the inequality + /// relationship. + /// @returns true if *this != Val + /// @brief Inequality comparison + template + INLINE bool ne(const ap_private<_AP_W, _AP_S1>& RHS) const { + return !((*this) == RHS); + } + + /// Regards both *this and RHS as unsigned quantities and compares them for + /// the validity of the less-than relationship. + /// @returns true if *this < RHS when both are considered unsigned. + /// @brief Unsigned less than comparison + template + INLINE bool ult(const ap_private<_AP_W, _AP_S1>& RHS) const { + // Get active bit length of both operands + uint32_t n1 = getActiveBits(); + uint32_t n2 = RHS.getActiveBits(); + + // If magnitude of LHS is less than RHS, return true. + if (n1 < n2) return true; + + // If magnitude of RHS is greather than LHS, return false. + if (n2 < n1) return false; + + // If they bot fit in a word, just compare the low order word + if (n1 <= APINT_BITS_PER_WORD && n2 <= APINT_BITS_PER_WORD) + return pVal[0] < RHS.get_pVal(0); + + // Otherwise, compare all words + uint32_t topWord = whichWord(AESL_std::max(n1, n2) - 1); + for (int i = topWord; i >= 0; --i) { + if (pVal[i] > RHS.get_pVal(i)) return false; + if (pVal[i] < RHS.get_pVal(i)) return true; + } + return false; + } + + INLINE bool ult(uint64_t RHS) const { + // Get active bit length of both operands + uint32_t n1 = getActiveBits(); + uint32_t n2 = + 64 - ap_private_ops::CountLeadingZeros_64(RHS); // RHS.getActiveBits(); + + // If magnitude of LHS is less than RHS, return true. + if (n1 < n2) return true; + + // If magnitude of RHS is greather than LHS, return false. + if (n2 < n1) return false; + + // If they bot fit in a word, just compare the low order word + if (n1 <= APINT_BITS_PER_WORD && n2 <= APINT_BITS_PER_WORD) + return pVal[0] < RHS; + assert(0); + } + + template + INLINE bool slt(const ap_private<_AP_W, _AP_S1>& RHS) const { + ap_private lhs(*this); + ap_private<_AP_W, _AP_S1> rhs(RHS); + bool lhsNeg = isNegative(); + bool rhsNeg = rhs.isNegative(); + if (lhsNeg) { + // Sign bit is set so perform two's complement to make it positive + lhs.flip(); + lhs++; + } + if (rhsNeg) { + // Sign bit is set so perform two's complement to make it positive + rhs.flip(); + rhs++; + } + + // Now we have unsigned values to compare so do the comparison if necessary + // based on the negativeness of the values. + if (lhsNeg) + if (rhsNeg) + return lhs.ugt(rhs); + else + return true; + else if (rhsNeg) + return false; + else + return lhs.ult(rhs); + } + + /// Regards both *this and RHS as unsigned quantities and compares them for + /// validity of the less-or-equal relationship. + /// @returns true if *this <= RHS when both are considered unsigned. + /// @brief Unsigned less or equal comparison + template + INLINE bool ule(const ap_private<_AP_W, _AP_S1>& RHS) const { + return ult(RHS) || eq(RHS); + } + + /// Regards both *this and RHS as signed quantities and compares them for + /// validity of the less-or-equal relationship. + /// @returns true if *this <= RHS when both are considered signed. + /// @brief Signed less or equal comparison + template + INLINE bool sle(const ap_private<_AP_W, _AP_S1>& RHS) const { + return slt(RHS) || eq(RHS); + } + + /// Regards both *this and RHS as unsigned quantities and compares them for + /// the validity of the greater-than relationship. + /// @returns true if *this > RHS when both are considered unsigned. + /// @brief Unsigned greather than comparison + template + INLINE bool ugt(const ap_private<_AP_W, _AP_S1>& RHS) const { + return !ult(RHS) && !eq(RHS); + } + + /// Regards both *this and RHS as signed quantities and compares them for + /// the validity of the greater-than relationship. + /// @returns true if *this > RHS when both are considered signed. + /// @brief Signed greather than comparison + template + INLINE bool sgt(const ap_private<_AP_W, _AP_S1>& RHS) const { + return !slt(RHS) && !eq(RHS); + } + + /// Regards both *this and RHS as unsigned quantities and compares them for + /// validity of the greater-or-equal relationship. + /// @returns true if *this >= RHS when both are considered unsigned. + /// @brief Unsigned greater or equal comparison + template + INLINE bool uge(const ap_private<_AP_W, _AP_S>& RHS) const { + return !ult(RHS); + } + + /// Regards both *this and RHS as signed quantities and compares them for + /// validity of the greater-or-equal relationship. + /// @returns true if *this >= RHS when both are considered signed. + /// @brief Signed greather or equal comparison + template + INLINE bool sge(const ap_private<_AP_W, _AP_S1>& RHS) const { + return !slt(RHS); + } + + // Sign extend to a new width. + template + INLINE void cpSext(const ap_private<_AP_W1, _AP_S1>& that) { + assert(_AP_W1 < BitWidth && "Invalid ap_private SignExtend request"); + assert(_AP_W1 <= MAX_INT_BITS && "Too many bits"); + // If the sign bit isn't set, this is the same as zext. + if (!that.isNegative()) { + cpZext(that); + return; + } + + // The sign bit is set. First, get some facts + enum { wordBits = _AP_W1 % APINT_BITS_PER_WORD }; + const int _AP_N1 = ap_private<_AP_W1, _AP_S1>::_AP_N; + // Mask the high order word appropriately + if (_AP_N1 == _AP_N) { + enum { newWordBits = _AP_W % APINT_BITS_PER_WORD }; + // The extension is contained to the wordsBefore-1th word. + static const uint64_t mask = wordBits ? (~0ULL << (wordBits)) : 0ULL; + for (int i = 0; i < _AP_N; ++i) pVal[i] = that.get_pVal(i); + pVal[_AP_N - 1] |= mask; + return; + } + + enum { newWordBits = _AP_W % APINT_BITS_PER_WORD }; + // The extension is contained to the wordsBefore-1th word. + static const uint64_t mask = wordBits ? (~0ULL << (wordBits)) : 0ULL; + int i; + for (i = 0; i < _AP_N1; ++i) pVal[i] = that.get_pVal(i); + pVal[i - 1] |= mask; + for (; i < _AP_N - 1; i++) pVal[i] = ~0ULL; + pVal[i] = ~0ULL; + clearUnusedBits(); + return; + } + + // Zero extend to a new width. + template + INLINE void cpZext(const ap_private<_AP_W1, _AP_S1>& that) { + assert(_AP_W1 < BitWidth && "Invalid ap_private ZeroExtend request"); + assert(_AP_W1 <= MAX_INT_BITS && "Too many bits"); + const int _AP_N1 = ap_private<_AP_W1, _AP_S1>::_AP_N; + int i = 0; + for (; i < _AP_N1; ++i) pVal[i] = that.get_pVal(i); + for (; i < _AP_N; ++i) pVal[i] = 0; + clearUnusedBits(); + } + + template + INLINE void cpZextOrTrunc(const ap_private<_AP_W1, _AP_S1>& that) { + if (BitWidth > _AP_W1) + cpZext(that); + else { + for (int i = 0; i < _AP_N; ++i) pVal[i] = that.get_pVal(i); + clearUnusedBits(); + } + } + + template + INLINE void cpSextOrTrunc(const ap_private<_AP_W1, _AP_S1>& that) { + if (BitWidth > _AP_W1) + cpSext(that); + else { + for (int i = 0; i < _AP_N; ++i) pVal[i] = that.get_pVal(i); + clearUnusedBits(); + } + } + + /// @} + /// @name Value Characterization Functions + /// @{ + + /// @returns the total number of bits. + INLINE uint32_t getBitWidth() const { return BitWidth; } + + /// Here one word's bitwidth equals to that of uint64_t. + /// @returns the number of words to hold the integer value of this ap_private. + /// @brief Get the number of words. + INLINE uint32_t getNumWords() const { + return (BitWidth + APINT_BITS_PER_WORD - 1) / APINT_BITS_PER_WORD; + } + + /// This function returns the number of active bits which is defined as the + /// bit width minus the number of leading zeros. This is used in several + /// computations to see how "wide" the value is. + /// @brief Compute the number of active bits in the value + INLINE uint32_t getActiveBits() const { + uint32_t bits = BitWidth - countLeadingZeros(); + return bits ? bits : 1; + } + + /// This method attempts to return the value of this ap_private as a zero + /// extended + /// uint64_t. The bitwidth must be <= 64 or the value must fit within a + /// uint64_t. Otherwise an assertion will result. + /// @brief Get zero extended value + INLINE uint64_t getZExtValue() const { + assert(getActiveBits() <= 64 && "Too many bits for uint64_t"); + return *pVal; + } + + /// This method attempts to return the value of this ap_private as a sign + /// extended + /// int64_t. The bit width must be <= 64 or the value must fit within an + /// int64_t. Otherwise an assertion will result. + /// @brief Get sign extended value + INLINE int64_t getSExtValue() const { + assert(getActiveBits() <= 64 && "Too many bits for int64_t"); + return int64_t(pVal[0]); + } + + /// This method determines how many bits are required to hold the ap_private + /// equivalent of the string given by \p str of length \p slen. + /// @brief Get bits required for string value. + INLINE static uint32_t getBitsNeeded(const char* str, uint32_t slen, + uint8_t radix) { + assert(str != 0 && "Invalid value string"); + assert(slen > 0 && "Invalid string length"); + + // Each computation below needs to know if its negative + uint32_t isNegative = str[0] == '-'; + if (isNegative) { + slen--; + str++; + } + // For radixes of power-of-two values, the bits required is accurately and + // easily computed + if (radix == 2) return slen + isNegative; + if (radix == 8) return slen * 3 + isNegative; + if (radix == 16) return slen * 4 + isNegative; + + // Otherwise it must be radix == 10, the hard case + assert(radix == 10 && "Invalid radix"); + + // Convert to the actual binary value. + // ap_private<_AP_W, _AP_S> tmp(sufficient, str, slen, radix); + + // Compute how many bits are required. + // return isNegative + tmp.logBase2() + 1; + return isNegative + slen * 4; + } + + /// countLeadingZeros - This function is an ap_private version of the + /// countLeadingZeros_{32,64} functions in MathExtras.h. It counts the number + /// of zeros from the most significant bit to the first one bit. + /// @returns BitWidth if the value is zero. + /// @returns the number of zeros from the most significant bit to the first + /// one bits. + INLINE uint32_t countLeadingZeros() const { + enum { + msw_bits = (BitWidth % APINT_BITS_PER_WORD) + ? (BitWidth % APINT_BITS_PER_WORD) + : APINT_BITS_PER_WORD, + excessBits = APINT_BITS_PER_WORD - msw_bits + }; + uint32_t Count = ap_private_ops::CountLeadingZeros_64(pVal[_AP_N - 1]); + if (Count >= excessBits) Count -= excessBits; + if (!pVal[_AP_N - 1]) { + for (int i = _AP_N - 1; i; --i) { + if (!pVal[i - 1]) + Count += APINT_BITS_PER_WORD; + else { + Count += ap_private_ops::CountLeadingZeros_64(pVal[i - 1]); + break; + } + } + } + return Count; + } + + /// countLeadingOnes - This function counts the number of contiguous 1 bits + /// in the high order bits. The count stops when the first 0 bit is reached. + /// @returns 0 if the high order bit is not set + /// @returns the number of 1 bits from the most significant to the least + /// @brief Count the number of leading one bits. + INLINE uint32_t countLeadingOnes() const { + if (isSingleWord()) + return countLeadingOnes_64(get_VAL(), APINT_BITS_PER_WORD - BitWidth); + + uint32_t highWordBits = BitWidth % APINT_BITS_PER_WORD; + uint32_t shift = + (highWordBits == 0 ? 0 : APINT_BITS_PER_WORD - highWordBits); + int i = _AP_N - 1; + uint32_t Count = countLeadingOnes_64(get_pVal(i), shift); + if (Count == highWordBits) { + for (i--; i >= 0; --i) { + if (get_pVal(i) == ~0ULL) + Count += APINT_BITS_PER_WORD; + else { + Count += countLeadingOnes_64(get_pVal(i), 0); + break; + } + } + } + return Count; + } + + /// countTrailingZeros - This function is an ap_private version of the + /// countTrailingZoers_{32,64} functions in MathExtras.h. It counts + /// the number of zeros from the least significant bit to the first set bit. + /// @returns BitWidth if the value is zero. + /// @returns the number of zeros from the least significant bit to the first + /// one bit. + /// @brief Count the number of trailing zero bits. + INLINE uint32_t countTrailingZeros() const { + uint32_t Count = 0; + uint32_t i = 0; + for (; i < _AP_N && get_pVal(i) == 0; ++i) Count += APINT_BITS_PER_WORD; + if (i < _AP_N) Count += ap_private_ops::CountTrailingZeros_64(get_pVal(i)); + return AESL_std::min(Count, BitWidth); + } + /// countPopulation - This function is an ap_private version of the + /// countPopulation_{32,64} functions in MathExtras.h. It counts the number + /// of 1 bits in the ap_private value. + /// @returns 0 if the value is zero. + /// @returns the number of set bits. + /// @brief Count the number of bits set. + INLINE uint32_t countPopulation() const { + uint32_t Count = 0; + for (int i = 0; i < _AP_N - 1; ++i) + Count += ap_private_ops::CountPopulation_64(pVal[i]); + Count += ap_private_ops::CountPopulation_64(pVal[_AP_N - 1] & mask); + return Count; + } + + /// @} + /// @name Conversion Functions + /// @ + + /// This is used internally to convert an ap_private to a string. + /// @brief Converts an ap_private to a std::string + INLINE std::string toString(uint8_t radix, bool wantSigned) const; + + /// Considers the ap_private to be unsigned and converts it into a string in + /// the + /// radix given. The radix can be 2, 8, 10 or 16. + /// @returns a character interpretation of the ap_private + /// @brief Convert unsigned ap_private to string representation. + INLINE std::string toStringUnsigned(uint8_t radix = 10) const { + return toString(radix, false); + } + + /// Considers the ap_private to be unsigned and converts it into a string in + /// the + /// radix given. The radix can be 2, 8, 10 or 16. + /// @returns a character interpretation of the ap_private + /// @brief Convert unsigned ap_private to string representation. + INLINE std::string toStringSigned(uint8_t radix = 10) const { + return toString(radix, true); + } + + /// @brief Converts this ap_private to a double value. + INLINE double roundToDouble(bool isSigned) const { + // Handle the simple case where the value is contained in one uint64_t. + if (isSingleWord() || getActiveBits() <= APINT_BITS_PER_WORD) { + uint64_t val = pVal[0]; + if (isSigned) { + int64_t sext = ((int64_t(val)) << (64 - BitWidth)) >> (64 - BitWidth); + return double(sext); + } else + return double(val); + } + + // Determine if the value is negative. + bool isNeg = isSigned ? (*this)[BitWidth - 1] : false; + + // Construct the absolute value if we're negative. + ap_private<_AP_W, _AP_S> Tmp(isNeg ? -(*this) : (*this)); + + // Figure out how many bits we're using. + uint32_t n = Tmp.getActiveBits(); + + // The exponent (without bias normalization) is just the number of bits + // we are using. Note that the sign bit is gone since we constructed the + // absolute value. + uint64_t exp = n; + + // Return infinity for exponent overflow + if (exp > 1023) { + if (!isSigned || !isNeg) + return std::numeric_limits::infinity(); + else + return -std::numeric_limits::infinity(); + } + exp += 1023; // Increment for 1023 bias + + // Number of bits in mantissa is 52. To obtain the mantissa value, we must + // extract the high 52 bits from the correct words in pVal. + uint64_t mantissa; + unsigned hiWord = whichWord(n - 1); + if (hiWord == 0) { + mantissa = Tmp.get_pVal(0); + if (n > 52) + (mantissa) >>= (n - 52); // shift down, we want the top 52 bits. + } else { + assert(hiWord > 0 && "High word is negative?"); + uint64_t hibits = (Tmp.get_pVal(hiWord)) + << (52 - n % APINT_BITS_PER_WORD); + uint64_t lobits = + (Tmp.get_pVal(hiWord - 1)) >> (11 + n % APINT_BITS_PER_WORD); + mantissa = hibits | lobits; + } + + // The leading bit of mantissa is implicit, so get rid of it. + uint64_t sign = isNeg ? (1ULL << (APINT_BITS_PER_WORD - 1)) : 0; + union { + double __D; + uint64_t __I; + } __T; + __T.__I = sign | ((exp) << 52) | mantissa; + return __T.__D; + } + + /// @brief Converts this unsigned ap_private to a double value. + INLINE double roundToDouble() const { return roundToDouble(false); } + + /// @brief Converts this signed ap_private to a double value. + INLINE double signedRoundToDouble() const { return roundToDouble(true); } + + /// The conversion does not do a translation from integer to double, it just + /// re-interprets the bits as a double. Note that it is valid to do this on + /// any bit width. Exactly 64 bits will be translated. + /// @brief Converts ap_private bits to a double + INLINE double bitsToDouble() const { + union { + uint64_t __I; + double __D; + } __T; + __T.__I = pVal[0]; + return __T.__D; + } + + /// The conversion does not do a translation from integer to float, it just + /// re-interprets the bits as a float. Note that it is valid to do this on + /// any bit width. Exactly 32 bits will be translated. + /// @brief Converts ap_private bits to a double + INLINE float bitsToFloat() const { + union { + uint32_t __I; + float __F; + } __T; + __T.__I = uint32_t(pVal[0]); + return __T.__F; + } + + /// The conversion does not do a translation from double to integer, it just + /// re-interprets the bits of the double. Note that it is valid to do this on + /// any bit width but bits from V may get truncated. + /// @brief Converts a double to ap_private bits. + INLINE ap_private& doubleToBits(double __V) { + union { + uint64_t __I; + double __D; + } __T; + __T.__D = __V; + pVal[0] = __T.__I; + return *this; + } + + /// The conversion does not do a translation from float to integer, it just + /// re-interprets the bits of the float. Note that it is valid to do this on + /// any bit width but bits from V may get truncated. + /// @brief Converts a float to ap_private bits. + INLINE ap_private& floatToBits(float __V) { + union { + uint32_t __I; + float __F; + } __T; + __T.__F = __V; + pVal[0] = __T.__I; + } + + // Reduce operation + //----------------------------------------------------------- + INLINE bool and_reduce() const { return isMaxValue(); } + + INLINE bool nand_reduce() const { return isMinValue(); } + + INLINE bool or_reduce() const { return (bool)countPopulation(); } + + INLINE bool nor_reduce() const { return countPopulation() == 0; } + + INLINE bool xor_reduce() const { + unsigned int i = countPopulation(); + return (i % 2) ? true : false; + } + + INLINE bool xnor_reduce() const { + unsigned int i = countPopulation(); + return (i % 2) ? false : true; + } + INLINE std::string to_string(uint8_t radix = 16, bool sign = false) const { + return toString(radix, radix == 10 ? _AP_S : sign); + } +}; // End of class ap_private <_AP_W, _AP_S, false> + +namespace ap_private_ops { + +enum { APINT_BITS_PER_WORD = 64 }; +template +INLINE bool operator==(uint64_t V1, const ap_private<_AP_W, _AP_S>& V2) { + return V2 == V1; +} + +template +INLINE bool operator!=(uint64_t V1, const ap_private<_AP_W, _AP_S>& V2) { + return V2 != V1; +} + +template +INLINE bool get(const ap_private<_AP_W, _AP_S>& a) { + static const uint64_t mask = 1ULL << (index & 0x3f); + return ((mask & a.get_pVal((index) >> 6)) != 0); +} + +template +INLINE void set(ap_private<_AP_W, _AP_S>& a, + const ap_private& mark1 = 0, + const ap_private& mark2 = 0) { + enum { + APINT_BITS_PER_WORD = 64, + lsb_word = lsb_index / APINT_BITS_PER_WORD, + msb_word = msb_index / APINT_BITS_PER_WORD, + msb = msb_index % APINT_BITS_PER_WORD, + lsb = lsb_index % APINT_BITS_PER_WORD + }; + if (msb_word == lsb_word) { + const uint64_t mask = ~0ULL >> + (lsb) << (APINT_BITS_PER_WORD - msb + lsb - 1) >> + (APINT_BITS_PER_WORD - msb - 1); + // a.set_pVal(msb_word, a.get_pVal(msb_word) | mask); + a.get_pVal(msb_word) |= mask; + } else { + const uint64_t lsb_mask = ~0ULL >> (lsb) << (lsb); + const uint64_t msb_mask = ~0ULL << (APINT_BITS_PER_WORD - msb - 1) >> + (APINT_BITS_PER_WORD - msb - 1); + // a.set_pVal(lsb_word, a.get_pVal(lsb_word) | lsb_mask); + a.get_pVal(lsb_word) |= lsb_mask; + for (int i = lsb_word + 1; i < msb_word; i++) { + a.set_pVal(i, ~0ULL); + // a.get_pVal(i)=0; + } + // a.set_pVal(msb_word, a.get_pVal(msb_word) | msb_mask); + + a.get_pVal(msb_word) |= msb_mask; + } + a.clearUnusedBits(); +} + +template +INLINE void clear(ap_private<_AP_W, _AP_S>& a, + const ap_private& mark1 = 0, + const ap_private& mark2 = 0) { + enum { + APINT_BITS_PER_WORD = 64, + lsb_word = lsb_index / APINT_BITS_PER_WORD, + msb_word = msb_index / APINT_BITS_PER_WORD, + msb = msb_index % APINT_BITS_PER_WORD, + lsb = lsb_index % APINT_BITS_PER_WORD + }; + if (msb_word == lsb_word) { + const uint64_t mask = + ~(~0ULL >> (lsb) << (APINT_BITS_PER_WORD - msb + lsb - 1) >> + (APINT_BITS_PER_WORD - msb - 1)); + // a.set_pVal(msb_word, a.get_pVal(msb_word) & mask); + a.get_pVal(msb_word) &= mask; + } else { + const uint64_t lsb_mask = ~(~0ULL >> (lsb) << (lsb)); + const uint64_t msb_mask = ~(~0ULL << (APINT_BITS_PER_WORD - msb - 1) >> + (APINT_BITS_PER_WORD - msb - 1)); + // a.set_pVal(lsb_word, a.get_pVal(lsb_word) & lsb_mask); + a.get_pVal(lsb_word) &= lsb_mask; + for (int i = lsb_word + 1; i < msb_word; i++) { + // a.set_pVal(i, 0); + a.get_pVal(i) = 0; + } + // a.set_pVal(msb_word, a.get_pVal(msb_word) & msb_mask); + a.get_pVal(msb_word) &= msb_mask; + } + a.clearUnusedBits(); +} + +template +INLINE void set(ap_private<_AP_W, _AP_S>& a, + const ap_private& mark = 0) { + enum { APINT_BITS_PER_WORD = 64, word = index / APINT_BITS_PER_WORD }; + static const uint64_t mask = 1ULL << (index % APINT_BITS_PER_WORD); + // a.set_pVal(word, a.get_pVal(word) | mask); + a.get_pVal(word) |= mask; + a.clearUnusedBits(); +} + +template +INLINE void clear(ap_private<_AP_W, _AP_S>& a, + const ap_private& mark = 0) { + enum { APINT_BITS_PER_WORD = 64, word = index / APINT_BITS_PER_WORD }; + static const uint64_t mask = ~(1ULL << (index % APINT_BITS_PER_WORD)); + // a.set_pVal(word, a.get_pVal(word) & mask); + a.get_pVal(word) &= mask; + a.clearUnusedBits(); +} + +} // End of ap_private_ops namespace + +template +INLINE std::string ap_private<_AP_W, _AP_S, false>::toString( + uint8_t radix, bool wantSigned) const { + assert((radix == 10 || radix == 8 || radix == 16 || radix == 2) && + "Radix should be 2, 8, 10, or 16!"); + static const char* digits[] = {"0", "1", "2", "3", "4", "5", "6", "7", + "8", "9", "A", "B", "C", "D", "E", "F"}; + std::string result; + + if (radix != 10) { + // For the 2, 8 and 16 bit cases, we can just shift instead of divide + // because the number of bits per digit (1,3 and 4 respectively) divides + // equaly. We just shift until there value is zero. + + // First, check for a zero value and just short circuit the logic below. + if (*this == (uint64_t)(0)) + result = "0"; + else { + ap_private<_AP_W, false> tmp(*this); + size_t insert_at = 0; + bool leading_zero = true; + if (wantSigned && isNegative()) { + // They want to print the signed version and it is a negative value + // Flip the bits and add one to turn it into the equivalent positive + // value and put a '-' in the result. + tmp.flip(); + tmp++; + tmp.clearUnusedBitsToZero(); + result = "-"; + insert_at = 1; + leading_zero = false; + } + switch (radix) { + case 2: + result += "0b"; + break; + case 8: + result += "0o"; + break; + case 16: + result += "0x"; + break; + default: + assert("invalid radix" && 0); + } + insert_at += 2; + // Just shift tmp right for each digit width until it becomes zero + uint32_t shift = (radix == 16 ? 4 : (radix == 8 ? 3 : 1)); + uint64_t mask = radix - 1; + ap_private<_AP_W, false> zero(0); + unsigned bits = 0; + while (tmp.ne(zero)) { + uint64_t digit = tmp.get_VAL() & mask; + result.insert(insert_at, digits[digit]); + tmp = tmp.lshr(shift); + ++bits; + } + bits *= shift; + if (bits < _AP_W && leading_zero) result.insert(insert_at, digits[0]); + } + return result; + } + + ap_private<_AP_W, false> tmp(*this); + ap_private<_AP_W, false> divisor(radix); + ap_private<_AP_W, false> zero(0); + size_t insert_at = 0; + if (wantSigned && isNegative()) { + // They want to print the signed version and it is a negative value + // Flip the bits and add one to turn it into the equivalent positive + // value and put a '-' in the result. + tmp.flip(); + tmp++; + tmp.clearUnusedBitsToZero(); + result = "-"; + insert_at = 1; + } + if (tmp == ap_private<_AP_W, false>(0)) + result = "0"; + else + while (tmp.ne(zero)) { + ap_private<_AP_W, false> APdigit(0); + ap_private<_AP_W, false> tmp2(0); + ap_private_ops::divide(tmp, tmp.getNumWords(), divisor, + divisor.getNumWords(), &tmp2, &APdigit); + uint64_t digit = APdigit.getZExtValue(); + assert(digit < radix && "divide failed"); + result.insert(insert_at, digits[digit]); + tmp = tmp2; + } + + return result; +} // End of ap_private<_AP_W, _AP_S, false>::toString() + +template +std::ostream &operator<<(std::ostream &os, const ap_private<_AP_W, _AP_S> &x) { + std::ios_base::fmtflags ff = std::cout.flags(); + if (ff & std::cout.hex) { + os << x.toString(16, false); // don't print sign + } else if (ff & std::cout.oct) { + os << x.toString(8, false); // don't print sign + } else { + os << x.toString(10, _AP_S); + } + return os; +} + +// ------------------------------------------------------------ // +// XXX moved here from ap_int_sim.h XXX // +// ------------------------------------------------------------ // + +/// Concatination reference. +/// Proxy class which allows concatination to be used as rvalue(for reading) and +/// lvalue(for writing) +// ---------------------------------------------------------------- +// template +// struct ap_concat_ref { +//#ifdef _MSC_VER +//#pragma warning(disable : 4521 4522) +//#endif +// enum { +// _AP_WR = _AP_W1 + _AP_W2, +// }; +// _AP_T1& mbv1; +// _AP_T2& mbv2; +// +// INLINE ap_concat_ref(const ap_concat_ref<_AP_W1, _AP_T1, _AP_W2, _AP_T2>& +// ref) +// : mbv1(ref.mbv1), mbv2(ref.mbv2) {} +// +// INLINE ap_concat_ref(_AP_T1& bv1, _AP_T2& bv2) : mbv1(bv1), mbv2(bv2) {} +// +// template +// INLINE ap_concat_ref& operator=(const ap_private<_AP_W3, _AP_S3>& val) { +// ap_private<_AP_W1 + _AP_W2, false> vval(val); +// int W_ref1 = mbv1.length(); +// int W_ref2 = mbv2.length(); +// ap_private<_AP_W1, false> mask1(-1); +// mask1 >>= _AP_W1 - W_ref1; +// ap_private<_AP_W2, false> mask2(-1); +// mask2 >>= _AP_W2 - W_ref2; +// mbv1.set(ap_private<_AP_W1, false>((vval >> W_ref2) & mask1)); +// mbv2.set(ap_private<_AP_W2, false>(vval & mask2)); +// return *this; +// } +// +// INLINE ap_concat_ref& operator=(unsigned long long val) { +// ap_private<_AP_W1 + _AP_W2, false> tmpVal(val); +// return operator=(tmpVal); +// } +// +// template +// INLINE ap_concat_ref& operator=( +// const ap_concat_ref<_AP_W3, _AP_T3, _AP_W4, _AP_T4>& val) { +// ap_private<_AP_W1 + _AP_W2, false> tmpVal(val); +// return operator=(tmpVal); +// } +// +// INLINE ap_concat_ref& operator=( +// const ap_concat_ref<_AP_W1, _AP_T1, _AP_W2, _AP_T2>& val) { +// ap_private<_AP_W1 + _AP_W2, false> tmpVal(val); +// return operator=(tmpVal); +// } +// +// template +// INLINE ap_concat_ref& operator=(const _private_bit_ref<_AP_W3, _AP_S3>& +// val) { +// ap_private<_AP_W1 + _AP_W2, false> tmpVal(val); +// return operator=(tmpVal); +// } +// +// template +// INLINE ap_concat_ref& operator=(const _private_range_ref<_AP_W3, _AP_S3>& +// val) { +// ap_private<_AP_W1 + _AP_W2, false> tmpVal(val); +// return operator=(tmpVal); +// } +// +// template +// INLINE ap_concat_ref& operator=( +// const af_range_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3>& val) +// { +// return operator=((const ap_private<_AP_W3, false>)(val)); +// } +// +// template +// INLINE ap_concat_ref& operator=( +// const ap_fixed_base<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3>& +// val) { +// return operator=(val.to_ap_private()); +// } +// +// template +// INLINE ap_concat_ref& operator=( +// const af_bit_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3>& val) { +// return operator=((unsigned long long)(bool)(val)); +// } +// +// INLINE operator ap_private<_AP_WR, false>() const { return get(); } +// +// INLINE operator unsigned long long() const { return get().to_uint64(); } +// +// template +// INLINE ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, +// _private_range_ref<_AP_W3, _AP_S3> > +// operator,(const _private_range_ref<_AP_W3, _AP_S3> &a2) { +// return ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, +// _private_range_ref<_AP_W3, _AP_S3> >( +// *this, const_cast<_private_range_ref<_AP_W3, _AP_S3>&>(a2)); +// } +// +// template +// INLINE +// ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, ap_private<_AP_W3, _AP_S3> +// > +// operator,(ap_private<_AP_W3, _AP_S3> &a2) { +// return ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, +// ap_private<_AP_W3, _AP_S3> >(*this, a2); +// } +// +// template +// INLINE +// ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, ap_private<_AP_W3, _AP_S3> +// > +// operator,(const ap_private<_AP_W3, _AP_S3> &a2) { +// return ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, +// ap_private<_AP_W3, _AP_S3> >( +// *this, const_cast&>(a2)); +// } +// +// template +// INLINE ap_concat_ref<_AP_WR, ap_concat_ref, 1, _private_bit_ref<_AP_W3, +// _AP_S3> > +// operator,(const _private_bit_ref<_AP_W3, _AP_S3> &a2) { +// return ap_concat_ref<_AP_WR, ap_concat_ref, 1, _private_bit_ref<_AP_W3, +// _AP_S3> >( +// *this, const_cast<_private_bit_ref<_AP_W3, _AP_S3>&>(a2)); +// } +// +// template +// INLINE ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3 + _AP_W4, +// ap_concat_ref<_AP_W3, _AP_T3, _AP_W4, _AP_T4> > +// operator,(const ap_concat_ref<_AP_W3, _AP_T3, _AP_W4, _AP_T4> &a2) { +// return ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3 + _AP_W4, +// ap_concat_ref<_AP_W3, _AP_T3, _AP_W4, _AP_T4> >( +// *this, const_cast&>(a2)); +// } +// +// template +// INLINE ap_concat_ref< +// _AP_WR, ap_concat_ref, _AP_W3, +// af_range_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> > +// operator,( +// const af_range_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> &a2) +// { +// return ap_concat_ref< +// _AP_WR, ap_concat_ref, _AP_W3, +// af_range_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> >( +// *this, +// const_cast< +// af_range_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, +// _AP_N3>&>(a2)); +// } +// +// template +// INLINE +// ap_concat_ref<_AP_WR, ap_concat_ref, 1, +// af_bit_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> +// > +// operator,(const af_bit_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, +// _AP_N3> +// &a2) { +// return ap_concat_ref< +// _AP_WR, ap_concat_ref, 1, +// af_bit_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> >( +// *this, +// const_cast&>( +// a2)); +// } +// +// template +// INLINE ap_private operator&( +// const ap_private<_AP_W3, _AP_S3>& a2) { +// return get() & a2; +// } +// +// template +// INLINE ap_private operator|( +// const ap_private<_AP_W3, _AP_S3>& a2) { +// return get() | a2; +// } +// +// template +// INLINE ap_private operator^( +// const ap_private<_AP_W3, _AP_S3>& a2) { +// return ap_private(get() ^ a2); +// } +// +// INLINE const ap_private<_AP_WR, false> get() const { +// ap_private<_AP_W1 + _AP_W2, false> tmpVal = +// ap_private<_AP_W1 + _AP_W2, false>(mbv1.get()); +// ap_private<_AP_W1 + _AP_W2, false> tmpVal2 = +// ap_private<_AP_W1 + _AP_W2, false>(mbv2.get()); +// int W_ref2 = mbv2.length(); +// tmpVal <<= W_ref2; +// tmpVal |= tmpVal2; +// return tmpVal; +// } +// +// INLINE const ap_private<_AP_WR, false> get() { +// ap_private<_AP_W1 + _AP_W2, false> tmpVal = +// ap_private<_AP_W1 + _AP_W2, false>(mbv1.get()); +// ap_private<_AP_W1 + _AP_W2, false> tmpVal2 = +// ap_private<_AP_W1 + _AP_W2, false>(mbv2.get()); +// int W_ref2 = mbv2.length(); +// tmpVal <<= W_ref2; +// tmpVal |= tmpVal2; +// return tmpVal; +// } +// +// template +// INLINE void set(const ap_private<_AP_W3, false>& val) { +// ap_private<_AP_W1 + _AP_W2, false> vval(val); +// int W_ref1 = mbv1.length(); +// int W_ref2 = mbv2.length(); +// ap_private<_AP_W1, false> mask1(-1); +// mask1 >>= _AP_W1 - W_ref1; +// ap_private<_AP_W2, false> mask2(-1); +// mask2 >>= _AP_W2 - W_ref2; +// mbv1.set(ap_private<_AP_W1, false>((vval >> W_ref2) & mask1)); +// mbv2.set(ap_private<_AP_W2, false>(vval & mask2)); +// } +// +// INLINE int length() const { return mbv1.length() + mbv2.length(); } +// +// INLINE std::string to_string(uint8_t radix = 2) const { +// return get().to_string(radix); +// } +//}; // struct ap_concat_ref. + +/// Range(slice) reference +/// Proxy class, which allows part selection to be used as rvalue(for reading) +/// and lvalue(for writing) +//------------------------------------------------------------ +template +struct _private_range_ref { +#ifdef _MSC_VER +#pragma warning(disable : 4521 4522) +#endif + ap_private<_AP_W, _AP_S>& d_bv; + int l_index; + int h_index; + + public: + /// copy ctor. + INLINE _private_range_ref(const _private_range_ref<_AP_W, _AP_S>& ref) + : d_bv(ref.d_bv), l_index(ref.l_index), h_index(ref.h_index) {} + + /// direct ctor. + INLINE _private_range_ref(ap_private<_AP_W, _AP_S>* bv, int h, int l) + : d_bv(*bv), l_index(l), h_index(h) { + _AP_WARNING(h < 0 || l < 0, + "Higher bound (%d) and lower bound (%d) cannot be " + "negative.", + h, l); + _AP_WARNING(h >= _AP_W || l >= _AP_W, + "Higher bound (%d) or lower bound (%d) out of range (%d).", h, l, + _AP_W); + } + + /// compound or assignment. + template + INLINE _private_range_ref<_AP_W, _AP_S>& operator|=( + const _private_range_ref<_AP_W2, _AP_S2>& ref) { + _AP_WARNING((h_index - l_index) != (ref.h_index - ref.l_index), + "Bitsize mismach for ap_private<>.range() &= " + "ap_private<>.range()."); + this->d_bv |= ref.d_bv; + return *this; + } + + /// compound or assignment with root type. + template + INLINE _private_range_ref<_AP_W, _AP_S>& operator|=( + const _AP_ROOT_TYPE<_AP_W2, _AP_S2>& ref) { + _AP_WARNING((h_index - l_index + 1) != _AP_W2, + "Bitsize mismach for ap_private<>.range() |= _AP_ROOT_TYPE<>."); + this->d_bv |= ref.V; + return *this; + } + + /// compound and assignment. + template + INLINE _private_range_ref<_AP_W, _AP_S>& operator&=( + const _private_range_ref<_AP_W2, _AP_S2>& ref) { + _AP_WARNING((h_index - l_index) != (ref.h_index - ref.l_index), + "Bitsize mismach for ap_private<>.range() &= " + "ap_private<>.range()."); + this->d_bv &= ref.d_bv; + return *this; + }; + + /// compound and assignment with root type. + template + INLINE _private_range_ref<_AP_W, _AP_S>& operator&=( + const _AP_ROOT_TYPE<_AP_W2, _AP_S2>& ref) { + _AP_WARNING((h_index - l_index + 1) != _AP_W2, + "Bitsize mismach for ap_private<>.range() &= _AP_ROOT_TYPE<>."); + this->d_bv &= ref.V; + return *this; + } + + /// compound xor assignment. + template + INLINE _private_range_ref<_AP_W, _AP_S>& operator^=( + const _private_range_ref<_AP_W2, _AP_S2>& ref) { + _AP_WARNING((h_index - l_index) != (ref.h_index - ref.l_index), + "Bitsize mismach for ap_private<>.range() ^= " + "ap_private<>.range()."); + this->d_bv ^= ref.d_bv; + return *this; + }; + + /// compound xor assignment with root type. + template + INLINE _private_range_ref<_AP_W, _AP_S>& operator^=( + const _AP_ROOT_TYPE<_AP_W2, _AP_S2>& ref) { + _AP_WARNING((h_index - l_index + 1) != _AP_W2, + "Bitsize mismach for ap_private<>.range() ^= _AP_ROOT_TYPE<>."); + this->d_bv ^= ref.V; + return *this; + } + + /// @name convertors. + // @{ + INLINE operator ap_private<_AP_W, false>() const { + ap_private<_AP_W, false> val(0); + if (h_index >= l_index) { + if (_AP_W > 64) { + val = d_bv; + ap_private<_AP_W, false> mask(-1); + mask >>= _AP_W - (h_index - l_index + 1); + val >>= l_index; + val &= mask; + } else { + const static uint64_t mask = (~0ULL >> (64 > _AP_W ? (64 - _AP_W) : 0)); + val = (d_bv >> l_index) & (mask >> (_AP_W - (h_index - l_index + 1))); + } + } else { + for (int i = 0, j = l_index; j >= 0 && j >= h_index; j--, i++) + if ((d_bv)[j]) val.set(i); + } + return val; + } + + INLINE operator unsigned long long() const { return to_uint64(); } + // @} + + template + INLINE _private_range_ref& operator=(const ap_private<_AP_W2, _AP_S2>& val) { + ap_private<_AP_W, false> vval = ap_private<_AP_W, false>(val); + if (l_index > h_index) { + for (int i = 0, j = l_index; j >= 0 && j >= h_index; j--, i++) + (vval)[i] ? d_bv.set(j) : d_bv.clear(j); + } else { + if (_AP_W > 64) { + ap_private<_AP_W, false> mask(-1); + if (l_index > 0) { + mask <<= l_index; + vval <<= l_index; + } + if (h_index < _AP_W - 1) { + ap_private<_AP_W, false> mask2(-1); + mask2 >>= _AP_W - h_index - 1; + mask &= mask2; + vval &= mask2; + } + mask.flip(); + d_bv &= mask; + d_bv |= vval; + } else { + unsigned shift = 64 - _AP_W; + uint64_t mask = ~0ULL >> (shift); + if (l_index > 0) { + vval = mask & vval << l_index; + mask = mask & mask << l_index; + } + if (h_index < _AP_W - 1) { + uint64_t mask2 = mask; + mask2 >>= (_AP_W - h_index - 1); + mask &= mask2; + vval &= mask2; + } + mask = ~mask; + d_bv &= mask; + d_bv |= vval; + } + } + return *this; + } // operator=(const ap_private<>&) + + INLINE _private_range_ref& operator=(unsigned long long val) { + const ap_private<_AP_W, _AP_S> vval = val; + return operator=(vval); + } + + template + INLINE _private_range_ref& operator=( + const _private_bit_ref<_AP_W2, _AP_S2>& val) { + return operator=((unsigned long long)(bool)val); + } + + template + INLINE _private_range_ref& operator=( + const _private_range_ref<_AP_W2, _AP_S2>& val) { + const ap_private<_AP_W, false> tmpVal(val); + return operator=(tmpVal); + } + +// template +// INLINE _private_range_ref& operator=( +// const ap_concat_ref<_AP_W3, _AP_T3, _AP_W4, _AP_T4>& val) { +// const ap_private<_AP_W, false> tmpVal(val); +// return operator=(tmpVal); +// } + + // TODO from ap_int_base, ap_bit_ref and ap_range_ref. + + template + INLINE _private_range_ref& operator=( + const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) { + return operator=(val.to_ap_int_base().V); + } + + template + INLINE _private_range_ref& operator=( + const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) { + return operator=(val.operator ap_int_base<_AP_W2, false>().V); + } + + template + INLINE _private_range_ref& operator=( + const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) { + return operator=((unsigned long long)(bool)val); + } + +// template +// INLINE ap_concat_ref<_AP_W, _private_range_ref, _AP_W2, +// _private_range_ref<_AP_W2, _AP_S2> > +// operator,(const _private_range_ref<_AP_W2, _AP_S2> &a2) { +// return ap_concat_ref<_AP_W, _private_range_ref, _AP_W2, +// _private_range_ref<_AP_W2, _AP_S2> >( +// *this, const_cast<_private_range_ref<_AP_W2, _AP_S2>&>(a2)); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, _private_range_ref, _AP_W2, +// ap_private<_AP_W2, _AP_S2> > +// operator,(ap_private<_AP_W2, _AP_S2> &a2) { +// return ap_concat_ref<_AP_W, _private_range_ref, _AP_W2, +// ap_private<_AP_W2, _AP_S2> >(*this, a2); +// } +// +// INLINE +// ap_concat_ref<_AP_W, _private_range_ref, _AP_W, ap_private<_AP_W, _AP_S> > +// operator,(ap_private<_AP_W, _AP_S>& a2) { +// return ap_concat_ref<_AP_W, _private_range_ref, _AP_W, +// ap_private<_AP_W, _AP_S> >(*this, a2); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, _private_range_ref, 1, +// _private_bit_ref<_AP_W2, _AP_S2> > +// operator,(const _private_bit_ref<_AP_W2, _AP_S2> &a2) { +// return ap_concat_ref<_AP_W, _private_range_ref, 1, +// _private_bit_ref<_AP_W2, _AP_S2> >( +// *this, const_cast<_private_bit_ref<_AP_W2, _AP_S2>&>(a2)); +// } +// +// template +// INLINE ap_concat_ref<_AP_W, _private_range_ref, _AP_W2 + _AP_W3, +// ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> > +// operator,(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &a2) { +// return ap_concat_ref<_AP_W, _private_range_ref, _AP_W2 + _AP_W3, +// ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >( +// *this, const_cast&>(a2)); +// } +// +// template +// INLINE ap_concat_ref< +// _AP_W, _private_range_ref, _AP_W2, +// af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> > +// operator,( +// const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> &a2) { +// return ap_concat_ref< +// _AP_W, _private_range_ref, _AP_W2, +// af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >( +// *this, +// const_cast< +// af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>&>(a2)); +// } +// +// template +// INLINE +// ap_concat_ref<_AP_W, _private_range_ref, 1, +// af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> > +// operator,(const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> +// &a2) { +// return ap_concat_ref< +// _AP_W, _private_range_ref, 1, +// af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >( +// *this, +// const_cast&>( +// a2)); +// } + + template + INLINE bool operator==(const _private_range_ref<_AP_W2, _AP_S2>& op2) { + ap_private<_AP_W, false> lhs = get(); + ap_private<_AP_W2, false> rhs = op2.get(); + return lhs == rhs; + } + + template + INLINE bool operator!=(const _private_range_ref<_AP_W2, _AP_S2>& op2) { + ap_private<_AP_W, false> lhs = get(); + ap_private<_AP_W2, false> rhs = op2.get(); + return lhs != rhs; + } + + template + INLINE bool operator>(const _private_range_ref<_AP_W2, _AP_S2>& op2) { + ap_private<_AP_W, false> lhs = get(); + ap_private<_AP_W2, false> rhs = op2.get(); + return lhs > rhs; + } + + template + INLINE bool operator>=(const _private_range_ref<_AP_W2, _AP_S2>& op2) { + ap_private<_AP_W, false> lhs = get(); + ap_private<_AP_W2, false> rhs = op2.get(); + return lhs >= rhs; + } + + template + INLINE bool operator<(const _private_range_ref<_AP_W2, _AP_S2>& op2) { + ap_private<_AP_W, false> lhs = get(); + ap_private<_AP_W2, false> rhs = op2.get(); + return lhs < rhs; + } + + template + INLINE bool operator<=(const _private_range_ref<_AP_W2, _AP_S2>& op2) { + ap_private<_AP_W, false> lhs = get(); + ap_private<_AP_W2, false> rhs = op2.get(); + return lhs <= rhs; + } + + template + INLINE void set(const ap_private<_AP_W2, false>& val) { + ap_private<_AP_W, _AP_S> vval = val; + if (l_index > h_index) { + for (int i = 0, j = l_index; j >= 0 && j >= h_index; j--, i++) + (vval)[i] ? d_bv.set(j) : d_bv.clear(j); + } else { + if (_AP_W > 64) { + ap_private<_AP_W, _AP_S> mask(-1); + if (l_index > 0) { + ap_private<_AP_W, false> mask1(-1); + mask1 >>= _AP_W - l_index; + mask1.flip(); + mask = mask1; + // vval&=mask1; + vval <<= l_index; + } + if (h_index < _AP_W - 1) { + ap_private<_AP_W, false> mask2(-1); + mask2 <<= h_index + 1; + mask2.flip(); + mask &= mask2; + vval &= mask2; + } + mask.flip(); + d_bv &= mask; + d_bv |= vval; + } else { + uint64_t mask = ~0ULL >> (64 - _AP_W); + if (l_index > 0) { + uint64_t mask1 = mask; + mask1 = mask & (mask1 >> (_AP_W - l_index)); + vval = mask & (vval << l_index); + mask = ~mask1 & mask; + // vval&=mask1; + } + if (h_index < _AP_W - 1) { + uint64_t mask2 = ~0ULL >> (64 - _AP_W); + mask2 = mask & (mask2 << (h_index + 1)); + mask &= ~mask2; + vval &= ~mask2; + } + d_bv &= (~mask & (~0ULL >> (64 - _AP_W))); + d_bv |= vval; + } + } + } + + INLINE ap_private<_AP_W, false> get() const { + ap_private<_AP_W, false> val(0); + if (h_index < l_index) { + for (int i = 0, j = l_index; j >= 0 && j >= h_index; j--, i++) + if ((d_bv)[j]) val.set(i); + } else { + val = d_bv; + val >>= l_index; + if (h_index < _AP_W - 1) { + if (_AP_W <= 64) { + const static uint64_t mask = + (~0ULL >> (64 > _AP_W ? (64 - _AP_W) : 0)); + val &= (mask >> (_AP_W - (h_index - l_index + 1))); + } else { + ap_private<_AP_W, false> mask(-1); + mask >>= _AP_W - (h_index - l_index + 1); + val &= mask; + } + } + } + return val; + } + + INLINE ap_private<_AP_W, false> get() { + ap_private<_AP_W, false> val(0); + if (h_index < l_index) { + for (int i = 0, j = l_index; j >= 0 && j >= h_index; j--, i++) + if ((d_bv)[j]) val.set(i); + } else { + val = d_bv; + val >>= l_index; + if (h_index < _AP_W - 1) { + if (_AP_W <= 64) { + static const uint64_t mask = ~0ULL >> (64 > _AP_W ? (64 - _AP_W) : 0); + return val &= ((mask) >> (_AP_W - (h_index - l_index + 1))); + } else { + ap_private<_AP_W, false> mask(-1); + mask >>= _AP_W - (h_index - l_index + 1); + val &= mask; + } + } + } + return val; + } + + INLINE int length() const { + return h_index >= l_index ? h_index - l_index + 1 : l_index - h_index + 1; + } + + INLINE int to_int() const { + ap_private<_AP_W, false> val = get(); + return val.to_int(); + } + + INLINE unsigned int to_uint() const { + ap_private<_AP_W, false> val = get(); + return val.to_uint(); + } + + INLINE long to_long() const { + ap_private<_AP_W, false> val = get(); + return val.to_long(); + } + + INLINE unsigned long to_ulong() const { + ap_private<_AP_W, false> val = get(); + return val.to_ulong(); + } + + INLINE ap_slong to_int64() const { + ap_private<_AP_W, false> val = get(); + return val.to_int64(); + } + + INLINE ap_ulong to_uint64() const { + ap_private<_AP_W, false> val = get(); + return val.to_uint64(); + } + + INLINE std::string to_string(uint8_t radix = 2) const { + return get().to_string(radix); + } + + INLINE bool and_reduce() { + bool ret = true; + bool reverse = l_index > h_index; + unsigned low = reverse ? h_index : l_index; + unsigned high = reverse ? l_index : h_index; + for (unsigned i = low; i != high; ++i) ret &= d_bv[i]; + return ret; + } + + INLINE bool or_reduce() { + bool ret = false; + bool reverse = l_index > h_index; + unsigned low = reverse ? h_index : l_index; + unsigned high = reverse ? l_index : h_index; + for (unsigned i = low; i != high; ++i) ret |= d_bv[i]; + return ret; + } + + INLINE bool xor_reduce() { + bool ret = false; + bool reverse = l_index > h_index; + unsigned low = reverse ? h_index : l_index; + unsigned high = reverse ? l_index : h_index; + for (unsigned i = low; i != high; ++i) ret ^= d_bv[i]; + return ret; + } +}; // struct _private_range_ref. + +/// Bit reference +/// Proxy class, which allows bit selection to be used as rvalue(for reading) +/// and lvalue(for writing) +//-------------------------------------------------------------- +template +struct _private_bit_ref { +#ifdef _MSC_VER +#pragma warning(disable : 4521 4522) +#endif + ap_private<_AP_W, _AP_S>& d_bv; + int d_index; + + public: + // copy ctor. + INLINE _private_bit_ref(const _private_bit_ref<_AP_W, _AP_S>& ref) + : d_bv(ref.d_bv), d_index(ref.d_index) {} + + // director ctor. + INLINE _private_bit_ref(ap_private<_AP_W, _AP_S>& bv, int index = 0) + : d_bv(bv), d_index(index) { + _AP_WARNING(d_index < 0, "Index of bit vector (%d) cannot be negative.\n", + d_index); + _AP_WARNING(d_index >= _AP_W, + "Index of bit vector (%d) out of range (%d).\n", d_index, _AP_W); + } + + INLINE operator bool() const { return d_bv.get_bit(d_index); } + + INLINE bool to_bool() const { return operator bool(); } + + template + INLINE _private_bit_ref& operator=(const T& val) { + if (!!val) + d_bv.set(d_index); + else + d_bv.clear(d_index); + return *this; + } + +// template +// INLINE ap_concat_ref<1, _private_bit_ref, _AP_W2, ap_private<_AP_W2, +// _AP_S2> > +// operator,(ap_private<_AP_W2, _AP_S2> &a2) const { +// return ap_concat_ref<1, _private_bit_ref, _AP_W2, ap_private<_AP_W2, +// _AP_S2> >( +// const_cast<_private_bit_ref<_AP_W, _AP_S>&>(*this), a2); +// } +// +// template +// INLINE ap_concat_ref<1, _private_bit_ref, _AP_W2, +// _private_range_ref<_AP_W2, +// _AP_S2> > +// operator,(const _private_range_ref<_AP_W2, _AP_S2> &a2) const { +// return ap_concat_ref<1, _private_bit_ref, _AP_W2, +// _private_range_ref<_AP_W2, +// _AP_S2> >( +// const_cast<_private_bit_ref<_AP_W, _AP_S>&>(*this), +// const_cast<_private_range_ref<_AP_W2, _AP_S2>&>(a2)); +// } +// +// template +// INLINE ap_concat_ref<1, _private_bit_ref, 1, _private_bit_ref<_AP_W2, +// _AP_S2> > operator,( +// const _private_bit_ref<_AP_W2, _AP_S2> &a2) const { +// return ap_concat_ref<1, _private_bit_ref, 1, +// _private_bit_ref<_AP_W2, _AP_S2> >( +// const_cast<_private_bit_ref<_AP_W, _AP_S>&>(*this), +// const_cast<_private_bit_ref<_AP_W2, _AP_S2>&>(a2)); +// } +// +// INLINE ap_concat_ref<1, _private_bit_ref, 1, _private_bit_ref> +// operator,( +// const _private_bit_ref &a2) const { +// return ap_concat_ref<1, _private_bit_ref, 1, _private_bit_ref>( +// const_cast<_private_bit_ref<_AP_W, _AP_S>&>(*this), +// const_cast<_private_bit_ref&>(a2)); +// } +// +// template +// INLINE ap_concat_ref<1, _private_bit_ref, _AP_W2 + _AP_W3, +// ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> > +// operator,(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &a2) const { +// return ap_concat_ref<1, _private_bit_ref, _AP_W2 + _AP_W3, +// ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >( +// const_cast<_private_bit_ref<_AP_W, _AP_S>&>(*this), +// const_cast&>(a2)); +// } +// +// template +// INLINE ap_concat_ref< +// 1, _private_bit_ref, _AP_W2, +// af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> > +// operator,(const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, +// _AP_N2> +// &a2) const { +// return ap_concat_ref< +// 1, _private_bit_ref, _AP_W2, +// af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >( +// const_cast<_private_bit_ref<_AP_W, _AP_S>&>(*this), +// const_cast< +// af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, +// _AP_N2>&>(a2)); +// } +// +// template +// INLINE +// ap_concat_ref<1, _private_bit_ref, 1, +// af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, +// _AP_N2> > +// operator,(const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, +// _AP_N2> +// &a2) const { +// return ap_concat_ref<1, _private_bit_ref, 1, af_bit_ref<_AP_W2, +// _AP_I2, _AP_S2, +// _AP_Q2, _AP_O2, +// _AP_N2> >( +// const_cast<_private_bit_ref<_AP_W, _AP_S>&>(*this), +// const_cast&>( +// a2)); +// } + + template + INLINE bool operator==(const _private_bit_ref<_AP_W2, _AP_S2>& op) const { + return get() == op.get(); + } + + template + INLINE bool operator!=(const _private_bit_ref<_AP_W2, _AP_S2>& op) const { + return get() != op.get(); + } + + INLINE bool get() const { return operator bool(); } + + // template + // INLINE void set(const ap_private<_AP_W3, false>& val) { + // operator=(val); + // } + + // INLINE bool operator~() const { + // bool bit = (d_bv)[d_index]; + // return bit ? false : true; + // } + + INLINE int length() const { return 1; } + + // INLINE std::string to_string() const { + // bool val = get(); + // return val ? "1" : "0"; + // } + +}; // struct _private_bit_ref. + +// char a[100]; +// char* ptr = a; +// ap_int<2> n = 3; +// char* ptr2 = ptr + n*2; +// avoid ambiguous errors +#define OP_BIN_MIX_PTR(BIN_OP) \ + template \ + INLINE PTR_TYPE* operator BIN_OP(PTR_TYPE* i_op, \ + const ap_private<_AP_W, _AP_S>& op) { \ + typename ap_private<_AP_W, _AP_S>::ValType op2 = op; \ + return i_op BIN_OP op2; \ + } \ + template \ + INLINE PTR_TYPE* operator BIN_OP(const ap_private<_AP_W, _AP_S>& op, \ + PTR_TYPE* i_op) { \ + typename ap_private<_AP_W, _AP_S>::ValType op2 = op; \ + return op2 BIN_OP i_op; \ + } + +OP_BIN_MIX_PTR(+) +OP_BIN_MIX_PTR(-) +#undef OP_BIN_MIX_PTR + +// float OP ap_int +// when ap_int's width > 64, then trunc ap_int to ap_int<64> +#define OP_BIN_MIX_FLOAT(BIN_OP, C_TYPE) \ + template \ + INLINE C_TYPE operator BIN_OP(C_TYPE i_op, \ + const ap_private<_AP_W, _AP_S>& op) { \ + typename ap_private<_AP_W, _AP_S>::ValType op2 = op; \ + return i_op BIN_OP op2; \ + } \ + template \ + INLINE C_TYPE operator BIN_OP(const ap_private<_AP_W, _AP_S>& op, \ + C_TYPE i_op) { \ + typename ap_private<_AP_W, _AP_S>::ValType op2 = op; \ + return op2 BIN_OP i_op; \ + } + +#define OPS_MIX_FLOAT(C_TYPE) \ + OP_BIN_MIX_FLOAT(*, C_TYPE) \ + OP_BIN_MIX_FLOAT(/, C_TYPE) \ + OP_BIN_MIX_FLOAT(+, C_TYPE) \ + OP_BIN_MIX_FLOAT(-, C_TYPE) + +OPS_MIX_FLOAT(float) +OPS_MIX_FLOAT(double) +#undef OP_BIN_MIX_FLOAT +#undef OPS_MIX_FLOAT + +/// Operators mixing Integers with AP_Int +// ---------------------------------------------------------------- + +// partially specialize template argument _AP_C in order that: +// for _AP_W > 64, we will explicitly convert operand with native data type +// into corresponding ap_private +// for _AP_W <= 64, we will implicitly convert operand with ap_private into +// (unsigned) long long +#define OP_BIN_MIX_INT(BIN_OP, C_TYPE, _AP_WI, _AP_SI, RTYPE) \ + template \ + INLINE \ + typename ap_private<_AP_WI, _AP_SI>::template RType<_AP_W, _AP_S>::RTYPE \ + operator BIN_OP(C_TYPE i_op, const ap_private<_AP_W, _AP_S>& op) { \ + return ap_private<_AP_WI, _AP_SI>(i_op).operator BIN_OP(op); \ + } \ + template \ + INLINE \ + typename ap_private<_AP_W, _AP_S>::template RType<_AP_WI, _AP_SI>::RTYPE \ + operator BIN_OP(const ap_private<_AP_W, _AP_S>& op, C_TYPE i_op) { \ + return op.operator BIN_OP(ap_private<_AP_WI, _AP_SI>(i_op)); \ + } + +#define OP_REL_MIX_INT(REL_OP, C_TYPE, _AP_W2, _AP_S2) \ + template \ + INLINE bool operator REL_OP(const ap_private<_AP_W, _AP_S>& op, \ + C_TYPE op2) { \ + return op.operator REL_OP(ap_private<_AP_W2, _AP_S2>(op2)); \ + } \ + template \ + INLINE bool operator REL_OP(C_TYPE op2, \ + const ap_private<_AP_W, _AP_S, false>& op) { \ + return ap_private<_AP_W2, _AP_S2>(op2).operator REL_OP(op); \ + } + +#define OP_ASSIGN_MIX_INT(ASSIGN_OP, C_TYPE, _AP_W2, _AP_S2) \ + template \ + INLINE ap_private<_AP_W, _AP_S>& operator ASSIGN_OP( \ + ap_private<_AP_W, _AP_S>& op, C_TYPE op2) { \ + return op.operator ASSIGN_OP(ap_private<_AP_W2, _AP_S2>(op2)); \ + } + +#define OP_BIN_SHIFT_INT(BIN_OP, C_TYPE, _AP_WI, _AP_SI, RTYPE) \ + template \ + C_TYPE operator BIN_OP(C_TYPE i_op, \ + const ap_private<_AP_W, _AP_S, false>& op) { \ + return i_op BIN_OP(op.get_VAL()); \ + } \ + template \ + INLINE \ + typename ap_private<_AP_W, _AP_S>::template RType<_AP_WI, _AP_SI>::RTYPE \ + operator BIN_OP(const ap_private<_AP_W, _AP_S>& op, C_TYPE i_op) { \ + return op.operator BIN_OP(i_op); \ + } + +#define OP_ASSIGN_RSHIFT_INT(ASSIGN_OP, C_TYPE, _AP_W2, _AP_S2) \ + template \ + INLINE ap_private<_AP_W, _AP_S>& operator ASSIGN_OP( \ + ap_private<_AP_W, _AP_S>& op, C_TYPE op2) { \ + op = op.operator>>(op2); \ + return op; \ + } + +#define OP_ASSIGN_LSHIFT_INT(ASSIGN_OP, C_TYPE, _AP_W2, _AP_S2) \ + template \ + INLINE ap_private<_AP_W, _AP_S>& operator ASSIGN_OP( \ + ap_private<_AP_W, _AP_S>& op, C_TYPE op2) { \ + op = op.operator<<(op2); \ + return op; \ + } + +#define OPS_MIX_INT(C_TYPE, _AP_W2, _AP_S2) \ + OP_BIN_MIX_INT(*, C_TYPE, (_AP_W2), (_AP_S2), mult) \ + OP_BIN_MIX_INT(+, C_TYPE, (_AP_W2), (_AP_S2), plus) \ + OP_BIN_MIX_INT(-, C_TYPE, (_AP_W2), (_AP_S2), minus) \ + OP_BIN_MIX_INT(/, C_TYPE, (_AP_W2), (_AP_S2), div) \ + OP_BIN_MIX_INT(%, C_TYPE, (_AP_W2), (_AP_S2), mod) \ + OP_BIN_MIX_INT(&, C_TYPE, (_AP_W2), (_AP_S2), logic) \ + OP_BIN_MIX_INT(|, C_TYPE, (_AP_W2), (_AP_S2), logic) \ + OP_BIN_MIX_INT (^, C_TYPE, (_AP_W2), (_AP_S2), logic) \ + OP_BIN_SHIFT_INT(>>, C_TYPE, (_AP_W2), (_AP_S2), arg1) \ + OP_BIN_SHIFT_INT(<<, C_TYPE, (_AP_W2), (_AP_S2), arg1) \ + \ + OP_ASSIGN_MIX_INT(+=, C_TYPE, (_AP_W2), (_AP_S2)) \ + OP_ASSIGN_MIX_INT(-=, C_TYPE, (_AP_W2), (_AP_S2)) \ + OP_ASSIGN_MIX_INT(*=, C_TYPE, (_AP_W2), (_AP_S2)) \ + OP_ASSIGN_MIX_INT(/=, C_TYPE, (_AP_W2), (_AP_S2)) \ + OP_ASSIGN_MIX_INT(%=, C_TYPE, (_AP_W2), (_AP_S2)) \ + OP_ASSIGN_MIX_INT(&=, C_TYPE, (_AP_W2), (_AP_S2)) \ + OP_ASSIGN_MIX_INT(|=, C_TYPE, (_AP_W2), (_AP_S2)) \ + OP_ASSIGN_MIX_INT(^=, C_TYPE, (_AP_W2), (_AP_S2)) \ + OP_ASSIGN_RSHIFT_INT(>>=, C_TYPE, (_AP_W2), (_AP_S2)) \ + OP_ASSIGN_LSHIFT_INT(<<=, C_TYPE, (_AP_W2), (_AP_S2)) \ + \ + OP_REL_MIX_INT(>, C_TYPE, (_AP_W2), (_AP_S2)) \ + OP_REL_MIX_INT(<, C_TYPE, (_AP_W2), (_AP_S2)) \ + OP_REL_MIX_INT(>=, C_TYPE, (_AP_W2), (_AP_S2)) \ + OP_REL_MIX_INT(<=, C_TYPE, (_AP_W2), (_AP_S2)) \ + OP_REL_MIX_INT(==, C_TYPE, (_AP_W2), (_AP_S2)) \ + OP_REL_MIX_INT(!=, C_TYPE, (_AP_W2), (_AP_S2)) + +OPS_MIX_INT(bool, 1, false) +OPS_MIX_INT(char, 8, CHAR_IS_SIGNED) +OPS_MIX_INT(signed char, 8, true) +OPS_MIX_INT(unsigned char, 8, false) +OPS_MIX_INT(short, sizeof(short) * 8, true) +OPS_MIX_INT(unsigned short, sizeof(unsigned short) * 8, false) +OPS_MIX_INT(int, sizeof(int) * 8, true) +OPS_MIX_INT(unsigned int, sizeof(unsigned int) * 8, false) +OPS_MIX_INT(long, sizeof(long) * 8, true) +OPS_MIX_INT(unsigned long, sizeof(unsigned long) * 8, false) +OPS_MIX_INT(ap_slong, sizeof(ap_slong) * 8, true) +OPS_MIX_INT(ap_ulong, sizeof(ap_ulong) * 8, false) + +#undef OP_BIN_MIX_INT +#undef OP_BIN_SHIFT_INT +#undef OP_ASSIGN_MIX_INT +#undef OP_ASSIGN_RSHIFT_INT +#undef OP_ASSIGN_LSHIFT_INT +#undef OP_REL_MIX_INT +#undef OPS_MIX_INT + +#define OP_BIN_MIX_RANGE(BIN_OP, RTYPE) \ + template \ + INLINE typename ap_private<_AP_W1, _AP_S1>::template RType<_AP_W2, \ + _AP_S2>::RTYPE \ + operator BIN_OP(const _private_range_ref<_AP_W1, _AP_S1>& op1, \ + const ap_private<_AP_W2, _AP_S2>& op2) { \ + return ap_private<_AP_W1, false>(op1).operator BIN_OP(op2); \ + } \ + template \ + INLINE typename ap_private<_AP_W1, _AP_S1>::template RType<_AP_W2, \ + _AP_S2>::RTYPE \ + operator BIN_OP(const ap_private<_AP_W1, _AP_S1>& op1, \ + const _private_range_ref<_AP_W2, _AP_S2>& op2) { \ + return op1.operator BIN_OP(ap_private<_AP_W2, false>(op2)); \ + } + +#define OP_ASSIGN_MIX_RANGE(ASSIGN_OP) \ + template \ + INLINE ap_private<_AP_W1, _AP_S1>& operator ASSIGN_OP( \ + ap_private<_AP_W1, _AP_S1>& op1, \ + const _private_range_ref<_AP_W2, _AP_S2>& op2) { \ + return op1.operator ASSIGN_OP(ap_private<_AP_W2, false>(op2)); \ + } \ + template \ + INLINE _private_range_ref<_AP_W1, _AP_S1>& operator ASSIGN_OP( \ + _private_range_ref<_AP_W1, _AP_S1>& op1, \ + ap_private<_AP_W2, _AP_S2>& op2) { \ + ap_private<_AP_W1, false> tmp(op1); \ + tmp.operator ASSIGN_OP(op2); \ + op1 = tmp; \ + return op1; \ + } + +#define OP_REL_MIX_RANGE(REL_OP) \ + template \ + INLINE bool operator REL_OP(const _private_range_ref<_AP_W1, _AP_S1>& op1, \ + const ap_private<_AP_W2, _AP_S2>& op2) { \ + return ap_private<_AP_W1, false>(op1).operator REL_OP(op2); \ + } \ + template \ + INLINE bool operator REL_OP(const ap_private<_AP_W1, _AP_S1>& op1, \ + const _private_range_ref<_AP_W2, _AP_S2>& op2) { \ + return op1.operator REL_OP(op2.operator ap_private<_AP_W2, false>()); \ + } + +OP_BIN_MIX_RANGE(+, plus) +OP_BIN_MIX_RANGE(-, minus) +OP_BIN_MIX_RANGE(*, mult) +OP_BIN_MIX_RANGE(/, div) +OP_BIN_MIX_RANGE(%, mod) +OP_BIN_MIX_RANGE(&, logic) +OP_BIN_MIX_RANGE(|, logic) +OP_BIN_MIX_RANGE(^, logic) +OP_BIN_MIX_RANGE(>>, arg1) +OP_BIN_MIX_RANGE(<<, arg1) +#undef OP_BIN_MIX_RANGE + +OP_ASSIGN_MIX_RANGE(+=) +OP_ASSIGN_MIX_RANGE(-=) +OP_ASSIGN_MIX_RANGE(*=) +OP_ASSIGN_MIX_RANGE(/=) +OP_ASSIGN_MIX_RANGE(%=) +OP_ASSIGN_MIX_RANGE(&=) +OP_ASSIGN_MIX_RANGE(|=) +OP_ASSIGN_MIX_RANGE(^=) +OP_ASSIGN_MIX_RANGE(>>=) +OP_ASSIGN_MIX_RANGE(<<=) +#undef OP_ASSIGN_MIX_RANGE + +OP_REL_MIX_RANGE(>) +OP_REL_MIX_RANGE(<) +OP_REL_MIX_RANGE(>=) +OP_REL_MIX_RANGE(<=) +OP_REL_MIX_RANGE(==) +OP_REL_MIX_RANGE(!=) +#undef OP_REL_MIX_RANGE + +#define OP_BIN_MIX_BIT(BIN_OP, RTYPE) \ + template \ + INLINE typename ap_private<1, false>::template RType<_AP_W2, _AP_S2>::RTYPE \ + operator BIN_OP(const _private_bit_ref<_AP_W1, _AP_S1>& op1, \ + const ap_private<_AP_W2, _AP_S2>& op2) { \ + return ap_private<1, false>(op1).operator BIN_OP(op2); \ + } \ + template \ + INLINE typename ap_private<_AP_W1, _AP_S1>::template RType<1, false>::RTYPE \ + operator BIN_OP(const ap_private<_AP_W1, _AP_S1>& op1, \ + const _private_bit_ref<_AP_W2, _AP_S2>& op2) { \ + return op1.operator BIN_OP(ap_private<1, false>(op2)); \ + } + +#define OP_ASSIGN_MIX_BIT(ASSIGN_OP) \ + template \ + INLINE ap_private<_AP_W1, _AP_S1>& operator ASSIGN_OP( \ + ap_private<_AP_W1, _AP_S1>& op1, \ + _private_bit_ref<_AP_W2, _AP_S2>& op2) { \ + return op1.operator ASSIGN_OP(ap_private<1, false>(op2)); \ + } \ + template \ + INLINE _private_bit_ref<_AP_W1, _AP_S1>& operator ASSIGN_OP( \ + _private_bit_ref<_AP_W1, _AP_S1>& op1, \ + ap_private<_AP_W2, _AP_S2>& op2) { \ + ap_private<1, false> tmp(op1); \ + tmp.operator ASSIGN_OP(op2); \ + op1 = tmp; \ + return op1; \ + } + +#define OP_REL_MIX_BIT(REL_OP) \ + template \ + INLINE bool operator REL_OP(const _private_bit_ref<_AP_W1, _AP_S1>& op1, \ + const ap_private<_AP_W2, _AP_S2>& op2) { \ + return ap_private<_AP_W1, false>(op1).operator REL_OP(op2); \ + } \ + template \ + INLINE bool operator REL_OP(const ap_private<_AP_W1, _AP_S1>& op1, \ + const _private_bit_ref<_AP_W2, _AP_S2>& op2) { \ + return op1.operator REL_OP(ap_private<1, false>(op2)); \ + } + +OP_ASSIGN_MIX_BIT(+=) +OP_ASSIGN_MIX_BIT(-=) +OP_ASSIGN_MIX_BIT(*=) +OP_ASSIGN_MIX_BIT(/=) +OP_ASSIGN_MIX_BIT(%=) +OP_ASSIGN_MIX_BIT(&=) +OP_ASSIGN_MIX_BIT(|=) +OP_ASSIGN_MIX_BIT(^=) +OP_ASSIGN_MIX_BIT(>>=) +OP_ASSIGN_MIX_BIT(<<=) +#undef OP_ASSIGN_MIX_BIT + +OP_BIN_MIX_BIT(+, plus) +OP_BIN_MIX_BIT(-, minus) +OP_BIN_MIX_BIT(*, mult) +OP_BIN_MIX_BIT(/, div) +OP_BIN_MIX_BIT(%, mod) +OP_BIN_MIX_BIT(&, logic) +OP_BIN_MIX_BIT(|, logic) +OP_BIN_MIX_BIT(^, logic) +OP_BIN_MIX_BIT(>>, arg1) +OP_BIN_MIX_BIT(<<, arg1) +#undef OP_BIN_MIX_BIT + +OP_REL_MIX_BIT(>) +OP_REL_MIX_BIT(<) +OP_REL_MIX_BIT(<=) +OP_REL_MIX_BIT(>=) +OP_REL_MIX_BIT(==) +OP_REL_MIX_BIT(!=) +#undef OP_REL_MIX_BIT + +#define REF_REL_OP_MIX_INT(REL_OP, C_TYPE, _AP_W2, _AP_S2) \ + template \ + INLINE bool operator REL_OP(const _private_range_ref<_AP_W, _AP_S>& op, \ + C_TYPE op2) { \ + return (ap_private<_AP_W, false>(op)) \ + . \ + operator REL_OP(ap_private<_AP_W2, _AP_S2>(op2)); \ + } \ + template \ + INLINE bool operator REL_OP(C_TYPE op2, \ + const _private_range_ref<_AP_W, _AP_S>& op) { \ + return ap_private<_AP_W2, _AP_S2>(op2).operator REL_OP( \ + ap_private<_AP_W, false>(op)); \ + } \ + template \ + INLINE bool operator REL_OP(const _private_bit_ref<_AP_W, _AP_S>& op, \ + C_TYPE op2) { \ + return (bool(op))REL_OP op2; \ + } \ + template \ + INLINE bool operator REL_OP(C_TYPE op2, \ + const _private_bit_ref<_AP_W, _AP_S>& op) { \ + return op2 REL_OP(bool(op)); \ + } + +#define REF_REL_MIX_INT(C_TYPE, _AP_W2, _AP_S2) \ + REF_REL_OP_MIX_INT(>, C_TYPE, (_AP_W2), (_AP_S2)) \ + REF_REL_OP_MIX_INT(<, C_TYPE, (_AP_W2), (_AP_S2)) \ + REF_REL_OP_MIX_INT(>=, C_TYPE, (_AP_W2), (_AP_S2)) \ + REF_REL_OP_MIX_INT(<=, C_TYPE, (_AP_W2), (_AP_S2)) \ + REF_REL_OP_MIX_INT(==, C_TYPE, (_AP_W2), (_AP_S2)) \ + REF_REL_OP_MIX_INT(!=, C_TYPE, (_AP_W2), (_AP_S2)) + +REF_REL_MIX_INT(bool, 1, false) +REF_REL_MIX_INT(char, 8, CHAR_IS_SIGNED) +REF_REL_MIX_INT(signed char, 8, true) +REF_REL_MIX_INT(unsigned char, 8, false) +REF_REL_MIX_INT(short, sizeof(short) * 8, true) +REF_REL_MIX_INT(unsigned short, sizeof(unsigned short) * 8, false) +REF_REL_MIX_INT(int, sizeof(int) * 8, true) +REF_REL_MIX_INT(unsigned int, sizeof(unsigned int) * 8, false) +REF_REL_MIX_INT(long, sizeof(long) * 8, true) +REF_REL_MIX_INT(unsigned long, sizeof(unsigned long) * 8, false) +REF_REL_MIX_INT(ap_slong, sizeof(ap_slong) * 8, true) +REF_REL_MIX_INT(ap_ulong, sizeof(ap_ulong) * 8, false) +#undef REF_REL_OP_MIX_INT +#undef REF_REL_MIX_INT + +#define REF_BIN_OP_MIX_INT(BIN_OP, RTYPE, C_TYPE, _AP_W2, _AP_S2) \ + template \ + INLINE \ + typename ap_private<_AP_W, false>::template RType<_AP_W2, _AP_S2>::RTYPE \ + operator BIN_OP(const _private_range_ref<_AP_W, _AP_S>& op, \ + C_TYPE op2) { \ + return (ap_private<_AP_W, false>(op)) \ + . \ + operator BIN_OP(ap_private<_AP_W2, _AP_S2>(op2)); \ + } \ + template \ + INLINE \ + typename ap_private<_AP_W2, _AP_S2>::template RType<_AP_W, false>::RTYPE \ + operator BIN_OP(C_TYPE op2, \ + const _private_range_ref<_AP_W, _AP_S>& op) { \ + return ap_private<_AP_W2, _AP_S2>(op2).operator BIN_OP( \ + ap_private<_AP_W, false>(op)); \ + } + +#define REF_BIN_MIX_INT(C_TYPE, _AP_W2, _AP_S2) \ + REF_BIN_OP_MIX_INT(+, plus, C_TYPE, (_AP_W2), (_AP_S2)) \ + REF_BIN_OP_MIX_INT(-, minus, C_TYPE, (_AP_W2), (_AP_S2)) \ + REF_BIN_OP_MIX_INT(*, mult, C_TYPE, (_AP_W2), (_AP_S2)) \ + REF_BIN_OP_MIX_INT(/, div, C_TYPE, (_AP_W2), (_AP_S2)) \ + REF_BIN_OP_MIX_INT(%, mod, C_TYPE, (_AP_W2), (_AP_S2)) \ + REF_BIN_OP_MIX_INT(&, logic, C_TYPE, (_AP_W2), (_AP_S2)) \ + REF_BIN_OP_MIX_INT(|, logic, C_TYPE, (_AP_W2), (_AP_S2)) \ + REF_BIN_OP_MIX_INT(^, logic, C_TYPE, (_AP_W2), (_AP_S2)) \ + REF_BIN_OP_MIX_INT(>>, arg1, C_TYPE, (_AP_W2), (_AP_S2)) \ + REF_BIN_OP_MIX_INT(<<, arg1, C_TYPE, (_AP_W2), (_AP_S2)) + +REF_BIN_MIX_INT(bool, 1, false) +REF_BIN_MIX_INT(char, 8, CHAR_IS_SIGNED) +REF_BIN_MIX_INT(signed char, 8, true) +REF_BIN_MIX_INT(unsigned char, 8, false) +REF_BIN_MIX_INT(short, sizeof(short) * 8, true) +REF_BIN_MIX_INT(unsigned short, sizeof(unsigned short) * 8, false) +REF_BIN_MIX_INT(int, sizeof(int) * 8, true) +REF_BIN_MIX_INT(unsigned int, sizeof(unsigned int) * 8, false) +REF_BIN_MIX_INT(long, sizeof(long) * 8, true) +REF_BIN_MIX_INT(unsigned long, sizeof(unsigned long) * 8, false) +REF_BIN_MIX_INT(ap_slong, sizeof(ap_slong) * 8, true) +REF_BIN_MIX_INT(ap_ulong, sizeof(ap_ulong) * 8, false) +#undef REF_BIN_OP_MIX_INT +#undef REF_BIN_MIX_INT + +#define REF_BIN_OP(BIN_OP, RTYPE) \ + template \ + INLINE \ + typename ap_private<_AP_W, false>::template RType<_AP_W2, false>::RTYPE \ + operator BIN_OP(const _private_range_ref<_AP_W, _AP_S>& lhs, \ + const _private_range_ref<_AP_W2, _AP_S2>& rhs) { \ + return ap_private<_AP_W, false>(lhs).operator BIN_OP( \ + ap_private<_AP_W2, false>(rhs)); \ + } + +REF_BIN_OP(+, plus) +REF_BIN_OP(-, minus) +REF_BIN_OP(*, mult) +REF_BIN_OP(/, div) +REF_BIN_OP(%, mod) +REF_BIN_OP(&, logic) +REF_BIN_OP(|, logic) +REF_BIN_OP(^, logic) +REF_BIN_OP(>>, arg1) +REF_BIN_OP(<<, arg1) +#undef REF_BIN_OP + +//************************************************************************ +// Implement +// ap_private = ap_concat_ref OP ap_concat_ref +// for operators +, -, *, /, %, >>, <<, &, |, ^ +// Without these operators the operands are converted to int64 and +// larger results lose informations (higher order bits). +// +// operand OP +// / | +// left-concat right-concat +// / | / | +// +// +// _AP_LW1, _AP_LT1 (width and type of left-concat's left side) +// _AP_LW2, _AP_LT2 (width and type of left-concat's right side) +// Similarly for RHS of operand OP: _AP_RW1, AP_RW2, _AP_RT1, _AP_RT2 +// +// In Verilog 2001 result of concatenation is always unsigned even +// when both sides are signed. +//************************************************************************ + +#endif // ifndef __AP_PRIVATE_H__ + +// -*- cpp -*- diff --git a/firmware/ap_types/hls_math.h b/firmware/ap_types/hls_math.h new file mode 100644 index 0000000000000000000000000000000000000000..f12997141cbb482cc691941097fee4248b96afa0 --- /dev/null +++ b/firmware/ap_types/hls_math.h @@ -0,0 +1,27 @@ +#ifndef X_HLS_MATH_H +#define X_HLS_MATH_H + +#include +#include "ap_fixed.h" + +namespace hls { + +template +static T exp(const T x) { + return (T) std::exp(x.to_double()); +} + +template T sin(T x) { return (T) std::sin(x.to_double()); }; + +template T cos(T x) { return (T) std::cos(x.to_double()); }; + +template T asin(T x) { return (T) std::asin(x.to_double()); }; + +template T acos(T x) { return (T) std::acos(x.to_double()); }; + +template T atan(T x) { return (T) std::atan(x.to_double()); }; + +template T atan2(T x, T y) { return (T) hls::atan2(x.to_double(), y.to_double()); }; + +} +#endif diff --git a/firmware/ap_types/hls_stream.h b/firmware/ap_types/hls_stream.h new file mode 100644 index 0000000000000000000000000000000000000000..f516c39e082a7b06a9f955de62438a1a317f7147 --- /dev/null +++ b/firmware/ap_types/hls_stream.h @@ -0,0 +1,263 @@ +/* +#- (c) Copyright 2011-2018 Xilinx, Inc. All rights reserved. +#- +#- This file contains confidential and proprietary information +#- of Xilinx, Inc. and is protected under U.S. and +#- international copyright and other intellectual property +#- laws. +#- +#- DISCLAIMER +#- This disclaimer is not a license and does not grant any +#- rights to the materials distributed herewith. Except as +#- otherwise provided in a valid license issued to you by +#- Xilinx, and to the maximum extent permitted by applicable +#- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +#- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +#- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +#- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +#- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +#- (2) Xilinx shall not be liable (whether in contract or tort, +#- including negligence, or under any other theory of +#- liability) for any loss or damage of any kind or nature +#- related to, arising under or in connection with these +#- materials, including for any direct, or any indirect, +#- special, incidental, or consequential loss or damage +#- (including loss of data, profits, goodwill, or any type of +#- loss or damage suffered as a result of any action brought +#- by a third party) even if such damage or loss was +#- reasonably foreseeable or Xilinx had been advised of the +#- possibility of the same. +#- +#- CRITICAL APPLICATIONS +#- Xilinx products are not designed or intended to be fail- +#- safe, or for use in any application requiring fail-safe +#- performance, such as life-support or safety devices or +#- systems, Class III medical devices, nuclear facilities, +#- applications related to the deployment of airbags, or any +#- other applications that could lead to death, personal +#- injury, or severe property or environmental damage +#- (individually and collectively, "Critical +#- Applications"). Customer assumes the sole risk and +#- liability of any use of Xilinx products in Critical +#- Applications, subject only to applicable laws and +#- regulations governing limitations on product liability. +#- +#- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +#- PART OF THIS FILE AT ALL TIMES. +#- ************************************************************************ + + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef X_HLS_STREAM_SIM_H +#define X_HLS_STREAM_SIM_H + +/* + * This file contains a C++ model of hls::stream. + * It defines C simulation model. + */ +#ifndef __cplusplus + +#error C++ is required to include this header file + +#else + +////////////////////////////////////////////// +// C level simulation models for hls::stream +////////////////////////////////////////////// +#include +#include +#include +#include +#include + +#ifdef HLS_STREAM_THREAD_SAFE +#include +#include +#endif + +#ifndef _MSC_VER +#include +#include +#endif + +namespace hls { + +template +class stream +{ + protected: + std::string _name; + std::deque<__STREAM_T__> _data; // container for the elements +#ifdef HLS_STREAM_THREAD_SAFE + std::mutex _mutex; + std::condition_variable _condition_var; +#endif + + public: + /// Constructors + // Keep consistent with the synthesis model's constructors + stream() { + static unsigned _counter = 1; + std::stringstream ss; +#ifndef _MSC_VER + char* _demangle_name = abi::__cxa_demangle(typeid(*this).name(), 0, 0, 0); + if (_demangle_name) { + _name = _demangle_name; + free(_demangle_name); + } + else { + _name = "hls_stream"; + } +#else + _name = typeid(*this).name(); +#endif + + ss << _counter++; + _name += "." + ss.str(); + } + + stream(const std::string name) { + // default constructor, + // capacity set to predefined maximum + _name = name; + } + + /// Make copy constructor and assignment operator private + private: + stream(const stream< __STREAM_T__ >& chn): + _name(chn._name), _data(chn._data) { + } + + stream& operator = (const stream< __STREAM_T__ >& chn) { + _name = chn._name; + _data = chn._data; + return *this; + } + + public: + /// Overload >> and << operators to implement read() and write() + void operator >> (__STREAM_T__& rdata) { + read(rdata); + } + + void operator << (const __STREAM_T__& wdata) { + write(wdata); + } + + + public: + /// Destructor + /// Check status of the queue + virtual ~stream() { + if (!_data.empty()) + { + std::cout << "WARNING: Hls::stream '" + << _name + << "' contains leftover data," + << " which may result in RTL simulation hanging." + << std::endl; + } + } + + /// Status of the queue + bool empty() { +#ifdef HLS_STREAM_THREAD_SAFE + std::lock_guard lg(_mutex); +#endif + return _data.empty(); + } + + bool full() const { return false; } + + /// Blocking read + void read(__STREAM_T__& head) { + head = read(); + } + +#ifdef HLS_STREAM_THREAD_SAFE + __STREAM_T__ read() { + std::unique_lock ul(_mutex); + while (_data.empty()) { + _condition_var.wait(ul); + } + + __STREAM_T__ elem; + elem = _data.front(); + _data.pop_front(); + return elem; + } +#else + __STREAM_T__ read() { + __STREAM_T__ elem; + if (_data.empty()) { + std::cout << "WARNING: Hls::stream '" + << _name + << "' is read while empty," + << " which may result in RTL simulation hanging." + << std::endl; + elem = __STREAM_T__(); + } else { + elem = _data.front(); + _data.pop_front(); + } + return elem; + } +#endif + + /// Blocking write + void write(const __STREAM_T__& tail) { +#ifdef HLS_STREAM_THREAD_SAFE + std::unique_lock ul(_mutex); +#endif + _data.push_back(tail); +#ifdef HLS_STREAM_THREAD_SAFE + _condition_var.notify_one(); +#endif + } + + /// Nonblocking read + bool read_nb(__STREAM_T__& head) { +#ifdef HLS_STREAM_THREAD_SAFE + std::lock_guard lg(_mutex); +#endif + bool is_empty = _data.empty(); + if (is_empty) { + head = __STREAM_T__(); + } else { + __STREAM_T__ elem(_data.front()); + _data.pop_front(); + head = elem; + } + return !is_empty; + } + + /// Nonblocking write + bool write_nb(const __STREAM_T__& tail) { + bool is_full = full(); + write(tail); + return !is_full; + } + + /// Fifo size + size_t size() { + return _data.size(); + } +}; + +} // namespace hls + +#endif // __cplusplus +#endif // X_HLS_STREAM_SIM_H + diff --git a/firmware/ap_types/utils/x_hls_utils.h b/firmware/ap_types/utils/x_hls_utils.h new file mode 100644 index 0000000000000000000000000000000000000000..3e751c36bf334f13f28ad1fa23ca361beeea2349 --- /dev/null +++ b/firmware/ap_types/utils/x_hls_utils.h @@ -0,0 +1,80 @@ +#ifndef X_HLS_UTILS_H +#define X_HLS_UTILS_H +#include "ap_fixed.h" +#include + +namespace hls { + + template + class numeric_limits { + public: + static T max() { return std::numeric_limits::max(); } + static T min() { return std::numeric_limits::min(); } + static T epsilon() { return std::numeric_limits::epsilon(); } + }; + + template + class numeric_limits > { + public: + static ap_fixed max() { + ap_int m = ::hls::numeric_limits >::max(); + ap_fixed x; + x(W-1,0) = m(W-1,0); + return x; + } + static ap_fixed min() { + ap_int m = ::hls::numeric_limits >::min(); + ap_fixed x; + x(W-1,0) = m(W-1,0); + return x; + } + static ap_fixed epsilon() { + ap_fixed x = 0; + x[0] = 1; + return x; + } + }; + + template + class numeric_limits > { + public: + static ap_ufixed max() { + ap_uint m = ::hls::numeric_limits >::max(); + ap_ufixed x; + x(W-1,0) = m(W-1,0); + return x; + } + static ap_ufixed min() { return 0; } + static ap_ufixed epsilon() { + ap_ufixed x = 0; + x[0] = 1; + return x; + } + }; + + template + class numeric_limits > { + public: + static ap_int max() { ap_int m = min(); return ~m; } + static ap_int min() { ap_int m = 0; m[W-1] = 1; return m; } + static ap_int epsilon() { + ap_int x = 0; + x[0] = 1; + return x; + } + }; + + template + class numeric_limits > { + public: + static ap_uint max() { ap_uint zero = 0; return ~zero; } + static ap_uint min() { return 0; } + static ap_uint epsilon() { + ap_uint x = 0; + x[0] = 1; + return x; + } + }; +} + +#endif diff --git a/firmware/nnet_utils/nnet_code_gen.h b/firmware/nnet_utils/nnet_code_gen.h new file mode 100644 index 0000000000000000000000000000000000000000..6011e20cca617f4a8df4343f34dfd535b735b9ab --- /dev/null +++ b/firmware/nnet_utils/nnet_code_gen.h @@ -0,0 +1,28 @@ +#ifndef NNET_INSTR_GEN_H_ +#define NNET_INSTR_GEN_H_ + +#include "nnet_conv1d_latency.h" +#include "nnet_helpers.h" + +#include "hls_stream.h" +#include "nnet_common.h" +#include "nnet_function_stubs.h" +#include "nnet_mult.h" + +namespace nnet { + +template class PointwiseConv1D { + public: + static void pointwise_conv(data_T data[CONFIG_T::in_width * CONFIG_T::n_chan], + res_T res[CONFIG_T::out_width * CONFIG_T::n_filt], + typename CONFIG_T::weight_t weights[CONFIG_T::n_chan * CONFIG_T::n_filt], + typename CONFIG_T::bias_t biases[CONFIG_T::n_filt]) { + // To be implemented in subclasses + } +}; + +// hls4ml insert code + +} // namespace nnet + +#endif diff --git a/firmware/nnet_utils/nnet_conv1d_stream.h b/firmware/nnet_utils/nnet_conv1d_stream.h new file mode 100644 index 0000000000000000000000000000000000000000..1156dde9220e12bb374fd6f2b3bad008ca2cb7a0 --- /dev/null +++ b/firmware/nnet_utils/nnet_conv1d_stream.h @@ -0,0 +1,37 @@ +#ifndef NNET_CONV1D_STREAM_H_ +#define NNET_CONV1D_STREAM_H_ + +#include "hls_stream.h" +#include "nnet_common.h" +#include "nnet_conv_stream.h" +#include + +namespace nnet { + +template +void conv_1d_cl(hls::stream &data, hls::stream &res, + typename CONFIG_T::weight_t weights[CONFIG_T::filt_width * CONFIG_T::n_chan * CONFIG_T::n_filt], + typename CONFIG_T::bias_t biases[CONFIG_T::n_filt]) { + assert(CONFIG_T::implementation == conv_implementation::linebuffer && + "Only \"linebuffer\" implementation is supported in Vitis HLS."); + + assert(CONFIG_T::pad_left == 0 && CONFIG_T::pad_right == 0); + + if (CONFIG_T::strategy == nnet::latency || CONFIG_T::strategy == nnet::distributed_arithmetic) { + ReadInputWidth: + for (unsigned i_iw = 0; i_iw < CONFIG_T::in_width; i_iw++) { + #pragma HLS PIPELINE II=CONFIG_T::reuse_factor + compute_output_buffer_1d(data.read(), res, weights, biases); + } + } else if (CONFIG_T::strategy == nnet::resource || CONFIG_T::strategy == nnet::resource_unrolled) { + ReadInputWidthSerial: + for (unsigned i_iw = 0; i_iw < CONFIG_T::in_width; i_iw++) { + compute_output_buffer_1d(data.read(), res, weights, biases); + } + } else { + assert(false && "Unsupported strategy for conv_1d_cl"); + } +} + +} // namespace nnet +#endif diff --git a/firmware/nnet_utils/nnet_conv2d_latency.h b/firmware/nnet_utils/nnet_conv2d_latency.h new file mode 100644 index 0000000000000000000000000000000000000000..c286e86f07281754997a02a8d92204fff8c07b09 --- /dev/null +++ b/firmware/nnet_utils/nnet_conv2d_latency.h @@ -0,0 +1,90 @@ +#ifndef NNET_CONV2D_LATENCY_H_ +#define NNET_CONV2D_LATENCY_H_ + +#include "nnet_common.h" +#include "nnet_mult.h" +#include + +namespace nnet { + +template +void conv_2d_latency_cl( + data_T data[CONFIG_T::in_height * CONFIG_T::in_width * CONFIG_T::n_chan], + res_T res[CONFIG_T::out_height * CONFIG_T::out_width * CONFIG_T::n_filt], + typename CONFIG_T::weight_t weights[CONFIG_T::filt_height * CONFIG_T::filt_width * CONFIG_T::n_chan * CONFIG_T::n_filt], + typename CONFIG_T::bias_t biases[CONFIG_T::n_filt]) { + constexpr unsigned mult_n_in = CONFIG_T::filt_height * CONFIG_T::filt_width * CONFIG_T::n_chan; + constexpr unsigned mult_n_out = CONFIG_T::n_filt; + + data_T data_buf[CONFIG_T::n_pixels][mult_n_in]; + #pragma HLS ARRAY_PARTITION variable=data_buf complete dim=0 + + typename CONFIG_T::accum_t mult[mult_n_in * mult_n_out]; + #pragma HLS ARRAY_PARTITION variable=mult complete + + typename CONFIG_T::accum_t acc[mult_n_out]; + #pragma HLS ARRAY_PARTITION variable=acc complete + + #pragma HLS ARRAY_PARTITION variable=weights complete + #pragma HLS ARRAY_PARTITION variable=biases complete + + // Limit multipliers to control parallelization + #pragma HLS ALLOCATION operation instances=mul limit=CONFIG_T::mult_config::multiplier_limit + +PartitionLoop: + for (int i_part = 0; i_part < CONFIG_T::n_partitions; i_part++) { + #pragma HLS PIPELINE II=CONFIG_T::reuse_factor rewind + + CONFIG_T::template fill_buffer::fill_buffer(data, data_buf, i_part); + + PixelLoop: + for (unsigned i_pxl = 0; i_pxl < CONFIG_T::n_pixels; i_pxl++) { + #pragma HLS UNROLL + + data_T cache; + + // Do the matrix-multiply + Product1: + for (int i_in = 0; i_in < mult_n_in; i_in++) { + #pragma HLS UNROLL + cache = data_buf[i_pxl][i_in]; + Product2: + for (int i_out = 0; i_out < mult_n_out; i_out++) { + #pragma HLS UNROLL + mult[i_in * mult_n_out + i_out] = + CONFIG_T::mult_config::template product::product( + cache, weights[i_in * mult_n_out + i_out]); + } + } + + // Initialize accumulator with input biases + ResetAccum: + for (int i_acc = 0; i_acc < mult_n_out; i_acc++) { + #pragma HLS UNROLL + acc[i_acc] = (typename CONFIG_T::accum_t)biases[i_acc]; + } + + // Accumulate multiplication result + Accum1: + for (int i_in = 0; i_in < mult_n_in; i_in++) { + #pragma HLS UNROLL + Accum2: + for (int i_out = 0; i_out < mult_n_out; i_out++) { + #pragma HLS UNROLL + acc[i_out] += mult[i_in * mult_n_out + i_out]; + } + } + + // Cast to "res_t" type + Result: + for (int i_res = 0; i_res < mult_n_out; i_res++) { + #pragma HLS UNROLL + res[i_part * CONFIG_T::n_pixels * mult_n_out + i_pxl * mult_n_out + i_res] = + cast(acc[i_res]); + } + } + } +} + +} // namespace nnet +#endif diff --git a/firmware/nnet_utils/nnet_conv2d_resource.h b/firmware/nnet_utils/nnet_conv2d_resource.h new file mode 100644 index 0000000000000000000000000000000000000000..e427bd708dc3f7c34a631163c1b4302ee9ac8782 --- /dev/null +++ b/firmware/nnet_utils/nnet_conv2d_resource.h @@ -0,0 +1,108 @@ +#ifndef NNET_CONV2D_RESOURCE_H_ +#define NNET_CONV2D_RESOURCE_H_ + +#include "nnet_common.h" +#include "nnet_dense.h" + +namespace nnet { + +template +void conv_2d_resource_cl( + data_T data[CONFIG_T::in_height * CONFIG_T::in_width * CONFIG_T::n_chan], + res_T res[CONFIG_T::out_height * CONFIG_T::out_width * CONFIG_T::n_filt], + typename CONFIG_T::weight_t weights[CONFIG_T::filt_height * CONFIG_T::filt_width * CONFIG_T::n_chan * CONFIG_T::n_filt], + typename CONFIG_T::bias_t biases[CONFIG_T::n_filt]) { + constexpr unsigned mult_n_in = CONFIG_T::filt_height * CONFIG_T::filt_width * CONFIG_T::n_chan; + constexpr unsigned mult_n_out = CONFIG_T::n_filt; + constexpr unsigned block_factor = DIV_ROUNDUP(mult_n_in * mult_n_out, CONFIG_T::reuse_factor); + + constexpr unsigned multiplier_limit = DIV_ROUNDUP(mult_n_in * mult_n_out, CONFIG_T::reuse_factor); + constexpr unsigned multscale = multiplier_limit / mult_n_out; + + assert((multiplier_limit % mult_n_out == 0 || CONFIG_T::reuse_factor >= mult_n_in) && + "The current Reuse Factor is not allowed"); + assert((multiplier_limit == block_factor) && + "This function is correct only for RF <= FILT_HEIGHT * FILT_WIDTH * N_CHAN"); + + // Treating weights as 2d is required to make sure Vitis doesn't use urem cores to calculate indices. + // Also, we don't apply ARRAY_RESHAPE pragma as Vitis figures this out on its own. + typename CONFIG_T::weight_t(*weights_2d)[CONFIG_T::reuse_factor] = + (typename CONFIG_T::weight_t(*)[CONFIG_T::reuse_factor])weights; + + data_T data_buf[CONFIG_T::n_pixels][mult_n_in]; + #pragma HLS ARRAY_PARTITION variable=data_buf complete dim=0 + + #pragma HLS ARRAY_PARTITION variable=biases complete + + typename CONFIG_T::accum_t acc[CONFIG_T::n_pixels][mult_n_out]; + #pragma HLS ARRAY_PARTITION variable=acc complete dim=0 + +PartitionLoop: + for (unsigned i_part = 0; i_part < CONFIG_T::n_partitions; i_part++) { + //#pragma HLS UNROLL // We don't want this loop unrolled + + CONFIG_T::template fill_buffer::fill_buffer(data, data_buf, i_part); + + PixelInitAccumLoop: + for (unsigned i_pxl = 0; i_pxl < CONFIG_T::n_pixels; i_pxl++) { + #pragma HLS UNROLL + + InitAccumLoop: + for (unsigned i_acc = 0; i_acc < mult_n_out; i_acc++) { + #pragma HLS UNROLL + acc[i_pxl][i_acc] = (typename CONFIG_T::accum_t)biases[i_acc]; + } + } + + ReuseLoop: + for (unsigned i_rf = 0; i_rf < CONFIG_T::reuse_factor; i_rf++) { + #pragma HLS PIPELINE II=1 rewind + + unsigned i_in = i_rf; + unsigned i_out = 0; + unsigned i_acc = 0; + + MultLoop: + for (unsigned i_blk = 0; i_blk < block_factor; i_blk++) { + #pragma HLS UNROLL + + PixelMultLoop: + for (unsigned i_pxl = 0; i_pxl < CONFIG_T::n_pixels; i_pxl++) { + #pragma HLS UNROLL + + acc[i_pxl][i_out] += static_cast( + CONFIG_T::mult_config::template product::product( + data_buf[i_pxl][i_in], weights_2d[i_blk][i_rf])); + } + + // Increment i_in + i_in += CONFIG_T::reuse_factor; + if (i_in >= mult_n_in) { + i_in = i_rf; + } + // Increment i_out + if (i_acc + 1 >= multscale) { + i_acc = 0; + i_out++; + } else { + i_acc++; + } + } + } + + PixelResultLoop: + for (unsigned i_pxl = 0; i_pxl < CONFIG_T::n_pixels; i_pxl++) { + #pragma HLS UNROLL + // Cast to "res_t" type + ResultLoop: + for (unsigned i_res = 0; i_res < mult_n_out; i_res++) { + #pragma HLS UNROLL + res[i_part * CONFIG_T::n_pixels * mult_n_out + i_pxl * mult_n_out + i_res] = + cast(acc[i_pxl][i_res]); + } + } + } +} + +} // namespace nnet +#endif diff --git a/firmware/nnet_utils/nnet_embed_stream.h b/firmware/nnet_utils/nnet_embed_stream.h new file mode 100644 index 0000000000000000000000000000000000000000..79ae9bc10983f395abdf8e5e892e6bb91e0f6e71 --- /dev/null +++ b/firmware/nnet_utils/nnet_embed_stream.h @@ -0,0 +1,33 @@ +#ifndef NNET_EMBED_STREAM_H_ +#define NNET_EMBED_STREAM_H_ + +#include "hls_stream.h" +#include "nnet_common.h" +#include "nnet_helpers.h" + +namespace nnet { + +template +void embedding(hls::stream &data, hls::stream &res, + typename CONFIG_T::embeddings_t embeddings[CONFIG_T::vocab_size * CONFIG_T::n_out]) { + data_T in_data = data.read(); + +InputSequence: + for (int j = 0; j < data_T::size; j++) { + #pragma HLS PIPELINE II=CONFIG_T::reuse_factor + + res_T res_pack; + PRAGMA_DATA_PACK(res_pack) + + DenseEmbedding: + for (int i = 0; i < CONFIG_T::n_out; i++) { + #pragma HLS UNROLL + res_pack[i] = embeddings[in_data[j] * CONFIG_T::n_out + i]; + } + res.write(res_pack); + } +} + +} // namespace nnet + +#endif diff --git a/firmware/nnet_utils/nnet_helpers.h b/firmware/nnet_utils/nnet_helpers.h new file mode 100644 index 0000000000000000000000000000000000000000..225bce181d87e32f2461c049233f37e1e32e0e53 --- /dev/null +++ b/firmware/nnet_utils/nnet_helpers.h @@ -0,0 +1,382 @@ +#ifndef NNET_HELPERS_H +#define NNET_HELPERS_H + +#include "hls_stream.h" +#include +#include +#include +#include +#include +#include +#include +#include + +namespace nnet { + +#ifndef __SYNTHESIS__ + +#ifndef WEIGHTS_DIR +#define WEIGHTS_DIR "weights" +#endif + +template void load_weights_from_txt(T *w, const char *fname) { + + std::string full_path = std::string(WEIGHTS_DIR) + "/" + std::string(fname); + std::ifstream infile(full_path.c_str(), std::ios::binary); + + if (infile.fail()) { + std::cerr << "ERROR: file " << std::string(full_path) << " does not exist" << std::endl; + exit(1); + } + + std::string line; + if (std::getline(infile, line)) { + std::istringstream iss(line); + std::string token; + + size_t i = 0; + while (std::getline(iss, token, ',')) { + std::istringstream(token) >> w[i]; + i++; + } + + if (SIZE != i) { + std::cerr << "ERROR: Expected " << SIZE << " values"; + std::cerr << " but read only " << i << " values" << std::endl; + } + } +} + +template void load_compressed_weights_from_txt(T *w, const char *fname) { + + std::string full_path = std::string(WEIGHTS_DIR) + "/" + std::string(fname); + std::ifstream infile(full_path.c_str(), std::ios::binary); + + if (infile.fail()) { + std::cerr << "ERROR: file " << std::string(fname) << " does not exist" << std::endl; + exit(1); + } + + std::string line; + if (std::getline(infile, line)) { + std::istringstream iss(line); + std::string token; + std::string extra_chars = "} "; + + size_t i = 0; + while (std::getline(iss, token, '{')) { + if (token.length() == 0) { + continue; + } + for (char c : extra_chars) { + token.erase(std::remove(token.begin(), token.end(), c), token.end()); + } + if (token.back() == ',') { + token.erase(token.end() - 1); + } + + std::replace(token.begin(), token.end(), ',', ' '); + std::istringstream structss(token); + + if (!(structss >> w[i].row_index >> w[i].col_index >> w[i].weight)) { + std::cerr << "ERROR: Unable to parse file " << std::string(fname); + exit(1); + } + i++; + } + + if (SIZE != i) { + std::cerr << "ERROR: Expected " << SIZE << " values"; + std::cerr << " but read only " << i << " values" << std::endl; + } + } +} + +template void load_exponent_weights_from_txt(T *w, const char *fname) { + + std::string full_path = std::string(WEIGHTS_DIR) + "/" + std::string(fname); + std::ifstream infile(full_path.c_str(), std::ios::binary); + + if (infile.fail()) { + std::cerr << "ERROR: file " << std::string(fname) << " does not exist" << std::endl; + exit(1); + } + + std::string line; + if (std::getline(infile, line)) { + std::istringstream iss(line); + std::string token; + std::string extra_chars = "} "; + + size_t i = 0; + while (std::getline(iss, token, '{')) { + if (token.length() == 0) { + continue; + } + for (char c : extra_chars) { + token.erase(std::remove(token.begin(), token.end(), c), token.end()); + } + if (token.back() == ',') { + token.erase(token.end() - 1); + } + + std::replace(token.begin(), token.end(), ',', ' '); + std::istringstream structss(token); + + if (!(structss >> w[i].sign >> w[i].weight)) { + std::cerr << "ERROR: Unable to parse file " << std::string(fname); + exit(1); + } + i++; + } + + if (SIZE != i) { + std::cerr << "ERROR: Expected " << SIZE << " values"; + std::cerr << " but read only " << i << " values" << std::endl; + } + } +} +template void convert_data(srcType *src, dstType *dst) { + for (size_t i = 0; i < SIZE; i++) { + dst[i] = dstType(src[i]); + } +} + +template void convert_data(srcType *src, hls::stream &dst) { + for (size_t i = 0; i < SIZE / dstType::size; i++) { + dstType ctype; + for (size_t j = 0; j < dstType::size; j++) { + ctype[j] = typename dstType::value_type(src[i * dstType::size + j]); + } + dst.write(ctype); + } +} + +template void convert_data(hls::stream &src, dstType *dst) { + for (size_t i = 0; i < SIZE / srcType::size; i++) { + srcType ctype = src.read(); + for (size_t j = 0; j < srcType::size; j++) { + dst[i * srcType::size + j] = dstType(ctype[j]); + } + } +} + +extern bool trace_enabled; +extern std::map *trace_outputs; +extern size_t trace_type_size; + +template void save_output_array(data_T *data, save_T *ptr, size_t layer_size) { + for (int i = 0; i < layer_size; i++) { + ptr[i] = save_T(data[i]); + } +} + +template void save_output_array(hls::stream &data, save_T *ptr, size_t layer_size) { + for (size_t i = 0; i < layer_size / data_T::size; i++) { + data_T ctype = data.read(); + for (size_t j = 0; j < data_T::size; j++) { + ptr[i * data_T::size + j] = save_T(ctype[j]); + } + data.write(ctype); + } +} + +// We don't want to include save_T in this function because it will be inserted into myproject.cpp +// so a workaround with element size is used +template void save_layer_output(data_T *data, const char *layer_name, size_t layer_size) { + if (!trace_enabled) + return; + + if (trace_outputs) { + if (trace_outputs->count(layer_name) > 0) { + if (trace_type_size == 4) { + save_output_array(data, (float *)(*trace_outputs)[layer_name], layer_size); + } else if (trace_type_size == 8) { + save_output_array(data, (double *)(*trace_outputs)[layer_name], layer_size); + } else { + std::cout << "Unknown trace type!" << std::endl; + } + } else { + std::cout << "Layer name: " << layer_name << " not found in debug storage!" << std::endl; + } + } else { + std::ostringstream filename; + filename << "./tb_data/" << layer_name << "_output.log"; // TODO if run as a shared lib, path should be ../tb_data + std::fstream out; + out.open(filename.str(), std::ios::app); + assert(out.is_open()); + for (int i = 0; i < layer_size; i++) { + out << float(data[i]) << " "; // We don't care about precision in text files + } + out << std::endl; + out.close(); + } +} + +template void save_layer_output(hls::stream &data, const char *layer_name, size_t layer_size) { + if (!trace_enabled) + return; + + if (trace_outputs) { + if (trace_outputs->count(layer_name) > 0) { + if (trace_type_size == 4) { + save_output_array(data, (float *)(*trace_outputs)[layer_name], layer_size); + } else if (trace_type_size == 8) { + save_output_array(data, (double *)(*trace_outputs)[layer_name], layer_size); + } else { + std::cout << "Unknown trace type!" << std::endl; + } + } else { + std::cout << "Layer name: " << layer_name << " not found in debug storage!" << std::endl; + } + } else { + std::ostringstream filename; + filename << "./tb_data/" << layer_name << "_output.log"; // TODO if run as a shared lib, path should be ../tb_data + std::fstream out; + out.open(filename.str(), std::ios::app); + assert(out.is_open()); + for (size_t i = 0; i < layer_size / data_T::size; i++) { + data_T ctype = data.read(); + for (size_t j = 0; j < data_T::size; j++) { + out << float(ctype[j]) << " "; // We don't care about precision in text files + } + data.write(ctype); + } + out << std::endl; + out.close(); + } +} + +#endif + +template void copy_data(std::vector src, dst_T dst[SIZE]) { + typename std::vector::const_iterator in_begin = src.cbegin() + OFFSET; + typename std::vector::const_iterator in_end = in_begin + SIZE; + std::copy(in_begin, in_end, dst); +} + +template +void copy_data(std::vector src, hls::stream &dst) { + typename std::vector::const_iterator in_begin = src.cbegin() + OFFSET; + typename std::vector::const_iterator in_end = in_begin + SIZE; + + size_t i_pack = 0; + dst_T dst_pack; + for (typename std::vector::const_iterator i = in_begin; i != in_end; ++i) { + dst_pack[i_pack++] = typename dst_T::value_type(*i); + if (i_pack == dst_T::size) { + i_pack = 0; + dst.write(dst_pack); + } + } +} + +template void copy_data_axi(std::vector src, dst_T dst[SIZE]) { + for (auto i = 0; i < SIZE; i++) + if (i == SIZE - 1) { + dst[i].data = src[i]; + dst[i].last = 1; + } else { + dst[i].data = src[i]; + dst[i].last = 0; + } +} + +template void print_result(res_T result[SIZE], std::ostream &out, bool keep = false) { + for (int i = 0; i < SIZE; i++) { + out << result[i] << " "; + } + out << std::endl; +} + +template void print_result(hls::stream &result, std::ostream &out, bool keep = false) { + for (int i = 0; i < SIZE / res_T::size; i++) { + res_T res_pack = result.read(); + for (int j = 0; j < res_T::size; j++) { + out << res_pack[j] << " "; + } + if (keep) + result.write(res_pack); + } + out << std::endl; +} + +template void fill_zero(data_T data[SIZE]) { std::fill_n(data, SIZE, 0.); } + +template void fill_zero(hls::stream &data) { + for (int i = 0; i < SIZE / data_T::size; i++) { + data_T data_pack; + for (int j = 0; j < data_T::size; j++) { + data_pack[j] = 0.; + } + data.write(data_pack); + } +} + +template int read_file_1D(const char *filename, dataType data[nrows]) { + FILE *fp; + fp = fopen(filename, "r"); + if (fp == 0) { + return -1; + } + // Read data from file + float newval; + for (int ii = 0; ii < nrows; ii++) { + if (fscanf(fp, "%f\n", &newval) != 0) { + data[ii] = newval; + } else { + return -2; + } + } + fclose(fp); + return 0; +} + +template +int read_file_2D(const char *filename, dataType data[nrows][ncols]) { + FILE *fp; + fp = fopen(filename, "r"); + if (fp == 0) { + return -1; + } + // Read data from file + float newval; + for (int ii = 0; ii < nrows; ii++) { + for (int jj = 0; jj < ncols; jj++) { + if (fscanf(fp, "%f\n", &newval) != 0) { + data[ii][jj] = newval; + } else { + return -2; + } + } + } + fclose(fp); + return 0; +} + +template void change_type(hls::stream &in, hls::stream &out) { + in_T datareg; + hls::stream input_trunc; + for (int ii = 0; ii < N_IN; ii++) { + out << (out_T)in.read(); + } +} + +template void hls_stream_debug(hls::stream &data, hls::stream &res) { + data_T datareg; + for (int ii = 0; ii < N_IN; ii++) { + datareg = data.read(); + std::cout << "[" << ii << "]: " << datareg << std::endl; + res << datareg; + } +} + +constexpr int ceillog2(int x) { return (x <= 2) ? 1 : 1 + ceillog2((x + 1) / 2); } + +constexpr int floorlog2(int x) { return (x < 2) ? 0 : 1 + floorlog2(x / 2); } + +constexpr int pow2(int x) { return x == 0 ? 1 : 2 * pow2(x - 1); } + +} // namespace nnet + +#endif diff --git a/firmware/nnet_utils/nnet_sepconv2d.h b/firmware/nnet_utils/nnet_sepconv2d.h new file mode 100644 index 0000000000000000000000000000000000000000..602a205a451e482ee9eb714f1c723335247e1725 --- /dev/null +++ b/firmware/nnet_utils/nnet_sepconv2d.h @@ -0,0 +1,51 @@ +#ifndef NNET_SEPARABLE_CONV2D_H_ +#define NNET_SEPARABLE_CONV2D_H_ + +#include "nnet_common.h" +#include "nnet_conv2d.h" +#include "nnet_sepconv2d_latency.h" +//#include "nnet_sepconv2d_resource.h" +#include + +namespace nnet { + +template +void depthwise_conv_2d_cl( + data_T data[CONFIG_T::in_height * CONFIG_T::in_width * CONFIG_T::n_chan], + res_T res[CONFIG_T::out_height * CONFIG_T::out_width * CONFIG_T::n_filt], + typename CONFIG_T::weight_t weights[CONFIG_T::filt_height * CONFIG_T::filt_width * CONFIG_T::n_chan], + typename CONFIG_T::bias_t biases[CONFIG_T::n_chan]) { + #pragma HLS INLINE recursive + if (CONFIG_T::strategy == nnet::latency || CONFIG_T::strategy == nnet::distributed_arithmetic) { + depthwise_conv_2d_latency_cl(data, res, weights, biases); + } else { + assert("Resource strategy for DepthwiseConv2D is not supported." && false); + } +} + +template +void separable_conv_2d_cl(data_T data[CONFIG_T::depthwise_config::in_height * CONFIG_T::depthwise_config::in_width * + CONFIG_T::depthwise_config::n_chan], + res_T res[CONFIG_T::pointwise_config::out_height * CONFIG_T::pointwise_config::out_width * + CONFIG_T::pointwise_config::n_filt], + typename CONFIG_T::depthwise_config::weight_t + depthwise_weights[CONFIG_T::depthwise_config::filt_height * + CONFIG_T::depthwise_config::filt_width * CONFIG_T::depthwise_config::n_chan], + typename CONFIG_T::pointwise_config::weight_t + pointwise_weights[CONFIG_T::pointwise_config::n_chan * CONFIG_T::pointwise_config::n_filt], + typename CONFIG_T::depthwise_config::bias_t depthwise_biases[CONFIG_T::depthwise_config::n_chan], + typename CONFIG_T::pointwise_config::bias_t pointwise_biases[CONFIG_T::pointwise_config::n_filt]) { + #pragma HLS INLINE recursive + + dw_res_T depthwise_res[CONFIG_T::depthwise_config::out_height * CONFIG_T::depthwise_config::out_width * + CONFIG_T::depthwise_config::n_filt]; + + depthwise_conv_2d_cl(data, depthwise_res, depthwise_weights, + depthwise_biases); + pointwise_conv_2d_cl(depthwise_res, res, pointwise_weights, + pointwise_biases); +} + +} // namespace nnet + +#endif diff --git a/firmware/nnet_utils/nnet_transpose.h b/firmware/nnet_utils/nnet_transpose.h new file mode 100644 index 0000000000000000000000000000000000000000..f775d25f75cd38bcb7b9b391c6f3f8121922c957 --- /dev/null +++ b/firmware/nnet_utils/nnet_transpose.h @@ -0,0 +1,39 @@ +#ifndef NNET_PERMUTE_H_ +#define NNET_PERMUTE_H_ + +namespace nnet { + +struct transpose_config { + static const unsigned dims; + static const unsigned N; + // vivado/vitis hls can't index constexpr array for some reason + // and vivado hls don't like template recursion either (vitis is fine) + // thus this appears to be the only workaround (or overkill it with codegen) + static const unsigned *const from_shape; + static const unsigned *const to_shape; + static const unsigned *const perm; + static const unsigned *const perm_strides; +}; + +template unsigned transfer_idx(int index) { + // Given output idx in c-order flat array, return input idx + int idx = 0; + for (int i = CONFIG_T::dims - 1; i >= 0; i--) { + idx += (index % CONFIG_T::to_shape[i]) * CONFIG_T::perm_strides[i]; + index /= CONFIG_T::to_shape[i]; + } + return idx; +} + +template +void transpose(const data_T data[CONFIG_T::N], res_T res[CONFIG_T::N]) { + for (int i = 0; i < CONFIG_T::N; i++) { + #pragma HLS UNROLL + int idx = transfer_idx(i); + res[i] = data[idx]; + } +} + +} // namespace nnet + +#endif diff --git a/firmware/nnet_utils/nnet_types.h b/firmware/nnet_utils/nnet_types.h new file mode 100644 index 0000000000000000000000000000000000000000..41d965685a02ac426be6a551458c40574a3e7179 --- /dev/null +++ b/firmware/nnet_utils/nnet_types.h @@ -0,0 +1,80 @@ +#ifndef NNET_TYPES_H_ +#define NNET_TYPES_H_ + +#include +#include +#include + +namespace nnet { + +// Fixed-size array +template struct array { + typedef T value_type; + static const unsigned size = N; + + T data[N]; + + T &operator[](size_t pos) { return data[pos]; } + + const T &operator[](size_t pos) const { return data[pos]; } + + array &operator=(const array &other) { + if (&other == this) + return *this; + + assert(N == other.size && "Array sizes must match."); + + for (unsigned i = 0; i < N; i++) { + #pragma HLS UNROLL + data[i] = other[i]; + } + return *this; + } + + bool operator==(const array &other) const { + if (N != other.size) { + return false; + } + + for (unsigned i = 0; i < N; i++) { + if (data[i] != other[i]) { + return false; + } + } + + return true; + } + + bool operator!=(const array &other) const { return !(*this == other); } +}; + +// Generic lookup-table implementation, for use in approximations of math functions +template class lookup_table { + public: + lookup_table(T from, T to) : range_start(from), range_end(to), base_div(ap_uint<16>(N) / T(to - from)) { + T step = (range_end - range_start) / ap_uint<16>(N); + for (size_t i = 0; i < N; i++) { + T num = range_start + ap_uint<16>(i) * step; + T sample = func(num); + samples[i] = sample; + } + } + + T operator()(T n) const { + int index = (n - range_start) * base_div; + if (index < 0) + index = 0; + else if (index > N - 1) + index = N - 1; + return samples[index]; + } + + private: + T samples[N]; + const T range_start, range_end; + ap_fixed<20, 16> base_div; +}; + +} // namespace nnet + +#endif diff --git a/logs/hls_run_tcl.log b/logs/hls_run_tcl.log new file mode 100644 index 0000000000000000000000000000000000000000..52f5b596ffd7038d26aa49fecffca975cb09f73b --- /dev/null +++ b/logs/hls_run_tcl.log @@ -0,0 +1,10395 @@ +INFO: [vitis-run 82-31] Launching vitis_hls: vitis_hls -nolog -run tcl -f /home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl -work_dir /home/ubuntu/lithobench/hls4ml_mini_unet + +****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2024.1 (64-bit) + **** SW Build 5069499 on May 21 2024 + **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 + **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 + **** Start of session at: Sun Apr 5 21:32:45 2026 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. + +source /opt/Xilinx/Vitis_HLS/2024.1/scripts/vitis_hls/hls.tcl -notrace +INFO: [HLS 200-10] For user 'ubuntu' on host 'ip-172-31-42-252.ec2.internal' (Linux_x86_64 version 5.15.0-1084-aws) on Sun Apr 05 21:32:47 UTC 2026 +INFO: [HLS 200-10] On os Ubuntu 20.04.6 LTS +INFO: [HLS 200-10] In directory '/home/ubuntu/lithobench/hls4ml_mini_unet' +Sourcing Tcl script '/home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl' +INFO: [HLS 200-1510] Running: open_project myproject_prj +INFO: [HLS 200-10] Opening project '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj'. +INFO: [HLS 200-1510] Running: set_top myproject +INFO: [HLS 200-1510] Running: add_files firmware/myproject.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding design file 'firmware/myproject.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb myproject_test.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding test bench file 'myproject_test.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb firmware/weights +INFO: [HLS 200-10] Adding test bench file 'firmware/weights' to the project +INFO: [HLS 200-1510] Running: add_files -tb tb_data +INFO: [HLS 200-10] Adding test bench file 'tb_data' to the project +INFO: [HLS 200-1510] Running: open_solution solution1 +INFO: [HLS 200-10] Opening solution '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1'. +INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. +INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 1.35ns. +INFO: [HLS 200-1611] Setting target device to 'xcvu47p-fsvh2892-2L-e' +INFO: [HLS 200-1505] Using flow_target 'vivado' +Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1505.html +INFO: [HLS 200-1464] Running solution command: config_compile -name_max_length=80 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_compile -complex-mul-dsp=0 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_compile -unsafe_math_optimizations=0 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_schedule -enable_dsp_full_reg=0 +INFO: [HLS 200-1464] Running solution command: config_array_partition -complete_threshold=4096 +INFO: [XFORM 203-102] Size-based automatic array partition enabled: cut-off elements per dimension is 4096. +INFO: [HLS 200-1510] Running: config_array_partition -maximum_size 4096 +ERROR: [HLS 200-101] config_array_partition: Unknown option '-maximum_size'. +ERROR: [HLS 200-101] config_array_partition: Unknown option '4096'. +SYNTAX + config_array_partition [OPTIONS] + -auto_partition_threshold *** DEPRECATED*** + -auto_promotion_threshold *** DEPRECATED*** + -complete_threshold + -throughput_driven + +SEE ALSO + INI: syn.array_partition.complete_threshold syn.array_partition.throughput_driven + docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1399-vitis-hls&resourceid=vyw1583260160301.html + +INFO: [HLS 200-1510] Running: config_compile -name_max_length 80 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: set_part xcvu47p-fsvh2892-2L-e +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: config_schedule -enable_dsp_full_reg=false +INFO: [HLS 200-1510] Running: create_clock -period 4 -name default +INFO: [SYN 201-201] Setting up clock 'default' with a period of 4ns. +INFO: [HLS 200-1510] Running: set_clock_uncertainty 27% default +***** C/RTL SYNTHESIS ***** +INFO: [HLS 200-1510] Running: csynth_design +INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0.06 seconds. CPU system time: 0.07 seconds. Elapsed time: 0.21 seconds; current allocated memory: 276.809 MB. +INFO: [HLS 200-10] Analyzing design file 'firmware/myproject.cpp' ... +WARNING: [HLS 207-5570] unexpected pragma argument 'softmax', expects function/operation (firmware/nnet_utils/nnet_activation.h:402:36) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:33:9) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:107:9) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:189:9) +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:234:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:234:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:240:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:240:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:250:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:250:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:256:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:256:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:266:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:266:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:272:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:272:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:282:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:282:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:288:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:288:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:298:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:298:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:304:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:304:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:314:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:314:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:320:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:320:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:330:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:330:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:336:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:336:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:340:100) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:340:105) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 200-471] Dataflow form checks found 30 issue(s) in file firmware/myproject.cpp +Resolution: For help on HLS 200-471 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-471.html +WARNING: [HLS 207-5292] unused parameter 'keep' (firmware/nnet_utils/nnet_helpers.h:285:99) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:14:36) +WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:15:36) +WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:16:44) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:24:24) +WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:25:24) +WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:26:32) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:33:30) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:33:58) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:34:51) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:35:49) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:42:30) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:42:58) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:43:51) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:44:49) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:51:29) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:51:80) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:52:50) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:53:48) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_code_gen.h:16:39) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_code_gen.h:17:38) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_code_gen.h:18:60) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_code_gen.h:19:58) +WARNING: [HLS 207-5584] there are more than one pragma inline in the function scope, ignore the pragma (/opt/Xilinx/Vitis_HLS/2024.1/common/technology/autopilot/ap_shift_reg.h:47:9) +INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 36.41 seconds. CPU system time: 2.27 seconds. Elapsed time: 39.6 seconds; current allocated memory: 287.895 MB. +INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target. +INFO: [HLS 200-1995] There were 28,299 instructions in the design after the 'Compile/Link' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 169,202 instructions in the design after the 'Unroll/Inline (step 1)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 90,029 instructions in the design after the 'Unroll/Inline (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 78,923 instructions in the design after the 'Unroll/Inline (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 35,354 instructions in the design after the 'Unroll/Inline (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 53,132 instructions in the design after the 'Array/Struct' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 39,560 instructions in the design after the 'Array/Struct (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 40,455 instructions in the design after the 'Array/Struct (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 85,724 instructions in the design after the 'Array/Struct (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 83,664 instructions in the design after the 'Array/Struct (step 5)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 85,310 instructions in the design after the 'Performance' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 196,081 instructions in the design after the 'Performance (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 193,395 instructions in the design after the 'Performance (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 193,395 instructions in the design after the 'Performance (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 154,571 instructions in the design after the 'HW Transforms' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 146,893 instructions in the design after the 'HW Transforms (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>' (firmware/nnet_utils/nnet_sepconv_stream.h:103:9) +WARNING: [HLS 214-273] In function 'void nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config58_mult::weight_t*, config58_mult::bias_t*)', Pragma conflict happens on 'INLINE' and 'FUNCTION_INSTANTIATE' pragmas: same function (firmware/nnet_utils/nnet_dense_resource.h:15:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 1u>, config2>(nnet::array, 1u>::value_type (*) [config2::n_chan], nnet::array, 1u>::value_type*)' into 'void nnet::shift_line_buffer, 1u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], nnet::array, 1u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, config2_mult::weight_t*, config2_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*) (.55)' into 'void nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config4>(nnet::array, 8u>::value_type (*) [config4::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config4_mult::weight_t*, config4_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 8u>, config4>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*) (.54)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config6>(nnet::array, 8u>::value_type (*) [config6::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::Op_max >::operator()(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>) (.36)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' (firmware/nnet_utils/nnet_common.h:44:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:15) +INFO: [HLS 214-131] Inlining function 'nnet::Op_max >::operator()(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>) (.36)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:12) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:44) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config6>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.52)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config6>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.52)' into 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 8u>::operator[](unsigned long) (.51)' into 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' into 'void nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config7>(nnet::array, 8u>::value_type (*) [config7::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config7_mult::weight_t*, config7_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 16u>, config7>(hls::stream, 8u>, 0>&, hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*) (.48)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>(hls::stream, 8u>, 0>&, hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config9>(nnet::array, 16u>::value_type (*) [config9::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config9_mult::weight_t*, config9_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 16u>, config9>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*) (.47)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config11>(nnet::array, 16u>::value_type (*) [config11::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config11>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.45)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config11>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.45)' into 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 16u>::operator[](unsigned long) (.44)' into 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' into 'void nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config12>(nnet::array, 16u>::value_type (*) [config12::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config12_mult::weight_t*, config12_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 32u>, config12>(hls::stream, 16u>, 0>&, hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*) (.41)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>(hls::stream, 16u>, 0>&, hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config14>(nnet::array, 32u>::value_type (*) [config14::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config14_mult::weight_t*, config14_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 32u>, config14>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*) (.40)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config16>(nnet::array, 32u>::value_type (*) [config16::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config16>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.34)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config16>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.34)' into 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 32u>::operator[](unsigned long) (.33)' into 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' into 'void nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config17>(nnet::array, 32u>::value_type (*) [config17::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config17_mult::weight_t*, config17_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 64u>, config17>(hls::stream, 32u>, 0>&, hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*) (.30)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>(hls::stream, 32u>, 0>&, hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 64u>, config19>(nnet::array, 64u>::value_type (*) [config19::n_chan], nnet::array, 64u>::value_type*)' into 'void nnet::shift_line_buffer, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], nnet::array, 64u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config19_mult::weight_t*, config19_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 64u>, nnet::array, 64u>, config19>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*) (.26)' into 'void nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 96u>, config23>(nnet::array, 96u>::value_type (*) [config23::n_chan], nnet::array, 96u>::value_type*)' into 'void nnet::shift_line_buffer, 96u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], nnet::array, 96u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config23_mult::weight_t*, config23_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 96u>, nnet::array, 32u>, config23>(hls::stream, 96u>, 0>&, hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*) (.23)' into 'void nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>(hls::stream, 96u>, 0>&, hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config25>(nnet::array, 32u>::value_type (*) [config25::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config25_mult::weight_t*, config25_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 32u>, config25>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*) (.19)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 48u>, config29>(nnet::array, 48u>::value_type (*) [config29::n_chan], nnet::array, 48u>::value_type*)' into 'void nnet::shift_line_buffer, 48u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], nnet::array, 48u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config29_mult::weight_t*, config29_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 48u>, nnet::array, 16u>, config29>(hls::stream, 48u>, 0>&, hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*) (.16)' into 'void nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>(hls::stream, 48u>, 0>&, hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config31>(nnet::array, 16u>::value_type (*) [config31::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config31_mult::weight_t*, config31_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 16u>, config31>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*) (.12)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 24u>, config35>(nnet::array, 24u>::value_type (*) [config35::n_chan], nnet::array, 24u>::value_type*)' into 'void nnet::shift_line_buffer, 24u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], nnet::array, 24u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config35_mult::weight_t*, config35_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 24u>, nnet::array, 8u>, config35>(hls::stream, 24u>, 0>&, hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*) (.9)' into 'void nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>(hls::stream, 24u>, 0>&, hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config37>(nnet::array, 8u>::value_type (*) [config37::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config37_mult::weight_t*, config37_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 8u>, config37>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*) (.5)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config58_mult::weight_t*, config58_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const (.4)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:100:13) +INFO: [HLS 214-131] Inlining function 'nnet::array, 1u>::operator[](unsigned long) (.2)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:110:2) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.3)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:104:2) +INFO: [HLS 214-131] Inlining function 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' into 'void nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>(hls::stream, 8u>, 0>&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv2d_stream.h:86:21) +INFO: [HLS 214-291] Loop 'SigmoidPackLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_activation_stream.h:88:9) +INFO: [HLS 214-291] Loop 'MultLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_dense_resource.h:55:9) +INFO: [HLS 214-291] Loop 'ReLUPackLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_activation_stream.h:49:9) +INFO: [HLS 214-291] Loop 'MultLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_dense_resource.h:142:9) +INFO: [HLS 214-291] Loop 'KernelPushHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:205:5) +INFO: [HLS 214-291] Loop 'KernelPushChannel' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:208:9) +INFO: [HLS 214-291] Loop 'KernelShiftWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:189:5) +INFO: [HLS 214-291] Loop 'KernelShiftHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:192:9) +INFO: [HLS 214-291] Loop 'KernelShiftChannel' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:194:13) +INFO: [HLS 214-291] Loop 'LineBufferDataIn' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:236:5) +INFO: [HLS 214-291] Loop 'LineBufferShift' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:239:9) +INFO: [HLS 214-291] Loop 'UpdateBuffer' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:228:5) +INFO: [HLS 214-291] Loop 'ConcatPackInput1' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_merge_stream.h:245:13) +INFO: [HLS 214-291] Loop 'ConcatPackInput2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_merge_stream.h:251:13) +INFO: [HLS 214-291] Loop 'ImageWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:22:9) +INFO: [HLS 214-291] Loop 'ImageChan' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:28:13) +INFO: [HLS 214-291] Loop 'ResizeHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:36:9) +INFO: [HLS 214-291] Loop 'ImageWidth2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:40:13) +INFO: [HLS 214-291] Loop 'ResizeWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:44:17) +INFO: [HLS 214-291] Loop 'ResizeChan' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:51:21) +INFO: [HLS 214-291] Loop 'FiltLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_pooling_stream.h:57:9) +INFO: [HLS 214-291] Loop 'PoolLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_pooling_stream.h:62:13) +INFO: [HLS 214-291] Loop 'ClonePack' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_stream.h:32:9) +INFO: [HLS 214-186] Unrolling loop 'SigmoidPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:88:9) in function 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>' completely with a factor of 1 (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-186] Unrolling loop 'InitData' (firmware/nnet_utils/nnet_sepconv_stream.h:98:5) in function 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>' completely with a factor of 8 (firmware/nnet_utils/nnet_sepconv2d_stream.h:58:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_sepconv_stream.h:108:5) in function 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>' completely with a factor of 1 (firmware/nnet_utils/nnet_sepconv2d_stream.h:58:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config38>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 2 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config37>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config36>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 24u>, config35>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>' completely with a factor of 24 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' completely with a factor of 16 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' completely with a factor of 8 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config32>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 4 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config31>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config30>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 48u>, config29>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>' completely with a factor of 48 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' completely with a factor of 32 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' completely with a factor of 16 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config26>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config25>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config24>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 96u>, config23>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>' completely with a factor of 96 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' completely with a factor of 64 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' completely with a factor of 32 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 8 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 64 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 8 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 64 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 64u>, nnet::array, 64u>, relu_config20>' completely with a factor of 64 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 64u>, config19>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 64u>, nnet::array, 64u>, relu_config18>' completely with a factor of 64 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config17>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config16>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>' completely with a factor of 32 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config15>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config14>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config13>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config12>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config11>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>' completely with a factor of 16 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config10>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config9>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config8>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config7>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config6>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>' completely with a factor of 8 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config5>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 4 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config4>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config3>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 1u>, config2>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>' completely with a factor of 1 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 1u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], nnet::array, 1u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(config2_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, config2_mult::weight_t*, config2_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config3>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config3>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(config4_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config4_mult::weight_t*, config4_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config5>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config5>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(config7_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config7_mult::weight_t*, config7_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config8>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config8>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(config9_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config9_mult::weight_t*, config9_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config10>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config10>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(config12_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config12_mult::weight_t*, config12_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config13>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config13>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(config14_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config14_mult::weight_t*, config14_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config15>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config15>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config18>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config18>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], nnet::array, 64u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config20>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config20>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 64u>, config21>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 96u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], nnet::array, 96u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(config23_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config23_mult::weight_t*, config23_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config24>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config24>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(config25_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config25_mult::weight_t*, config25_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config26>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config26>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 32u>, config27>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 48u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], nnet::array, 48u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(config29_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config29_mult::weight_t*, config29_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config30>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config30>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(config31_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config31_mult::weight_t*, config31_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config32>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config32>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 16u>, config33>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 24u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], nnet::array, 24u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(config35_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config35_mult::weight_t*, config35_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config36>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config36>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(config37_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config37_mult::weight_t*, config37_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config38>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config38>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(config58_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config58_mult::weight_t*, config58_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj1EEENS1_IS2_ILi37ELi17ELS3_5ELS4_3ELi0EELj8EEE7config2EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEES6_7config6EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to 'b2': Complete partitioning on dimension 1. (firmware/weights/b2.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b4': Complete partitioning on dimension 1. (firmware/weights/b4.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b7': Complete partitioning on dimension 1. (firmware/weights/b7.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b9': Complete partitioning on dimension 1. (firmware/weights/b9.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b12': Complete partitioning on dimension 1. (firmware/weights/b12.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b14': Complete partitioning on dimension 1. (firmware/weights/b14.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b17': Complete partitioning on dimension 1. (firmware/weights/b17.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b19': Complete partitioning on dimension 1. (firmware/weights/b19.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b23': Complete partitioning on dimension 1. (firmware/weights/b23.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b25': Complete partitioning on dimension 1. (firmware/weights/b25.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b29': Complete partitioning on dimension 1. (firmware/weights/b29.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b31': Complete partitioning on dimension 1. (firmware/weights/b31.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b35': Complete partitioning on dimension 1. (firmware/weights/b35.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b37': Complete partitioning on dimension 1. (firmware/weights/b37.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'w39': Complete partitioning on dimension 1. (firmware/weights/w39.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b39': Complete partitioning on dimension 1. (firmware/weights/b39.h:12:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEES6_7config6EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj1EEENS1_IS2_ILi37ELi17ELS3_5ELS4_3ELi0EELj8EEE7config2EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to 'acc': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_dense_resource.h:110:32) +INFO: [HLS 214-248] Applying array_partition to 'res_out': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:274:29) +INFO: [HLS 214-248] Applying array_partition to 'shift_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv_stream.h:224:30) +INFO: [HLS 214-248] Applying array_partition to 'data.i': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_sepconv_stream.h:88:30) +INFO: [HLS 214-248] Applying array_partition to 'res.i': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_sepconv_stream.h:91:29) +WARNING: [HLS 214-322] Unsuported scalar variable on pragma 'Resource/Bind_Storage', ignore it. (firmware/myproject.cpp:340:5) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer39_out' with compact=bit mode in 36-bits (firmware/myproject.cpp:229:35) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer38_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:226:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer57_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:220:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer36_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:217:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer46_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:85:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer6_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:82:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer41_cpy1' with compact=bit mode in 128-bits (firmware/myproject.cpp:76:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer41_cpy2' with compact=bit mode in 128-bits (firmware/myproject.cpp:79:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer5_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:73:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer45_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:67:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer3_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:64:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer37_out' with compact=bit mode in 320-bits (firmware/myproject.cpp:223:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer4_out' with compact=bit mode in 320-bits (firmware/myproject.cpp:70:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer35_out' with compact=bit mode in 328-bits (firmware/myproject.cpp:214:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer56_out' with compact=bit mode in 384-bits (firmware/myproject.cpp:211:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer34_out' with compact=bit mode in 384-bits (firmware/myproject.cpp:208:30) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer33_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:205:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer32_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:202:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer55_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:196:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer30_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:193:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer48_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:112:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer11_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:109:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer42_cpy1' with compact=bit mode in 256-bits (firmware/myproject.cpp:103:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer42_cpy2' with compact=bit mode in 256-bits (firmware/myproject.cpp:106:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer10_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:100:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer47_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:94:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer8_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:91:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer31_out' with compact=bit mode in 656-bits (firmware/myproject.cpp:199:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer9_out' with compact=bit mode in 656-bits (firmware/myproject.cpp:97:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer29_out' with compact=bit mode in 672-bits (firmware/myproject.cpp:190:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer54_out' with compact=bit mode in 768-bits (firmware/myproject.cpp:187:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer28_out' with compact=bit mode in 768-bits (firmware/myproject.cpp:184:30) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer27_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:181:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer26_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:178:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer53_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:172:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer24_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:169:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer50_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:139:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer16_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:136:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer43_cpy1' with compact=bit mode in 512-bits (firmware/myproject.cpp:130:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer43_cpy2' with compact=bit mode in 512-bits (firmware/myproject.cpp:133:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer15_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:127:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer49_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:121:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer13_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:118:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer25_out' with compact=bit mode in 1344-bits (firmware/myproject.cpp:175:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer14_out' with compact=bit mode in 1344-bits (firmware/myproject.cpp:124:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer23_out' with compact=bit mode in 1376-bits (firmware/myproject.cpp:166:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer52_out' with compact=bit mode in 1536-bits (firmware/myproject.cpp:163:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer22_out' with compact=bit mode in 1536-bits (firmware/myproject.cpp:160:28) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer21_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:157:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer20_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:154:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer51_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:148:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer18_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:145:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer19_out' with compact=bit mode in 2752-bits (firmware/myproject.cpp:151:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer17_out' with compact=bit mode in 2688-bits (firmware/myproject.cpp:142:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer12_out' with compact=bit mode in 1312-bits (firmware/myproject.cpp:115:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer7_out' with compact=bit mode in 640-bits (firmware/myproject.cpp:88:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer2_out' with compact=bit mode in 296-bits (firmware/myproject.cpp:61:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer44_out' with compact=bit mode in 16-bits (firmware/myproject.cpp:58:25) +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::conv_2d_buffer_resource_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_64' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_65' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_66' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_67' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_68' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_69' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_70' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_71' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_72' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_73' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_74' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_75' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_76' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_77' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_78' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_79' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_80' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_81' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_82' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_83' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_84' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_85' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_86' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_87' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_88' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_89' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_90' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_91' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_92' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_93' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_94' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_95' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_64' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_65' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_66' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_67' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_68' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_69' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_70' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_71' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_72' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_73' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_74' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_75' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_76' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_77' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_78' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_79' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_80' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_81' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_82' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_83' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_84' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_85' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_86' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_87' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_88' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_89' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_90' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_91' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_92' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_93' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_94' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_95' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-248] Applying array_reshape to 'w4': Block reshaping with factor 4 on dimension 1. (firmware/weights/w4.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w7': Block reshaping with factor 8 on dimension 1. (firmware/weights/w7.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w9': Block reshaping with factor 16 on dimension 1. (firmware/weights/w9.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w12': Block reshaping with factor 8 on dimension 1. (firmware/weights/w12.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w14': Block reshaping with factor 16 on dimension 1. (firmware/weights/w14.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w17': Block reshaping with factor 16 on dimension 1. (firmware/weights/w17.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w19': Block reshaping with factor 32 on dimension 1. (firmware/weights/w19.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w23': Block reshaping with factor 32 on dimension 1. (firmware/weights/w23.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w25': Block reshaping with factor 8 on dimension 1. (firmware/weights/w25.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w29': Block reshaping with factor 16 on dimension 1. (firmware/weights/w29.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w31': Block reshaping with factor 4 on dimension 1. (firmware/weights/w31.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w35': Block reshaping with factor 8 on dimension 1. (firmware/weights/w35.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w37': Block reshaping with factor 2 on dimension 1. (firmware/weights/w37.h:12:0) +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadTopWidth> at firmware/nnet_utils/nnet_padding_stream.h:53:9 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadMain> at firmware/nnet_utils/nnet_padding_stream.h:59:5 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadBottomWidth> at firmware/nnet_utils/nnet_padding_stream.h:77:9 +INFO: [HLS 214-291] Loop 'CopyMain' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_padding_stream.h:65:9) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-270] Inferring pragma 'array_partition type=complete dim=1' for array 'ref.tmp.i' due to pipeline pragma +INFO: [HLS 214-248] Applying array_partition to 'ref.tmp.i': Complete partitioning on dimension 1. +INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 296.97 seconds. CPU system time: 5.15 seconds. Elapsed time: 291.55 seconds; current allocated memory: 351.164 MB. +INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 351.332 MB. +INFO: [HLS 200-10] Starting code transformations ... +INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 28.29 seconds. CPU system time: 0.06 seconds. Elapsed time: 28.46 seconds; current allocated memory: 430.727 MB. +INFO: [HLS 200-10] Checking synthesizability ... +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' into 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_dense_resource.h:164) automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' into 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_dense_resource.h:164) automatically. +INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 102.33 seconds. CPU system time: 0.06 seconds. Elapsed time: 102.4 seconds; current allocated memory: 552.035 MB. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' into 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_dense_resource.h:164) automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' into 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_dense_resource.h:164) automatically. +INFO: [XFORM 203-712] Applying dataflow to function 'myproject' (firmware/myproject.cpp:8), detected/extracted 56 process function(s): + 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>' + 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config3>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config5>' + 'nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>' + 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config8>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config10>' + 'nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>' + 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config13>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config15>' + 'nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>' + 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>' + 'nnet::relu, 64u>, nnet::array, 64u>, relu_config18>' + 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>' + 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>' + 'nnet::relu, 64u>, nnet::array, 64u>, relu_config20>' + 'nnet::resize_nearest, 64u>, config21>' + 'nnet::concatenate3d, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' + 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>' + 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config24>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config26>' + 'nnet::resize_nearest, 32u>, config27>' + 'nnet::concatenate3d, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' + 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>' + 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config30>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config32>' + 'nnet::resize_nearest, 16u>, config33>' + 'nnet::concatenate3d, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' + 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>' + 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config36>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config38>' + 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>' + 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>'. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_activation_stream.h:81:9) to (firmware/nnet_utils/nnet_activation_stream.h:80:5) in function 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>'... converting 3 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>'... converting 65 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>'... converting 73 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>'... converting 145 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>'... converting 33 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>'... converting 37 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>'... converting 73 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>'... converting 17 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>'... converting 9 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>'... converting 19 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>'... converting 18 basic blocks. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...24 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...48 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...12 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...24 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...6 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...13 expression(s) balanced. +INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 247.78 seconds. CPU system time: 0.11 seconds. Elapsed time: 247.92 seconds; current allocated memory: 683.547 MB. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_pooling_stream.h:109:5) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_pooling_stream.h:109:5) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_pooling_stream.h:109:5) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeightSerial' (firmware/nnet_utils/nnet_sepconv2d_stream.h:81:9) in function 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ConcatLoopHeight' (firmware/nnet_utils/nnet_merge_stream.h:234:5) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ConcatLoopHeight' (firmware/nnet_utils/nnet_merge_stream.h:234:5) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ConcatLoopHeight' (firmware/nnet_utils/nnet_merge_stream.h:234:5) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>'. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config23_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config29_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config9_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config35_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config58_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0,config7_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0,config4_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0,config2_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config23_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config29_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config9_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config35_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config58_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0,config7_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0,config4_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0,config2_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0'. +INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 34.3 seconds. CPU system time: 0.6 seconds. Elapsed time: 34.91 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] Starting hardware synthesis ... +INFO: [HLS 200-10] Synthesizing 'myproject' ... +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,1u>,config44>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,1u>,config44>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config44>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,1u>,config44>' to 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 1u>, config2>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0,config2_mult>' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config2>' to 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config2>' to 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config3>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config45>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config45>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config45>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,8u>,config45>' to 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config4>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0,config4_mult>' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config4>' to 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config4>' to 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config5>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s'. +WARNING: [SYN 201-103] Legalizing function name 'clone_stream,array,8u>,32768>' to 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config6>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +WARNING: [SYN 201-103] Legalizing function name 'pooling2d_cl,array,8u>,config6>' to 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config46>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config46>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config46>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,8u>,config46>' to 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config7>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0,config7_mult>' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config7>' to 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,16u>,config7>' to 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config8>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config47>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config47>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config47>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config47>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config9>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config9_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config9>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,16u>,config9>' to 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config10>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s'. +WARNING: [SYN 201-103] Legalizing function name 'clone_stream,array,16u>,16384>' to 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config11>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +WARNING: [SYN 201-103] Legalizing function name 'pooling2d_cl,16u>,config11>' to 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config48>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config48>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config48>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config48>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config12>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config12>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config12>' to 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config13>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config49>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config49>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config49>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config49>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config14>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config14>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config14>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config15>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s'. +WARNING: [SYN 201-103] Legalizing function name 'clone_stream,array,32u>,8192>' to 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config16>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +WARNING: [SYN 201-103] Legalizing function name 'pooling2d_cl,32u>,config16>' to 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config50>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config50>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config50>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config50>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config17>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,64u>,config17>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,64u>,config17>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,64u>,relu_config18>' to 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config51>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,64u>,config51>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config51>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,64u>,config51>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 64u>, config19>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,64u>,config19>' to 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,64u>,config19>' to 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,64u>,relu_config20>' to 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s'. +WARNING: [SYN 201-103] Legalizing function name 'resize_nearest, 64u>, config21>' to 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d_2,96u>,config22>' to 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d,96u>,config22>' to 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config52>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,96u>,config52>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config52>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,96u>,config52>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 96u>, config23>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config23_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config23>' to 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config23>' to 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config24>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config53>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config53>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config53>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config53>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config25>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config25>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config25>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config26>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s'. +WARNING: [SYN 201-103] Legalizing function name 'resize_nearest, 32u>, config27>' to 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d_2,48u>,config28>' to 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d,48u>,config28>' to 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config54>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,48u>,config54>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config54>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,48u>,config54>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 48u>, config29>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config29_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config29>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,16u>,config29>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config30>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config55>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config55>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config55>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config55>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config31>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config31>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,16u>,config31>' to 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config32>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s'. +WARNING: [SYN 201-103] Legalizing function name 'resize_nearest, 16u>, config33>' to 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d_2,24u>,config34>' to 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d,24u>,config34>' to 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config56>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,24u>,config56>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config56>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,24u>,config56>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 24u>, config35>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config35_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config35>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config35>' to 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config36>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config57>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config57>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config57>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,8u>,config57>' to 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config37>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config37>' to 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config37>' to 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config38>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config58_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'pointwise_conv_2d_cl,1u>,config58>' to 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_s'. +WARNING: [SYN 201-103] Legalizing function name 'sigmoid,1u>,sigmoid_config40>' to 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s'. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 4.1 seconds. CPU system time: 0.31 seconds. Elapsed time: 4.45 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.05 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.96 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.99 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 1u>, config2>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 1u>, config2>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.411 ns) exceeds the target (target clock period: 4.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 2.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' consists of the following: + 'or' operation 1 bit ('or_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [82] (0.000 ns) + 'or' operation 1 bit ('or_ln144_2', firmware/nnet_utils/nnet_dense_resource.h:144) [84] (0.000 ns) + 'or' operation 1 bit ('or_ln144_6', firmware/nnet_utils/nnet_dense_resource.h:144) [88] (0.000 ns) + 'select' operation 37 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [89] (0.229 ns) + 'select' operation 37 bit ('acc_87', firmware/nnet_utils/nnet_dense_resource.h:144) [93] (0.229 ns) + multiplexor before 'phi' operation 37 bit ('acc') with incoming values : ('acc_87', firmware/nnet_utils/nnet_dense_resource.h:144) [33] (0.387 ns) + 'phi' operation 37 bit ('acc') with incoming values : ('acc_87', firmware/nnet_utils/nnet_dense_resource.h:144) [33] (0.000 ns) + 'sparsemux' operation 37 bit ('tmp_i', firmware/nnet_utils/nnet_dense_resource.h:144) [70] (0.584 ns) + 'add' operation 38 bit of DSP[73] ('add_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [73] (2.039 ns) + 'icmp' operation 1 bit ('icmp_ln144_17', firmware/nnet_utils/nnet_dense_resource.h:144) [81] (0.943 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.99 seconds. CPU system time: 0.02 seconds. Elapsed time: 1.01 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config4>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config4>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.079 ns) exceeds the target (target clock period: 4.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 2.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s' consists of the following: + 'icmp' operation 1 bit ('icmp_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [328] (0.963 ns) + 'select' operation 40 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [331] (0.230 ns) + 'select' operation 40 bit ('acc_74', firmware/nnet_utils/nnet_dense_resource.h:144) [338] (0.230 ns) + multiplexor before 'phi' operation 40 bit ('acc') with incoming values : ('acc_74', firmware/nnet_utils/nnet_dense_resource.h:144) [153] (0.387 ns) + 'phi' operation 40 bit ('acc') with incoming values : ('acc_74', firmware/nnet_utils/nnet_dense_resource.h:144) [153] (0.000 ns) + 'select' operation 40 bit ('select_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [324] (0.230 ns) + 'add' operation 41 bit of DSP[327] ('add_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [327] (2.039 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.31 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.32 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'CloneLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'CloneLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config6>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config6>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReadInputHeight_ReadInputWidth'. +WARNING: [HLS 200-880] The II Violation in module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' (loop 'ReadInputHeight_ReadInputWidth'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between 'load' operation 16 bit ('void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_32', firmware/nnet_utils/nnet_pooling_stream.h:63->firmware/nnet_utils/nnet_pooling_stream.h:115) on static variable 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel' and 'call' operation 0 bit ('_ln52', firmware/nnet_utils/nnet_pooling_stream.h:52->firmware/nnet_utils/nnet_pooling_stream.h:115) to 'shift_line_buffer, 8u>, config6>'. +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 2, Depth = 4, loop 'ReadInputHeight_ReadInputWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.45 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.48 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config7>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config7>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.079 ns) exceeds the target (target clock period: 4.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 2.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s' consists of the following: + 'icmp' operation 1 bit ('icmp_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [336] (0.963 ns) + 'select' operation 40 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [339] (0.230 ns) + 'select' operation 40 bit ('acc_40', firmware/nnet_utils/nnet_dense_resource.h:144) [346] (0.230 ns) + multiplexor before 'phi' operation 40 bit ('acc') with incoming values : ('acc_40', firmware/nnet_utils/nnet_dense_resource.h:144) [153] (0.387 ns) + 'phi' operation 40 bit ('acc') with incoming values : ('acc_40', firmware/nnet_utils/nnet_dense_resource.h:144) [153] (0.000 ns) + 'select' operation 40 bit ('select_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [332] (0.230 ns) + 'add' operation 41 bit of DSP[335] ('add_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [335] (2.039 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.34 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.36 seconds; current allocated memory: 2.241 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.241 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.241 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.241 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.241 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.241 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.242 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.242 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.242 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.242 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.46 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.48 seconds; current allocated memory: 2.244 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.244 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.244 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.244 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.244 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.244 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config9>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config9>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.244 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.246 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.39 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.39 seconds; current allocated memory: 2.253 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.253 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.253 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.254 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.254 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.255 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.255 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.255 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'CloneLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'CloneLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.256 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.256 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config11>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config11>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.257 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.257 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReadInputHeight_ReadInputWidth'. +WARNING: [HLS 200-880] The II Violation in module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' (loop 'ReadInputHeight_ReadInputWidth'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between 'load' operation 16 bit ('void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_52', firmware/nnet_utils/nnet_pooling_stream.h:63->firmware/nnet_utils/nnet_pooling_stream.h:115) on static variable 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_20' and 'call' operation 0 bit ('_ln52', firmware/nnet_utils/nnet_pooling_stream.h:52->firmware/nnet_utils/nnet_pooling_stream.h:115) to 'shift_line_buffer, 16u>, config11>'. +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 2, Depth = 4, loop 'ReadInputHeight_ReadInputWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.21 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.23 seconds; current allocated memory: 2.258 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.259 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.260 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.260 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.3 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.32 seconds; current allocated memory: 2.260 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.261 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.261 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.261 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.261 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.261 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config12>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config12>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.261 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.263 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.437 ns) exceeds the target (target clock period: 4.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 2.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s' consists of the following: + 'or' operation 1 bit ('or_ln144_76', firmware/nnet_utils/nnet_dense_resource.h:144) [695] (0.122 ns) + 'or' operation 1 bit ('or_ln144_77', firmware/nnet_utils/nnet_dense_resource.h:144) [696] (0.000 ns) + 'select' operation 41 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [697] (0.237 ns) + 'select' operation 41 bit ('acc_568', firmware/nnet_utils/nnet_dense_resource.h:144) [707] (0.237 ns) + multiplexor before 'phi' operation 41 bit ('acc') with incoming values : ('acc_568', firmware/nnet_utils/nnet_dense_resource.h:144) [308] (0.387 ns) + 'phi' operation 41 bit ('acc') with incoming values : ('acc_568', firmware/nnet_utils/nnet_dense_resource.h:144) [308] (0.000 ns) + 'sparsemux' operation 41 bit ('tmp_26_i', firmware/nnet_utils/nnet_dense_resource.h:144) [685] (0.453 ns) + 'add' operation 42 bit of DSP[692] ('add_ln144_64', firmware/nnet_utils/nnet_dense_resource.h:144) [692] (2.039 ns) + 'icmp' operation 1 bit ('icmp_ln144_74', firmware/nnet_utils/nnet_dense_resource.h:144) [693] (0.962 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.65 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.68 seconds; current allocated memory: 2.293 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.293 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.293 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.293 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.293 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.293 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.293 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.293 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.293 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.293 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.3 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.33 seconds; current allocated memory: 2.293 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.293 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.293 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.293 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.293 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.293 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config14>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config14>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.29 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.31 seconds; current allocated memory: 2.293 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.293 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.118 ns) exceeds the target (target clock period: 4.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 2.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s' consists of the following: + 'icmp' operation 1 bit ('icmp_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [1216] (0.962 ns) + 'select' operation 42 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [1219] (0.243 ns) + 'select' operation 42 bit ('acc_526', firmware/nnet_utils/nnet_dense_resource.h:144) [1226] (0.243 ns) + multiplexor before 'phi' operation 42 bit ('acc') with incoming values : ('acc_526', firmware/nnet_utils/nnet_dense_resource.h:144) [585] (0.387 ns) + 'phi' operation 42 bit ('acc') with incoming values : ('acc_526', firmware/nnet_utils/nnet_dense_resource.h:144) [585] (0.000 ns) + 'select' operation 42 bit ('select_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [1212] (0.243 ns) + 'add' operation 43 bit of DSP[1215] ('add_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [1215] (2.039 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.25 seconds. CPU system time: 0.05 seconds. Elapsed time: 1.29 seconds; current allocated memory: 2.312 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.22 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.24 seconds; current allocated memory: 2.312 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.21 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.312 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.312 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.312 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.312 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.312 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.312 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'CloneLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'CloneLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.312 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.312 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config16>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config16>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.312 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.312 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReadInputHeight_ReadInputWidth'. +WARNING: [HLS 200-880] The II Violation in module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' (loop 'ReadInputHeight_ReadInputWidth'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between 'load' operation 16 bit ('void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_42', firmware/nnet_utils/nnet_pooling_stream.h:63->firmware/nnet_utils/nnet_pooling_stream.h:115) on static variable 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_19' and 'call' operation 0 bit ('_ln52', firmware/nnet_utils/nnet_pooling_stream.h:52->firmware/nnet_utils/nnet_pooling_stream.h:115) to 'shift_line_buffer, 32u>, config16>'. +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 2, Depth = 4, loop 'ReadInputHeight_ReadInputWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.32 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.33 seconds; current allocated memory: 2.312 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.312 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.312 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.312 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 7, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 9, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 10, Depth = 11, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.22 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.27 seconds; current allocated memory: 2.312 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.312 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.312 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.312 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.312 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.312 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config17>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config17>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.29 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.31 seconds; current allocated memory: 2.312 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.312 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.327 ns) exceeds the target (target clock period: 4.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 2.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s' consists of the following: + 'xor' operation 1 bit ('xor_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [1497] (0.000 ns) + 'or' operation 1 bit ('or_ln144_63', firmware/nnet_utils/nnet_dense_resource.h:144) [1498] (0.000 ns) + 'or' operation 1 bit ('or_ln144_65', firmware/nnet_utils/nnet_dense_resource.h:144) [1500] (0.000 ns) + 'select' operation 42 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [1501] (0.243 ns) + 'select' operation 42 bit ('acc_418', firmware/nnet_utils/nnet_dense_resource.h:144) [1505] (0.243 ns) + multiplexor before 'phi' operation 42 bit ('acc') with incoming values : ('acc_418', firmware/nnet_utils/nnet_dense_resource.h:144) [647] (0.387 ns) + 'phi' operation 42 bit ('acc') with incoming values : ('acc_418', firmware/nnet_utils/nnet_dense_resource.h:144) [647] (0.000 ns) + 'sparsemux' operation 42 bit ('tmp_22_i', firmware/nnet_utils/nnet_dense_resource.h:144) [1487] (0.453 ns) + 'add' operation 43 bit of DSP[1494] ('add_ln144_46', firmware/nnet_utils/nnet_dense_resource.h:144) [1494] (2.039 ns) + 'icmp' operation 1 bit ('icmp_ln144_53', firmware/nnet_utils/nnet_dense_resource.h:144) [1495] (0.962 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.83 seconds. CPU system time: 0.04 seconds. Elapsed time: 1.87 seconds; current allocated memory: 2.374 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.26 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.27 seconds; current allocated memory: 2.374 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.22 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.26 seconds; current allocated memory: 2.374 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.374 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.374 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.374 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.23 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.25 seconds; current allocated memory: 2.374 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.374 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.374 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.374 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 7, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 9, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 10, Depth = 11, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.26 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.28 seconds; current allocated memory: 2.374 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.374 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.374 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.374 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.374 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.374 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 64u>, config19>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 64u>, config19>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.6 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.62 seconds; current allocated memory: 2.374 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.21 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.23 seconds; current allocated memory: 2.374 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.138 ns) exceeds the target (target clock period: 4.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 2.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s' consists of the following: + 'icmp' operation 1 bit ('icmp_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [2400] (0.961 ns) + 'select' operation 43 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [2404] (0.250 ns) + 'select' operation 43 bit ('acc_287', firmware/nnet_utils/nnet_dense_resource.h:144) [2411] (0.250 ns) + multiplexor before 'phi' operation 43 bit ('acc') with incoming values : ('acc_287', firmware/nnet_utils/nnet_dense_resource.h:144) [1160] (0.387 ns) + 'phi' operation 43 bit ('acc') with incoming values : ('acc_287', firmware/nnet_utils/nnet_dense_resource.h:144) [1160] (0.000 ns) + 'select' operation 43 bit ('select_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [2396] (0.250 ns) + 'add' operation 44 bit of DSP[2399] ('add_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [2399] (2.039 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 2.36 seconds. CPU system time: 0.03 seconds. Elapsed time: 2.37 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.48 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.51 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.31 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.36 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.25 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.27 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ImageHeight'. +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_1', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_2', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_3', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_4', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 32, Depth = 32, loop 'ImageHeight' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.38 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.41 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ConcatLoopHeight_ConcatLoopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'ConcatLoopHeight_ConcatLoopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.32 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.36 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 96u>, config23>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 96u>, config23>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 1.08 seconds; current allocated memory: 2.379 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.31 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.32 seconds; current allocated memory: 2.383 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 2.4 seconds. CPU system time: 0.06 seconds. Elapsed time: 2.46 seconds; current allocated memory: 2.440 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.81 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.85 seconds; current allocated memory: 2.440 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.45 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.49 seconds; current allocated memory: 2.440 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.440 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.26 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.26 seconds; current allocated memory: 2.440 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.440 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.24 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.27 seconds; current allocated memory: 2.440 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.440 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.440 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.440 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.34 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.38 seconds; current allocated memory: 2.440 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.440 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.440 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.440 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.440 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.440 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config25>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config25>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.31 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.33 seconds; current allocated memory: 2.440 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.440 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.449 ns) exceeds the target (target clock period: 4.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 2.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s' consists of the following: + 'or' operation 1 bit ('or_ln144_12', firmware/nnet_utils/nnet_dense_resource.h:144) [1271] (0.122 ns) + 'or' operation 1 bit ('or_ln144_13', firmware/nnet_utils/nnet_dense_resource.h:144) [1272] (0.000 ns) + 'select' operation 42 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [1273] (0.243 ns) + 'select' operation 42 bit ('acc_137', firmware/nnet_utils/nnet_dense_resource.h:144) [1283] (0.243 ns) + multiplexor before 'phi' operation 42 bit ('acc') with incoming values : ('acc_137', firmware/nnet_utils/nnet_dense_resource.h:144) [596] (0.387 ns) + 'phi' operation 42 bit ('acc') with incoming values : ('acc_137', firmware/nnet_utils/nnet_dense_resource.h:144) [596] (0.000 ns) + 'sparsemux' operation 42 bit ('tmp_4_i', firmware/nnet_utils/nnet_dense_resource.h:144) [1261] (0.453 ns) + 'add' operation 43 bit of DSP[1268] ('add_ln144_17', firmware/nnet_utils/nnet_dense_resource.h:144) [1268] (2.039 ns) + 'icmp' operation 1 bit ('icmp_ln144_35', firmware/nnet_utils/nnet_dense_resource.h:144) [1269] (0.962 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.12 seconds. CPU system time: 0.06 seconds. Elapsed time: 1.18 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.25 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.26 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.22 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.24 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.22 seconds. CPU system time: 0 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ImageHeight'. +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_1', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_2', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_3', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_4', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 64, Depth = 64, loop 'ImageHeight' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.68 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.72 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ConcatLoopHeight_ConcatLoopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'ConcatLoopHeight_ConcatLoopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.55 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.57 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 48u>, config29>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 48u>, config29>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.46 seconds. CPU system time: 0 seconds. Elapsed time: 0.47 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1 seconds. CPU system time: 0.01 seconds. Elapsed time: 1.01 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.34 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.36 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.25 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.28 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.21 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.54 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.58 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config31>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config31>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.22 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.23 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.315 ns) exceeds the target (target clock period: 4.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 2.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s' consists of the following: + 'xor' operation 1 bit ('xor_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [679] (0.000 ns) + 'or' operation 1 bit ('or_ln144_24', firmware/nnet_utils/nnet_dense_resource.h:144) [680] (0.000 ns) + 'or' operation 1 bit ('or_ln144_26', firmware/nnet_utils/nnet_dense_resource.h:144) [682] (0.000 ns) + 'select' operation 41 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [683] (0.237 ns) + 'select' operation 41 bit ('acc_116', firmware/nnet_utils/nnet_dense_resource.h:144) [687] (0.237 ns) + multiplexor before 'phi' operation 41 bit ('acc') with incoming values : ('acc_116', firmware/nnet_utils/nnet_dense_resource.h:144) [311] (0.387 ns) + 'phi' operation 41 bit ('acc') with incoming values : ('acc_116', firmware/nnet_utils/nnet_dense_resource.h:144) [311] (0.000 ns) + 'sparsemux' operation 41 bit ('tmp_24_i', firmware/nnet_utils/nnet_dense_resource.h:144) [669] (0.453 ns) + 'add' operation 42 bit of DSP[676] ('add_ln144_14', firmware/nnet_utils/nnet_dense_resource.h:144) [676] (2.039 ns) + 'icmp' operation 1 bit ('icmp_ln144_28', firmware/nnet_utils/nnet_dense_resource.h:144) [677] (0.962 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.53 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.57 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.488 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ImageHeight'. +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_1', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_2', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_3', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_4', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 67, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 98, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 114, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 122, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 126, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 127, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 128, Depth = 128, loop 'ImageHeight' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.75 seconds. CPU system time: 0.06 seconds. Elapsed time: 1.8 seconds; current allocated memory: 2.503 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.503 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ConcatLoopHeight_ConcatLoopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'ConcatLoopHeight_ConcatLoopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.503 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.503 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.503 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.503 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.503 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.503 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.15 seconds. CPU system time: 0.03 seconds. Elapsed time: 1.18 seconds; current allocated memory: 2.503 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.503 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.503 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.503 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.503 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.503 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 24u>, config35>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 24u>, config35>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.28 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.29 seconds; current allocated memory: 2.503 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.503 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.52 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.54 seconds; current allocated memory: 2.503 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.2 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.503 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.503 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.503 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.503 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.503 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.503 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.503 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.503 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.503 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.14 seconds. CPU system time: 0.03 seconds. Elapsed time: 1.17 seconds; current allocated memory: 2.508 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.508 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.508 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.508 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.508 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.508 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config37>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config37>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.508 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.508 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.424 ns) exceeds the target (target clock period: 4.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 2.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s' consists of the following: + 'or' operation 1 bit ('or_ln144_9', firmware/nnet_utils/nnet_dense_resource.h:144) [333] (0.122 ns) + 'or' operation 1 bit ('or_ln144_10', firmware/nnet_utils/nnet_dense_resource.h:144) [334] (0.000 ns) + 'select' operation 40 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [335] (0.230 ns) + 'select' operation 40 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [345] (0.230 ns) + multiplexor before 'phi' operation 40 bit ('acc') with incoming values : ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [152] (0.387 ns) + 'phi' operation 40 bit ('acc') with incoming values : ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [152] (0.000 ns) + 'sparsemux' operation 40 bit ('tmp_i', firmware/nnet_utils/nnet_dense_resource.h:144) [324] (0.453 ns) + 'add' operation 41 bit of DSP[327] ('add_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [327] (2.039 ns) + 'icmp' operation 1 bit ('icmp_ln144_20', firmware/nnet_utils/nnet_dense_resource.h:144) [331] (0.963 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.36 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.38 seconds; current allocated memory: 2.510 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.510 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.510 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.510 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.510 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.510 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.510 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.510 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.510 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.510 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.510 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.511 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'SigmoidActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 5, loop 'SigmoidActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.511 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.512 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'myproject' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +WARNING: [HLS 200-1020] Increasing the depth of FIFO start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0 (from clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0 to concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0) to 10 to improve performance and/or avoid deadlocks. +WARNING: [HLS 200-1020] Increasing the depth of FIFO start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0 (from clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_U0 to concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0) to 26 to improve performance and/or avoid deadlocks. +WARNING: [HLS 200-1020] Increasing the depth of FIFO start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0 (from clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0 to concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0) to 42 to improve performance and/or avoid deadlocks. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.42 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.44 seconds; current allocated memory: 2.512 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.34 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.35 seconds; current allocated memory: 2.522 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.7 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.74 seconds; current allocated memory: 2.523 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.526 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.2 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.529 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.530 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_cud' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.530 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_outidx_1_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_oudEe' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_w2_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_w2eOg' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_37s_38_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_17_3_37_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_19_4_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_oudEe' using auto ROMs. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_w2eOg' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.35 seconds; current allocated memory: 2.534 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_7' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.43 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.48 seconds; current allocated memory: 2.536 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.537 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.538 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.14 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.540 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.543 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.545 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.546 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1375_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_fYi' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1383_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_g8j' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1376_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_hbi' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1384_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_ibs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1377_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_jbC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1385_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_kbM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1378_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_lbW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1386_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_mb6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1379_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_ncg' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1387_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_ocq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1380_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_pcA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1388_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_qcK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1381_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_rcU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1389_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_sc4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1382_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_tde' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1390_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_udo' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.5 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.53 seconds; current allocated memory: 2.548 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_outidx_2_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_ouvdy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_w4_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_w4wdI' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_40s_41_1_1': 3 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_40s_41_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_ouvdy' using auto ROMs. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_w4wdI' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.38 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.42 seconds; current allocated memory: 2.553 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_13' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.93 seconds. CPU system time: 0.2 seconds. Elapsed time: 2.14 seconds; current allocated memory: 2.562 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.565 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.566 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.567 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stxdS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_styd2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stzec' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stAem' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stBew' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stCeG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stDeQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stEe0' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.31 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.34 seconds; current allocated memory: 2.570 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'sY' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX' is power-on initialization. +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' pipeline 'ReadInputHeight_ReadInputWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.03 seconds. CPU system time: 0.08 seconds. Elapsed time: 1.1 seconds; current allocated memory: 2.572 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.2 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.576 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.579 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.581 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.581 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1359_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Ffa' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1367_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Gfk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1360_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Hfu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1368_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_IfE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1361_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_JfO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1369_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_KfY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1362_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Lf8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1370_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Mgi' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1363_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Ngs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1371_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_OgC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1364_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_PgM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1372_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_QgW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1365_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Rg6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1373_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Shg' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1366_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Thq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1374_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_UhA' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.5 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.55 seconds; current allocated memory: 2.583 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_outidx_3_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_ouVhK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_w7_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_w7WhU' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_11s_40s_41_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_40s_41_1_1': 7 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_w7WhU' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.4 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.43 seconds; current allocated memory: 2.591 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_38' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_30' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_39' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_31' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_32' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_33' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_34' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_35' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_36' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_37' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_15' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 2 seconds. CPU system time: 0.21 seconds. Elapsed time: 2.2 seconds; current allocated memory: 2.600 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.602 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.604 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.605 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.609 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.611 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.11 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.611 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_799_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dXh4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_815_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dYie' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_800_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dZio' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_816_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d0iy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_807_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d1iI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_823_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d2iS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_808_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d3i2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_824_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d4jc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_809_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d5jm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_825_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d6jw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_810_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d7jG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_826_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d8jQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_811_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d9j0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_827_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbak' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_812_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbbk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_828_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbck' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_813_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbdk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_829_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbek' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_814_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbfk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_830_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbgk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_801_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbhl' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_817_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbil' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_802_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbjl' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_818_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbkl' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_803_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbll' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_819_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbml' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_804_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbnm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_820_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbom' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_805_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbpm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_821_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbqm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_806_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbrm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_822_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbsm' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.91 seconds. CPU system time: 0.09 seconds. Elapsed time: 0.99 seconds; current allocated memory: 2.613 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbtn' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_11s_34s_34_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_39s_39_1_1': 15 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_289_8_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbtn' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.45 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.5 seconds; current allocated memory: 2.625 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4177' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4178' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4179' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4180' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4181' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4182' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4183' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4184' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4185' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4186' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4188' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4122' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4189' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4134' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4190' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4191' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4192' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4137' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4123' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4124' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4125' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4126' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4127' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4128' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4129' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4130' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4131' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4133' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4135' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4136' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_9' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 3.94 seconds. CPU system time: 0.38 seconds. Elapsed time: 4.34 seconds; current allocated memory: 2.643 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.23 seconds; current allocated memory: 2.646 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.648 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.650 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bun' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bvn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bwn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bxn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_byn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bzo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bAo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bBo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bCo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bDo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_27_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbEo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_26_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbFp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_25_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbGp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_24_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbHp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_23_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbIp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_22_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbJp' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.53 seconds. CPU system time: 0.06 seconds. Elapsed time: 0.59 seconds; current allocated memory: 2.653 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'sY_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_11' is power-on initialization. +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' pipeline 'ReadInputHeight_ReadInputWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.91 seconds. CPU system time: 0.23 seconds. Elapsed time: 2.14 seconds; current allocated memory: 2.658 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.24 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.28 seconds; current allocated memory: 2.664 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.665 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.668 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.668 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_863_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_879_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bLp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_864_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bMq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_880_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bNq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_871_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bOq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_887_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bPq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_872_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bQq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_888_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bRq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_873_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bSr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_889_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bTr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_874_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bUr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_890_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bVr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_875_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bWr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_891_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bXr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_876_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bYs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_892_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bZs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_877_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b0s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_893_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b1s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_878_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b2s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_894_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b3s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_865_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b4t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_881_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b5t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_866_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b6t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_882_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b7t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_867_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b8t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_883_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b9t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_868_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2cau' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_884_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2cbu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_869_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2ccu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_885_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2cdu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_870_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2ceu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_886_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2cfu' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.97 seconds. CPU system time: 0.1 seconds. Elapsed time: 1.07 seconds; current allocated memory: 2.671 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s_outidx_4_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s_outidx_4_ROM_cgu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s_w12_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s_w12_ROM_NP_BRchv' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_41s_42_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_41s_42_1_1': 7 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_289_8_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_9_2_41_1_1': 8 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s_outidx_4_ROM_cgu' using auto ROMs. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s_w12_ROM_NP_BRchv' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.61 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.66 seconds; current allocated memory: 2.685 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4416' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4428' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4441' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4453' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4465' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4432' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4433' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4434' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4435' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4436' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4417' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4437' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4419' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4438' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4420' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4439' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4421' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4442' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4422' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4443' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4423' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4444' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4424' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4445' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4425' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4446' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4426' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4447' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4427' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4448' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4430' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4449' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4431' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4450' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4452' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4454' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4455' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4456' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4457' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4458' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4459' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4460' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4461' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4463' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4464' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4466' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4467' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4468' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4469' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_8' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.15 seconds. CPU system time: 0.47 seconds. Elapsed time: 4.62 seconds; current allocated memory: 2.706 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.22 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.24 seconds; current allocated memory: 2.709 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.2 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.24 seconds; current allocated memory: 2.712 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.21 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.24 seconds; current allocated memory: 2.717 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.718 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.718 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_943_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2civ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_975_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cjv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_944_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2ckv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_976_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2clv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_955_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cmv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_987_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cnw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_966_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cow' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_998_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cpw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_969_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cqw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1001_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2crw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_970_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2csw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1002_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2ctx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_971_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cux' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1003_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cvx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_972_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cwx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1004_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cxx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_973_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cyx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1005_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2czy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_974_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cAy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1006_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cBy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_945_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cCy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_977_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cDy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_946_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cEy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_978_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cFz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_947_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cGz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_979_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cHz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_948_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cIz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_980_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cJz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_949_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cKz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_981_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cLz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_950_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cMA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_982_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cNA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_951_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cOA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_983_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cPA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_952_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cQA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_984_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cRA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_953_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cSB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_985_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cTB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_954_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cUB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_986_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cVB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_956_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cWB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_988_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cXB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_957_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cYC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_989_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cZC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_958_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c0C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_990_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c1C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_959_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c2C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_991_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c3C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_960_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c4D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_992_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c5D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_961_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c6D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_993_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c7D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_962_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c8D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_994_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c9D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_963_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2daE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_995_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dbE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_964_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dcE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_996_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2ddE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_965_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2deE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_997_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dfE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_967_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dgE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_999_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dhF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_968_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2diF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1000_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2djF' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.85 seconds. CPU system time: 0.2 seconds. Elapsed time: 2.05 seconds; current allocated memory: 2.725 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_outidx_5_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_outidx_5_ROM_dkF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_w14_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_w14_ROM_NP_BRdlF' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s' is 9216, found 2 HDL expressions with this fanout: (ap_phi_mux_do_init_phi_fu_1359_p6 == 1'd1), (ap_phi_mux_do_init_phi_fu_1359_p6 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_42s_43_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_42s_43_1_1': 15 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_577_9_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_outidx_5_ROM_dkF' using auto ROMs. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_w14_ROM_NP_BRdlF' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.79 seconds. CPU system time: 0.08 seconds. Elapsed time: 0.86 seconds; current allocated memory: 2.749 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5021' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_89' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5022' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_88' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5024' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_87' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5025' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_86' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5026' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_85' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5027' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_84' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5028' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_83' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5029' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_82' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5030' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_81' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5031' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_80' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5032' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5033' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5035' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5036' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5037' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4839' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5038' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4851' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5039' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4863' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5040' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4875' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5041' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4887' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5042' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4899' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5043' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4911' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5044' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4923' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5046' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4936' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5047' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4948' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5048' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4960' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5049' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4972' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5050' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4984' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5051' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4996' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5052' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5008' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5053' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5018' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5054' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5019' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5055' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5020' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5092' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5093' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5094' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5095' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4840' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4841' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4842' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4843' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4844' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4845' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4846' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4848' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4849' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4850' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4852' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4853' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4854' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4855' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4856' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4857' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4859' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4860' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4861' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4862' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4941' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4903' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4942' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4904' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4943' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4905' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4944' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4906' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4945' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4907' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4947' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4908' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4949' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4909' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4950' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4910' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4951' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4912' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4952' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4914' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4953' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4915' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4954' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4916' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4955' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4917' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4956' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4918' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4958' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4919' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4959' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4920' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4961' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4921' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4962' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4922' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4963' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4925' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4964' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4926' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4965' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4927' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4966' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4928' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4967' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4929' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4969' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4930' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4970' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4931' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4971' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4932' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4973' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4933' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4974' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4934' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4975' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4937' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4976' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4938' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4977' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4939' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4978' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4940' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5057' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5058' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5059' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5060' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5061' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5062' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5063' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5064' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5065' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5066' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5068' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5069' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5070' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5071' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5072' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5073' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5074' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5075' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5076' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5077' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5079' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5080' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5081' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5082' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5083' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5084' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5085' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5086' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5087' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5088' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5090' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5091' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4864' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4865' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4866' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4867' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4868' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4870' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4871' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4872' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4873' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4874' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4876' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4877' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4878' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4879' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4881' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4882' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4883' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4884' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4885' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4886' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4888' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4889' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4890' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4892' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4893' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4894' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4895' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4896' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4897' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4898' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4900' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4901' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4980' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4981' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4982' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4983' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4985' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4986' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4987' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4988' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4989' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4991' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4992' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4993' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4994' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4995' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4997' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4998' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5000' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5002' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5003' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5004' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5005' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5006' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5007' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5009' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5010' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5011' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5013' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5014' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5015' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5016' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5017' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_5' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 8.52 seconds. CPU system time: 0.78 seconds. Elapsed time: 9.31 seconds; current allocated memory: 2.785 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.28 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.3 seconds; current allocated memory: 2.790 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.27 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.28 seconds; current allocated memory: 2.794 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.797 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dmF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dnG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_doG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dpG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dqG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_drG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dsG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dtH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_duH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dvH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_21_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindwH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_20_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindxH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_19_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindyH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_18_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindzI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_17_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindAI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_16_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindBI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_15_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindCI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_14_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindDI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_13_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindEI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_12_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindFJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_11_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindGJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_10_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindHJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindIJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindJJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindKJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindLJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindMK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindNK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindOK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindPK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindQK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindRK' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.07 seconds. CPU system time: 0.11 seconds. Elapsed time: 1.17 seconds; current allocated memory: 2.800 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'sY_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_89' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_57' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_88' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_56' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_87' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_55' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_86' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_54' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_85' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_53' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_84' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_52' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_83' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_51' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_82' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_50' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_81' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_49' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_80' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_48' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_79' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_47' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_78' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_46' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_77' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_45' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_76' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_44' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_75' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_43' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_74' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_42' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_73' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_41' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_72' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_40' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_71' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_39' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_70' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_38' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_69' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_37' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_68' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_36' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_99' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_67' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_35' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_98' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_66' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_34' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_97' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_65' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_33' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_96' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_64' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_32' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_95' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_63' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_31' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_94' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_62' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_30' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_93' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_61' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_92' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_60' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_91' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_59' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_90' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_58' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_3' is power-on initialization. +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' pipeline 'ReadInputHeight_ReadInputWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4 seconds. CPU system time: 0.46 seconds. Elapsed time: 4.47 seconds; current allocated memory: 2.812 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.33 seconds. CPU system time: 0.07 seconds. Elapsed time: 0.4 seconds; current allocated memory: 2.822 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.823 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.21 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.23 seconds; current allocated memory: 2.826 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.826 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1071_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dSL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1103_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dTL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1072_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dUL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1104_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dVL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1083_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dWL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1115_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dXL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1094_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dYM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1126_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dZM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1097_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d0M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1129_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d1M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1098_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d2M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1130_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d3M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1099_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d4N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1131_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d5N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1100_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d6N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1132_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d7N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1101_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d8N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1133_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d9N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1102_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eaO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1134_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ebO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1073_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ecO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1105_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2edO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1074_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eeO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1106_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2efO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1075_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2egO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1107_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ehP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1076_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eiP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1108_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ejP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1077_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ekP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1109_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2elP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1078_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2emP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1110_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2enQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1079_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eoQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1111_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2epQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1080_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eqQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1112_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2erQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1081_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2esQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1113_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2etR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1082_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2euR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1114_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2evR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1084_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ewR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1116_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2exR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1085_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eyR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1117_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ezS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1086_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eAS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1118_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eBS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1087_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eCS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1119_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eDS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1088_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eES' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1120_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eFT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1089_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eGT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1121_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eHT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1090_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eIT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1122_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eJT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1091_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eKT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1123_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eLT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1092_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eMU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1124_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eNU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1093_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eOU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1125_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ePU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1095_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eQU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1127_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eRU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1096_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eSV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1128_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eTV' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 2.1 seconds. CPU system time: 0.18 seconds. Elapsed time: 2.28 seconds; current allocated memory: 2.831 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s_outidx_6_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s_outidx_6_ROM_eUV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s_w17_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s_w17_ROM_NP_BReVV' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s' is 9216 from HDL expression: (do_init_reg_1434 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_42s_43_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_42s_43_1_1': 15 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_577_9_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_9_2_42_1_1': 16 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s_outidx_6_ROM_eUV' using auto ROMs. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s_w17_ROM_NP_BReVV' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1 seconds. CPU system time: 0.08 seconds. Elapsed time: 1.08 seconds; current allocated memory: 2.866 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_69' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_68' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_67' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_66' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_65' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_64' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_63' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_62' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_61' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_60' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5402' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5414' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5426' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5438' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5450' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5462' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5436' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5437' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5439' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5440' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5442' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5403' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5443' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5404' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5444' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5405' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5445' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5406' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5446' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5407' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5447' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5409' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5448' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5410' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5449' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5411' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5451' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5412' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5453' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5413' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5454' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5415' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5455' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5416' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5456' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5417' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5457' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5418' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5458' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5420' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5459' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5421' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5460' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5422' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5461' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5423' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5464' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5424' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5465' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5425' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5466' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5427' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5467' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5428' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5468' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5429' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5469' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5431' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5432' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5433' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5434' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5435' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_10' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 9.6 seconds. CPU system time: 0.91 seconds. Elapsed time: 10.52 seconds; current allocated memory: 2.907 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.33 seconds; current allocated memory: 2.913 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.34 seconds; current allocated memory: 2.917 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.29 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.32 seconds; current allocated memory: 2.923 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.21 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.24 seconds; current allocated memory: 2.924 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.21 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.24 seconds; current allocated memory: 2.925 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.926 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1231_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eWV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1295_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eXV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1232_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eYW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1296_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eZW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1243_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e0W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1307_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e1W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1254_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e2W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1318_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e3W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1265_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e4X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1329_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e5X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1276_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e6X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1340_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e7X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1287_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e8X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1351_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e9X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1292_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2faY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1356_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fbY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1293_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fcY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1357_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fdY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1294_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2feY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1358_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ffY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1233_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fgY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1297_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fhZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1234_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fiZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1298_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fjZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1235_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fkZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1299_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2flZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1236_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fmZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1300_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fn0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1237_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fo0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1301_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fp0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1238_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fq0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1302_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fr0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1239_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fs0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1303_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ft1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1240_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fu1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1304_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fv1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1241_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fw1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1305_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fx1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1242_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fy1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1306_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fz2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1244_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fA2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1308_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fB2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1245_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fC2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1309_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fD2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1246_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fE2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1310_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fF3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1247_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fG3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1311_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fH3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1248_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fI3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1312_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fJ3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1249_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fK3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1313_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fL3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1250_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fM4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1314_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fN4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1251_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fO4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1315_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fP4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1252_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fQ4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1316_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fR4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1253_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fS5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1317_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fT5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1255_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fU5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1319_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fV5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1256_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fW5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1320_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fX5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1257_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fY6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1321_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fZ6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1258_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f06' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1322_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f16' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1259_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f26' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1323_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f36' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1260_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f47' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1324_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f57' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1261_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f67' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1325_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f77' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1262_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f87' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1326_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f97' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1263_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ga8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1327_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gb8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1264_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gc8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1328_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gd8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1266_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ge8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1330_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gf8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1267_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gg8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1331_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gh9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1268_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gi9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1332_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gj9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1269_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gk9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1333_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gl9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1270_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gm9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1334_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1271_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1335_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1272_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1336_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2grb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1273_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1337_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gtb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1274_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1338_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1275_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1339_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1277_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1341_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1278_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gAb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1342_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gBb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1279_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gCb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1343_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gDb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1280_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gEb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1344_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gFb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1281_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gGb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1345_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gHb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1282_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gIb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1346_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gJb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1283_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gKb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1347_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gLb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1284_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gMb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1348_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1285_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1349_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1286_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1350_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1288_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1352_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1289_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1353_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1290_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1354_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1291_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1355_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gZb_x' due to conflict. +INFO: [RTGEN 206-104] Estimated max fanout for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s' is 9216 from HDL expression: (1'b1 == ap_CS_fsm_state1) +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.67 seconds. CPU system time: 0.53 seconds. Elapsed time: 5.2 seconds; current allocated memory: 2.938 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s_outidx_7_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s_outidx_7_ROM_g0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s_w19_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s_w19_ROM_NP_BRg1b' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s' is 18432, found 2 HDL expressions with this fanout: (ap_phi_mux_do_init_phi_fu_2639_p6 == 1'd1), (ap_phi_mux_do_init_phi_fu_2639_p6 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_43s_44_1_1': 31 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_43s_44_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_1153_10_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s_outidx_7_ROM_g0b' using auto ROMs. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s_w19_ROM_NP_BRg1b' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.44 seconds. CPU system time: 0.11 seconds. Elapsed time: 1.55 seconds; current allocated memory: 2.992 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_49' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_48' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_47' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_46' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_45' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_44' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_43' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_42' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_41' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_40' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6184' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6293' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6305' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6317' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6329' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6341' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6353' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6366' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6378' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6390' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6402' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6414' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6426' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6438' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6450' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6462' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6177' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6179' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6180' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6181' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6182' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6183' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6185' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6186' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6187' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6188' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6190' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6191' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6192' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6361' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6362' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6363' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6364' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6287' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6367' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6289' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6368' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6290' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6369' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6291' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6370' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6292' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6371' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6294' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6372' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6295' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6373' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6296' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6374' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6297' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6375' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6298' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6377' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6300' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6379' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6301' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6380' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6302' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6381' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6303' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6382' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6304' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6383' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6306' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6384' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6307' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6385' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6308' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6386' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6309' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6388' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6311' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6389' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6312' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6391' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6313' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6392' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6314' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6393' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6315' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6394' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6316' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6395' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6318' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6396' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6319' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6397' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6320' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6399' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6322' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6400' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6323' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6401' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6324' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6403' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6325' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6404' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6326' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6405' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6327' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6406' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6328' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6407' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6330' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6408' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6331' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6410' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6333' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6411' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6334' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6412' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6335' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6413' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6336' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6415' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6337' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6416' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6338' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6417' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6339' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6418' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6340' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6419' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6342' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6421' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6344' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6422' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6345' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6423' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6346' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6424' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6347' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6425' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6348' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6427' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6349' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6428' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6350' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6429' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6351' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6430' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6352' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6432' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6355' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6433' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6356' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6434' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6357' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6435' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6358' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6436' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6359' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6437' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6360' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6439' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6440' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6441' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6443' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6444' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6445' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6446' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6447' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6448' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6449' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6451' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6452' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6454' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6455' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6456' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6457' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6458' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6459' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6460' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6461' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6463' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6465' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6466' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6467' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6468' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6469' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_16' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 20.58 seconds. CPU system time: 1.92 seconds. Elapsed time: 22.52 seconds; current allocated memory: 3.061 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.46 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.48 seconds; current allocated memory: 3.070 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.38 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.42 seconds; current allocated memory: 3.076 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.3 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.32 seconds; current allocated memory: 3.082 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' pipeline 'ConcatLoopHeight_ConcatLoopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.24 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.28 seconds; current allocated memory: 3.084 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.22 seconds. CPU system time: 0 seconds. Elapsed time: 0.22 seconds; current allocated memory: 3.085 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.24 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.26 seconds; current allocated memory: 3.085 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.25 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.27 seconds; current allocated memory: 3.088 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.26 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.28 seconds; current allocated memory: 3.089 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.21 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.22 seconds; current allocated memory: 3.091 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1407_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_95_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1408_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_94_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1419_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_83_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1430_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_72_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1441_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_61_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1452_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_50_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1463_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2heb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_39_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1474_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_28_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1485_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_17_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1496_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hlb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1409_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_93_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1410_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_92_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1411_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_91_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1412_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_90_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2htb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1413_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_89_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1414_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_88_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1415_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_87_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1416_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_86_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1417_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_85_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1418_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_84_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1420_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_82_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1421_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_81_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1422_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_80_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1423_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_79_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1424_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_78_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1425_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_77_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1426_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_76_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1427_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_75_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1428_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_74_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1429_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_73_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1431_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_71_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1432_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_70_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1433_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_69_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1434_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_68_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1435_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_67_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1436_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_66_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ibb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1437_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2icb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_65_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2idb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1438_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ieb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_64_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ifb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1439_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2igb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_63_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ihb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1440_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_62_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ijb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1442_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ikb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_60_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ilb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1443_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2imb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_59_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2inb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1444_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_58_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ipb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1445_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_57_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2irb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1446_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2isb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_56_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2itb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1447_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_55_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ivb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1448_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_54_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ixb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1449_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_53_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2izb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1450_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_52_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1451_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_51_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1453_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_49_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1454_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_48_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1455_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_47_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1456_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_46_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1457_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_45_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1458_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_44_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1459_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_43_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1460_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_42_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1461_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_41_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1462_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_40_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1464_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_38_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1465_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_37_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1466_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_36_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1467_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_35_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1468_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_34_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1469_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_33_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1470_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_32_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1471_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_31_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1472_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jeb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_30_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1473_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_29_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1475_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_27_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1476_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_26_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jlb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1477_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_25_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1478_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2job' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_24_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1479_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_23_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1480_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_22_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jtb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1481_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_21_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1482_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_20_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1483_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_19_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1484_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_18_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1486_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_16_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1487_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_15_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1488_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_14_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1489_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_13_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1490_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_12_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1491_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_11_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1492_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_10_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1493_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1494_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1495_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1497_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1498_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_99_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_98_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_97_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_96_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j7b' due to the length limit 80 +INFO: [RTGEN 206-104] Estimated max fanout for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s' is 13824 from HDL expression: (1'b1 == ap_CS_fsm_state1) +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 10.4 seconds. CPU system time: 0.98 seconds. Elapsed time: 11.39 seconds; current allocated memory: 3.110 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_w23_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_w23_Rj8b' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' is 27648 from HDL expression: (do_init_reg_3699 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_41s_41_1_1': 31 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_34s_34_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_1729_10_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_w23_Rj8b' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.79 seconds. CPU system time: 0.15 seconds. Elapsed time: 1.96 seconds; current allocated memory: 3.175 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3846' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3857' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3868' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3879' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3890' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3901' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3912' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3923' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3934' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3945' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3956' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3967' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3978' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3989' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4000' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4011' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4022' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4033' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4044' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4055' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4066' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4077' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4088' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4099' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4110' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4121' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4363' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4847' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4968' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5089' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5331' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5452' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5936' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6057' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6178' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6299' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6420' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_94' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_83' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_72' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_61' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_50' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_39' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3928' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3929' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3930' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3931' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3932' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3933' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3935' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3936' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3937' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3938' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3939' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3940' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3941' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3942' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3943' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3944' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3839' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3946' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3840' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3947' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3841' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3948' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3842' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3949' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3843' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3950' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3844' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3951' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3845' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3952' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3847' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3953' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3848' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3954' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3849' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3955' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3850' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3957' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3851' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3958' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3852' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3959' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3853' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3960' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3854' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3961' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3855' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3962' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3856' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3963' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3858' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3964' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3859' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3965' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3860' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3966' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3861' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3968' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3862' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3969' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3863' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3970' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3864' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3971' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3865' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3972' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3866' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3973' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3867' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3974' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3869' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3975' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3870' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3976' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3871' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3977' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3872' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3979' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3873' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3980' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3874' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3981' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3875' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3982' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3876' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3983' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3877' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3984' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3878' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3985' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3880' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3986' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3881' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3987' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3882' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3988' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3883' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3990' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3884' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3991' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3885' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3992' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3886' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3993' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3887' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3994' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3888' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3995' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3889' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3996' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3891' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3997' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3892' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3998' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3893' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3894' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4001' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3895' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4002' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3896' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4003' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3897' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4004' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3898' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4005' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3899' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4006' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3900' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4007' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3902' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4008' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3903' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4009' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3904' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4010' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3905' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4012' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3906' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4013' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3907' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4014' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3908' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4015' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3909' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4016' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3910' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4017' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3911' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4018' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3913' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4019' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3914' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4020' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3915' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4021' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3916' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4023' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3917' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4024' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3918' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4025' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3919' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4026' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3920' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4027' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3921' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4028' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3922' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4029' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3924' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4030' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3925' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4031' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3926' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4032' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3927' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4319' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4330' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4341' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4352' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4374' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4385' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4396' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4407' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4418' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4429' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4440' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4451' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4462' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5848' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5859' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5870' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5881' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5892' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5903' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5914' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5925' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5947' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5958' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5969' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5980' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5991' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6002' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6013' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4858' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6024' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4869' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6035' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4880' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6046' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4891' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6068' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4902' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6079' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4913' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6090' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4924' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6101' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4935' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6112' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4946' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6123' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4957' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6134' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4979' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4990' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5001' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5012' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6189' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5023' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5034' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5045' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5056' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5067' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5078' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5100' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5111' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5122' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6288' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5133' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6310' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6321' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6332' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6343' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5177' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6354' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5188' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6365' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6376' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6387' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6398' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6409' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6431' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6442' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6453' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5287' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6464' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5298' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5309' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5320' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5342' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5353' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5364' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5375' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5386' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5397' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5408' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5419' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5430' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5441' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5463' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4034' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4035' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4036' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4037' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4038' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4039' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4040' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4041' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4042' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4043' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4045' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4046' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4047' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4048' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4049' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4050' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4051' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4052' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4053' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4054' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4056' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4057' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4058' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4059' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4060' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4061' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4062' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4063' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4064' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4065' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4067' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4068' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4069' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4070' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4071' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4072' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4073' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4074' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4075' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4076' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4078' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4079' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4080' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4081' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4082' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4083' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4084' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4085' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4086' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4087' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4089' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4090' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4091' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4092' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4093' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4094' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4095' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4096' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4097' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4098' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4100' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4101' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4102' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4103' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4104' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4105' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4106' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4107' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4108' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4109' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4111' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4112' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4113' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4114' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4115' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4116' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4117' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4118' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4119' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4120' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4132' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4187' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4297' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4308' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_99' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_98' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_97' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_96' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_95' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_93' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_92' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_91' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_90' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_89' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_88' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_87' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_86' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_85' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_84' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_82' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_81' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_80' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_79' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_78' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_77' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_76' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_75' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_74' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_73' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_71' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_70' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_69' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_68' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_67' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_66' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_65' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_64' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_63' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_62' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_60' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_59' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_58' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_57' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_56' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_55' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_54' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_53' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_52' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_51' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_49' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_48' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_47' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_46' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_45' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_44' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_43' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_42' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_41' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_40' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_38' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_37' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_36' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_35' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_34' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_33' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_32' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_31' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_30' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_12' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 35.8 seconds. CPU system time: 4.18 seconds. Elapsed time: 40.02 seconds; current allocated memory: 3.274 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.62 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.65 seconds; current allocated memory: 3.287 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.47 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.5 seconds; current allocated memory: 3.293 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.31 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.35 seconds; current allocated memory: 3.296 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.3 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.32 seconds; current allocated memory: 3.300 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.27 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.32 seconds; current allocated memory: 3.302 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.22 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.26 seconds; current allocated memory: 3.302 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1007_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1039_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1008_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1040_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1019_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1051_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2keb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1030_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1062_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1033_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2khb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1065_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1034_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1066_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1035_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2klb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1067_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1036_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2knb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1068_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1037_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1069_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1038_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2krb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1070_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2ksb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1009_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2ktb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1041_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1010_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1042_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1011_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1043_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1012_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1044_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1013_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1045_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1014_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1046_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1015_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1047_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1016_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1048_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1017_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1049_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1018_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1050_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1020_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1052_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1021_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1053_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1022_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1054_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1023_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1055_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1024_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1056_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1025_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1057_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1026_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1058_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1027_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1059_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1028_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1060_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1029_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1061_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1031_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1063_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1032_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1064_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2lab' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.14 seconds. CPU system time: 0.33 seconds. Elapsed time: 4.48 seconds; current allocated memory: 3.306 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s_outidx_8_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s_outidx_8_ROM_lbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s_w25_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s_w25_ROM_NP_BRlcb' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s' is 9216 from HDL expression: (do_init_reg_1334 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_11s_42s_43_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_42s_43_1_1': 7 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_577_9_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_9_2_42_1_1': 8 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s_w25_ROM_NP_BRlcb' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.01 seconds. CPU system time: 0.11 seconds. Elapsed time: 1.12 seconds; current allocated memory: 3.331 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5327' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_79' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5328' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_78' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5329' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_77' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5330' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_76' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5332' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_75' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5333' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_74' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5334' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_73' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5335' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_72' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5336' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_71' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5337' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_70' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5338' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5096' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5339' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5108' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5340' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5120' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5341' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5132' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5343' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5344' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5345' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5346' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5181' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5347' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5348' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5349' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5350' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5351' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5352' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5354' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5355' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5356' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5290' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5357' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5302' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5358' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5314' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5359' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5324' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5360' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5325' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5361' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5326' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5130' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5398' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5131' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5399' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5134' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5400' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5135' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5401' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5136' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5097' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5137' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5098' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5099' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5101' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5102' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5103' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5104' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5105' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5106' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5107' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5109' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5110' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5112' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5113' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5114' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5115' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5116' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5117' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5118' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5119' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5121' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5123' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5124' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5125' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5126' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5127' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5128' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5129' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5362' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5363' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5365' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5366' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5367' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5368' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5369' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5370' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5371' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5372' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5373' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5374' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5376' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5377' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5378' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5379' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5380' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5381' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5382' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5383' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5384' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5385' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5387' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5388' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5389' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5390' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5391' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5392' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5393' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5394' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5395' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5396' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5178' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5179' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5180' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5182' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5183' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5184' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5185' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5186' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5187' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5189' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5190' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5191' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5192' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5288' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5289' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5291' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5292' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5293' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5294' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5295' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5296' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5297' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5299' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5300' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5301' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5303' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5304' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5305' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5306' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5307' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5308' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5310' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5311' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5312' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5313' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5315' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5316' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5317' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5318' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5319' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5321' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5322' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5323' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_4' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 13.17 seconds. CPU system time: 1.25 seconds. Elapsed time: 14.42 seconds; current allocated memory: 3.366 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.37 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.41 seconds; current allocated memory: 3.371 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.37 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.4 seconds; current allocated memory: 3.375 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.34 seconds; current allocated memory: 3.379 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' pipeline 'ConcatLoopHeight_ConcatLoopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.34 seconds; current allocated memory: 3.381 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.25 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.27 seconds; current allocated memory: 3.382 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.29 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.32 seconds; current allocated memory: 3.385 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.34 seconds; current allocated memory: 3.387 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.3 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.35 seconds; current allocated memory: 3.389 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.26 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.27 seconds; current allocated memory: 3.390 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1135_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2ldb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1183_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2leb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1136_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1184_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1147_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1195_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1158_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2ljb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1206_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1169_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2llb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1217_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1178_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1226_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1179_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1227_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1180_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1228_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1181_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2ltb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1229_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1182_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1230_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1137_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1185_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1138_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1186_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lAb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1139_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lBb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1187_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lCb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1140_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1188_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1141_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1189_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1142_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1190_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1143_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1191_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1144_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1192_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1145_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1193_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1146_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1194_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1148_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1196_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1149_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1197_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1150_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1198_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1151_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1199_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1152_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1200_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1153_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1201_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1154_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1202_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1155_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1203_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1156_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1204_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1157_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1205_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1159_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1207_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1160_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1208_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2meb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1161_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1209_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1162_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1210_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1163_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1211_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1164_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mlb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1212_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1165_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1213_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1166_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1214_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1167_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1215_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2msb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1168_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mtb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1216_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1170_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1218_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1171_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1219_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2myb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1172_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mzc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1220_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mAc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1173_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mBc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1221_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mCc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1174_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mDc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1222_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mEc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1175_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mFc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1223_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mGc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1176_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mHc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1224_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mIc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1177_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mJc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1225_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mKc' due to the length limit 80 +INFO: [RTGEN 206-104] Estimated max fanout for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s' is 6912 from HDL expression: (1'b1 == ap_CS_fsm_state1) +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 5.62 seconds. CPU system time: 0.55 seconds. Elapsed time: 6.17 seconds; current allocated memory: 3.397 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_w29_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_w29_RmLc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' is 13824 from HDL expression: (do_init_reg_1875 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_40s_40_1_1': 15 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_33s_33_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_865_9_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_w29_RmLc' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.17 seconds. CPU system time: 0.08 seconds. Elapsed time: 1.25 seconds; current allocated memory: 3.429 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6115' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_59' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6116' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_58' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6117' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_57' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6118' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_56' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6119' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_55' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6120' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_54' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6121' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_53' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6122' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_52' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6124' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_51' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6125' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_50' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6126' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6127' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6128' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6129' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6130' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6131' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6132' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6133' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6135' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6136' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6137' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5841' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5853' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5865' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5877' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5889' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5901' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5913' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5926' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5938' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5950' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5962' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5974' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5986' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5998' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6010' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6022' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6034' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6047' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6059' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6071' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6083' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6095' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6107' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6110' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6111' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6113' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6114' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5839' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5840' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5842' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5843' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5844' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5845' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5846' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5847' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5849' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5850' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5851' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5852' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5854' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5855' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5856' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5857' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5858' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5860' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5861' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5862' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5863' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5864' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5866' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5867' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5868' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5869' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5871' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5872' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5873' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5874' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5875' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5876' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5994' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5935' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5995' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5937' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5996' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5939' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5997' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5940' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5941' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6000' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5942' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6001' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5943' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6003' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5944' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6004' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5945' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6005' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5946' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6006' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5948' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6007' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5949' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6008' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5951' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6009' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5952' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6011' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5953' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6012' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5954' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6014' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5955' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6015' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5956' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6016' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5957' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6017' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5959' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6018' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5960' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6019' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5961' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6020' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5963' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6021' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5964' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6023' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5965' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6025' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5966' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6026' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5967' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6027' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5968' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6028' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5970' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6029' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5971' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6030' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5972' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6031' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5973' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6032' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5975' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6033' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5976' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6036' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5977' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6037' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5978' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6038' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5979' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6039' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5981' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6040' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5982' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6041' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5983' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6042' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5984' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6043' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5985' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6044' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5987' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6045' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5988' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6048' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5989' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6049' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5990' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6050' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5992' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6051' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5993' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5878' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5879' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5880' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5882' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5883' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5884' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5885' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5886' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5887' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5888' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5890' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5891' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5893' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5894' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5895' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5896' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5897' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5898' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5899' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5900' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5902' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5904' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5905' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5906' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5907' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5908' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5909' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5910' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5911' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5912' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5915' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5916' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5917' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5918' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5919' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5920' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5921' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5922' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5923' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5924' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5927' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5928' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5929' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5930' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5931' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5932' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5933' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5934' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6052' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6053' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6054' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6055' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6056' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6058' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6060' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6061' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6062' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6063' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6064' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6065' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6066' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6067' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6069' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6070' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6072' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6073' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6074' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6075' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6076' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6077' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6078' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6080' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6081' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6082' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6084' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6085' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6086' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6087' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6088' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6089' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6091' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6092' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6093' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6094' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6096' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6097' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6098' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6099' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6100' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6102' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6103' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6104' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6105' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6106' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6108' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6109' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_1' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 21.15 seconds. CPU system time: 1.88 seconds. Elapsed time: 23.05 seconds; current allocated memory: 3.475 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.43 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.48 seconds; current allocated memory: 3.483 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.39 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.42 seconds; current allocated memory: 3.486 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.36 seconds; current allocated memory: 3.489 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.36 seconds; current allocated memory: 3.492 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.34 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.36 seconds; current allocated memory: 3.494 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.27 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.29 seconds; current allocated memory: 3.495 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_831_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mMc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_847_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mNc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_832_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mOc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_848_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mPc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_839_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mQc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_855_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mRc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_840_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mSc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_856_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mTc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_841_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mUc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_857_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mVc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_842_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mWc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_858_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mXc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_843_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mYc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_859_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mZc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_844_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m0c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_860_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m1c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_845_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m2c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_861_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m3c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_846_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m4c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_862_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m5c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_833_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m6c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_849_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m7c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_834_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m8c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_850_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m9c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_835_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2nac' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_851_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2nbc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_836_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2ncc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_852_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2ndc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_837_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2nec' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_853_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2nfc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_838_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2ngc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_854_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2nhc' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.76 seconds. CPU system time: 0.2 seconds. Elapsed time: 1.95 seconds; current allocated memory: 3.498 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s_outidx_9_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s_outidx_9_ROM_nic' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s_w31_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s_w31_ROM_NP_BRnjc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_41s_42_1_1': 3 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_41s_42_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_289_8_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_9_2_41_1_1': 4 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s_w31_ROM_NP_BRnjc' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.82 seconds. CPU system time: 0.08 seconds. Elapsed time: 0.9 seconds; current allocated memory: 3.508 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4324' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4325' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4326' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4327' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4328' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4329' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4331' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4332' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4333' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4334' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4335' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4336' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4337' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4293' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4338' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4305' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4339' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4317' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4340' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4323' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4377' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4359' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4378' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4360' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4379' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4361' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4380' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4362' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4381' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4364' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4382' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4365' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4383' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4366' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4384' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4367' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4386' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4368' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4387' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4369' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4388' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4370' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4389' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4371' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4390' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4372' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4391' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4373' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4392' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4375' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4393' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4376' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4412' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4413' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4287' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4414' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4288' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4415' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4289' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4290' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4291' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4292' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4294' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4295' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4296' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4298' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4299' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4300' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4301' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4302' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4342' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4343' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4344' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4345' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4346' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4347' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4348' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4349' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4350' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4351' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4353' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4354' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4355' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4356' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4357' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4358' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4394' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4395' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4397' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4398' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4399' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4400' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4401' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4402' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4403' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4404' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4405' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4406' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4408' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4409' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4410' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4411' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4303' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4304' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4306' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4307' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4309' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4310' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4311' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4312' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4313' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4314' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4315' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4316' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4318' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4320' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4321' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4322' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_2' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 7.77 seconds. CPU system time: 0.71 seconds. Elapsed time: 8.48 seconds; current allocated memory: 3.526 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.33 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.37 seconds; current allocated memory: 3.529 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.36 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.39 seconds; current allocated memory: 3.531 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.33 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.37 seconds; current allocated memory: 3.536 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' pipeline 'ConcatLoopHeight_ConcatLoopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.37 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.4 seconds; current allocated memory: 3.539 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.27 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.3 seconds; current allocated memory: 3.540 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.35 seconds; current allocated memory: 3.541 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.38 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.4 seconds; current allocated memory: 3.545 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.35 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.4 seconds; current allocated memory: 3.547 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.26 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.3 seconds; current allocated memory: 3.551 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_895_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nkc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_919_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nlc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_896_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nmc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_920_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nnc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_907_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2noc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_931_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2npc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_912_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nqc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_936_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nrc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_913_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nsc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_937_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2ntc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_914_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nuc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_938_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nvc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_915_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nwc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_939_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nxc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_916_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nyc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_940_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nzc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_917_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nAc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_941_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nBc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_918_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nCc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_942_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nDc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_897_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nEc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_921_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nFc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_898_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nGc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_922_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nHc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_899_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nIc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_923_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nJc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_900_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nKc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nKc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nKc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_924_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nLc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nLc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nLc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_901_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nMc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nMc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nMc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_925_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nNc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nNc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nNc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_902_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nOc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nOc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nOc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_926_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nPc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nPc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nPc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_903_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nQc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nQc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nQc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_927_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nRc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nRc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nRc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_904_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nSc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nSc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nSc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_928_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nTc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nTc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nTc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_905_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nUc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nUc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nUc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_929_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nVc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nVc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nVc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_906_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nWc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nWc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nWc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_930_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nXc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nXc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nXc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_908_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nYc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nYc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nYc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_932_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nZc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nZc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nZc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_909_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2n0c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_933_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2n1c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_910_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2n2c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_934_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2n3c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_911_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2n4c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_935_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2n5c' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 3.49 seconds. CPU system time: 0.28 seconds. Elapsed time: 3.77 seconds; current allocated memory: 3.555 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_w35_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_w35_Rn6c' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' is 6912 from HDL expression: (do_init_reg_963 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_33s_33_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_39s_39_1_1': 7 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_433_8_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_w35_Rn6c' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.89 seconds. CPU system time: 0.07 seconds. Elapsed time: 0.97 seconds; current allocated memory: 3.569 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_99' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_98' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_97' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_96' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_95' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_94' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_93' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_92' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_91' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_90' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_6' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 11.7 seconds. CPU system time: 1.05 seconds. Elapsed time: 12.75 seconds; current allocated memory: 3.593 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.38 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.4 seconds; current allocated memory: 3.597 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.37 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.41 seconds; current allocated memory: 3.603 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.34 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.38 seconds; current allocated memory: 3.603 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.39 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.41 seconds; current allocated memory: 3.606 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.38 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.41 seconds; current allocated memory: 3.609 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.3 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.32 seconds; current allocated memory: 3.610 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1391_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn7c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1399_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn8c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1392_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn9c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1400_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2doac' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1393_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dobc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1401_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2docc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1394_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dodc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1402_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2doec' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1395_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dofc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1403_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dogc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1396_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dohc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1404_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2doic' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1397_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dojc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1405_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dokc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1398_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dolc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1406_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2domc' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.1 seconds. CPU system time: 0.09 seconds. Elapsed time: 1.19 seconds; current allocated memory: 3.613 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s_outidx_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s_outidx_ROM_AUonc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s_w37_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s_w37_ROM_NP_BRooc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_11s_40s_41_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_40s_41_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_9_2_40_1_1': 2 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s_outidx_ROM_AUonc' using auto ROMs. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s_w37_ROM_NP_BRooc' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.8 seconds. CPU system time: 0.1 seconds. Elapsed time: 0.9 seconds; current allocated memory: 3.616 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_14' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.34 seconds. CPU system time: 0.33 seconds. Elapsed time: 4.67 seconds; current allocated memory: 3.626 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.28 seconds. CPU system time: 0.07 seconds. Elapsed time: 0.35 seconds; current allocated memory: 3.628 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.35 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.38 seconds; current allocated memory: 3.630 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_12s_30s_30_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_17_3_12_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_17_3_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.52 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.55 seconds; current allocated memory: 3.635 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.29 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.33 seconds; current allocated memory: 3.635 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s_sigmoid_table_ROM_AUTO_1R' to 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s_sigmoid_table_Ropc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s' pipeline 'SigmoidActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s_sigmoid_table_Ropc' using auto ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.46 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.48 seconds; current allocated memory: 3.637 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'myproject' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low. +INFO: [RTGEN 206-500] Setting interface mode on port 'myproject/x' to 'axis' (register, both mode). +INFO: [RTGEN 206-500] Setting interface mode on port 'myproject/layer40_out' to 'axis' (register, both mode). +INFO: [RTGEN 206-500] Setting interface mode on function 'myproject' to 'ap_ctrl_hs'. +INFO: [SYN 201-210] Renamed object name 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_U0' to 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4oqc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_U0' to 'start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6orc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_U0' to 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4osc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_U0' to 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7otc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_U0' to 'start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configouc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_U0' to 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10ovc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_U0' to 'start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384owc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13oxc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15oyc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_U0' to 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18ozc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_U0' to 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20oAc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24oBc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26oCc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_U0' to 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30oDc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_U0' to 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32oEc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_U0' to 'start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3oFc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_U0' to 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config5oGc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_U0' to 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37oHc' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'myproject'. +INFO: [RTMG 210-285] Implementing FIFO 'layer44_out_U(myproject_fifo_w16_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer2_out_U(myproject_fifo_w296_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer3_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer45_out_U(myproject_fifo_w128_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer4_out_U(myproject_fifo_w320_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer5_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer41_cpy1_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer41_cpy2_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer6_out_U(myproject_fifo_w128_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer46_out_U(myproject_fifo_w128_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer7_out_U(myproject_fifo_w640_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer8_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer47_out_U(myproject_fifo_w256_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer9_out_U(myproject_fifo_w656_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer10_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer42_cpy1_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer42_cpy2_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer11_out_U(myproject_fifo_w256_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer48_out_U(myproject_fifo_w256_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer12_out_U(myproject_fifo_w1312_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer13_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer49_out_U(myproject_fifo_w512_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer14_out_U(myproject_fifo_w1344_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer15_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer43_cpy1_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer43_cpy2_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer16_out_U(myproject_fifo_w512_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer50_out_U(myproject_fifo_w512_d100_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer17_out_U(myproject_fifo_w2688_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer18_out_U(myproject_fifo_w1024_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer51_out_U(myproject_fifo_w1024_d100_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer19_out_U(myproject_fifo_w2752_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer20_out_U(myproject_fifo_w1024_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer21_out_U(myproject_fifo_w1024_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer22_out_U(myproject_fifo_w1536_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer52_out_U(myproject_fifo_w1536_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer23_out_U(myproject_fifo_w1376_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer24_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer53_out_U(myproject_fifo_w512_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer25_out_U(myproject_fifo_w1344_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer26_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer27_out_U(myproject_fifo_w512_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer28_out_U(myproject_fifo_w768_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer54_out_U(myproject_fifo_w768_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer29_out_U(myproject_fifo_w672_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer30_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer55_out_U(myproject_fifo_w256_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer31_out_U(myproject_fifo_w656_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer32_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer33_out_U(myproject_fifo_w256_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer34_out_U(myproject_fifo_w384_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer56_out_U(myproject_fifo_w384_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer35_out_U(myproject_fifo_w328_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer36_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer57_out_U(myproject_fifo_w128_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer37_out_U(myproject_fifo_w320_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer38_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer39_out_U(myproject_fifo_w36_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_U0_U(myproject_start_for_conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4oqc_U(myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4oqc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_U0_U(myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0_U(myproject_start_for_clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6orc_U(myproject_start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6orc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0_U(myproject_start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4osc_U(myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4osc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7otc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7otc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_U0_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configouc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configouc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10ovc_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10ovc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384owc_U(myproject_start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384owc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0_U(myproject_start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0_U(myproject_start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13oxc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13oxc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15oyc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15oyc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0_U(myproject_start_for_clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_U0_U(myproject_start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0_U(myproject_start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18ozc_U(myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18ozc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20oAc_U(myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20oAc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_U0_U(myproject_start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24oBc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24oBc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26oCc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26oCc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_U0_U(myproject_start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30oDc_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30oDc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32oEc_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32oEc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_U0_U(myproject_start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3oFc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3oFc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config5oGc_U(myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config5oGc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37oHc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37oHc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_U0_U(myproject_start_for_pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_U0_U(myproject_start_for_sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_U0)' using Shift Registers. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 7.26 seconds. CPU system time: 0.69 seconds. Elapsed time: 7.95 seconds; current allocated memory: 3.647 GB. +INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 1.91 seconds. CPU system time: 0.31 seconds. Elapsed time: 2.45 seconds; current allocated memory: 3.653 GB. +INFO: [HLS 200-111] Finished Updating report files: CPU user time: 13.85 seconds. CPU system time: 0.18 seconds. Elapsed time: 14.08 seconds; current allocated memory: 3.739 GB. +INFO: [VHDL 208-304] Generating VHDL RTL for myproject. +INFO: [VLOG 209-307] Generating Verilog RTL for myproject. +INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were NOT satisfied. +INFO: [HLS 200-789] **** Estimated Fmax: 224.75 MHz +INFO: [HLS 200-2161] Finished Command csynth_design Elapsed time: 00:18:24; Allocated memory: 3.492 GB. +***** C/RTL SYNTHESIS COMPLETED IN 0h18m24s ***** +INFO: [HLS 200-112] Total CPU user time: 1078.45 seconds. Total CPU system time: 38.26 seconds. Total elapsed time: 1108.39 seconds; peak allocated memory: 3.739 GB. +INFO: [vitis-run 60-791] Total elapsed time: 0h 18m 30s +INFO: [vitis-run 60-1662] Stopping dispatch session having empty uuid. diff --git a/logs/hls_run_tcl_137509.backup.log b/logs/hls_run_tcl_137509.backup.log new file mode 100644 index 0000000000000000000000000000000000000000..b0585516359472c1a2de991311685aefc76aae56 --- /dev/null +++ b/logs/hls_run_tcl_137509.backup.log @@ -0,0 +1,10299 @@ +INFO: [vitis-run 82-31] Launching vitis_hls: vitis_hls -nolog -run tcl -f /home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl -work_dir /home/ubuntu/lithobench/hls4ml_mini_unet + +****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2024.1 (64-bit) + **** SW Build 5069499 on May 21 2024 + **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 + **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 + **** Start of session at: Sat Apr 4 09:10:28 2026 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. + +source /opt/Xilinx/Vitis_HLS/2024.1/scripts/vitis_hls/hls.tcl -notrace +INFO: [HLS 200-10] For user 'ubuntu' on host 'ip-172-31-42-252.ec2.internal' (Linux_x86_64 version 5.15.0-1084-aws) on Sat Apr 04 09:10:29 UTC 2026 +INFO: [HLS 200-10] On os Ubuntu 20.04.6 LTS +INFO: [HLS 200-10] In directory '/home/ubuntu/lithobench/hls4ml_mini_unet' +Sourcing Tcl script '/home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl' +INFO: [HLS 200-1510] Running: open_project myproject_prj +INFO: [HLS 200-10] Opening project '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj'. +INFO: [HLS 200-1510] Running: set_top myproject +INFO: [HLS 200-1510] Running: add_files firmware/myproject.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding design file 'firmware/myproject.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb myproject_test.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding test bench file 'myproject_test.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb firmware/weights +INFO: [HLS 200-10] Adding test bench file 'firmware/weights' to the project +INFO: [HLS 200-1510] Running: add_files -tb tb_data +INFO: [HLS 200-10] Adding test bench file 'tb_data' to the project +INFO: [HLS 200-1510] Running: open_solution solution1 +INFO: [HLS 200-10] Opening solution '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1'. +INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. +INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 1.35ns. +INFO: [HLS 200-1611] Setting target device to 'xcvu47p-fsvh2892-2L-e' +INFO: [HLS 200-1505] Using flow_target 'vivado' +Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1505.html +INFO: [HLS 200-1464] Running solution command: config_compile -name_max_length=80 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_compile -complex-mul-dsp=0 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_compile -unsafe_math_optimizations=0 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_schedule -enable_dsp_full_reg=0 +INFO: [HLS 200-1464] Running solution command: config_array_partition -complete_threshold=4096 +INFO: [XFORM 203-102] Size-based automatic array partition enabled: cut-off elements per dimension is 4096. +INFO: [HLS 200-1510] Running: config_array_partition -maximum_size 4096 +ERROR: [HLS 200-101] config_array_partition: Unknown option '-maximum_size'. +ERROR: [HLS 200-101] config_array_partition: Unknown option '4096'. +SYNTAX + config_array_partition [OPTIONS] + -auto_partition_threshold *** DEPRECATED*** + -auto_promotion_threshold *** DEPRECATED*** + -complete_threshold + -throughput_driven + +SEE ALSO + INI: syn.array_partition.complete_threshold syn.array_partition.throughput_driven + docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1399-vitis-hls&resourceid=vyw1583260160301.html + +INFO: [HLS 200-1510] Running: config_compile -name_max_length 80 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: set_part xcvu47p-fsvh2892-2L-e +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: config_schedule -enable_dsp_full_reg=false +INFO: [HLS 200-1510] Running: create_clock -period 5 -name default +INFO: [HLS 200-1510] Running: set_clock_uncertainty 27% default +***** C/RTL SYNTHESIS ***** +INFO: [HLS 200-1510] Running: csynth_design +INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 276.809 MB. +INFO: [HLS 200-10] Analyzing design file 'firmware/myproject.cpp' ... +WARNING: [HLS 207-5570] unexpected pragma argument 'softmax', expects function/operation (firmware/nnet_utils/nnet_activation.h:402:36) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:33:9) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:107:9) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:189:9) +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:234:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:234:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:240:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:240:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:250:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:250:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:256:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:256:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:266:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:266:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:272:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:272:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:282:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:282:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:288:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:288:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:298:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:298:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:304:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:304:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:314:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:314:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:320:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:320:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:330:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:330:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:336:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:336:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:340:100) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:340:105) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 200-471] Dataflow form checks found 30 issue(s) in file firmware/myproject.cpp +Resolution: For help on HLS 200-471 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-471.html +WARNING: [HLS 207-5292] unused parameter 'keep' (firmware/nnet_utils/nnet_helpers.h:285:99) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:14:36) +WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:15:36) +WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:16:44) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:24:24) +WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:25:24) +WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:26:32) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:33:30) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:33:58) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:34:51) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:35:49) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:42:30) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:42:58) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:43:51) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:44:49) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:51:29) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:51:80) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:52:50) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:53:48) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_code_gen.h:16:39) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_code_gen.h:17:38) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_code_gen.h:18:60) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_code_gen.h:19:58) +WARNING: [HLS 207-5584] there are more than one pragma inline in the function scope, ignore the pragma (/opt/Xilinx/Vitis_HLS/2024.1/common/technology/autopilot/ap_shift_reg.h:47:9) +INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 36.12 seconds. CPU system time: 2.01 seconds. Elapsed time: 38.17 seconds; current allocated memory: 287.750 MB. +INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target. +INFO: [HLS 200-1995] There were 28,161 instructions in the design after the 'Compile/Link' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 217,805 instructions in the design after the 'Unroll/Inline (step 1)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 105,657 instructions in the design after the 'Unroll/Inline (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 87,893 instructions in the design after the 'Unroll/Inline (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 42,044 instructions in the design after the 'Unroll/Inline (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 35,226 instructions in the design after the 'Array/Struct (step 1)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 32,725 instructions in the design after the 'Array/Struct (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 33,620 instructions in the design after the 'Array/Struct (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 83,995 instructions in the design after the 'Array/Struct (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 77,574 instructions in the design after the 'Array/Struct (step 5)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 79,220 instructions in the design after the 'Performance' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 189,991 instructions in the design after the 'Performance (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 187,305 instructions in the design after the 'Performance (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 187,305 instructions in the design after the 'Performance (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 148,481 instructions in the design after the 'HW Transforms' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 140,742 instructions in the design after the 'HW Transforms (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>' (firmware/nnet_utils/nnet_sepconv_stream.h:103:9) +WARNING: [HLS 214-273] In function 'void nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config58_mult::weight_t*, config58_mult::bias_t*)', Pragma conflict happens on 'INLINE' and 'FUNCTION_INSTANTIATE' pragmas: same function (firmware/nnet_utils/nnet_dense_resource.h:15:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 1u>, config2>(nnet::array, 1u>::value_type (*) [config2::n_chan], nnet::array, 1u>::value_type*)' into 'void nnet::shift_line_buffer, 1u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], nnet::array, 1u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, config2_mult::weight_t*, config2_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*) (.55)' into 'void nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config4>(nnet::array, 8u>::value_type (*) [config4::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config4_mult::weight_t*, config4_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 8u>, config4>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*) (.54)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config6>(nnet::array, 8u>::value_type (*) [config6::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::Op_max >::operator()(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>) (.36)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' (firmware/nnet_utils/nnet_common.h:44:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:15) +INFO: [HLS 214-131] Inlining function 'nnet::Op_max >::operator()(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>) (.36)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:12) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:44) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config6>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.52)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config6>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.52)' into 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 8u>::operator[](unsigned long) (.51)' into 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' into 'void nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config7>(nnet::array, 8u>::value_type (*) [config7::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config7_mult::weight_t*, config7_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 16u>, config7>(hls::stream, 8u>, 0>&, hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*) (.48)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>(hls::stream, 8u>, 0>&, hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config9>(nnet::array, 16u>::value_type (*) [config9::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config9_mult::weight_t*, config9_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 16u>, config9>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*) (.47)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config11>(nnet::array, 16u>::value_type (*) [config11::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config11>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.45)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config11>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.45)' into 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 16u>::operator[](unsigned long) (.44)' into 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' into 'void nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config12>(nnet::array, 16u>::value_type (*) [config12::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config12_mult::weight_t*, config12_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 32u>, config12>(hls::stream, 16u>, 0>&, hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*) (.41)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>(hls::stream, 16u>, 0>&, hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config14>(nnet::array, 32u>::value_type (*) [config14::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config14_mult::weight_t*, config14_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 32u>, config14>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*) (.40)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config16>(nnet::array, 32u>::value_type (*) [config16::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config16>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.34)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config16>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.34)' into 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 32u>::operator[](unsigned long) (.33)' into 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' into 'void nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config17>(nnet::array, 32u>::value_type (*) [config17::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config17_mult::weight_t*, config17_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 64u>, config17>(hls::stream, 32u>, 0>&, hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*) (.30)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>(hls::stream, 32u>, 0>&, hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 64u>, config19>(nnet::array, 64u>::value_type (*) [config19::n_chan], nnet::array, 64u>::value_type*)' into 'void nnet::shift_line_buffer, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], nnet::array, 64u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config19_mult::weight_t*, config19_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 64u>, nnet::array, 64u>, config19>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*) (.26)' into 'void nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 96u>, config23>(nnet::array, 96u>::value_type (*) [config23::n_chan], nnet::array, 96u>::value_type*)' into 'void nnet::shift_line_buffer, 96u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], nnet::array, 96u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config23_mult::weight_t*, config23_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 96u>, nnet::array, 32u>, config23>(hls::stream, 96u>, 0>&, hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*) (.23)' into 'void nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>(hls::stream, 96u>, 0>&, hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config25>(nnet::array, 32u>::value_type (*) [config25::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config25_mult::weight_t*, config25_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 32u>, config25>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*) (.19)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 48u>, config29>(nnet::array, 48u>::value_type (*) [config29::n_chan], nnet::array, 48u>::value_type*)' into 'void nnet::shift_line_buffer, 48u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], nnet::array, 48u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config29_mult::weight_t*, config29_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 48u>, nnet::array, 16u>, config29>(hls::stream, 48u>, 0>&, hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*) (.16)' into 'void nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>(hls::stream, 48u>, 0>&, hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config31>(nnet::array, 16u>::value_type (*) [config31::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config31_mult::weight_t*, config31_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 16u>, config31>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*) (.12)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 24u>, config35>(nnet::array, 24u>::value_type (*) [config35::n_chan], nnet::array, 24u>::value_type*)' into 'void nnet::shift_line_buffer, 24u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], nnet::array, 24u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config35_mult::weight_t*, config35_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 24u>, nnet::array, 8u>, config35>(hls::stream, 24u>, 0>&, hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*) (.9)' into 'void nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>(hls::stream, 24u>, 0>&, hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config37>(nnet::array, 8u>::value_type (*) [config37::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config37_mult::weight_t*, config37_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 8u>, config37>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*) (.5)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config58_mult::weight_t*, config58_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const (.4)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:100:13) +INFO: [HLS 214-131] Inlining function 'nnet::array, 1u>::operator[](unsigned long) (.2)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:110:2) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.3)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:104:2) +INFO: [HLS 214-131] Inlining function 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' into 'void nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>(hls::stream, 8u>, 0>&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv2d_stream.h:86:21) +INFO: [HLS 214-291] Loop 'SigmoidPackLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_activation_stream.h:88:9) +INFO: [HLS 214-291] Loop 'MultLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_dense_resource.h:55:9) +INFO: [HLS 214-291] Loop 'ReLUPackLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_activation_stream.h:49:9) +INFO: [HLS 214-291] Loop 'MultLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_dense_resource.h:142:9) +INFO: [HLS 214-291] Loop 'KernelPushHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:205:5) +INFO: [HLS 214-291] Loop 'KernelPushChannel' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:208:9) +INFO: [HLS 214-291] Loop 'KernelShiftWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:189:5) +INFO: [HLS 214-291] Loop 'KernelShiftHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:192:9) +INFO: [HLS 214-291] Loop 'KernelShiftChannel' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:194:13) +INFO: [HLS 214-291] Loop 'LineBufferDataIn' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:236:5) +INFO: [HLS 214-291] Loop 'LineBufferShift' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:239:9) +INFO: [HLS 214-291] Loop 'UpdateBuffer' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:228:5) +INFO: [HLS 214-291] Loop 'ConcatPackInput1' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_merge_stream.h:245:13) +INFO: [HLS 214-291] Loop 'ConcatPackInput2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_merge_stream.h:251:13) +INFO: [HLS 214-291] Loop 'ImageWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:22:9) +INFO: [HLS 214-291] Loop 'ImageChan' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:28:13) +INFO: [HLS 214-291] Loop 'ResizeHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:36:9) +INFO: [HLS 214-291] Loop 'ImageWidth2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:40:13) +INFO: [HLS 214-291] Loop 'ResizeWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:44:17) +INFO: [HLS 214-291] Loop 'ResizeChan' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:51:21) +INFO: [HLS 214-291] Loop 'FiltLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_pooling_stream.h:57:9) +INFO: [HLS 214-291] Loop 'PoolLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_pooling_stream.h:62:13) +INFO: [HLS 214-291] Loop 'ClonePack' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_stream.h:32:9) +INFO: [HLS 214-186] Unrolling loop 'SigmoidPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:88:9) in function 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>' completely with a factor of 1 (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-186] Unrolling loop 'InitData' (firmware/nnet_utils/nnet_sepconv_stream.h:98:5) in function 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>' completely with a factor of 8 (firmware/nnet_utils/nnet_sepconv2d_stream.h:58:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_sepconv_stream.h:108:5) in function 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>' completely with a factor of 1 (firmware/nnet_utils/nnet_sepconv2d_stream.h:58:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config38>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 4 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config37>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config36>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 24u>, config35>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>' completely with a factor of 24 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' completely with a factor of 16 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' completely with a factor of 8 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config32>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config31>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config30>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 48 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 48u>, config29>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>' completely with a factor of 48 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' completely with a factor of 32 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' completely with a factor of 16 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config26>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config25>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config24>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 192 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 96u>, config23>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>' completely with a factor of 96 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' completely with a factor of 64 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' completely with a factor of 32 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 8 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 64 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 8 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 64 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 64u>, nnet::array, 64u>, relu_config20>' completely with a factor of 64 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 256 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 64u>, config19>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 64u>, nnet::array, 64u>, relu_config18>' completely with a factor of 64 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 128 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config17>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config16>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>' completely with a factor of 32 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config15>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config14>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config13>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config12>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config11>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>' completely with a factor of 16 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config10>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config9>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config8>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config7>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config6>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>' completely with a factor of 8 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config5>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 4 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config4>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config3>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 1u>, config2>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>' completely with a factor of 1 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 1u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], nnet::array, 1u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(config2_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, config2_mult::weight_t*, config2_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config3>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config3>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(config4_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config4_mult::weight_t*, config4_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config5>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config5>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(config7_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config7_mult::weight_t*, config7_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config8>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config8>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(config9_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config9_mult::weight_t*, config9_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config10>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config10>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(config12_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config12_mult::weight_t*, config12_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config13>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config13>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(config14_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config14_mult::weight_t*, config14_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config15>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config15>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config18>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config18>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], nnet::array, 64u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config20>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config20>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 64u>, config21>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 96u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], nnet::array, 96u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(config23_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config23_mult::weight_t*, config23_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config24>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config24>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(config25_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config25_mult::weight_t*, config25_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config26>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config26>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 32u>, config27>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 48u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], nnet::array, 48u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(config29_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config29_mult::weight_t*, config29_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config30>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config30>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(config31_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config31_mult::weight_t*, config31_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config32>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config32>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 16u>, config33>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 24u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], nnet::array, 24u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(config35_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config35_mult::weight_t*, config35_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config36>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config36>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(config37_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config37_mult::weight_t*, config37_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config38>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config38>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(config58_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config58_mult::weight_t*, config58_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj1EEENS1_IS2_ILi37ELi17ELS3_5ELS4_3ELi0EELj8EEE7config2EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEES6_7config6EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to 'b2': Complete partitioning on dimension 1. (firmware/weights/b2.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b4': Complete partitioning on dimension 1. (firmware/weights/b4.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b7': Complete partitioning on dimension 1. (firmware/weights/b7.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b9': Complete partitioning on dimension 1. (firmware/weights/b9.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b12': Complete partitioning on dimension 1. (firmware/weights/b12.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b14': Complete partitioning on dimension 1. (firmware/weights/b14.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b17': Complete partitioning on dimension 1. (firmware/weights/b17.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b19': Complete partitioning on dimension 1. (firmware/weights/b19.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b23': Complete partitioning on dimension 1. (firmware/weights/b23.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b25': Complete partitioning on dimension 1. (firmware/weights/b25.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b29': Complete partitioning on dimension 1. (firmware/weights/b29.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b31': Complete partitioning on dimension 1. (firmware/weights/b31.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b35': Complete partitioning on dimension 1. (firmware/weights/b35.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b37': Complete partitioning on dimension 1. (firmware/weights/b37.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'w39': Complete partitioning on dimension 1. (firmware/weights/w39.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b39': Complete partitioning on dimension 1. (firmware/weights/b39.h:12:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEES6_7config6EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj1EEENS1_IS2_ILi37ELi17ELS3_5ELS4_3ELi0EELj8EEE7config2EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to 'acc': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_dense_resource.h:110:32) +INFO: [HLS 214-248] Applying array_partition to 'res_out': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:274:29) +INFO: [HLS 214-248] Applying array_partition to 'shift_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv_stream.h:224:30) +INFO: [HLS 214-248] Applying array_partition to 'data.i': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_sepconv_stream.h:88:30) +INFO: [HLS 214-248] Applying array_partition to 'res.i': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_sepconv_stream.h:91:29) +WARNING: [HLS 214-322] Unsuported scalar variable on pragma 'Resource/Bind_Storage', ignore it. (firmware/myproject.cpp:340:5) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer39_out' with compact=bit mode in 36-bits (firmware/myproject.cpp:229:35) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer38_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:226:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer57_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:220:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer36_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:217:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer46_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:85:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer6_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:82:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer41_cpy1' with compact=bit mode in 128-bits (firmware/myproject.cpp:76:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer41_cpy2' with compact=bit mode in 128-bits (firmware/myproject.cpp:79:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer5_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:73:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer45_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:67:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer3_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:64:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer37_out' with compact=bit mode in 320-bits (firmware/myproject.cpp:223:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer4_out' with compact=bit mode in 320-bits (firmware/myproject.cpp:70:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer35_out' with compact=bit mode in 328-bits (firmware/myproject.cpp:214:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer56_out' with compact=bit mode in 384-bits (firmware/myproject.cpp:211:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer34_out' with compact=bit mode in 384-bits (firmware/myproject.cpp:208:30) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer33_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:205:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer32_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:202:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer55_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:196:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer30_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:193:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer48_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:112:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer11_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:109:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer42_cpy1' with compact=bit mode in 256-bits (firmware/myproject.cpp:103:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer42_cpy2' with compact=bit mode in 256-bits (firmware/myproject.cpp:106:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer10_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:100:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer47_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:94:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer8_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:91:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer31_out' with compact=bit mode in 656-bits (firmware/myproject.cpp:199:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer9_out' with compact=bit mode in 656-bits (firmware/myproject.cpp:97:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer29_out' with compact=bit mode in 672-bits (firmware/myproject.cpp:190:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer54_out' with compact=bit mode in 768-bits (firmware/myproject.cpp:187:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer28_out' with compact=bit mode in 768-bits (firmware/myproject.cpp:184:30) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer27_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:181:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer26_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:178:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer53_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:172:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer24_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:169:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer50_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:139:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer16_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:136:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer43_cpy1' with compact=bit mode in 512-bits (firmware/myproject.cpp:130:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer43_cpy2' with compact=bit mode in 512-bits (firmware/myproject.cpp:133:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer15_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:127:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer49_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:121:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer13_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:118:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer25_out' with compact=bit mode in 1344-bits (firmware/myproject.cpp:175:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer14_out' with compact=bit mode in 1344-bits (firmware/myproject.cpp:124:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer23_out' with compact=bit mode in 1376-bits (firmware/myproject.cpp:166:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer52_out' with compact=bit mode in 1536-bits (firmware/myproject.cpp:163:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer22_out' with compact=bit mode in 1536-bits (firmware/myproject.cpp:160:28) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer21_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:157:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer20_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:154:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer51_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:148:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer18_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:145:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer19_out' with compact=bit mode in 2752-bits (firmware/myproject.cpp:151:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer17_out' with compact=bit mode in 2688-bits (firmware/myproject.cpp:142:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer12_out' with compact=bit mode in 1312-bits (firmware/myproject.cpp:115:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer7_out' with compact=bit mode in 640-bits (firmware/myproject.cpp:88:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer2_out' with compact=bit mode in 296-bits (firmware/myproject.cpp:61:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer44_out' with compact=bit mode in 16-bits (firmware/myproject.cpp:58:25) +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::conv_2d_buffer_resource_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_64' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_65' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_66' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_67' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_68' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_69' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_70' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_71' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_72' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_73' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_74' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_75' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_76' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_77' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_78' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_79' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_80' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_81' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_82' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_83' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_84' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_85' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_86' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_87' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_88' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_89' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_90' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_91' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_92' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_93' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_94' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_95' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_64' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_65' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_66' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_67' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_68' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_69' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_70' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_71' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_72' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_73' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_74' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_75' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_76' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_77' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_78' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_79' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_80' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_81' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_82' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_83' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_84' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_85' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_86' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_87' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_88' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_89' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_90' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_91' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_92' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_93' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_94' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_95' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-248] Applying array_reshape to 'w4': Block reshaping with factor 4 on dimension 1. (firmware/weights/w4.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w7': Block reshaping with factor 8 on dimension 1. (firmware/weights/w7.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w9': Block reshaping with factor 16 on dimension 1. (firmware/weights/w9.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w12': Block reshaping with factor 32 on dimension 1. (firmware/weights/w12.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w14': Block reshaping with factor 64 on dimension 1. (firmware/weights/w14.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w17': Block reshaping with factor 128 on dimension 1. (firmware/weights/w17.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w19': Block reshaping with factor 256 on dimension 1. (firmware/weights/w19.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w23': Block reshaping with factor 192 on dimension 1. (firmware/weights/w23.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w25': Block reshaping with factor 64 on dimension 1. (firmware/weights/w25.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w29': Block reshaping with factor 48 on dimension 1. (firmware/weights/w29.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w31': Block reshaping with factor 16 on dimension 1. (firmware/weights/w31.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w35': Block reshaping with factor 16 on dimension 1. (firmware/weights/w35.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w37': Block reshaping with factor 4 on dimension 1. (firmware/weights/w37.h:12:0) +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadTopWidth> at firmware/nnet_utils/nnet_padding_stream.h:53:9 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadMain> at firmware/nnet_utils/nnet_padding_stream.h:59:5 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadBottomWidth> at firmware/nnet_utils/nnet_padding_stream.h:77:9 +INFO: [HLS 214-291] Loop 'CopyMain' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_padding_stream.h:65:9) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-270] Inferring pragma 'array_partition type=complete dim=1' for array 'ref.tmp.i' due to pipeline pragma +INFO: [HLS 214-248] Applying array_partition to 'ref.tmp.i': Complete partitioning on dimension 1. +INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 263.79 seconds. CPU system time: 5.25 seconds. Elapsed time: 255.78 seconds; current allocated memory: 350.344 MB. +INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 350.414 MB. +INFO: [HLS 200-10] Starting code transformations ... +INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 27.4 seconds. CPU system time: 0.04 seconds. Elapsed time: 27.45 seconds; current allocated memory: 416.434 MB. +INFO: [HLS 200-10] Checking synthesizability ... +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 97.25 seconds. CPU system time: 0.07 seconds. Elapsed time: 97.33 seconds; current allocated memory: 513.395 MB. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-712] Applying dataflow to function 'myproject' (firmware/myproject.cpp:8), detected/extracted 56 process function(s): + 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>' + 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config3>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config5>' + 'nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>' + 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config8>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config10>' + 'nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>' + 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config13>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config15>' + 'nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>' + 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>' + 'nnet::relu, 64u>, nnet::array, 64u>, relu_config18>' + 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>' + 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>' + 'nnet::relu, 64u>, nnet::array, 64u>, relu_config20>' + 'nnet::resize_nearest, 64u>, config21>' + 'nnet::concatenate3d, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' + 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>' + 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config24>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config26>' + 'nnet::resize_nearest, 32u>, config27>' + 'nnet::concatenate3d, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' + 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>' + 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config30>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config32>' + 'nnet::resize_nearest, 16u>, config33>' + 'nnet::concatenate3d, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' + 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>' + 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config36>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config38>' + 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>' + 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>'. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_activation_stream.h:81:9) to (firmware/nnet_utils/nnet_activation_stream.h:80:5) in function 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>'... converting 3 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>'... converting 17 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>'... converting 9 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>'... converting 9 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>'... converting 18 basic blocks. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' (firmware/nnet_utils/nnet_dense_resource.h:46:20)...192 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_mult.h:46:11)...256 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' (firmware/nnet_utils/nnet_dense_resource.h:46:5)...48 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...13 expression(s) balanced. +INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 236.63 seconds. CPU system time: 0.12 seconds. Elapsed time: 236.78 seconds; current allocated memory: 716.414 MB. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_pooling_stream.h:109:5) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_pooling_stream.h:109:5) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_pooling_stream.h:109:5) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeightSerial' (firmware/nnet_utils/nnet_sepconv2d_stream.h:81:9) in function 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ConcatLoopHeight' (firmware/nnet_utils/nnet_merge_stream.h:234:5) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ConcatLoopHeight' (firmware/nnet_utils/nnet_merge_stream.h:234:5) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ConcatLoopHeight' (firmware/nnet_utils/nnet_merge_stream.h:234:5) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>'. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config23_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config19_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config29_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config25_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config17_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config14_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config9_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config35_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config31_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config12_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config58_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0,config7_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0,config4_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0,config2_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config23_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config19_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config29_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config25_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config17_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config14_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config9_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config35_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config31_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config12_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config58_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0,config7_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0,config4_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0,config2_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0'. +INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 34.2 seconds. CPU system time: 0.6 seconds. Elapsed time: 34.8 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] Starting hardware synthesis ... +INFO: [HLS 200-10] Synthesizing 'myproject' ... +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,1u>,config44>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,1u>,config44>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config44>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,1u>,config44>' to 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 1u>, config2>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0,config2_mult>' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config2>' to 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config2>' to 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config3>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config45>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config45>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config45>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,8u>,config45>' to 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config4>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0,config4_mult>' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config4>' to 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config4>' to 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config5>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s'. +WARNING: [SYN 201-103] Legalizing function name 'clone_stream,array,8u>,32768>' to 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config6>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +WARNING: [SYN 201-103] Legalizing function name 'pooling2d_cl,array,8u>,config6>' to 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config46>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config46>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config46>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,8u>,config46>' to 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config7>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0,config7_mult>' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config7>' to 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,16u>,config7>' to 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config8>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config47>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config47>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config47>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config47>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config9>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config9_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config9>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,16u>,config9>' to 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config10>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s'. +WARNING: [SYN 201-103] Legalizing function name 'clone_stream,array,16u>,16384>' to 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config11>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +WARNING: [SYN 201-103] Legalizing function name 'pooling2d_cl,16u>,config11>' to 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config48>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config48>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config48>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config48>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config12>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config12_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config12>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config12>' to 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config13>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config49>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config49>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config49>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config49>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config14>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config14_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config14>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config14>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config15>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s'. +WARNING: [SYN 201-103] Legalizing function name 'clone_stream,array,32u>,8192>' to 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config16>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +WARNING: [SYN 201-103] Legalizing function name 'pooling2d_cl,32u>,config16>' to 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config50>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config50>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config50>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config50>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config17>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config17_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,64u>,config17>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,64u>,config17>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,64u>,relu_config18>' to 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config51>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,64u>,config51>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config51>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,64u>,config51>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 64u>, config19>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config19_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,64u>,config19>' to 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,64u>,config19>' to 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,64u>,relu_config20>' to 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s'. +WARNING: [SYN 201-103] Legalizing function name 'resize_nearest, 64u>, config21>' to 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d_2,96u>,config22>' to 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d,96u>,config22>' to 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config52>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,96u>,config52>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config52>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,96u>,config52>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 96u>, config23>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config23_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config23>' to 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config23>' to 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config24>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config53>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config53>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config53>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config53>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config25>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config25_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config25>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config25>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config26>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s'. +WARNING: [SYN 201-103] Legalizing function name 'resize_nearest, 32u>, config27>' to 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d_2,48u>,config28>' to 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d,48u>,config28>' to 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config54>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,48u>,config54>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config54>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,48u>,config54>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 48u>, config29>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config29_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config29>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,16u>,config29>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config30>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config55>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config55>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config55>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config55>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config31>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config31_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config31>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,16u>,config31>' to 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config32>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s'. +WARNING: [SYN 201-103] Legalizing function name 'resize_nearest, 16u>, config33>' to 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d_2,24u>,config34>' to 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d,24u>,config34>' to 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config56>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,24u>,config56>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config56>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,24u>,config56>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 24u>, config35>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config35_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config35>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config35>' to 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config36>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config57>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config57>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config57>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,8u>,config57>' to 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config37>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config37>' to 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config37>' to 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config38>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config58_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'pointwise_conv_2d_cl,1u>,config58>' to 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_s'. +WARNING: [SYN 201-103] Legalizing function name 'sigmoid,1u>,sigmoid_config40>' to 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s'. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 4.12 seconds. CPU system time: 0.29 seconds. Elapsed time: 4.42 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.95 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.97 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 1u>, config2>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 1u>, config2>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.05 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.411 ns) exceeds the target (target clock period: 5.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 3.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' consists of the following: + 'or' operation 1 bit ('or_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [82] (0.000 ns) + 'or' operation 1 bit ('or_ln144_2', firmware/nnet_utils/nnet_dense_resource.h:144) [84] (0.000 ns) + 'or' operation 1 bit ('or_ln144_6', firmware/nnet_utils/nnet_dense_resource.h:144) [88] (0.000 ns) + 'select' operation 37 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [89] (0.229 ns) + 'select' operation 37 bit ('acc_87', firmware/nnet_utils/nnet_dense_resource.h:144) [93] (0.229 ns) + multiplexor before 'phi' operation 37 bit ('acc') with incoming values : ('acc_87', firmware/nnet_utils/nnet_dense_resource.h:144) [33] (0.387 ns) + 'phi' operation 37 bit ('acc') with incoming values : ('acc_87', firmware/nnet_utils/nnet_dense_resource.h:144) [33] (0.000 ns) + 'sparsemux' operation 37 bit ('tmp_i', firmware/nnet_utils/nnet_dense_resource.h:144) [70] (0.584 ns) + 'add' operation 38 bit of DSP[73] ('add_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [73] (2.039 ns) + 'icmp' operation 1 bit ('icmp_ln144_17', firmware/nnet_utils/nnet_dense_resource.h:144) [81] (0.943 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.99 seconds. CPU system time: 0.01 seconds. Elapsed time: 1 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config4>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config4>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.309 ns) exceeds the target (target clock period: 5.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 3.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s' consists of the following: + 'select' operation 40 bit ('select_ln144_40', firmware/nnet_utils/nnet_dense_resource.h:144) [329] (0.230 ns) + 'select' operation 40 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [331] (0.230 ns) + 'select' operation 40 bit ('acc_74', firmware/nnet_utils/nnet_dense_resource.h:144) [338] (0.230 ns) + multiplexor before 'phi' operation 40 bit ('acc') with incoming values : ('acc_74', firmware/nnet_utils/nnet_dense_resource.h:144) [153] (0.387 ns) + 'phi' operation 40 bit ('acc') with incoming values : ('acc_74', firmware/nnet_utils/nnet_dense_resource.h:144) [153] (0.000 ns) + 'select' operation 40 bit ('select_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [324] (0.230 ns) + 'add' operation 41 bit of DSP[327] ('add_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [327] (2.039 ns) + 'icmp' operation 1 bit ('icmp_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [328] (0.963 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.29 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.31 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'CloneLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'CloneLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config6>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config6>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReadInputHeight_ReadInputWidth'. +WARNING: [HLS 200-880] The II Violation in module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' (loop 'ReadInputHeight_ReadInputWidth'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between 'load' operation 16 bit ('void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_32', firmware/nnet_utils/nnet_pooling_stream.h:63->firmware/nnet_utils/nnet_pooling_stream.h:115) on static variable 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel' and 'call' operation 0 bit ('_ln52', firmware/nnet_utils/nnet_pooling_stream.h:52->firmware/nnet_utils/nnet_pooling_stream.h:115) to 'shift_line_buffer, 8u>, config6>'. +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 2, Depth = 3, loop 'ReadInputHeight_ReadInputWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.45 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.46 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config7>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config7>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.324 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.324 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.309 ns) exceeds the target (target clock period: 5.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 3.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s' consists of the following: + 'select' operation 40 bit ('select_ln144_1', firmware/nnet_utils/nnet_dense_resource.h:144) [337] (0.230 ns) + 'select' operation 40 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [339] (0.230 ns) + 'select' operation 40 bit ('acc_40', firmware/nnet_utils/nnet_dense_resource.h:144) [346] (0.230 ns) + multiplexor before 'phi' operation 40 bit ('acc') with incoming values : ('acc_40', firmware/nnet_utils/nnet_dense_resource.h:144) [153] (0.387 ns) + 'phi' operation 40 bit ('acc') with incoming values : ('acc_40', firmware/nnet_utils/nnet_dense_resource.h:144) [153] (0.000 ns) + 'select' operation 40 bit ('select_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [332] (0.230 ns) + 'add' operation 41 bit of DSP[335] ('add_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [335] (2.039 ns) + 'icmp' operation 1 bit ('icmp_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [336] (0.963 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.34 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.35 seconds; current allocated memory: 2.329 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.329 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.329 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.329 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.329 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.329 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.329 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.330 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.330 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.330 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.45 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.49 seconds; current allocated memory: 2.332 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.333 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.333 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.333 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.333 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.333 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config9>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config9>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.333 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.333 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.47 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.5 seconds; current allocated memory: 2.348 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.348 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.348 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.348 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.348 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.348 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.348 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.348 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'CloneLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'CloneLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.348 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.348 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config11>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config11>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.348 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.348 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReadInputHeight_ReadInputWidth'. +WARNING: [HLS 200-880] The II Violation in module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' (loop 'ReadInputHeight_ReadInputWidth'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between 'load' operation 16 bit ('void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_52', firmware/nnet_utils/nnet_pooling_stream.h:63->firmware/nnet_utils/nnet_pooling_stream.h:115) on static variable 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_20' and 'call' operation 0 bit ('_ln52', firmware/nnet_utils/nnet_pooling_stream.h:52->firmware/nnet_utils/nnet_pooling_stream.h:115) to 'shift_line_buffer, 16u>, config11>'. +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 2, Depth = 3, loop 'ReadInputHeight_ReadInputWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.21 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.23 seconds; current allocated memory: 2.348 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.348 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.348 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.348 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.29 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.32 seconds; current allocated memory: 2.348 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.348 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.348 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.348 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.348 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.348 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config12>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config12>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.348 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.348 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.6 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.64 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.16 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.31 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.33 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config14>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config14>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.28 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.31 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.1 seconds. CPU system time: 0.03 seconds. Elapsed time: 1.13 seconds; current allocated memory: 2.421 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.27 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.28 seconds; current allocated memory: 2.421 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.23 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.25 seconds; current allocated memory: 2.421 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.421 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.421 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.421 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.2 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.421 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.421 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'CloneLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'CloneLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.421 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.421 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config16>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config16>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.421 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.421 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReadInputHeight_ReadInputWidth'. +WARNING: [HLS 200-880] The II Violation in module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' (loop 'ReadInputHeight_ReadInputWidth'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between 'load' operation 16 bit ('void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_42', firmware/nnet_utils/nnet_pooling_stream.h:63->firmware/nnet_utils/nnet_pooling_stream.h:115) on static variable 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_19' and 'call' operation 0 bit ('_ln52', firmware/nnet_utils/nnet_pooling_stream.h:52->firmware/nnet_utils/nnet_pooling_stream.h:115) to 'shift_line_buffer, 32u>, config16>'. +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 2, Depth = 3, loop 'ReadInputHeight_ReadInputWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.31 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.33 seconds; current allocated memory: 2.421 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.421 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.421 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.421 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 7, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 9, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 10, Depth = 11, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.25 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.27 seconds; current allocated memory: 2.421 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.421 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.421 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.421 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.421 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.421 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config17>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config17>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.3 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.31 seconds; current allocated memory: 2.421 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.421 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.7 seconds. CPU system time: 0.05 seconds. Elapsed time: 1.76 seconds; current allocated memory: 2.497 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.38 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.39 seconds; current allocated memory: 2.497 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.26 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.3 seconds; current allocated memory: 2.497 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.497 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.497 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.497 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.22 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.25 seconds; current allocated memory: 2.497 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.497 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.497 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.497 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 7, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 9, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 10, Depth = 11, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.25 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.27 seconds; current allocated memory: 2.497 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.497 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.497 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.497 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.497 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.497 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 64u>, config19>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 64u>, config19>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.6 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.62 seconds; current allocated memory: 2.497 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.19 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.497 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 4.04 seconds. CPU system time: 0.08 seconds. Elapsed time: 4.11 seconds; current allocated memory: 2.578 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.94 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.97 seconds; current allocated memory: 2.578 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.43 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.47 seconds; current allocated memory: 2.578 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.578 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.2 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.578 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.578 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.27 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.29 seconds; current allocated memory: 2.578 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.578 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ImageHeight'. +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_1', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_2', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_3', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_4', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 32, Depth = 32, loop 'ImageHeight' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.37 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.41 seconds; current allocated memory: 2.578 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.578 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ConcatLoopHeight_ConcatLoopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'ConcatLoopHeight_ConcatLoopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.578 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.578 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.578 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.578 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.578 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.578 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.34 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.36 seconds; current allocated memory: 2.578 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.578 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.578 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.578 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.578 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.578 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 96u>, config23>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 96u>, config23>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.08 seconds. CPU system time: 0 seconds. Elapsed time: 1.08 seconds; current allocated memory: 2.578 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.29 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.32 seconds; current allocated memory: 2.578 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 5, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 4.26 seconds. CPU system time: 0.08 seconds. Elapsed time: 4.33 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 1.11 seconds. CPU system time: 0.05 seconds. Elapsed time: 1.15 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.48 seconds. CPU system time: 0.06 seconds. Elapsed time: 0.55 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.14 seconds. CPU system time: 0 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.25 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.26 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.25 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.27 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.34 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.37 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config25>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config25>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.32 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.32 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 1.13 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.3 seconds. CPU system time: 0 seconds. Elapsed time: 0.3 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.23 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.25 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.21 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ImageHeight'. +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_1', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_2', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_3', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_4', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 64, Depth = 64, loop 'ImageHeight' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.7 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.72 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ConcatLoopHeight_ConcatLoopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'ConcatLoopHeight_ConcatLoopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.56 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.57 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 48u>, config29>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 48u>, config29>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.46 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.47 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.16 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.28 seconds. CPU system time: 0.01 seconds. Elapsed time: 1.3 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.37 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.4 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.28 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.3 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.2 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.55 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.58 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config31>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config31>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.23 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.23 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.52 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.53 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ImageHeight'. +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_1', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_2', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_3', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_4', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 67, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 98, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 114, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 122, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 126, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 127, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 128, Depth = 128, loop 'ImageHeight' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.74 seconds. CPU system time: 0.04 seconds. Elapsed time: 1.79 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ConcatLoopHeight_ConcatLoopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'ConcatLoopHeight_ConcatLoopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.13 seconds. CPU system time: 0.05 seconds. Elapsed time: 1.18 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 24u>, config35>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 24u>, config35>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.29 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.3 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.59 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.61 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.19 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.11 seconds. CPU system time: 0.05 seconds. Elapsed time: 1.16 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config37>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config37>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.2 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.309 ns) exceeds the target (target clock period: 5.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 3.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s' consists of the following: + 'select' operation 40 bit ('select_ln144_59', firmware/nnet_utils/nnet_dense_resource.h:144) [329] (0.230 ns) + 'select' operation 40 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [331] (0.230 ns) + 'select' operation 40 bit ('acc_109', firmware/nnet_utils/nnet_dense_resource.h:144) [338] (0.230 ns) + multiplexor before 'phi' operation 40 bit ('acc') with incoming values : ('acc_109', firmware/nnet_utils/nnet_dense_resource.h:144) [153] (0.387 ns) + 'phi' operation 40 bit ('acc') with incoming values : ('acc_109', firmware/nnet_utils/nnet_dense_resource.h:144) [153] (0.000 ns) + 'select' operation 40 bit ('select_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [324] (0.230 ns) + 'add' operation 41 bit of DSP[327] ('add_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [327] (2.039 ns) + 'icmp' operation 1 bit ('icmp_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [328] (0.963 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.37 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.38 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'SigmoidActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 4, loop 'SigmoidActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'myproject' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +WARNING: [HLS 200-1020] Increasing the depth of FIFO start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0 (from clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0 to concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0) to 10 to improve performance and/or avoid deadlocks. +WARNING: [HLS 200-1020] Increasing the depth of FIFO start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0 (from clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_U0 to concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0) to 26 to improve performance and/or avoid deadlocks. +WARNING: [HLS 200-1020] Increasing the depth of FIFO start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0 (from clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0 to concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0) to 42 to improve performance and/or avoid deadlocks. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.44 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.45 seconds; current allocated memory: 2.636 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.33 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.35 seconds; current allocated memory: 2.636 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.72 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.76 seconds; current allocated memory: 2.637 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.641 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.643 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.644 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_cud' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.644 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_outidx_1_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_oudEe' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_w2_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_w2eOg' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_37s_38_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_17_3_37_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_19_4_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_oudEe' using auto ROMs. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_w2eOg' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.3 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.33 seconds; current allocated memory: 2.646 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_7' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.41 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.47 seconds; current allocated memory: 2.651 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.651 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.652 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.655 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.657 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.659 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.660 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1375_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_fYi' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1383_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_g8j' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1376_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_hbi' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1384_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_ibs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1377_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_jbC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1385_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_kbM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1378_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_lbW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1386_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_mb6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1379_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_ncg' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1387_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_ocq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1380_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_pcA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1388_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_qcK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1381_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_rcU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1389_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_sc4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1382_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_tde' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1390_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_udo' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.47 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.51 seconds; current allocated memory: 2.663 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_outidx_2_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_ouvdy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_w4_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_w4wdI' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_40s_41_1_1': 3 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_40s_41_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_ouvdy' using auto ROMs. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_w4wdI' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.38 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.41 seconds; current allocated memory: 2.668 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_13' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.87 seconds. CPU system time: 0.19 seconds. Elapsed time: 2.06 seconds; current allocated memory: 2.677 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.680 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.14 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.681 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.1 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.682 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stxdS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_styd2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stzec' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stAem' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stBew' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stCeG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stDeQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stEe0' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.31 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.32 seconds; current allocated memory: 2.685 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'sY' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX' is power-on initialization. +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' pipeline 'ReadInputHeight_ReadInputWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.97 seconds. CPU system time: 0.09 seconds. Elapsed time: 1.06 seconds; current allocated memory: 2.687 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.690 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.693 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.14 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.696 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.696 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1359_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Ffa' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1367_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Gfk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1360_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Hfu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1368_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_IfE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1361_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_JfO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1369_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_KfY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1362_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Lf8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1370_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Mgi' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1363_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Ngs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1371_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_OgC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1364_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_PgM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1372_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_QgW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1365_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Rg6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1373_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Shg' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1366_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Thq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1374_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_UhA' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.48 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.53 seconds; current allocated memory: 2.698 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_outidx_3_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_ouVhK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_w7_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_w7WhU' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_11s_40s_41_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_40s_41_1_1': 7 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_w7WhU' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.37 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.41 seconds; current allocated memory: 2.702 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_38' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_30' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_39' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_31' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_32' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_33' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_34' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_35' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_36' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_37' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_15' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 2 seconds. CPU system time: 0.19 seconds. Elapsed time: 2.2 seconds; current allocated memory: 2.715 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.718 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.721 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.724 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.725 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.727 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_799_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dXh4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_815_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dYie' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_800_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dZio' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_816_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d0iy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_807_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d1iI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_823_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d2iS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_808_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d3i2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_824_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d4jc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_809_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d5jm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_825_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d6jw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_810_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d7jG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_826_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d8jQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_811_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d9j0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_827_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbak' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_812_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbbk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_828_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbck' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_813_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbdk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_829_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbek' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_814_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbfk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_830_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbgk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_801_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbhl' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_817_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbil' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_802_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbjl' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_818_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbkl' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_803_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbll' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_819_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbml' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_804_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbnm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_820_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbom' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_805_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbpm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_821_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbqm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_806_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbrm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_822_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbsm' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.91 seconds. CPU system time: 0.08 seconds. Elapsed time: 0.98 seconds; current allocated memory: 2.730 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbtn' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_11s_34s_34_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_39s_39_1_1': 15 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_289_8_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbtn' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.42 seconds. CPU system time: 0.06 seconds. Elapsed time: 0.49 seconds; current allocated memory: 2.740 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4177' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4178' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4179' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4180' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4181' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4182' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4183' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4184' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4185' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4186' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4188' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4122' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4189' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4134' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4190' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4191' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4192' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4137' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4123' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4124' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4125' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4126' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4127' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4128' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4129' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4130' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4131' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4133' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4135' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4136' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_9' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 3.91 seconds. CPU system time: 0.38 seconds. Elapsed time: 4.27 seconds; current allocated memory: 2.758 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.2 seconds. CPU system time: 0 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.761 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.763 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.765 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bun' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bvn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bwn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bxn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_byn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bzo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bAo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bBo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bCo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bDo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_27_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbEo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_26_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbFp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_25_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbGp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_24_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbHp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_23_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbIp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_22_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbJp' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.54 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.58 seconds; current allocated memory: 2.768 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'sY_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_11' is power-on initialization. +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' pipeline 'ReadInputHeight_ReadInputWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.9 seconds. CPU system time: 0.19 seconds. Elapsed time: 2.08 seconds; current allocated memory: 2.773 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.24 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.27 seconds; current allocated memory: 2.779 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.780 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.783 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.783 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_863_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_879_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bLp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_864_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bMq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_880_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bNq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_871_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bOq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_887_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bPq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_872_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bQq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_888_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bRq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_873_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bSr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_889_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bTr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_874_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bUr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_890_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bVr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_875_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bWr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_891_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bXr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_876_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bYs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_892_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bZs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_877_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b0s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_893_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b1s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_878_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b2s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_894_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b3s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_865_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b4t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_881_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b5t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_866_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b6t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_882_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b7t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_867_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b8t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_883_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b9t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_868_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2cau' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_884_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2cbu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_869_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2ccu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_885_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2cdu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_870_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2ceu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_886_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2cfu' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.92 seconds. CPU system time: 0.12 seconds. Elapsed time: 1.03 seconds; current allocated memory: 2.786 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s_w12_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s_w12_Rcgu' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_33s_33_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_39s_39_1_1': 31 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_289_8_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s_w12_Rcgu' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.49 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.55 seconds; current allocated memory: 2.800 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4416' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4428' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4441' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4453' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4465' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4432' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4433' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4434' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4435' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4436' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4417' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4437' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4419' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4438' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4420' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4439' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4421' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4442' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4422' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4443' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4423' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4444' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4424' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4445' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4425' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4446' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4426' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4447' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4427' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4448' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4430' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4449' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4431' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4450' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4452' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4454' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4455' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4456' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4457' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4458' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4459' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4460' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4461' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4463' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4464' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4466' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4467' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4468' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4469' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_8' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.2 seconds. CPU system time: 0.34 seconds. Elapsed time: 4.54 seconds; current allocated memory: 2.821 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.21 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.825 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.2 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.23 seconds; current allocated memory: 2.827 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.21 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.830 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.832 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.835 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.835 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_943_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2chv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_975_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2civ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_944_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cjv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_976_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2ckv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_955_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2clv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_987_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cmv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_966_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cnw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_998_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cow' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_969_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cpw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1001_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cqw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_970_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2crw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1002_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2csw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_971_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2ctx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1003_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cux' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_972_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cvx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1004_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cwx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_973_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cxx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1005_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cyx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_974_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2czy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1006_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cAy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_945_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cBy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_977_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cCy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_946_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cDy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_978_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cEy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_947_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cFz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_979_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cGz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_948_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cHz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_980_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cIz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_949_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cJz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_981_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cKz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_950_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cLz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_982_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cMA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_951_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cNA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_983_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cOA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_952_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cPA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_984_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cQA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_953_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cRA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_985_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cSB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_954_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cTB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_986_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cUB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_956_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cVB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_988_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cWB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_957_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cXB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_989_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cYC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_958_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cZC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_990_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c0C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_959_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c1C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_991_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c2C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_960_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c3C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_992_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c4D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_961_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c5D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_993_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c6D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_962_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c7D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_994_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c8D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_963_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c9D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_995_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2daE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_964_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dbE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_996_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dcE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_965_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2ddE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_997_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2deE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_967_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dfE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_999_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dgE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_968_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dhF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1000_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2diF' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.84 seconds. CPU system time: 0.18 seconds. Elapsed time: 2.03 seconds; current allocated memory: 2.840 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s_w14_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s_w14_RdjF' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s' is 9216 from HDL expression: (do_init_reg_1233 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 31 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 32 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_289_8_16_1_1': 2 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s_w14_RdjF' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.78 seconds. CPU system time: 0.06 seconds. Elapsed time: 0.85 seconds; current allocated memory: 2.866 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5021' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_89' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5022' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_88' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5024' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_87' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5025' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_86' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5026' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_85' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5027' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_84' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5028' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_83' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5029' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_82' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5030' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_81' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5031' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_80' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5032' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5033' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5035' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5036' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5037' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4839' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5038' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4851' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5039' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4863' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5040' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4875' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5041' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4887' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5042' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4899' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5043' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4911' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5044' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4923' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5046' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4936' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5047' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4948' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5048' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4960' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5049' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4972' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5050' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4984' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5051' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4996' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5052' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5008' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5053' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5018' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5054' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5019' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5055' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5020' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5092' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5093' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5094' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5095' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4840' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4841' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4842' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4843' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4844' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4845' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4846' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4848' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4849' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4850' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4852' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4853' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4854' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4855' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4856' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4857' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4859' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4860' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4861' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4862' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4941' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4903' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4942' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4904' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4943' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4905' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4944' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4906' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4945' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4907' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4947' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4908' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4949' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4909' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4950' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4910' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4951' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4912' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4952' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4914' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4953' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4915' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4954' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4916' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4955' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4917' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4956' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4918' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4958' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4919' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4959' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4920' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4961' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4921' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4962' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4922' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4963' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4925' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4964' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4926' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4965' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4927' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4966' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4928' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4967' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4929' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4969' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4930' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4970' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4931' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4971' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4932' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4973' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4933' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4974' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4934' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4975' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4937' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4976' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4938' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4977' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4939' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4978' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4940' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5057' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5058' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5059' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5060' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5061' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5062' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5063' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5064' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5065' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5066' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5068' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5069' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5070' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5071' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5072' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5073' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5074' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5075' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5076' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5077' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5079' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5080' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5081' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5082' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5083' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5084' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5085' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5086' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5087' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5088' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5090' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5091' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4864' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4865' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4866' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4867' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4868' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4870' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4871' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4872' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4873' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4874' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4876' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4877' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4878' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4879' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4881' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4882' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4883' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4884' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4885' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4886' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4888' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4889' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4890' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4892' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4893' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4894' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4895' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4896' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4897' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4898' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4900' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4901' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4980' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4981' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4982' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4983' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4985' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4986' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4987' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4988' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4989' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4991' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4992' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4993' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4994' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4995' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4997' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4998' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5000' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5002' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5003' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5004' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5005' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5006' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5007' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5009' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5010' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5011' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5013' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5014' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5015' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5016' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5017' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_5' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 8.52 seconds. CPU system time: 0.82 seconds. Elapsed time: 9.35 seconds; current allocated memory: 2.903 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.27 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.3 seconds; current allocated memory: 2.909 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.26 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.27 seconds; current allocated memory: 2.912 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.2 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.915 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dkF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dlF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dmF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dnG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_doG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dpG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dqG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_drG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dsG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dtH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_21_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolinduH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_20_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindvH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_19_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindwH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_18_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindxH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_17_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindyH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_16_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindzI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_15_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindAI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_14_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindBI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_13_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindCI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_12_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindDI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_11_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindEI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_10_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindFJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindGJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindHJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindIJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindJJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindKJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindLJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindMK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindNK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindOK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindPK' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.07 seconds. CPU system time: 0.08 seconds. Elapsed time: 1.16 seconds; current allocated memory: 2.918 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'sY_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_89' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_57' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_88' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_56' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_87' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_55' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_86' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_54' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_85' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_53' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_84' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_52' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_83' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_51' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_82' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_50' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_81' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_49' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_80' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_48' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_79' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_47' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_78' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_46' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_77' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_45' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_76' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_44' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_75' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_43' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_74' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_42' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_73' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_41' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_72' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_40' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_71' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_39' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_70' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_38' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_69' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_37' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_68' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_36' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_99' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_67' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_35' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_98' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_66' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_34' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_97' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_65' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_33' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_96' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_64' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_32' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_95' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_63' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_31' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_94' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_62' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_30' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_93' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_61' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_92' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_60' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_91' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_59' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_90' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_58' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_3' is power-on initialization. +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' pipeline 'ReadInputHeight_ReadInputWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.03 seconds. CPU system time: 0.4 seconds. Elapsed time: 4.42 seconds; current allocated memory: 2.930 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.38 seconds; current allocated memory: 2.940 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.941 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.942 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.944 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1071_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dQK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1103_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dRK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1072_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dSL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1104_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dTL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1083_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dUL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1115_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dVL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1094_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dWL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1126_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dXL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1097_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dYM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1129_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dZM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1098_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d0M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1130_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d1M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1099_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d2M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1131_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d3M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1100_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d4N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1132_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d5N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1101_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d6N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1133_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d7N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1102_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d8N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1134_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d9N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1073_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eaO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1105_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ebO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1074_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ecO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1106_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2edO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1075_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eeO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1107_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2efO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1076_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2egO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1108_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ehP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1077_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eiP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1109_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ejP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1078_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ekP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1110_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2elP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1079_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2emP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1111_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2enQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1080_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eoQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1112_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2epQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1081_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eqQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1113_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2erQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1082_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2esQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1114_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2etR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1084_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2euR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1116_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2evR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1085_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ewR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1117_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2exR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1086_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eyR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1118_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ezS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1087_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eAS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1119_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eBS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1088_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eCS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1120_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eDS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1089_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eES' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1121_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eFT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1090_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eGT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1122_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eHT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1091_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eIT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1123_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eJT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1092_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eKT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1124_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eLT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1093_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eMU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1125_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eNU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1095_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eOU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1127_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ePU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1096_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eQU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1128_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eRU' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 2.05 seconds. CPU system time: 0.19 seconds. Elapsed time: 2.24 seconds; current allocated memory: 2.949 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s_w17_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s_w17_ReSV' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s' is 9216 from HDL expression: (do_init_reg_1555 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 63 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 64 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_289_8_16_1_1': 2 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s_w17_ReSV' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.99 seconds. CPU system time: 0.08 seconds. Elapsed time: 1.08 seconds; current allocated memory: 2.986 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_69' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_68' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_67' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_66' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_65' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_64' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_63' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_62' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_61' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_60' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5402' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5414' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5426' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5438' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5450' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5462' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5436' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5437' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5439' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5440' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5442' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5403' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5443' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5404' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5444' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5405' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5445' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5406' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5446' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5407' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5447' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5409' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5448' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5410' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5449' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5411' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5451' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5412' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5453' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5413' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5454' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5415' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5455' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5416' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5456' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5417' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5457' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5418' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5458' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5420' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5459' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5421' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5460' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5422' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5461' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5423' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5464' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5424' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5465' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5425' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5466' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5427' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5467' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5428' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5468' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5429' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5469' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5431' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5432' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5433' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5434' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5435' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_10' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 9.55 seconds. CPU system time: 1.04 seconds. Elapsed time: 10.6 seconds; current allocated memory: 3.034 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.33 seconds; current allocated memory: 3.040 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.34 seconds; current allocated memory: 3.044 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.28 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.31 seconds; current allocated memory: 3.050 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.2 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.22 seconds; current allocated memory: 3.051 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.21 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.22 seconds; current allocated memory: 3.052 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.18 seconds; current allocated memory: 3.053 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1231_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eTV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1295_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eUV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1232_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eVV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1296_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eWV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1243_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eXV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1307_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eYW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1254_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eZW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1318_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e0W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1265_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e1W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1329_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e2W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1276_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e3W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1340_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e4X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1287_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e5X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1351_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e6X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1292_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e7X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1356_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e8X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1293_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e9X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1357_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2faY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1294_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fbY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1358_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fcY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1233_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fdY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1297_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2feY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1234_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ffY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1298_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fgY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1235_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fhZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1299_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fiZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1236_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fjZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1300_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fkZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1237_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2flZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1301_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fmZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1238_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fn0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1302_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fo0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1239_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fp0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1303_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fq0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1240_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fr0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1304_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fs0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1241_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ft1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1305_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fu1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1242_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fv1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1306_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fw1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1244_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fx1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1308_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fy1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1245_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fz2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1309_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fA2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1246_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fB2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1310_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fC2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1247_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fD2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1311_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fE2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1248_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fF3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1312_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fG3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1249_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fH3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1313_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fI3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1250_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fJ3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1314_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fK3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1251_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fL3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1315_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fM4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1252_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fN4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1316_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fO4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1253_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fP4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1317_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fQ4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1255_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fR4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1319_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fS5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1256_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fT5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1320_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fU5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1257_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fV5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1321_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fW5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1258_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fX5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1322_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fY6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1259_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fZ6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1323_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f06' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1260_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f16' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1324_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f26' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1261_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f36' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1325_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f47' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1262_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f57' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1326_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f67' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1263_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f77' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1327_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f87' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1264_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f97' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1328_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ga8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1266_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gb8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1330_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gc8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1267_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gd8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1331_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ge8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1268_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gf8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1332_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gg8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1269_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gh9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1333_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gi9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1270_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gj9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1334_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gk9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1271_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gl9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1335_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gm9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1272_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1336_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1273_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1337_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1274_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2grb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1338_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1275_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gtb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1339_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1277_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1341_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1278_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1342_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1279_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1343_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gAb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1280_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gBb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1344_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gCb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1281_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gDb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1345_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gEb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1282_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gFb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1346_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gGb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1283_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gHb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1347_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gIb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1284_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gJb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1348_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gKb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1285_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gLb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1349_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gMb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1286_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1350_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1288_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1352_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1289_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1353_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1290_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1354_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1291_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1355_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gWb_x' due to conflict. +INFO: [RTGEN 206-104] Estimated max fanout for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s' is 9216 from HDL expression: (1'b1 == ap_CS_fsm_state1) +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.6 seconds. CPU system time: 0.44 seconds. Elapsed time: 5.04 seconds; current allocated memory: 3.066 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s_w19_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s_w19_RgXb' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s' is 18432 from HDL expression: (do_init_reg_2641 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 127 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 128 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_289_8_16_1_1': 4 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s_w19_RgXb' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.6 seconds. CPU system time: 0.14 seconds. Elapsed time: 1.75 seconds; current allocated memory: 3.128 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_49' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_48' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_47' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_46' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_45' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_44' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_43' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_42' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_41' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_40' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6184' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6293' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6305' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6317' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6329' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6341' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6353' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6366' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6378' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6390' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6402' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6414' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6426' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6438' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6450' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6462' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6177' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6179' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6180' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6181' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6182' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6183' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6185' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6186' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6187' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6188' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6190' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6191' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6192' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6361' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6362' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6363' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6364' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6287' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6367' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6289' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6368' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6290' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6369' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6291' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6370' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6292' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6371' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6294' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6372' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6295' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6373' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6296' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6374' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6297' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6375' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6298' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6377' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6300' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6379' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6301' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6380' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6302' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6381' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6303' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6382' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6304' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6383' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6306' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6384' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6307' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6385' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6308' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6386' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6309' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6388' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6311' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6389' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6312' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6391' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6313' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6392' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6314' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6393' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6315' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6394' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6316' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6395' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6318' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6396' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6319' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6397' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6320' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6399' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6322' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6400' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6323' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6401' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6324' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6403' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6325' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6404' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6326' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6405' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6327' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6406' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6328' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6407' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6330' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6408' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6331' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6410' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6333' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6411' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6334' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6412' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6335' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6413' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6336' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6415' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6337' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6416' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6338' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6417' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6339' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6418' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6340' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6419' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6342' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6421' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6344' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6422' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6345' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6423' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6346' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6424' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6347' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6425' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6348' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6427' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6349' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6428' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6350' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6429' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6351' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6430' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6352' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6432' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6355' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6433' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6356' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6434' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6357' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6435' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6358' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6436' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6359' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6437' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6360' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6439' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6440' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6441' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6443' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6444' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6445' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6446' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6447' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6448' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6449' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6451' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6452' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6454' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6455' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6456' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6457' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6458' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6459' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6460' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6461' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6463' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6465' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6466' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6467' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6468' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6469' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_16' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 20.84 seconds. CPU system time: 1.92 seconds. Elapsed time: 22.8 seconds; current allocated memory: 3.216 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.45 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.48 seconds; current allocated memory: 3.225 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.38 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.43 seconds; current allocated memory: 3.230 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.28 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.31 seconds; current allocated memory: 3.237 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' pipeline 'ConcatLoopHeight_ConcatLoopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.22 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.26 seconds; current allocated memory: 3.240 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.21 seconds; current allocated memory: 3.242 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.22 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.25 seconds; current allocated memory: 3.242 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.23 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.26 seconds; current allocated memory: 3.243 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.24 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.26 seconds; current allocated memory: 3.244 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.21 seconds; current allocated memory: 3.246 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1407_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2gYb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_95_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2gZb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1408_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_94_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1419_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_83_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1430_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_72_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1441_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_61_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1452_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_50_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1463_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_39_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1474_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_28_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1485_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2heb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_17_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1496_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1409_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_93_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1410_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_92_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hlb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1411_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_91_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1412_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_90_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1413_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_89_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1414_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_88_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2htb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1415_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_87_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1416_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_86_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1417_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_85_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1418_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_84_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1420_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_82_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1421_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_81_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1422_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_80_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1423_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_79_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1424_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_78_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1425_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_77_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1426_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_76_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1427_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_75_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1428_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_74_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1429_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_73_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1431_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_71_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1432_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_70_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1433_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_69_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1434_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_68_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1435_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_67_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1436_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_66_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1437_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_65_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1438_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_64_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ibb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1439_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2icb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_63_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2idb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1440_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ieb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_62_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ifb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1442_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2igb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_60_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ihb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1443_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_59_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ijb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1444_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ikb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_58_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ilb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1445_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2imb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_57_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2inb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1446_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_56_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ipb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1447_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_55_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2irb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1448_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2isb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_54_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2itb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1449_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_53_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ivb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1450_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_52_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ixb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1451_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_51_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2izb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1453_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_49_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1454_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_48_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1455_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_47_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1456_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_46_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1457_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_45_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1458_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_44_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1459_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_43_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1460_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_42_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1461_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_41_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1462_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_40_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1464_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_38_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1465_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_37_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1466_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_36_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1467_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_35_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1468_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_34_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1469_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_33_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1470_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_32_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1471_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_31_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1472_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_30_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1473_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_29_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1475_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jeb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_27_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1476_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_26_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1477_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_25_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1478_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_24_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jlb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1479_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_23_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1480_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2job' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_22_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1481_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_21_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1482_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_20_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jtb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1483_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_19_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1484_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_18_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1486_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_16_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1487_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_15_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1488_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_14_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1489_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_13_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1490_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_12_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1491_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_11_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1492_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_10_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1493_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1494_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1495_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1497_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1498_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_99_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_98_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_97_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_96_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j3b' due to the length limit 80 +INFO: [RTGEN 206-104] Estimated max fanout for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s' is 13824 from HDL expression: (1'b1 == ap_CS_fsm_state1) +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 10.2 seconds. CPU system time: 1.04 seconds. Elapsed time: 11.25 seconds; current allocated memory: 3.264 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_w23_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_w23_Rj4b' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' is 27648 from HDL expression: (do_init_reg_2899 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 64 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_33s_33_1_1': 63 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 64 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_289_8_16_1_1': 6 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_w23_Rj4b' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 2.05 seconds. CPU system time: 0.15 seconds. Elapsed time: 2.22 seconds; current allocated memory: 3.335 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3846' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3857' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3868' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3879' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3890' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3901' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3912' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3923' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3934' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3945' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3956' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3967' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3978' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3989' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4000' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4011' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4022' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4033' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4044' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4055' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4066' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4077' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4088' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4099' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4110' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4121' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4363' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4847' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4968' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5089' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5331' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5452' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5936' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6057' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6178' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6299' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6420' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_94' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_83' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_72' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_61' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_50' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_39' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3928' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3929' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3930' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3931' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3932' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3933' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3935' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3936' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3937' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3938' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3939' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3940' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3941' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3942' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3943' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3944' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3839' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3946' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3840' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3947' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3841' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3948' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3842' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3949' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3843' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3950' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3844' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3951' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3845' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3952' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3847' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3953' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3848' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3954' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3849' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3955' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3850' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3957' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3851' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3958' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3852' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3959' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3853' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3960' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3854' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3961' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3855' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3962' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3856' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3963' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3858' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3964' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3859' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3965' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3860' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3966' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3861' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3968' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3862' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3969' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3863' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3970' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3864' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3971' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3865' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3972' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3866' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3973' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3867' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3974' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3869' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3975' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3870' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3976' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3871' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3977' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3872' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3979' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3873' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3980' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3874' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3981' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3875' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3982' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3876' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3983' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3877' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3984' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3878' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3985' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3880' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3986' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3881' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3987' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3882' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3988' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3883' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3990' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3884' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3991' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3885' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3992' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3886' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3993' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3887' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3994' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3888' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3995' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3889' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3996' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3891' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3997' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3892' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3998' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3893' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3894' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4001' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3895' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4002' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3896' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4003' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3897' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4004' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3898' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4005' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3899' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4006' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3900' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4007' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3902' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4008' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3903' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4009' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3904' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4010' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3905' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4012' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3906' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4013' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3907' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4014' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3908' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4015' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3909' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4016' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3910' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4017' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3911' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4018' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3913' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4019' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3914' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4020' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3915' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4021' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3916' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4023' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3917' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4024' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3918' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4025' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3919' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4026' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3920' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4027' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3921' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4028' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3922' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4029' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3924' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4030' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3925' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4031' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3926' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4032' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3927' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4319' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4330' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4341' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4352' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4374' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4385' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4396' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4407' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4418' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4429' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4440' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4451' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4462' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5848' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5859' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5870' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5881' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5892' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5903' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5914' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5925' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5947' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5958' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5969' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5980' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5991' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6002' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6013' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4858' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6024' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4869' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6035' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4880' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6046' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4891' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6068' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4902' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6079' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4913' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6090' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4924' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6101' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4935' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6112' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4946' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6123' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4957' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6134' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4979' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4990' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5001' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5012' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6189' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5023' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5034' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5045' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5056' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5067' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5078' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5100' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5111' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5122' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6288' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5133' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6310' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6321' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6332' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6343' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5177' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6354' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5188' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6365' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6376' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6387' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6398' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6409' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6431' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6442' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6453' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5287' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6464' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5298' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5309' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5320' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5342' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5353' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5364' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5375' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5386' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5397' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5408' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5419' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5430' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5441' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5463' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4034' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4035' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4036' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4037' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4038' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4039' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4040' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4041' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4042' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4043' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4045' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4046' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4047' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4048' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4049' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4050' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4051' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4052' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4053' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4054' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4056' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4057' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4058' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4059' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4060' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4061' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4062' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4063' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4064' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4065' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4067' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4068' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4069' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4070' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4071' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4072' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4073' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4074' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4075' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4076' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4078' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4079' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4080' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4081' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4082' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4083' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4084' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4085' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4086' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4087' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4089' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4090' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4091' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4092' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4093' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4094' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4095' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4096' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4097' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4098' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4100' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4101' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4102' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4103' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4104' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4105' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4106' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4107' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4108' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4109' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4111' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4112' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4113' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4114' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4115' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4116' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4117' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4118' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4119' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4120' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4132' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4187' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4297' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4308' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_99' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_98' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_97' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_96' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_95' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_93' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_92' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_91' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_90' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_89' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_88' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_87' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_86' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_85' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_84' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_82' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_81' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_80' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_79' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_78' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_77' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_76' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_75' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_74' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_73' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_71' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_70' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_69' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_68' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_67' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_66' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_65' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_64' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_63' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_62' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_60' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_59' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_58' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_57' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_56' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_55' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_54' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_53' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_52' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_51' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_49' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_48' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_47' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_46' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_45' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_44' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_43' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_42' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_41' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_40' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_38' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_37' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_36' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_35' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_34' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_33' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_32' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_31' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_30' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_12' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 36.22 seconds. CPU system time: 3.59 seconds. Elapsed time: 39.87 seconds; current allocated memory: 3.439 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.61 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.65 seconds; current allocated memory: 3.452 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.45 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.5 seconds; current allocated memory: 3.457 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.31 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.34 seconds; current allocated memory: 3.460 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.27 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.3 seconds; current allocated memory: 3.464 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.27 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.3 seconds; current allocated memory: 3.465 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.22 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.25 seconds; current allocated memory: 3.467 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1007_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1039_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1008_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1040_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1019_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1051_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1030_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1062_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1033_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1065_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2keb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1034_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1066_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1035_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2khb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1067_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1036_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1068_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1037_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2klb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1069_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1038_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2knb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1070_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1009_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1041_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1010_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2krb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1042_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2ksb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1011_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2ktb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1043_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1012_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1044_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1013_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1045_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1014_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1046_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1015_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1047_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1016_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1048_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1017_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1049_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1018_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1050_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1020_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1052_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1021_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1053_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1022_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1054_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1023_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1055_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1024_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1056_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1025_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1057_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1026_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1058_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1027_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1059_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1028_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1060_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1029_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1061_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1031_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1063_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1032_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1064_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k6b' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.01 seconds. CPU system time: 0.39 seconds. Elapsed time: 4.4 seconds; current allocated memory: 3.473 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s_w25_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s_w25_Rk7b' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s' is 9216 from HDL expression: (do_init_reg_1231 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 31 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 32 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_289_8_16_1_1': 2 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s_w25_Rk7b' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.98 seconds. CPU system time: 0.1 seconds. Elapsed time: 1.08 seconds; current allocated memory: 3.496 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5327' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_79' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5328' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_78' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5329' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_77' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5330' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_76' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5332' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_75' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5333' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_74' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5334' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_73' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5335' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_72' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5336' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_71' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5337' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_70' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5338' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5096' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5339' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5108' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5340' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5120' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5341' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5132' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5343' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5344' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5345' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5346' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5181' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5347' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5348' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5349' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5350' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5351' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5352' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5354' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5355' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5356' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5290' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5357' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5302' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5358' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5314' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5359' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5324' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5360' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5325' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5361' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5326' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5130' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5398' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5131' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5399' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5134' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5400' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5135' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5401' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5136' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5097' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5137' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5098' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5099' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5101' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5102' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5103' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5104' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5105' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5106' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5107' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5109' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5110' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5112' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5113' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5114' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5115' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5116' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5117' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5118' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5119' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5121' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5123' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5124' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5125' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5126' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5127' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5128' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5129' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5362' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5363' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5365' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5366' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5367' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5368' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5369' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5370' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5371' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5372' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5373' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5374' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5376' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5377' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5378' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5379' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5380' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5381' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5382' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5383' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5384' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5385' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5387' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5388' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5389' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5390' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5391' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5392' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5393' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5394' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5395' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5396' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5178' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5179' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5180' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5182' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5183' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5184' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5185' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5186' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5187' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5189' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5190' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5191' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5192' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5288' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5289' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5291' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5292' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5293' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5294' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5295' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5296' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5297' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5299' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5300' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5301' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5303' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5304' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5305' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5306' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5307' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5308' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5310' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5311' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5312' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5313' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5315' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5316' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5317' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5318' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5319' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5321' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5322' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5323' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_4' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 13.15 seconds. CPU system time: 1.24 seconds. Elapsed time: 14.39 seconds; current allocated memory: 3.534 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.36 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.39 seconds; current allocated memory: 3.540 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.37 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.38 seconds; current allocated memory: 3.544 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.29 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.33 seconds; current allocated memory: 3.547 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' pipeline 'ConcatLoopHeight_ConcatLoopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.3 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.33 seconds; current allocated memory: 3.552 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.24 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.26 seconds; current allocated memory: 3.554 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.28 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.3 seconds; current allocated memory: 3.555 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.3 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.32 seconds; current allocated memory: 3.556 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.29 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.33 seconds; current allocated memory: 3.558 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.24 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.26 seconds; current allocated memory: 3.559 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1135_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2k8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1183_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2k9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1136_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1184_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1147_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1195_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2ldb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1158_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2leb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1206_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1169_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1217_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1178_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1226_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2ljb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1179_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1227_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2llb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1180_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1228_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1181_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1229_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1182_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1230_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1137_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1185_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2ltb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1138_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1186_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1139_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1187_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1140_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1188_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1141_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1189_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1142_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1190_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1143_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1191_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1144_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1192_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1145_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1193_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1146_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1194_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1148_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1196_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1149_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1197_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1150_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1198_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1151_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1199_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1152_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1200_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1153_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1201_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1154_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1202_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1155_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1203_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1156_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1204_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1157_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1205_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1159_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1207_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1160_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1208_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1161_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1209_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1162_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1210_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1163_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2meb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1211_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1164_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1212_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1165_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1213_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1166_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1214_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mlb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1167_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1215_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1168_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1216_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1170_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1218_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1171_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2msb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1219_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mtb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1172_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1220_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1173_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1221_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1174_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2myb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1222_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mzc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1175_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mAc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1223_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mBc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1176_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mCc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1224_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mDc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1177_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mEc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1225_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mFc' due to the length limit 80 +INFO: [RTGEN 206-104] Estimated max fanout for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s' is 6912 from HDL expression: (1'b1 == ap_CS_fsm_state1) +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 5.69 seconds. CPU system time: 0.51 seconds. Elapsed time: 6.2 seconds; current allocated memory: 3.567 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_w29_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_w29_RmGc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' is 13824 from HDL expression: (do_init_reg_1427 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 16 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_33s_33_1_1': 15 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 16 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_289_8_16_1_1': 3 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_w29_RmGc' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.22 seconds. CPU system time: 0.12 seconds. Elapsed time: 1.35 seconds; current allocated memory: 3.598 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6115' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_59' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6116' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_58' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6117' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_57' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6118' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_56' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6119' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_55' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6120' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_54' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6121' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_53' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6122' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_52' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6124' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_51' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6125' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_50' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6126' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6127' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6128' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6129' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6130' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6131' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6132' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6133' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6135' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6136' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6137' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5841' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5853' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5865' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5877' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5889' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5901' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5913' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5926' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5938' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5950' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5962' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5974' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5986' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5998' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6010' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6022' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6034' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6047' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6059' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6071' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6083' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6095' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6107' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6110' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6111' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6113' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6114' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5839' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5840' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5842' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5843' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5844' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5845' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5846' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5847' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5849' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5850' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5851' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5852' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5854' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5855' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5856' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5857' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5858' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5860' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5861' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5862' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5863' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5864' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5866' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5867' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5868' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5869' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5871' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5872' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5873' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5874' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5875' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5876' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5994' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5935' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5995' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5937' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5996' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5939' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5997' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5940' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5941' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6000' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5942' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6001' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5943' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6003' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5944' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6004' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5945' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6005' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5946' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6006' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5948' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6007' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5949' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6008' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5951' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6009' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5952' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6011' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5953' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6012' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5954' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6014' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5955' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6015' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5956' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6016' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5957' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6017' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5959' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6018' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5960' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6019' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5961' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6020' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5963' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6021' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5964' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6023' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5965' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6025' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5966' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6026' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5967' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6027' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5968' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6028' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5970' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6029' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5971' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6030' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5972' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6031' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5973' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6032' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5975' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6033' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5976' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6036' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5977' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6037' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5978' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6038' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5979' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6039' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5981' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6040' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5982' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6041' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5983' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6042' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5984' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6043' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5985' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6044' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5987' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6045' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5988' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6048' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5989' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6049' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5990' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6050' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5992' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6051' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5993' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5878' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5879' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5880' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5882' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5883' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5884' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5885' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5886' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5887' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5888' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5890' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5891' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5893' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5894' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5895' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5896' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5897' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5898' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5899' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5900' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5902' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5904' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5905' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5906' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5907' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5908' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5909' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5910' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5911' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5912' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5915' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5916' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5917' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5918' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5919' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5920' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5921' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5922' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5923' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5924' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5927' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5928' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5929' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5930' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5931' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5932' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5933' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5934' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6052' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6053' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6054' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6055' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6056' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6058' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6060' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6061' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6062' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6063' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6064' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6065' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6066' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6067' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6069' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6070' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6072' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6073' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6074' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6075' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6076' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6077' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6078' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6080' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6081' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6082' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6084' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6085' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6086' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6087' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6088' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6089' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6091' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6092' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6093' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6094' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6096' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6097' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6098' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6099' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6100' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6102' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6103' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6104' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6105' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6106' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6108' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6109' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_1' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 20.64 seconds. CPU system time: 2.1 seconds. Elapsed time: 22.76 seconds; current allocated memory: 3.643 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.43 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.46 seconds; current allocated memory: 3.654 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.33 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.36 seconds; current allocated memory: 3.659 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.35 seconds; current allocated memory: 3.662 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.33 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.35 seconds; current allocated memory: 3.664 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.3 seconds. CPU system time: 0.06 seconds. Elapsed time: 0.36 seconds; current allocated memory: 3.666 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.27 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.28 seconds; current allocated memory: 3.668 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_831_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mHc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_847_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mIc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_832_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mJc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_848_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mKc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_839_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mLc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_855_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mMc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_840_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mNc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_856_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mOc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_841_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mPc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_857_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mQc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_842_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mRc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_858_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mSc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_843_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mTc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_859_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mUc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_844_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mVc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_860_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mWc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_845_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mXc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_861_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mYc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_846_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mZc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_862_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m0c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_833_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m1c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_849_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m2c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_834_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m3c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_850_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m4c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_835_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m5c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_851_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m6c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_836_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m7c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_852_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m8c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_837_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m9c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_853_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2nac' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_838_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2nbc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_854_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2ncc' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.81 seconds. CPU system time: 0.13 seconds. Elapsed time: 1.95 seconds; current allocated memory: 3.673 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s_w31_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s_w31_Rndc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_39s_39_1_1': 15 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_289_8_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s_w31_Rndc' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.72 seconds. CPU system time: 0.07 seconds. Elapsed time: 0.8 seconds; current allocated memory: 3.679 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4324' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4325' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4326' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4327' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4328' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4329' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4331' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4332' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4333' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4334' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4335' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4336' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4337' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4293' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4338' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4305' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4339' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4317' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4340' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4323' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4377' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4359' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4378' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4360' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4379' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4361' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4380' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4362' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4381' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4364' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4382' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4365' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4383' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4366' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4384' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4367' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4386' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4368' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4387' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4369' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4388' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4370' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4389' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4371' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4390' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4372' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4391' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4373' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4392' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4375' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4393' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4376' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4412' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4413' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4287' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4414' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4288' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4415' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4289' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4290' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4291' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4292' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4294' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4295' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4296' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4298' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4299' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4300' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4301' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4302' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4342' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4343' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4344' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4345' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4346' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4347' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4348' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4349' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4350' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4351' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4353' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4354' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4355' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4356' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4357' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4358' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4394' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4395' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4397' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4398' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4399' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4400' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4401' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4402' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4403' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4404' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4405' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4406' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4408' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4409' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4410' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4411' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4303' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4304' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4306' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4307' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4309' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4310' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4311' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4312' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4313' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4314' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4315' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4316' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4318' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4320' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4321' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4322' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_2' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 7.62 seconds. CPU system time: 0.72 seconds. Elapsed time: 8.33 seconds; current allocated memory: 3.697 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.33 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.36 seconds; current allocated memory: 3.702 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.28 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.32 seconds; current allocated memory: 3.705 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.33 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.36 seconds; current allocated memory: 3.707 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' pipeline 'ConcatLoopHeight_ConcatLoopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.34 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.39 seconds; current allocated memory: 3.712 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.27 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.29 seconds; current allocated memory: 3.716 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.33 seconds; current allocated memory: 3.716 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.35 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.39 seconds; current allocated memory: 3.717 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.36 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.39 seconds; current allocated memory: 3.721 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.27 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.29 seconds; current allocated memory: 3.723 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_895_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nec' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_919_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nfc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_896_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2ngc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_920_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nhc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_907_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nic' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_931_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2njc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_912_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nkc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_936_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nlc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_913_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nmc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_937_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nnc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_914_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2noc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_938_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2npc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_915_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nqc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_939_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nrc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_916_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nsc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_940_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2ntc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_917_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nuc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_941_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nvc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_918_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nwc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_942_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nxc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_897_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nyc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_921_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nzc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_898_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nAc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_922_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nBc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_899_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nCc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_923_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nDc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_900_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nEc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nEc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nEc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_924_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nFc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nFc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nFc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_901_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nGc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nGc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nGc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_925_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nHc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nHc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nHc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_902_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nIc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nIc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nIc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_926_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nJc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nJc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nJc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_903_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nKc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nKc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nKc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_927_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nLc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nLc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nLc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_904_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nMc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nMc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nMc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_928_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nNc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nNc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nNc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_905_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nOc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nOc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nOc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_929_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nPc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nPc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nPc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_906_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nQc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nQc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nQc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_930_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nRc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nRc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nRc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_908_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nSc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nSc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nSc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_932_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nTc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nTc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nTc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_909_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nUc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nUc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nUc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_933_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nVc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nVc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nVc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_910_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nWc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nWc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nWc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_934_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nXc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nXc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nXc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_911_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nYc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nYc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nYc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_935_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nZc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nZc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nZc_x' due to conflict. +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 3.69 seconds. CPU system time: 0.36 seconds. Elapsed time: 4.05 seconds; current allocated memory: 3.728 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_w35_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_w35_Rn0c' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' is 6912 from HDL expression: (do_init_reg_779 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 7 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 8 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_217_7_16_1_1': 2 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_w35_Rn0c' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.92 seconds. CPU system time: 0.1 seconds. Elapsed time: 1.02 seconds; current allocated memory: 3.740 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_99' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_98' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_97' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_96' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_95' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_94' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_93' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_92' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_91' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_90' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_6' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 11.43 seconds. CPU system time: 1.1 seconds. Elapsed time: 12.54 seconds; current allocated memory: 3.764 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.36 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.4 seconds; current allocated memory: 3.770 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.36 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.4 seconds; current allocated memory: 3.774 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.33 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.36 seconds; current allocated memory: 3.776 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.36 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.4 seconds; current allocated memory: 3.778 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.36 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.39 seconds; current allocated memory: 3.782 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.28 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.3 seconds; current allocated memory: 3.784 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1391_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn1c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1399_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn2c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1392_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn3c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1400_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn4c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1393_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn5c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1401_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn6c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1394_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn7c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1402_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn8c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1395_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn9c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1403_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2doac' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1396_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dobc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1404_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2docc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1397_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dodc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1405_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2doec' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1398_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dofc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1406_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dogc' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.05 seconds. CPU system time: 0.12 seconds. Elapsed time: 1.17 seconds; current allocated memory: 3.785 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s_outidx_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s_outidx_ROM_AUohc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s_w37_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s_w37_ROM_NP_BRoic' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_11s_40s_41_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_40s_41_1_1': 3 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s_w37_ROM_NP_BRoic' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.69 seconds. CPU system time: 0.07 seconds. Elapsed time: 0.76 seconds; current allocated memory: 3.791 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_14' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.13 seconds. CPU system time: 0.48 seconds. Elapsed time: 4.62 seconds; current allocated memory: 3.798 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.31 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.34 seconds; current allocated memory: 3.803 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.34 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.37 seconds; current allocated memory: 3.806 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_12s_30s_30_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_17_3_12_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_17_3_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.49 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.54 seconds; current allocated memory: 3.807 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.29 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.31 seconds; current allocated memory: 3.809 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s_sigmoid_table_ROM_AUTO_1R' to 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s_sigmoid_table_Rojc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s' pipeline 'SigmoidActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s_sigmoid_table_Rojc' using auto ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.43 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.48 seconds; current allocated memory: 3.811 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'myproject' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low. +INFO: [RTGEN 206-500] Setting interface mode on port 'myproject/x' to 'axis' (register, both mode). +INFO: [RTGEN 206-500] Setting interface mode on port 'myproject/layer40_out' to 'axis' (register, both mode). +INFO: [RTGEN 206-500] Setting interface mode on function 'myproject' to 'ap_ctrl_hs'. +INFO: [SYN 201-210] Renamed object name 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_U0' to 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4okc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_U0' to 'start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6olc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_U0' to 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4omc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_U0' to 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7onc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_U0' to 'start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configooc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_U0' to 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10opc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_U0' to 'start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384oqc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13orc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15osc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_U0' to 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18otc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_U0' to 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20ouc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24ovc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26owc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_U0' to 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30oxc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_U0' to 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32oyc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_U0' to 'start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3ozc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_U0' to 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config5oAc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_U0' to 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37oBc' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'myproject'. +INFO: [RTMG 210-285] Implementing FIFO 'layer44_out_U(myproject_fifo_w16_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer2_out_U(myproject_fifo_w296_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer3_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer45_out_U(myproject_fifo_w128_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer4_out_U(myproject_fifo_w320_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer5_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer41_cpy1_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer41_cpy2_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer6_out_U(myproject_fifo_w128_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer46_out_U(myproject_fifo_w128_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer7_out_U(myproject_fifo_w640_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer8_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer47_out_U(myproject_fifo_w256_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer9_out_U(myproject_fifo_w656_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer10_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer42_cpy1_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer42_cpy2_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer11_out_U(myproject_fifo_w256_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer48_out_U(myproject_fifo_w256_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer12_out_U(myproject_fifo_w1312_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer13_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer49_out_U(myproject_fifo_w512_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer14_out_U(myproject_fifo_w1344_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer15_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer43_cpy1_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer43_cpy2_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer16_out_U(myproject_fifo_w512_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer50_out_U(myproject_fifo_w512_d100_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer17_out_U(myproject_fifo_w2688_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer18_out_U(myproject_fifo_w1024_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer51_out_U(myproject_fifo_w1024_d100_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer19_out_U(myproject_fifo_w2752_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer20_out_U(myproject_fifo_w1024_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer21_out_U(myproject_fifo_w1024_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer22_out_U(myproject_fifo_w1536_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer52_out_U(myproject_fifo_w1536_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer23_out_U(myproject_fifo_w1376_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer24_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer53_out_U(myproject_fifo_w512_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer25_out_U(myproject_fifo_w1344_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer26_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer27_out_U(myproject_fifo_w512_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer28_out_U(myproject_fifo_w768_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer54_out_U(myproject_fifo_w768_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer29_out_U(myproject_fifo_w672_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer30_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer55_out_U(myproject_fifo_w256_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer31_out_U(myproject_fifo_w656_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer32_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer33_out_U(myproject_fifo_w256_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer34_out_U(myproject_fifo_w384_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer56_out_U(myproject_fifo_w384_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer35_out_U(myproject_fifo_w328_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer36_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer57_out_U(myproject_fifo_w128_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer37_out_U(myproject_fifo_w320_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer38_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer39_out_U(myproject_fifo_w36_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_U0_U(myproject_start_for_conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4okc_U(myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4okc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_U0_U(myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0_U(myproject_start_for_clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6olc_U(myproject_start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6olc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0_U(myproject_start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4omc_U(myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4omc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7onc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7onc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_U0_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configooc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configooc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10opc_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10opc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384oqc_U(myproject_start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384oqc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0_U(myproject_start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0_U(myproject_start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13orc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13orc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15osc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15osc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0_U(myproject_start_for_clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_U0_U(myproject_start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0_U(myproject_start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18otc_U(myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18otc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20ouc_U(myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20ouc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_U0_U(myproject_start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24ovc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24ovc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26owc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26owc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_U0_U(myproject_start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30oxc_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30oxc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32oyc_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32oyc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_U0_U(myproject_start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3ozc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3ozc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config5oAc_U(myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config5oAc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37oBc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37oBc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_U0_U(myproject_start_for_pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_U0_U(myproject_start_for_sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_U0)' using Shift Registers. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 7.16 seconds. CPU system time: 0.68 seconds. Elapsed time: 7.83 seconds; current allocated memory: 3.815 GB. +INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 2.03 seconds. CPU system time: 0.27 seconds. Elapsed time: 2.32 seconds; current allocated memory: 3.823 GB. +INFO: [HLS 200-111] Finished Updating report files: CPU user time: 14.62 seconds. CPU system time: 0.19 seconds. Elapsed time: 14.81 seconds; current allocated memory: 3.927 GB. +INFO: [VHDL 208-304] Generating VHDL RTL for myproject. +INFO: [VLOG 209-307] Generating Verilog RTL for myproject. +INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were NOT satisfied. +INFO: [HLS 200-789] **** Estimated Fmax: 226.71 MHz +INFO: [HLS 200-2161] Finished Command csynth_design Elapsed time: 00:17:32; Allocated memory: 3.679 GB. +***** C/RTL SYNTHESIS COMPLETED IN 0h17m32s ***** +INFO: [HLS 200-112] Total CPU user time: 1031.37 seconds. Total CPU system time: 37.38 seconds. Total elapsed time: 1055.74 seconds; peak allocated memory: 3.950 GB. +INFO: [vitis-run 60-791] Total elapsed time: 0h 17m 37s +INFO: [vitis-run 60-1662] Stopping dispatch session having empty uuid. diff --git a/logs/hls_run_tcl_17873.backup.log b/logs/hls_run_tcl_17873.backup.log new file mode 100644 index 0000000000000000000000000000000000000000..20182e7467a3b7294aa87236b39b998888479d90 --- /dev/null +++ b/logs/hls_run_tcl_17873.backup.log @@ -0,0 +1,1826 @@ +INFO: [vitis-run 82-31] Launching vitis_hls: vitis_hls -nolog -run tcl -f /home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl -work_dir /home/ubuntu/lithobench/hls4ml_mini_unet + +****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2024.1 (64-bit) + **** SW Build 5069499 on May 21 2024 + **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 + **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 + **** Start of session at: Sun Mar 29 15:55:02 2026 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. + +source /opt/Xilinx/Vitis_HLS/2024.1/scripts/vitis_hls/hls.tcl -notrace +INFO: [HLS 200-10] For user 'ubuntu' on host 'ip-172-31-42-252.ec2.internal' (Linux_x86_64 version 5.15.0-1084-aws) on Sun Mar 29 15:55:04 UTC 2026 +INFO: [HLS 200-10] On os Ubuntu 20.04.6 LTS +INFO: [HLS 200-10] In directory '/home/ubuntu/lithobench/hls4ml_mini_unet' +Sourcing Tcl script '/home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl' +INFO: [HLS 200-1510] Running: open_project myproject_prj +INFO: [HLS 200-10] Opening project '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj'. +INFO: [HLS 200-1510] Running: set_top myproject +INFO: [HLS 200-1510] Running: add_files firmware/myproject.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding design file 'firmware/myproject.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb myproject_test.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding test bench file 'myproject_test.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb firmware/weights +INFO: [HLS 200-10] Adding test bench file 'firmware/weights' to the project +INFO: [HLS 200-1510] Running: add_files -tb tb_data +INFO: [HLS 200-10] Adding test bench file 'tb_data' to the project +INFO: [HLS 200-1510] Running: open_solution solution1 +INFO: [HLS 200-10] Opening solution '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1'. +INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. +INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 1.35ns. +INFO: [HLS 200-1611] Setting target device to 'xcvu47p-fsvh2892-2L-e' +INFO: [HLS 200-1505] Using flow_target 'vivado' +Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1505.html +INFO: [HLS 200-1464] Running solution command: config_compile -name_max_length=80 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_compile -complex-mul-dsp=0 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_schedule -enable_dsp_full_reg=0 +INFO: [HLS 200-1510] Running: config_array_partition -maximum_size 4096 +ERROR: [HLS 200-101] config_array_partition: Unknown option '-maximum_size'. +ERROR: [HLS 200-101] config_array_partition: Unknown option '4096'. +SYNTAX + config_array_partition [OPTIONS] + -auto_partition_threshold *** DEPRECATED*** + -auto_promotion_threshold *** DEPRECATED*** + -complete_threshold + -throughput_driven + +SEE ALSO + INI: syn.array_partition.complete_threshold syn.array_partition.throughput_driven + docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1399-vitis-hls&resourceid=vyw1583260160301.html + +INFO: [HLS 200-1510] Running: config_compile -name_max_length 80 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: set_part xcvu47p-fsvh2892-2L-e +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: config_schedule -enable_dsp_full_reg=false +INFO: [HLS 200-1510] Running: create_clock -period 5 -name default +INFO: [HLS 200-1510] Running: set_clock_uncertainty 27% default +***** C/RTL SYNTHESIS ***** +INFO: [HLS 200-1510] Running: csynth_design +INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 264.766 MB. +INFO: [HLS 200-10] Analyzing design file 'firmware/myproject.cpp' ... +WARNING: [HLS 207-5570] unexpected pragma argument 'softmax', expects function/operation (firmware/nnet_utils/nnet_activation.h:402:36) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:33:9) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:107:9) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:189:9) +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:242:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:242:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:248:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:248:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:258:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:258:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:264:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:264:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:274:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:274:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:280:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:280:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:290:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:290:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:296:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:296:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:306:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:306:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:312:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:312:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:322:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:322:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:328:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:328:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:338:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:338:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:344:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:344:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:348:100) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:348:105) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 200-471] Dataflow form checks found 30 issue(s) in file firmware/myproject.cpp +Resolution: For help on HLS 200-471 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-471.html +WARNING: [HLS 207-5292] unused parameter 'keep' (firmware/nnet_utils/nnet_helpers.h:285:99) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:14:36) +WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:15:36) +WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:16:44) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:24:24) +WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:25:24) +WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:26:32) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:33:30) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:33:58) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:34:51) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:35:49) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:42:30) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:42:58) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:43:51) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:44:49) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:51:29) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:51:80) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:52:50) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:53:48) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_code_gen.h:16:39) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_code_gen.h:17:38) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_code_gen.h:18:60) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_code_gen.h:19:58) +WARNING: [HLS 207-5584] there are more than one pragma inline in the function scope, ignore the pragma (/opt/Xilinx/Vitis_HLS/2024.1/common/technology/autopilot/ap_shift_reg.h:47:9) +INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 36.44 seconds. CPU system time: 2.27 seconds. Elapsed time: 38.77 seconds; current allocated memory: 275.809 MB. +INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target. +INFO: [HLS 200-1995] There were 28,528 instructions in the design after the 'Compile/Link' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 188,474 instructions in the design after the 'Unroll/Inline (step 1)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 96,416 instructions in the design after the 'Unroll/Inline (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 82,279 instructions in the design after the 'Unroll/Inline (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 37,407 instructions in the design after the 'Unroll/Inline (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 65,234 instructions in the design after the 'Array/Struct' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 44,307 instructions in the design after the 'Array/Struct (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 45,206 instructions in the design after the 'Array/Struct (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 93,112 instructions in the design after the 'Array/Struct (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 93,567 instructions in the design after the 'Array/Struct (step 5)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 95,263 instructions in the design after the 'Performance' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 202,374 instructions in the design after the 'Performance (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 199,687 instructions in the design after the 'Performance (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 199,687 instructions in the design after the 'Performance (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 160,662 instructions in the design after the 'HW Transforms' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 152,727 instructions in the design after the 'HW Transforms (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config60>' (firmware/nnet_utils/nnet_sepconv_stream.h:103:9) +WARNING: [HLS 214-273] In function 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config60_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config60_mult::weight_t*, config60_mult::bias_t*)', Pragma conflict happens on 'INLINE' and 'FUNCTION_INSTANTIATE' pragmas: same function (firmware/nnet_utils/nnet_dense_resource.h:89:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config46>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config46>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config46>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config46>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 1u>, config2>(nnet::array, 1u>::value_type (*) [config2::n_chan], nnet::array, 1u>::value_type*)' into 'void nnet::shift_line_buffer, 1u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], nnet::array, 1u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, config2_mult::weight_t*, config2_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*) (.55)' into 'void nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config47>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config47>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config47>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config47>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config4>(nnet::array, 8u>::value_type (*) [config4::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config4_mult::weight_t*, config4_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 8u>, config4>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*) (.54)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config6>(nnet::array, 8u>::value_type (*) [config6::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::Op_max >::operator()(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>) (.36)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' (firmware/nnet_utils/nnet_common.h:44:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:15) +INFO: [HLS 214-131] Inlining function 'nnet::Op_max >::operator()(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>) (.36)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:12) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:44) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config6>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.52)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config6>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.52)' into 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 8u>::operator[](unsigned long) (.51)' into 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' into 'void nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config48>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config48>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config48>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config48>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config7>(nnet::array, 8u>::value_type (*) [config7::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config7_mult::weight_t*, config7_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 16u>, config7>(hls::stream, 8u>, 0>&, hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*) (.48)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>(hls::stream, 8u>, 0>&, hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config49>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config49>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config49>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config49>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config9>(nnet::array, 16u>::value_type (*) [config9::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config9_mult::weight_t*, config9_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 16u>, config9>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*) (.47)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config11>(nnet::array, 16u>::value_type (*) [config11::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config11>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.45)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config11>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.45)' into 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 16u>::operator[](unsigned long) (.44)' into 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' into 'void nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config50>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config50>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config50>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config50>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config12>(nnet::array, 16u>::value_type (*) [config12::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config12_mult::weight_t*, config12_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 32u>, config12>(hls::stream, 16u>, 0>&, hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*) (.41)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>(hls::stream, 16u>, 0>&, hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config51>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config51>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config51>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config51>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config14>(nnet::array, 32u>::value_type (*) [config14::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config14_mult::weight_t*, config14_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 32u>, config14>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*) (.40)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config16>(nnet::array, 32u>::value_type (*) [config16::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config16>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.34)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config16>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.34)' into 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 32u>::operator[](unsigned long) (.33)' into 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' into 'void nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config52>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config52>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config52>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config52>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config17>(nnet::array, 32u>::value_type (*) [config17::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config17_mult::weight_t*, config17_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 64u>, config17>(hls::stream, 32u>, 0>&, hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*) (.30)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>(hls::stream, 32u>, 0>&, hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config53>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config53>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config53>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config53>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 64u>, config19>(nnet::array, 64u>::value_type (*) [config19::n_chan], nnet::array, 64u>::value_type*)' into 'void nnet::shift_line_buffer, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], nnet::array, 64u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config19_mult::weight_t*, config19_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 64u>, nnet::array, 64u>, config19>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*) (.26)' into 'void nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config54>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config54>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config54>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config54>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 96u>, config23>(nnet::array, 96u>::value_type (*) [config23::n_chan], nnet::array, 96u>::value_type*)' into 'void nnet::shift_line_buffer, 96u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], nnet::array, 96u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config23_mult::weight_t*, config23_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 96u>, nnet::array, 32u>, config23>(hls::stream, 96u>, 0>&, hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*) (.23)' into 'void nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>(hls::stream, 96u>, 0>&, hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config55>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config55>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config55>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config55>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config25>(nnet::array, 32u>::value_type (*) [config25::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config25_mult::weight_t*, config25_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 32u>, config25>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*) (.19)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config56>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config56>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config56>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config56>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 48u>, config29>(nnet::array, 48u>::value_type (*) [config29::n_chan], nnet::array, 48u>::value_type*)' into 'void nnet::shift_line_buffer, 48u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], nnet::array, 48u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config29_mult::weight_t*, config29_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 48u>, nnet::array, 16u>, config29>(hls::stream, 48u>, 0>&, hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*) (.16)' into 'void nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>(hls::stream, 48u>, 0>&, hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config57>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config57>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config57>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config57>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config31>(nnet::array, 16u>::value_type (*) [config31::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config31_mult::weight_t*, config31_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 16u>, config31>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*) (.12)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config58>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config58>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config58>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config58>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 24u>, config35>(nnet::array, 24u>::value_type (*) [config35::n_chan], nnet::array, 24u>::value_type*)' into 'void nnet::shift_line_buffer, 24u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], nnet::array, 24u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config35_mult::weight_t*, config35_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 24u>, nnet::array, 8u>, config35>(hls::stream, 24u>, 0>&, hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*) (.9)' into 'void nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>(hls::stream, 24u>, 0>&, hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config59>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config59>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config59>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config59>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config37>(nnet::array, 8u>::value_type (*) [config37::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config37_mult::weight_t*, config37_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 8u>, config37>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*) (.5)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config60_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config60_mult::weight_t*, config60_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const (.4)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config60>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config60::weight_t*, config60::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:100:13) +INFO: [HLS 214-131] Inlining function 'nnet::array, 1u>::operator[](unsigned long) (.2)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config60>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config60::weight_t*, config60::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:110:2) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config60_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.3)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config60>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config60::weight_t*, config60::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:104:2) +INFO: [HLS 214-131] Inlining function 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config60>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config60::weight_t*, config60::bias_t*)' into 'void nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config60>(hls::stream, 8u>, 0>&, hls::stream, 1u>, 0>&, config60::weight_t*, config60::bias_t*)' (firmware/nnet_utils/nnet_sepconv2d_stream.h:86:21) +INFO: [HLS 214-291] Loop 'VITIS_LOOP_58_4' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_transpose_stream.h:58:26) +INFO: [HLS 214-291] Loop 'VITIS_LOOP_48_2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_transpose_stream.h:48:26) +INFO: [HLS 214-291] Loop 'VITIS_LOOP_21_1' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_transpose.h:21:22) +INFO: [HLS 214-291] Loop 'SigmoidPackLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_activation_stream.h:88:9) +INFO: [HLS 214-291] Loop 'ReLUPackLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_activation_stream.h:49:9) +INFO: [HLS 214-291] Loop 'MultLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_dense_resource.h:142:9) +INFO: [HLS 214-291] Loop 'KernelPushHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:205:5) +INFO: [HLS 214-291] Loop 'KernelPushChannel' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:208:9) +INFO: [HLS 214-291] Loop 'KernelShiftWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:189:5) +INFO: [HLS 214-291] Loop 'KernelShiftHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:192:9) +INFO: [HLS 214-291] Loop 'KernelShiftChannel' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:194:13) +INFO: [HLS 214-291] Loop 'LineBufferDataIn' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:236:5) +INFO: [HLS 214-291] Loop 'LineBufferShift' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:239:9) +INFO: [HLS 214-291] Loop 'UpdateBuffer' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:228:5) +INFO: [HLS 214-291] Loop 'MultLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_dense_resource.h:55:9) +INFO: [HLS 214-291] Loop 'ConcatPackInput1' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_merge_stream.h:245:13) +INFO: [HLS 214-291] Loop 'ConcatPackInput2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_merge_stream.h:251:13) +INFO: [HLS 214-291] Loop 'ImageWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:22:9) +INFO: [HLS 214-291] Loop 'ImageChan' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:28:13) +INFO: [HLS 214-291] Loop 'ResizeHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:36:9) +INFO: [HLS 214-291] Loop 'ImageWidth2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:40:13) +INFO: [HLS 214-291] Loop 'ResizeWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:44:17) +INFO: [HLS 214-291] Loop 'ResizeChan' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:51:21) +INFO: [HLS 214-291] Loop 'FiltLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_pooling_stream.h:57:9) +INFO: [HLS 214-291] Loop 'PoolLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_pooling_stream.h:62:13) +INFO: [HLS 214-291] Loop 'ClonePack' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_stream.h:32:9) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_58_4' (firmware/nnet_utils/nnet_transpose_stream.h:58:26) in function 'nnet::transpose, 1u>, nnet::array, 1u>, config42>' completely with a factor of 1 (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_48_2' (firmware/nnet_utils/nnet_transpose_stream.h:48:26) in function 'nnet::transpose, 1u>, nnet::array, 1u>, config42>' completely with a factor of 1 (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_21_1' (firmware/nnet_utils/nnet_transpose.h:21:22) in function 'nnet::transfer_idx' completely with a factor of 3 (firmware/nnet_utils/nnet_transpose.h:18:0) +INFO: [HLS 214-186] Unrolling loop 'SigmoidPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:88:9) in function 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>' completely with a factor of 1 (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-186] Unrolling loop 'InitData' (firmware/nnet_utils/nnet_sepconv_stream.h:98:5) in function 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config60>' completely with a factor of 8 (firmware/nnet_utils/nnet_sepconv2d_stream.h:58:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config38>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 2 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config37>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config36>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 24u>, config35>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>' completely with a factor of 24 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' completely with a factor of 16 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' completely with a factor of 8 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config32>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config31>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config30>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 48u>, config29>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>' completely with a factor of 48 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' completely with a factor of 32 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' completely with a factor of 16 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config26>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config25>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config24>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 96 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 96u>, config23>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>' completely with a factor of 96 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' completely with a factor of 64 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' completely with a factor of 32 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 8 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 64 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 8 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 64 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 64u>, nnet::array, 64u>, relu_config20>' completely with a factor of 64 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 128 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 64u>, config19>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 64u>, nnet::array, 64u>, relu_config18>' completely with a factor of 64 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config17>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config16>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>' completely with a factor of 32 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config15>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config14>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config13>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config12>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config11>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>' completely with a factor of 16 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config10>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config9>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config8>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 4 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config7>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config6>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>' completely with a factor of 8 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config5>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 2 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config4>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config3>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 1u>, config2>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>' completely with a factor of 1 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_58_4' (firmware/nnet_utils/nnet_transpose_stream.h:58:26) in function 'nnet::transpose, 64u>, nnet::array, 1u>, config41>' completely with a factor of 1 (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_48_2' (firmware/nnet_utils/nnet_transpose_stream.h:48:26) in function 'nnet::transpose, 64u>, nnet::array, 1u>, config41>' completely with a factor of 64 (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_21_1' (firmware/nnet_utils/nnet_transpose.h:21:22) in function 'nnet::transfer_idx' completely with a factor of 4 (firmware/nnet_utils/nnet_transpose.h:18:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'std::enable_if<(config41::dims) != (2), void>::type nnet::transpose, 64u>, nnet::array, 1u>, config41>(hls::stream, 64u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'std::enable_if<(config41::dims) != (2), void>::type nnet::transpose, 64u>, nnet::array, 1u>, config41>(hls::stream, 64u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-178] Inlining function 'unsigned int nnet::transfer_idx(int)' into 'std::enable_if<(config41::dims) != (2), void>::type nnet::transpose, 64u>, nnet::array, 1u>, config41>(hls::stream, 64u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 1u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], nnet::array, 1u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(config2_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, config2_mult::weight_t*, config2_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config3>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config3>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(config4_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config4_mult::weight_t*, config4_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config5>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config5>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(config7_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config7_mult::weight_t*, config7_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config8>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config8>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(config9_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config9_mult::weight_t*, config9_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config10>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config10>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(config12_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config12_mult::weight_t*, config12_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config13>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config13>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(config14_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config14_mult::weight_t*, config14_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config15>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config15>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config18>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config18>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], nnet::array, 64u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config20>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config20>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 64u>, config21>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 96u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], nnet::array, 96u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(config23_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config23_mult::weight_t*, config23_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config24>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config24>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(config25_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config25_mult::weight_t*, config25_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config26>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config26>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 32u>, config27>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 48u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], nnet::array, 48u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(config29_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config29_mult::weight_t*, config29_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config30>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config30>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(config31_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config31_mult::weight_t*, config31_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config32>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config32>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 16u>, config33>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 24u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], nnet::array, 24u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(config35_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config35_mult::weight_t*, config35_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config36>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config36>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(config37_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config37_mult::weight_t*, config37_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config38>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config38>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'std::enable_if<(config42::dims) != (2), void>::type nnet::transpose, 1u>, nnet::array, 1u>, config42>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-178] Inlining function 'unsigned int nnet::transfer_idx(int)' into 'std::enable_if<(config42::dims) != (2), void>::type nnet::transpose, 1u>, nnet::array, 1u>, config42>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj1EEENS1_IS2_ILi37ELi17ELS3_5ELS4_3ELi0EELj8EEE7config2EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEES6_7config6EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to 'b2': Complete partitioning on dimension 1. (firmware/weights/b2.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b4': Complete partitioning on dimension 1. (firmware/weights/b4.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b7': Complete partitioning on dimension 1. (firmware/weights/b7.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b9': Complete partitioning on dimension 1. (firmware/weights/b9.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b12': Complete partitioning on dimension 1. (firmware/weights/b12.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b14': Complete partitioning on dimension 1. (firmware/weights/b14.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b17': Complete partitioning on dimension 1. (firmware/weights/b17.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b19': Complete partitioning on dimension 1. (firmware/weights/b19.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b23': Complete partitioning on dimension 1. (firmware/weights/b23.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b25': Complete partitioning on dimension 1. (firmware/weights/b25.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b29': Complete partitioning on dimension 1. (firmware/weights/b29.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b31': Complete partitioning on dimension 1. (firmware/weights/b31.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b35': Complete partitioning on dimension 1. (firmware/weights/b35.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b37': Complete partitioning on dimension 1. (firmware/weights/b37.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'w39': Complete partitioning on dimension 1. (firmware/weights/w39.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b39': Complete partitioning on dimension 1. (firmware/weights/b39.h:12:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEES6_7config6EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj1EEENS1_IS2_ILi37ELi17ELS3_5ELS4_3ELi0EELj8EEE7config2EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to 'data_array': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_transpose_stream.h:42:33) +INFO: [HLS 214-248] Applying array_partition to 'acc': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_dense_resource.h:110:32) +INFO: [HLS 214-248] Applying array_partition to 'res_out': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:274:29) +INFO: [HLS 214-248] Applying array_partition to 'shift_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv_stream.h:224:30) +WARNING: [HLS 214-322] Unsuported scalar variable on pragma 'Resource/Bind_Storage', ignore it. (firmware/myproject.cpp:348:5) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer40_out' with compact=bit mode in 16-bits (firmware/myproject.cpp:235:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer46_out' with compact=bit mode in 16-bits (firmware/myproject.cpp:61:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer41_out' with compact=bit mode in 16-bits (firmware/myproject.cpp:58:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer39_out' with compact=bit mode in 36-bits (firmware/myproject.cpp:232:35) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer38_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:229:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer59_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:223:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer36_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:220:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer48_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:88:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer6_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:85:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer43_cpy1' with compact=bit mode in 128-bits (firmware/myproject.cpp:79:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer43_cpy2' with compact=bit mode in 128-bits (firmware/myproject.cpp:82:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer5_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:76:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer47_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:70:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer3_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:67:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer37_out' with compact=bit mode in 320-bits (firmware/myproject.cpp:226:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer4_out' with compact=bit mode in 320-bits (firmware/myproject.cpp:73:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer35_out' with compact=bit mode in 328-bits (firmware/myproject.cpp:217:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer58_out' with compact=bit mode in 384-bits (firmware/myproject.cpp:214:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer34_out' with compact=bit mode in 384-bits (firmware/myproject.cpp:211:30) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer33_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:208:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer32_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:205:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer57_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:199:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer30_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:196:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer50_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:115:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer11_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:112:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer44_cpy1' with compact=bit mode in 256-bits (firmware/myproject.cpp:106:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer44_cpy2' with compact=bit mode in 256-bits (firmware/myproject.cpp:109:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer10_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:103:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer49_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:97:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer8_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:94:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer31_out' with compact=bit mode in 656-bits (firmware/myproject.cpp:202:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer9_out' with compact=bit mode in 656-bits (firmware/myproject.cpp:100:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer29_out' with compact=bit mode in 672-bits (firmware/myproject.cpp:193:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer56_out' with compact=bit mode in 768-bits (firmware/myproject.cpp:190:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer28_out' with compact=bit mode in 768-bits (firmware/myproject.cpp:187:30) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer27_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:184:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer26_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:181:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer55_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:175:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer24_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:172:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer52_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:142:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer16_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:139:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer45_cpy1' with compact=bit mode in 512-bits (firmware/myproject.cpp:133:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer45_cpy2' with compact=bit mode in 512-bits (firmware/myproject.cpp:136:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer15_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:130:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer51_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:124:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer13_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:121:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer25_out' with compact=bit mode in 1344-bits (firmware/myproject.cpp:178:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer14_out' with compact=bit mode in 1344-bits (firmware/myproject.cpp:127:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer23_out' with compact=bit mode in 1376-bits (firmware/myproject.cpp:169:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer54_out' with compact=bit mode in 1536-bits (firmware/myproject.cpp:166:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer22_out' with compact=bit mode in 1536-bits (firmware/myproject.cpp:163:28) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer21_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:160:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer20_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:157:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer53_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:151:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer18_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:148:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer19_out' with compact=bit mode in 2752-bits (firmware/myproject.cpp:154:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer17_out' with compact=bit mode in 2688-bits (firmware/myproject.cpp:145:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer12_out' with compact=bit mode in 1312-bits (firmware/myproject.cpp:118:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer7_out' with compact=bit mode in 640-bits (firmware/myproject.cpp:91:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer2_out' with compact=bit mode in 296-bits (firmware/myproject.cpp:64:32) +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::conv_2d_buffer_resource_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_64' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_65' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_66' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_67' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_68' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_69' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_70' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_71' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_72' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_73' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_74' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_75' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_76' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_77' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_78' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_79' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_80' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_81' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_82' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_83' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_84' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_85' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_86' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_87' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_88' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_89' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_90' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_91' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_92' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_93' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_94' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_95' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_64' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_65' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_66' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_67' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_68' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_69' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_70' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_71' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_72' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_73' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_74' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_75' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_76' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_77' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_78' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_79' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_80' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_81' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_82' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_83' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_84' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_85' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_86' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_87' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_88' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_89' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_90' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_91' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_92' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_93' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_94' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_95' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-248] Applying array_reshape to 'w4': Block reshaping with factor 2 on dimension 1. (firmware/weights/w4.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w7': Block reshaping with factor 4 on dimension 1. (firmware/weights/w7.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w9': Block reshaping with factor 8 on dimension 1. (firmware/weights/w9.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w12': Block reshaping with factor 16 on dimension 1. (firmware/weights/w12.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w14': Block reshaping with factor 32 on dimension 1. (firmware/weights/w14.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w17': Block reshaping with factor 64 on dimension 1. (firmware/weights/w17.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w19': Block reshaping with factor 128 on dimension 1. (firmware/weights/w19.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w23': Block reshaping with factor 96 on dimension 1. (firmware/weights/w23.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w25': Block reshaping with factor 32 on dimension 1. (firmware/weights/w25.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w29': Block reshaping with factor 32 on dimension 1. (firmware/weights/w29.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w31': Block reshaping with factor 8 on dimension 1. (firmware/weights/w31.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w35': Block reshaping with factor 8 on dimension 1. (firmware/weights/w35.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w37': Block reshaping with factor 2 on dimension 1. (firmware/weights/w37.h:12:0) +INFO: [HLS 214-376] automatically set the pipeline for Loop< ReadInputWidthSerial> at firmware/nnet_utils/nnet_sepconv2d_stream.h:83:13 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadTopWidth> at firmware/nnet_utils/nnet_padding_stream.h:53:9 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadMain> at firmware/nnet_utils/nnet_padding_stream.h:59:5 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadBottomWidth> at firmware/nnet_utils/nnet_padding_stream.h:77:9 +INFO: [HLS 214-291] Loop 'CopyMain' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_padding_stream.h:65:9) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-270] Inferring pragma 'array_partition type=complete dim=1' for array 'ref.tmp.i' due to pipeline pragma +INFO: [HLS 214-248] Applying array_partition to 'ref.tmp.i': Complete partitioning on dimension 1. +INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 36798.3 seconds. CPU system time: 7.3 seconds. Elapsed time: 36792.3 seconds; current allocated memory: 334.363 MB. +INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 334.363 MB. +INFO: [HLS 200-10] Starting code transformations ... +INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 168.59 seconds. CPU system time: 0.55 seconds. Elapsed time: 169.25 seconds; current allocated memory: 980.180 MB. +INFO: [HLS 200-10] Checking synthesizability ... +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 145.14 seconds. CPU system time: 0.76 seconds. Elapsed time: 146.09 seconds; current allocated memory: 2.028 GB. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-712] Applying dataflow to function 'myproject' (firmware/myproject.cpp:8), detected/extracted 58 process function(s): + 'nnet::transpose, 64u>, nnet::array, 1u>, config41>' + 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>' + 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config3>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config5>' + 'nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>' + 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config8>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config10>' + 'nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>' + 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config13>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config15>' + 'nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>' + 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>' + 'nnet::relu, 64u>, nnet::array, 64u>, relu_config18>' + 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>' + 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>' + 'nnet::relu, 64u>, nnet::array, 64u>, relu_config20>' + 'nnet::resize_nearest, 64u>, config21>' + 'nnet::concatenate3d, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' + 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>' + 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config24>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config26>' + 'nnet::resize_nearest, 32u>, config27>' + 'nnet::concatenate3d, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' + 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>' + 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config30>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config32>' + 'nnet::resize_nearest, 16u>, config33>' + 'nnet::concatenate3d, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' + 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>' + 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config36>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config38>' + 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config60>' + 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>' + 'nnet::transpose, 1u>, nnet::array, 1u>, config42>'. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_activation_stream.h:81:9) to (firmware/nnet_utils/nnet_activation_stream.h:80:5) in function 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>'... converting 3 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>'... converting 17 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>'... converting 17 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>'... converting 33 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>'... converting 37 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>'... converting 19 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>'... converting 19 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>'... converting 18 basic blocks. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' (firmware/nnet_utils/nnet_dense_resource.h:46:5)...96 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...12 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...6 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...6 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...13 expression(s) balanced. +/opt/Xilinx/Vitis_HLS/2024.1/bin/rdiArgs.sh: line 387: 6719 Segmentation fault (core dumped) "$RDI_PROG" "$@" +segfault in /opt/Xilinx/Vitis_HLS/2024.1/bin/unwrapped/lnx64.o/vitis_hls -exec vitis_hls -nolog -run tcl -f /home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl -work_dir /home/ubuntu/lithobench/hls4ml_mini_unet, exiting... +INFO: [vitis-run 60-1662] Stopping dispatch session having empty uuid. diff --git a/logs/hls_run_tcl_181235.backup.log b/logs/hls_run_tcl_181235.backup.log new file mode 100644 index 0000000000000000000000000000000000000000..69c8fd8a0178c48b38f26cef63e48c9c2da90672 --- /dev/null +++ b/logs/hls_run_tcl_181235.backup.log @@ -0,0 +1,10260 @@ +INFO: [vitis-run 82-31] Launching vitis_hls: vitis_hls -nolog -run tcl -f /home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl -work_dir /home/ubuntu/lithobench/hls4ml_mini_unet + +****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2024.1 (64-bit) + **** SW Build 5069499 on May 21 2024 + **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 + **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 + **** Start of session at: Sat Apr 4 00:36:55 2026 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. + +source /opt/Xilinx/Vitis_HLS/2024.1/scripts/vitis_hls/hls.tcl -notrace +INFO: [HLS 200-10] For user 'ubuntu' on host 'ip-172-31-42-252.ec2.internal' (Linux_x86_64 version 5.15.0-1084-aws) on Sat Apr 04 00:36:57 UTC 2026 +INFO: [HLS 200-10] On os Ubuntu 20.04.6 LTS +INFO: [HLS 200-10] In directory '/home/ubuntu/lithobench/hls4ml_mini_unet' +Sourcing Tcl script '/home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl' +INFO: [HLS 200-1510] Running: open_project myproject_prj +INFO: [HLS 200-10] Opening project '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj'. +INFO: [HLS 200-1510] Running: set_top myproject +INFO: [HLS 200-1510] Running: add_files firmware/myproject.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding design file 'firmware/myproject.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb myproject_test.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding test bench file 'myproject_test.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb firmware/weights +INFO: [HLS 200-10] Adding test bench file 'firmware/weights' to the project +INFO: [HLS 200-1510] Running: add_files -tb tb_data +INFO: [HLS 200-10] Adding test bench file 'tb_data' to the project +INFO: [HLS 200-1510] Running: open_solution solution1 +INFO: [HLS 200-10] Opening solution '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1'. +INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. +INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 1.35ns. +INFO: [HLS 200-1611] Setting target device to 'xcvu47p-fsvh2892-2L-e' +INFO: [HLS 200-1505] Using flow_target 'vivado' +Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1505.html +INFO: [HLS 200-1464] Running solution command: config_compile -name_max_length=80 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_compile -complex-mul-dsp=0 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_compile -unsafe_math_optimizations=0 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_schedule -enable_dsp_full_reg=0 +INFO: [HLS 200-1464] Running solution command: config_array_partition -complete_threshold=4096 +INFO: [XFORM 203-102] Size-based automatic array partition enabled: cut-off elements per dimension is 4096. +INFO: [HLS 200-1510] Running: config_array_partition -maximum_size 4096 +ERROR: [HLS 200-101] config_array_partition: Unknown option '-maximum_size'. +ERROR: [HLS 200-101] config_array_partition: Unknown option '4096'. +SYNTAX + config_array_partition [OPTIONS] + -auto_partition_threshold *** DEPRECATED*** + -auto_promotion_threshold *** DEPRECATED*** + -complete_threshold + -throughput_driven + +SEE ALSO + INI: syn.array_partition.complete_threshold syn.array_partition.throughput_driven + docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1399-vitis-hls&resourceid=vyw1583260160301.html + +INFO: [HLS 200-1510] Running: config_compile -name_max_length 80 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: set_part xcvu47p-fsvh2892-2L-e +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: config_schedule -enable_dsp_full_reg=false +INFO: [HLS 200-1510] Running: create_clock -period 5 -name default +INFO: [HLS 200-1510] Running: set_clock_uncertainty 27% default +***** C/RTL SYNTHESIS ***** +INFO: [HLS 200-1510] Running: csynth_design +INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0.06 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.13 seconds; current allocated memory: 276.859 MB. +INFO: [HLS 200-10] Analyzing design file 'firmware/myproject.cpp' ... +WARNING: [HLS 207-5570] unexpected pragma argument 'softmax', expects function/operation (firmware/nnet_utils/nnet_activation.h:402:36) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:33:9) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:107:9) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:189:9) +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:234:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:234:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:240:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:240:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:250:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:250:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:256:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:256:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:266:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:266:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:272:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:272:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:282:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:282:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:288:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:288:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:298:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:298:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:304:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:304:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:314:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:314:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:320:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:320:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:330:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:330:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:336:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:336:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:340:100) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:340:105) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 200-471] Dataflow form checks found 30 issue(s) in file firmware/myproject.cpp +Resolution: For help on HLS 200-471 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-471.html +WARNING: [HLS 207-5292] unused parameter 'keep' (firmware/nnet_utils/nnet_helpers.h:285:99) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:14:36) +WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:15:36) +WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:16:44) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:24:24) +WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:25:24) +WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:26:32) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:33:30) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:33:58) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:34:51) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:35:49) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:42:30) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:42:58) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:43:51) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:44:49) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:51:29) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:51:80) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:52:50) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:53:48) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_code_gen.h:16:39) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_code_gen.h:17:38) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_code_gen.h:18:60) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_code_gen.h:19:58) +WARNING: [HLS 207-5584] there are more than one pragma inline in the function scope, ignore the pragma (/opt/Xilinx/Vitis_HLS/2024.1/common/technology/autopilot/ap_shift_reg.h:47:9) +INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 35.99 seconds. CPU system time: 2.22 seconds. Elapsed time: 39.11 seconds; current allocated memory: 287.965 MB. +INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target. +INFO: [HLS 200-1995] There were 28,092 instructions in the design after the 'Compile/Link' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 281,564 instructions in the design after the 'Unroll/Inline' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 126,649 instructions in the design after the 'Unroll/Inline (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 101,403 instructions in the design after the 'Unroll/Inline (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 52,850 instructions in the design after the 'Unroll/Inline (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 40,314 instructions in the design after the 'Array/Struct (step 1)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 38,449 instructions in the design after the 'Array/Struct (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 39,344 instructions in the design after the 'Array/Struct (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 94,283 instructions in the design after the 'Array/Struct (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 81,528 instructions in the design after the 'Array/Struct (step 5)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 83,186 instructions in the design after the 'Performance (step 1)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 193,957 instructions in the design after the 'Performance (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 191,271 instructions in the design after the 'Performance (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 191,271 instructions in the design after the 'Performance (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 152,447 instructions in the design after the 'HW Transforms' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 144,708 instructions in the design after the 'HW Transforms (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>' (firmware/nnet_utils/nnet_sepconv_stream.h:103:9) +WARNING: [HLS 214-273] In function 'void nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config58_mult::weight_t*, config58_mult::bias_t*)', Pragma conflict happens on 'INLINE' and 'FUNCTION_INSTANTIATE' pragmas: same function (firmware/nnet_utils/nnet_dense_resource.h:15:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 1u>, config2>(nnet::array, 1u>::value_type (*) [config2::n_chan], nnet::array, 1u>::value_type*)' into 'void nnet::shift_line_buffer, 1u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], nnet::array, 1u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, config2_mult::weight_t*, config2_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*) (.55)' into 'void nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config4>(nnet::array, 8u>::value_type (*) [config4::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config4_mult::weight_t*, config4_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 8u>, config4>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*) (.54)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config6>(nnet::array, 8u>::value_type (*) [config6::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::Op_max >::operator()(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>) (.36)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' (firmware/nnet_utils/nnet_common.h:44:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:15) +INFO: [HLS 214-131] Inlining function 'nnet::Op_max >::operator()(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>) (.36)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:12) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:44) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config6>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.52)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config6>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.52)' into 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 8u>::operator[](unsigned long) (.51)' into 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' into 'void nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config7>(nnet::array, 8u>::value_type (*) [config7::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config7_mult::weight_t*, config7_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 16u>, config7>(hls::stream, 8u>, 0>&, hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*) (.48)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>(hls::stream, 8u>, 0>&, hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config9>(nnet::array, 16u>::value_type (*) [config9::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config9_mult::weight_t*, config9_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 16u>, config9>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*) (.47)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config11>(nnet::array, 16u>::value_type (*) [config11::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config11>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.45)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config11>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.45)' into 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 16u>::operator[](unsigned long) (.44)' into 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' into 'void nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config12>(nnet::array, 16u>::value_type (*) [config12::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config12_mult::weight_t*, config12_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 32u>, config12>(hls::stream, 16u>, 0>&, hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*) (.41)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>(hls::stream, 16u>, 0>&, hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config14>(nnet::array, 32u>::value_type (*) [config14::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config14_mult::weight_t*, config14_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 32u>, config14>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*) (.40)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config16>(nnet::array, 32u>::value_type (*) [config16::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config16>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.34)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config16>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.34)' into 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 32u>::operator[](unsigned long) (.33)' into 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' into 'void nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config17>(nnet::array, 32u>::value_type (*) [config17::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config17_mult::weight_t*, config17_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 64u>, config17>(hls::stream, 32u>, 0>&, hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*) (.30)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>(hls::stream, 32u>, 0>&, hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 64u>, config19>(nnet::array, 64u>::value_type (*) [config19::n_chan], nnet::array, 64u>::value_type*)' into 'void nnet::shift_line_buffer, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], nnet::array, 64u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config19_mult::weight_t*, config19_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 64u>, nnet::array, 64u>, config19>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*) (.26)' into 'void nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 96u>, config23>(nnet::array, 96u>::value_type (*) [config23::n_chan], nnet::array, 96u>::value_type*)' into 'void nnet::shift_line_buffer, 96u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], nnet::array, 96u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config23_mult::weight_t*, config23_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 96u>, nnet::array, 32u>, config23>(hls::stream, 96u>, 0>&, hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*) (.23)' into 'void nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>(hls::stream, 96u>, 0>&, hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config25>(nnet::array, 32u>::value_type (*) [config25::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config25_mult::weight_t*, config25_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 32u>, config25>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*) (.19)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 48u>, config29>(nnet::array, 48u>::value_type (*) [config29::n_chan], nnet::array, 48u>::value_type*)' into 'void nnet::shift_line_buffer, 48u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], nnet::array, 48u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config29_mult::weight_t*, config29_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 48u>, nnet::array, 16u>, config29>(hls::stream, 48u>, 0>&, hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*) (.16)' into 'void nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>(hls::stream, 48u>, 0>&, hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config31>(nnet::array, 16u>::value_type (*) [config31::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config31_mult::weight_t*, config31_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 16u>, config31>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*) (.12)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 24u>, config35>(nnet::array, 24u>::value_type (*) [config35::n_chan], nnet::array, 24u>::value_type*)' into 'void nnet::shift_line_buffer, 24u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], nnet::array, 24u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config35_mult::weight_t*, config35_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 24u>, nnet::array, 8u>, config35>(hls::stream, 24u>, 0>&, hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*) (.9)' into 'void nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>(hls::stream, 24u>, 0>&, hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config37>(nnet::array, 8u>::value_type (*) [config37::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config37_mult::weight_t*, config37_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 8u>, config37>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*) (.5)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config58_mult::weight_t*, config58_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const (.4)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:100:13) +INFO: [HLS 214-131] Inlining function 'nnet::array, 1u>::operator[](unsigned long) (.2)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:110:2) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.3)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:104:2) +INFO: [HLS 214-131] Inlining function 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' into 'void nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>(hls::stream, 8u>, 0>&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv2d_stream.h:86:21) +INFO: [HLS 214-291] Loop 'SigmoidPackLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_activation_stream.h:88:9) +INFO: [HLS 214-291] Loop 'MultLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_dense_resource.h:55:9) +INFO: [HLS 214-291] Loop 'ReLUPackLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_activation_stream.h:49:9) +INFO: [HLS 214-291] Loop 'KernelPushHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:205:5) +INFO: [HLS 214-291] Loop 'KernelPushChannel' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:208:9) +INFO: [HLS 214-291] Loop 'KernelShiftWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:189:5) +INFO: [HLS 214-291] Loop 'KernelShiftHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:192:9) +INFO: [HLS 214-291] Loop 'KernelShiftChannel' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:194:13) +INFO: [HLS 214-291] Loop 'LineBufferDataIn' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:236:5) +INFO: [HLS 214-291] Loop 'LineBufferShift' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:239:9) +INFO: [HLS 214-291] Loop 'UpdateBuffer' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:228:5) +INFO: [HLS 214-291] Loop 'ConcatPackInput1' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_merge_stream.h:245:13) +INFO: [HLS 214-291] Loop 'ConcatPackInput2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_merge_stream.h:251:13) +INFO: [HLS 214-291] Loop 'ImageWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:22:9) +INFO: [HLS 214-291] Loop 'ImageChan' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:28:13) +INFO: [HLS 214-291] Loop 'ResizeHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:36:9) +INFO: [HLS 214-291] Loop 'ImageWidth2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:40:13) +INFO: [HLS 214-291] Loop 'ResizeWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:44:17) +INFO: [HLS 214-291] Loop 'ResizeChan' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:51:21) +INFO: [HLS 214-291] Loop 'FiltLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_pooling_stream.h:57:9) +INFO: [HLS 214-291] Loop 'PoolLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_pooling_stream.h:62:13) +INFO: [HLS 214-291] Loop 'ClonePack' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_stream.h:32:9) +INFO: [HLS 214-291] Loop 'MultLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_dense_resource.h:142:9) +INFO: [HLS 214-186] Unrolling loop 'SigmoidPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:88:9) in function 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>' completely with a factor of 1 (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-186] Unrolling loop 'InitData' (firmware/nnet_utils/nnet_sepconv_stream.h:98:5) in function 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>' completely with a factor of 8 (firmware/nnet_utils/nnet_sepconv2d_stream.h:58:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_sepconv_stream.h:108:5) in function 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>' completely with a factor of 1 (firmware/nnet_utils/nnet_sepconv2d_stream.h:58:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config38>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config37>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config36>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 24 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 24u>, config35>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>' completely with a factor of 24 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' completely with a factor of 16 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' completely with a factor of 8 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config32>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config31>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config30>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 96 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 48u>, config29>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>' completely with a factor of 48 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' completely with a factor of 32 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' completely with a factor of 16 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config26>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 128 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config25>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config24>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 384 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 96u>, config23>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>' completely with a factor of 96 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' completely with a factor of 64 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' completely with a factor of 32 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 8 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 64 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 8 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 64 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 64u>, nnet::array, 64u>, relu_config20>' completely with a factor of 64 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 576 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 64u>, config19>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 64u>, nnet::array, 64u>, relu_config18>' completely with a factor of 64 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 256 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config17>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config16>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>' completely with a factor of 32 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config15>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 128 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config14>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config13>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config12>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config11>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>' completely with a factor of 16 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config10>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config9>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config8>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config7>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config6>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>' completely with a factor of 8 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config5>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config4>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config3>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 1u>, config2>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>' completely with a factor of 1 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 1u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], nnet::array, 1u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(config2_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, config2_mult::weight_t*, config2_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config3>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config3>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(config4_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config4_mult::weight_t*, config4_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config5>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config5>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(config7_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config7_mult::weight_t*, config7_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config8>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config8>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(config9_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config9_mult::weight_t*, config9_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config10>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config10>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(config12_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config12_mult::weight_t*, config12_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config13>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config13>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(config14_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config14_mult::weight_t*, config14_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config15>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config15>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config18>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config18>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], nnet::array, 64u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config20>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config20>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 64u>, config21>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 96u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], nnet::array, 96u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(config23_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config23_mult::weight_t*, config23_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config24>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config24>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(config25_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config25_mult::weight_t*, config25_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config26>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config26>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 32u>, config27>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 48u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], nnet::array, 48u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(config29_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config29_mult::weight_t*, config29_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config30>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config30>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(config31_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config31_mult::weight_t*, config31_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config32>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config32>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 16u>, config33>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 24u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], nnet::array, 24u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(config35_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config35_mult::weight_t*, config35_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config36>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config36>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(config37_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config37_mult::weight_t*, config37_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config38>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config38>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(config58_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config58_mult::weight_t*, config58_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj1EEENS1_IS2_ILi37ELi17ELS3_5ELS4_3ELi0EELj8EEE7config2EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEES6_7config6EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to 'b2': Complete partitioning on dimension 1. (firmware/weights/b2.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b4': Complete partitioning on dimension 1. (firmware/weights/b4.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b7': Complete partitioning on dimension 1. (firmware/weights/b7.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b9': Complete partitioning on dimension 1. (firmware/weights/b9.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b12': Complete partitioning on dimension 1. (firmware/weights/b12.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b14': Complete partitioning on dimension 1. (firmware/weights/b14.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b17': Complete partitioning on dimension 1. (firmware/weights/b17.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b19': Complete partitioning on dimension 1. (firmware/weights/b19.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b23': Complete partitioning on dimension 1. (firmware/weights/b23.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b25': Complete partitioning on dimension 1. (firmware/weights/b25.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b29': Complete partitioning on dimension 1. (firmware/weights/b29.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b31': Complete partitioning on dimension 1. (firmware/weights/b31.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b35': Complete partitioning on dimension 1. (firmware/weights/b35.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b37': Complete partitioning on dimension 1. (firmware/weights/b37.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'w39': Complete partitioning on dimension 1. (firmware/weights/w39.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b39': Complete partitioning on dimension 1. (firmware/weights/b39.h:12:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEES6_7config6EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj1EEENS1_IS2_ILi37ELi17ELS3_5ELS4_3ELi0EELj8EEE7config2EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to 'acc': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_dense_resource.h:110:32) +INFO: [HLS 214-248] Applying array_partition to 'res_out': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:274:29) +INFO: [HLS 214-248] Applying array_partition to 'shift_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv_stream.h:224:30) +INFO: [HLS 214-248] Applying array_partition to 'data.i': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_sepconv_stream.h:88:30) +INFO: [HLS 214-248] Applying array_partition to 'res.i': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_sepconv_stream.h:91:29) +WARNING: [HLS 214-322] Unsuported scalar variable on pragma 'Resource/Bind_Storage', ignore it. (firmware/myproject.cpp:340:5) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer39_out' with compact=bit mode in 36-bits (firmware/myproject.cpp:229:35) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer38_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:226:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer57_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:220:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer36_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:217:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer46_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:85:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer6_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:82:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer41_cpy1' with compact=bit mode in 128-bits (firmware/myproject.cpp:76:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer41_cpy2' with compact=bit mode in 128-bits (firmware/myproject.cpp:79:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer5_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:73:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer45_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:67:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer3_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:64:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer37_out' with compact=bit mode in 320-bits (firmware/myproject.cpp:223:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer4_out' with compact=bit mode in 320-bits (firmware/myproject.cpp:70:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer35_out' with compact=bit mode in 328-bits (firmware/myproject.cpp:214:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer56_out' with compact=bit mode in 384-bits (firmware/myproject.cpp:211:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer34_out' with compact=bit mode in 384-bits (firmware/myproject.cpp:208:30) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer33_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:205:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer32_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:202:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer55_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:196:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer30_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:193:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer48_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:112:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer11_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:109:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer42_cpy1' with compact=bit mode in 256-bits (firmware/myproject.cpp:103:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer42_cpy2' with compact=bit mode in 256-bits (firmware/myproject.cpp:106:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer10_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:100:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer47_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:94:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer8_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:91:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer31_out' with compact=bit mode in 656-bits (firmware/myproject.cpp:199:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer9_out' with compact=bit mode in 656-bits (firmware/myproject.cpp:97:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer29_out' with compact=bit mode in 672-bits (firmware/myproject.cpp:190:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer54_out' with compact=bit mode in 768-bits (firmware/myproject.cpp:187:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer28_out' with compact=bit mode in 768-bits (firmware/myproject.cpp:184:30) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer27_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:181:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer26_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:178:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer53_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:172:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer24_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:169:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer50_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:139:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer16_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:136:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer43_cpy1' with compact=bit mode in 512-bits (firmware/myproject.cpp:130:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer43_cpy2' with compact=bit mode in 512-bits (firmware/myproject.cpp:133:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer15_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:127:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer49_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:121:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer13_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:118:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer25_out' with compact=bit mode in 1344-bits (firmware/myproject.cpp:175:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer14_out' with compact=bit mode in 1344-bits (firmware/myproject.cpp:124:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer23_out' with compact=bit mode in 1376-bits (firmware/myproject.cpp:166:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer52_out' with compact=bit mode in 1536-bits (firmware/myproject.cpp:163:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer22_out' with compact=bit mode in 1536-bits (firmware/myproject.cpp:160:28) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer21_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:157:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer20_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:154:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer51_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:148:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer18_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:145:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer19_out' with compact=bit mode in 2752-bits (firmware/myproject.cpp:151:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer17_out' with compact=bit mode in 2688-bits (firmware/myproject.cpp:142:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer12_out' with compact=bit mode in 1312-bits (firmware/myproject.cpp:115:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer7_out' with compact=bit mode in 640-bits (firmware/myproject.cpp:88:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer2_out' with compact=bit mode in 296-bits (firmware/myproject.cpp:61:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer44_out' with compact=bit mode in 16-bits (firmware/myproject.cpp:58:25) +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::conv_2d_buffer_resource_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_64' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_65' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_66' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_67' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_68' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_69' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_70' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_71' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_72' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_73' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_74' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_75' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_76' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_77' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_78' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_79' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_80' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_81' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_82' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_83' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_84' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_85' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_86' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_87' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_88' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_89' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_90' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_91' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_92' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_93' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_94' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_95' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_64' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_65' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_66' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_67' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_68' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_69' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_70' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_71' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_72' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_73' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_74' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_75' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_76' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_77' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_78' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_79' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_80' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_81' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_82' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_83' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_84' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_85' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_86' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_87' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_88' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_89' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_90' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_91' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_92' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_93' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_94' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_95' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-248] Applying array_reshape to 'w4': Block reshaping with factor 8 on dimension 1. (firmware/weights/w4.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w7': Block reshaping with factor 16 on dimension 1. (firmware/weights/w7.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w9': Block reshaping with factor 32 on dimension 1. (firmware/weights/w9.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w12': Block reshaping with factor 64 on dimension 1. (firmware/weights/w12.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w14': Block reshaping with factor 128 on dimension 1. (firmware/weights/w14.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w17': Block reshaping with factor 256 on dimension 1. (firmware/weights/w17.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w19': Block reshaping with factor 576 on dimension 1. (firmware/weights/w19.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w23': Block reshaping with factor 384 on dimension 1. (firmware/weights/w23.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w25': Block reshaping with factor 128 on dimension 1. (firmware/weights/w25.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w29': Block reshaping with factor 96 on dimension 1. (firmware/weights/w29.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w31': Block reshaping with factor 32 on dimension 1. (firmware/weights/w31.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w35': Block reshaping with factor 24 on dimension 1. (firmware/weights/w35.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w37': Block reshaping with factor 8 on dimension 1. (firmware/weights/w37.h:12:0) +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadTopWidth> at firmware/nnet_utils/nnet_padding_stream.h:53:9 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadMain> at firmware/nnet_utils/nnet_padding_stream.h:59:5 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadBottomWidth> at firmware/nnet_utils/nnet_padding_stream.h:77:9 +INFO: [HLS 214-291] Loop 'CopyMain' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_padding_stream.h:65:9) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-270] Inferring pragma 'array_partition type=complete dim=1' for array 'ref.tmp.i' due to pipeline pragma +INFO: [HLS 214-248] Applying array_partition to 'ref.tmp.i': Complete partitioning on dimension 1. +INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 282.56 seconds. CPU system time: 5.17 seconds. Elapsed time: 277.5 seconds; current allocated memory: 350.855 MB. +INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 350.922 MB. +INFO: [HLS 200-10] Starting code transformations ... +INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 27.85 seconds. CPU system time: 0.05 seconds. Elapsed time: 28.01 seconds; current allocated memory: 420.207 MB. +INFO: [HLS 200-10] Checking synthesizability ... +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 96.67 seconds. CPU system time: 0.07 seconds. Elapsed time: 96.75 seconds; current allocated memory: 538.688 MB. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-712] Applying dataflow to function 'myproject' (firmware/myproject.cpp:8), detected/extracted 56 process function(s): + 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>' + 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config3>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config5>' + 'nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>' + 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config8>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config10>' + 'nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>' + 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config13>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config15>' + 'nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>' + 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>' + 'nnet::relu, 64u>, nnet::array, 64u>, relu_config18>' + 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>' + 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>' + 'nnet::relu, 64u>, nnet::array, 64u>, relu_config20>' + 'nnet::resize_nearest, 64u>, config21>' + 'nnet::concatenate3d, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' + 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>' + 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config24>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config26>' + 'nnet::resize_nearest, 32u>, config27>' + 'nnet::concatenate3d, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' + 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>' + 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config30>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config32>' + 'nnet::resize_nearest, 16u>, config33>' + 'nnet::concatenate3d, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' + 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>' + 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config36>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config38>' + 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>' + 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>'. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_activation_stream.h:81:9) to (firmware/nnet_utils/nnet_activation_stream.h:80:5) in function 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>'... converting 3 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>'... converting 18 basic blocks. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' (firmware/nnet_utils/nnet_dense_resource.h:46:20)...384 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_mult.h:46:11)...576 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' (firmware/nnet_utils/nnet_dense_resource.h:46:5)...96 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' (firmware/nnet_utils/nnet_mult.h:46:11)...128 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_mult.h:46:11)...256 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' (firmware/nnet_utils/nnet_mult.h:46:11)...128 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' (firmware/nnet_utils/nnet_dense_resource.h:46:5)...24 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...13 expression(s) balanced. +INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 239.24 seconds. CPU system time: 0.17 seconds. Elapsed time: 239.43 seconds; current allocated memory: 886.375 MB. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_pooling_stream.h:109:5) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_pooling_stream.h:109:5) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_pooling_stream.h:109:5) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeightSerial' (firmware/nnet_utils/nnet_sepconv2d_stream.h:81:9) in function 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ConcatLoopHeight' (firmware/nnet_utils/nnet_merge_stream.h:234:5) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ConcatLoopHeight' (firmware/nnet_utils/nnet_merge_stream.h:234:5) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ConcatLoopHeight' (firmware/nnet_utils/nnet_merge_stream.h:234:5) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>'. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config23_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config19_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config29_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config25_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config17_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config14_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config9_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config35_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config31_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config12_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config7_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config4_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config37_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config58_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0,config2_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config23_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config19_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config29_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config25_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config17_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config14_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config9_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config35_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config31_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config12_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config7_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config4_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config37_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config58_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0,config2_mult>'. +INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 34.77 seconds. CPU system time: 0.68 seconds. Elapsed time: 35.46 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] Starting hardware synthesis ... +INFO: [HLS 200-10] Synthesizing 'myproject' ... +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,1u>,config44>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,1u>,config44>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config44>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,1u>,config44>' to 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 1u>, config2>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0,config2_mult>' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config2>' to 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config2>' to 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config3>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config45>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config45>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config45>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,8u>,config45>' to 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config4>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config4_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config4>' to 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config4>' to 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config5>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s'. +WARNING: [SYN 201-103] Legalizing function name 'clone_stream,array,8u>,32768>' to 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config6>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +WARNING: [SYN 201-103] Legalizing function name 'pooling2d_cl,array,8u>,config6>' to 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config46>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config46>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config46>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,8u>,config46>' to 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config7>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config7_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config7>' to 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,16u>,config7>' to 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config8>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config47>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config47>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config47>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config47>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config9>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config9_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config9>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,16u>,config9>' to 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config10>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s'. +WARNING: [SYN 201-103] Legalizing function name 'clone_stream,array,16u>,16384>' to 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config11>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +WARNING: [SYN 201-103] Legalizing function name 'pooling2d_cl,16u>,config11>' to 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config48>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config48>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config48>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config48>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config12>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config12_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config12>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config12>' to 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config13>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config49>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config49>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config49>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config49>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config14>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config14_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config14>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config14>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config15>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s'. +WARNING: [SYN 201-103] Legalizing function name 'clone_stream,array,32u>,8192>' to 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config16>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +WARNING: [SYN 201-103] Legalizing function name 'pooling2d_cl,32u>,config16>' to 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config50>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config50>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config50>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config50>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config17>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config17_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,64u>,config17>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,64u>,config17>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,64u>,relu_config18>' to 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config51>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,64u>,config51>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config51>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,64u>,config51>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 64u>, config19>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config19_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,64u>,config19>' to 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,64u>,config19>' to 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,64u>,relu_config20>' to 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s'. +WARNING: [SYN 201-103] Legalizing function name 'resize_nearest, 64u>, config21>' to 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d_2,96u>,config22>' to 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d,96u>,config22>' to 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config52>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,96u>,config52>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config52>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,96u>,config52>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 96u>, config23>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config23_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config23>' to 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config23>' to 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config24>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config53>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config53>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config53>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config53>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config25>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config25_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config25>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config25>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config26>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s'. +WARNING: [SYN 201-103] Legalizing function name 'resize_nearest, 32u>, config27>' to 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d_2,48u>,config28>' to 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d,48u>,config28>' to 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config54>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,48u>,config54>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config54>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,48u>,config54>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 48u>, config29>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config29_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config29>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,16u>,config29>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config30>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config55>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config55>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config55>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config55>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config31>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config31_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config31>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,16u>,config31>' to 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config32>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s'. +WARNING: [SYN 201-103] Legalizing function name 'resize_nearest, 16u>, config33>' to 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d_2,24u>,config34>' to 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d,24u>,config34>' to 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config56>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,24u>,config56>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config56>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,24u>,config56>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 24u>, config35>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config35_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config35>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config35>' to 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config36>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config57>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config57>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config57>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,8u>,config57>' to 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config37>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config37_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config37>' to 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config37>' to 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config38>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config58_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'pointwise_conv_2d_cl,1u>,config58>' to 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_s'. +WARNING: [SYN 201-103] Legalizing function name 'sigmoid,1u>,sigmoid_config40>' to 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s'. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 4.09 seconds. CPU system time: 0.35 seconds. Elapsed time: 4.48 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.94 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.97 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 1u>, config2>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 1u>, config2>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.411 ns) exceeds the target (target clock period: 5.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 3.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' consists of the following: + 'or' operation 1 bit ('or_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [82] (0.000 ns) + 'or' operation 1 bit ('or_ln144_2', firmware/nnet_utils/nnet_dense_resource.h:144) [84] (0.000 ns) + 'or' operation 1 bit ('or_ln144_6', firmware/nnet_utils/nnet_dense_resource.h:144) [88] (0.000 ns) + 'select' operation 37 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [89] (0.229 ns) + 'select' operation 37 bit ('acc_7', firmware/nnet_utils/nnet_dense_resource.h:144) [93] (0.229 ns) + multiplexor before 'phi' operation 37 bit ('acc') with incoming values : ('acc_7', firmware/nnet_utils/nnet_dense_resource.h:144) [33] (0.387 ns) + 'phi' operation 37 bit ('acc') with incoming values : ('acc_7', firmware/nnet_utils/nnet_dense_resource.h:144) [33] (0.000 ns) + 'sparsemux' operation 37 bit ('tmp_i', firmware/nnet_utils/nnet_dense_resource.h:144) [70] (0.584 ns) + 'add' operation 38 bit of DSP[73] ('add_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [73] (2.039 ns) + 'icmp' operation 1 bit ('icmp_ln144_7', firmware/nnet_utils/nnet_dense_resource.h:144) [81] (0.943 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.98 seconds. CPU system time: 0.02 seconds. Elapsed time: 1 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config4>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config4>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.26 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.26 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'CloneLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'CloneLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config6>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config6>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReadInputHeight_ReadInputWidth'. +WARNING: [HLS 200-880] The II Violation in module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' (loop 'ReadInputHeight_ReadInputWidth'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between 'load' operation 16 bit ('void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_32', firmware/nnet_utils/nnet_pooling_stream.h:63->firmware/nnet_utils/nnet_pooling_stream.h:115) on static variable 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel' and 'call' operation 0 bit ('_ln52', firmware/nnet_utils/nnet_pooling_stream.h:52->firmware/nnet_utils/nnet_pooling_stream.h:115) to 'shift_line_buffer, 8u>, config6>'. +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 2, Depth = 3, loop 'ReadInputHeight_ReadInputWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.44 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.48 seconds; current allocated memory: 2.625 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.625 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.625 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.625 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.625 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.625 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config7>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config7>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.626 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.626 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.3 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.31 seconds; current allocated memory: 2.632 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.632 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.632 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.632 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.632 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.632 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.632 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.632 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.632 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.632 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.46 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.49 seconds; current allocated memory: 2.633 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.633 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.633 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.633 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.633 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.633 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config9>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config9>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.634 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.635 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.48 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.51 seconds; current allocated memory: 2.646 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.646 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.646 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.646 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.646 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.646 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.646 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.646 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'CloneLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'CloneLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.646 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.646 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config11>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config11>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.646 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.646 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReadInputHeight_ReadInputWidth'. +WARNING: [HLS 200-880] The II Violation in module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' (loop 'ReadInputHeight_ReadInputWidth'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between 'load' operation 16 bit ('void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_52', firmware/nnet_utils/nnet_pooling_stream.h:63->firmware/nnet_utils/nnet_pooling_stream.h:115) on static variable 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_20' and 'call' operation 0 bit ('_ln52', firmware/nnet_utils/nnet_pooling_stream.h:52->firmware/nnet_utils/nnet_pooling_stream.h:115) to 'shift_line_buffer, 16u>, config11>'. +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 2, Depth = 3, loop 'ReadInputHeight_ReadInputWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.22 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.646 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.647 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.648 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.648 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.3 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.31 seconds; current allocated memory: 2.648 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.649 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.649 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.649 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.649 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.649 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config12>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config12>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.650 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.651 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.64 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.66 seconds; current allocated memory: 2.673 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.673 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.673 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.673 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.673 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.673 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.673 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.673 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.673 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.673 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.29 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.33 seconds; current allocated memory: 2.673 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.673 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.673 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.673 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.673 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.673 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config14>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config14>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.28 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.3 seconds; current allocated memory: 2.673 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.673 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.29 seconds. CPU system time: 0.03 seconds. Elapsed time: 1.31 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.36 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.37 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.25 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.28 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.2 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'CloneLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'CloneLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config16>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config16>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReadInputHeight_ReadInputWidth'. +WARNING: [HLS 200-880] The II Violation in module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' (loop 'ReadInputHeight_ReadInputWidth'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between 'load' operation 16 bit ('void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_42', firmware/nnet_utils/nnet_pooling_stream.h:63->firmware/nnet_utils/nnet_pooling_stream.h:115) on static variable 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_19' and 'call' operation 0 bit ('_ln52', firmware/nnet_utils/nnet_pooling_stream.h:52->firmware/nnet_utils/nnet_pooling_stream.h:115) to 'shift_line_buffer, 32u>, config16>'. +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 2, Depth = 3, loop 'ReadInputHeight_ReadInputWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.31 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.33 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 7, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 9, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 10, Depth = 11, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.25 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.26 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config17>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config17>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.3 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.32 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 2.08 seconds. CPU system time: 0.05 seconds. Elapsed time: 2.13 seconds; current allocated memory: 2.779 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.63 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.64 seconds; current allocated memory: 2.779 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.33 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.35 seconds; current allocated memory: 2.779 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.779 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.779 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.779 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.25 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.26 seconds; current allocated memory: 2.779 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.779 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.779 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.779 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 7, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 9, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 10, Depth = 11, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.25 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.28 seconds; current allocated memory: 2.779 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.779 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.779 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.779 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.779 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.779 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 64u>, config19>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 64u>, config19>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.6 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.63 seconds; current allocated memory: 2.779 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.2 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.779 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 5, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 4.92 seconds. CPU system time: 0.09 seconds. Elapsed time: 5 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 1.97 seconds. CPU system time: 0.05 seconds. Elapsed time: 2.06 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.57 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.64 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.21 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.23 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.3 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.31 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ImageHeight'. +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_1', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_2', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_3', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_4', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 32, Depth = 32, loop 'ImageHeight' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.38 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.41 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ConcatLoopHeight_ConcatLoopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'ConcatLoopHeight_ConcatLoopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.34 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.37 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 96u>, config23>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 96u>, config23>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.06 seconds. CPU system time: 0.01 seconds. Elapsed time: 1.07 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.32 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.33 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 5, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 4.58 seconds. CPU system time: 0.06 seconds. Elapsed time: 4.65 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 1.66 seconds. CPU system time: 0.04 seconds. Elapsed time: 1.7 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.57 seconds. CPU system time: 0.07 seconds. Elapsed time: 0.65 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.26 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.27 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.26 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.28 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.37 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.38 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config25>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config25>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.31 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.32 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.31 seconds. CPU system time: 0.01 seconds. Elapsed time: 1.32 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.36 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.39 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.26 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.29 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.21 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.24 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ImageHeight'. +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_1', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_2', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_3', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_4', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 64, Depth = 64, loop 'ImageHeight' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.72 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.73 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ConcatLoopHeight_ConcatLoopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'ConcatLoopHeight_ConcatLoopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.55 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.57 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 48u>, config29>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 48u>, config29>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.45 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.47 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.19 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 5, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.4 seconds. CPU system time: 0.03 seconds. Elapsed time: 1.43 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.43 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.46 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.28 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.32 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.2 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.52 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.58 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config31>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config31>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.22 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.24 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.52 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.54 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ImageHeight'. +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_1', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_2', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_3', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_4', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 67, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 98, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 114, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 122, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 126, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 127, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 128, Depth = 128, loop 'ImageHeight' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.78 seconds. CPU system time: 0.02 seconds. Elapsed time: 1.81 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ConcatLoopHeight_ConcatLoopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'ConcatLoopHeight_ConcatLoopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 1.18 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 24u>, config35>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 24u>, config35>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.27 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.3 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.16 seconds. CPU system time: 0 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.62 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.63 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.2 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.22 seconds. CPU system time: 0 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.11 seconds. CPU system time: 0.06 seconds. Elapsed time: 1.17 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config37>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config37>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.2 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.32 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.33 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.2 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'SigmoidActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 4, loop 'SigmoidActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.2 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'myproject' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +WARNING: [HLS 200-1020] Increasing the depth of FIFO start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0 (from clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0 to concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0) to 10 to improve performance and/or avoid deadlocks. +WARNING: [HLS 200-1020] Increasing the depth of FIFO start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0 (from clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_U0 to concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0) to 26 to improve performance and/or avoid deadlocks. +WARNING: [HLS 200-1020] Increasing the depth of FIFO start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0 (from clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0 to concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0) to 42 to improve performance and/or avoid deadlocks. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.45 seconds. CPU system time: 0 seconds. Elapsed time: 0.46 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.34 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.36 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.79 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.81 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.969 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.969 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_cud' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.13 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.970 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_outidx_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_oudEe' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_w2_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_w2eOg' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_37s_38_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_17_3_37_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_19_4_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_oudEe' using auto ROMs. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_w2eOg' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.28 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.33 seconds; current allocated memory: 2.973 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_7' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.41 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.46 seconds; current allocated memory: 2.976 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.977 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.977 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.979 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.982 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.985 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.985 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1375_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_fYi' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1383_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_g8j' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1376_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_hbi' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1384_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_ibs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1377_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_jbC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1385_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_kbM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1378_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_lbW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1386_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_mb6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1379_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_ncg' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1387_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_ocq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1380_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_pcA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1388_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_qcK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1381_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_rcU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1389_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_sc4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1382_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_tde' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1390_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_udo' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.47 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.51 seconds; current allocated memory: 2.989 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_w4_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_w4_ROMvdy' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_38s_38_1_1': 7 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_8s_30s_30_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_w4_ROMvdy' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.33 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.36 seconds; current allocated memory: 2.993 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_13' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.82 seconds. CPU system time: 0.25 seconds. Elapsed time: 2.07 seconds; current allocated memory: 3.002 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 3.005 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 3.006 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 3.008 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stwdI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stxdS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_styd2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stzec' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stAem' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stBew' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stCeG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stDeQ' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.29 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.33 seconds; current allocated memory: 3.009 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'sY' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX' is power-on initialization. +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' pipeline 'ReadInputHeight_ReadInputWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.01 seconds. CPU system time: 0.07 seconds. Elapsed time: 1.08 seconds; current allocated memory: 3.012 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.21 seconds; current allocated memory: 3.015 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 3.018 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0 seconds. Elapsed time: 0.18 seconds; current allocated memory: 3.021 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.11 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.13 seconds; current allocated memory: 3.021 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1359_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Ee0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1367_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Ffa' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1360_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Gfk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1368_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Hfu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1361_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_IfE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1369_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_JfO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1362_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_KfY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1370_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Lf8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1363_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Mgi' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1371_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Ngs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1364_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_OgC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1372_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_PgM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1365_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_QgW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1373_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Rg6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1366_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Shg' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1374_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Thq' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.47 seconds. CPU system time: 0.07 seconds. Elapsed time: 0.54 seconds; current allocated memory: 3.023 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_w7_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_w7_ROMUhA' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_38s_38_1_1': 15 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_w7_ROMUhA' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.35 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.39 seconds; current allocated memory: 3.028 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_38' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_30' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_39' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_31' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_32' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_33' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_34' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_35' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_36' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_37' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_15' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.99 seconds. CPU system time: 0.18 seconds. Elapsed time: 2.18 seconds; current allocated memory: 3.039 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 3.041 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 3.043 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 3.045 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 3.048 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 3.049 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.13 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 3.050 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_799_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dVhK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_815_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dWhU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_800_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dXh4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_816_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dYie' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_807_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dZio' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_823_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d0iy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_808_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d1iI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_824_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d2iS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_809_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d3i2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_825_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d4jc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_810_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d5jm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_826_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d6jw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_811_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d7jG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_827_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d8jQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_812_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d9j0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_828_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbak' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_813_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbbk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_829_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbck' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_814_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbdk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_830_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbek' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_801_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbfk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_817_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbgk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_802_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbhl' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_818_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbil' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_803_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbjl' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_819_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbkl' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_804_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbll' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_820_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbml' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_805_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbnm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_821_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbom' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_806_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbpm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_822_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbqm' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.91 seconds. CPU system time: 0.07 seconds. Elapsed time: 0.97 seconds; current allocated memory: 3.054 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbrm' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 15 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 16 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 2 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbrm' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.45 seconds. CPU system time: 0.07 seconds. Elapsed time: 0.53 seconds; current allocated memory: 3.065 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4177' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4178' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4179' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4180' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4181' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4182' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4183' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4184' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4185' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4186' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4188' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4122' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4189' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4134' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4190' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4191' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4192' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4137' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4123' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4124' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4125' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4126' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4127' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4128' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4129' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4130' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4131' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4133' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4135' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4136' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_9' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 3.87 seconds. CPU system time: 0.38 seconds. Elapsed time: 4.25 seconds; current allocated memory: 3.084 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.21 seconds; current allocated memory: 3.087 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.17 seconds; current allocated memory: 3.089 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 3.091 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bsm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_btn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bun' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bvn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bwn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bxn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_byn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bzo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bAo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bBo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_27_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbCo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_26_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbDo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_25_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbEo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_24_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbFp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_23_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbGp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_22_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbHp' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.51 seconds. CPU system time: 0.06 seconds. Elapsed time: 0.58 seconds; current allocated memory: 3.094 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'sY_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_11' is power-on initialization. +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' pipeline 'ReadInputHeight_ReadInputWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.87 seconds. CPU system time: 0.17 seconds. Elapsed time: 2.05 seconds; current allocated memory: 3.099 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.23 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.26 seconds; current allocated memory: 3.105 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 3.106 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0 seconds. Elapsed time: 0.18 seconds; current allocated memory: 3.109 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.14 seconds. CPU system time: 0 seconds. Elapsed time: 0.14 seconds; current allocated memory: 3.109 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_863_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bIp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_879_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bJp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_864_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_880_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bLp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_871_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bMq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_887_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bNq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_872_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bOq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_888_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bPq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_873_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bQq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_889_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bRq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_874_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bSr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_890_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bTr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_875_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bUr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_891_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bVr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_876_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bWr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_892_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bXr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_877_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bYs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_893_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bZs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_878_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b0s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_894_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b1s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_865_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b2s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_881_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b3s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_866_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b4t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_882_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b5t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_867_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b6t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_883_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b7t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_868_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b8t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_884_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b9t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_869_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2cau' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_885_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2cbu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_870_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2ccu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_886_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2cdu' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.91 seconds. CPU system time: 0.12 seconds. Elapsed time: 1.04 seconds; current allocated memory: 3.112 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s_w12_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s_w12_Rceu' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 31 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 32 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 2 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s_w12_Rceu' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.54 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.6 seconds; current allocated memory: 3.127 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4416' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4428' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4441' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4453' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4465' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4432' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4433' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4434' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4435' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4436' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4417' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4437' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4419' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4438' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4420' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4439' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4421' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4442' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4422' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4443' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4423' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4444' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4424' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4445' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4425' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4446' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4426' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4447' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4427' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4448' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4430' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4449' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4431' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4450' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4452' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4454' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4455' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4456' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4457' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4458' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4459' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4460' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4461' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4463' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4464' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4466' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4467' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4468' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4469' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_8' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.12 seconds. CPU system time: 0.46 seconds. Elapsed time: 4.58 seconds; current allocated memory: 3.151 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.2 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.22 seconds; current allocated memory: 3.155 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.21 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.23 seconds; current allocated memory: 3.157 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.22 seconds; current allocated memory: 3.160 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 3.162 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 3.165 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 3.165 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_943_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cfu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_975_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cgu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_944_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2chv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_976_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2civ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_955_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cjv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_987_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2ckv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_966_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2clv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_998_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cmv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_969_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cnw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1001_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cow' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_970_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cpw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1002_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cqw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_971_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2crw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1003_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2csw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_972_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2ctx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1004_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cux' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_973_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cvx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1005_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cwx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_974_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cxx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1006_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cyx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_945_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2czy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_977_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cAy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_946_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cBy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_978_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cCy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_947_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cDy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_979_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cEy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_948_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cFz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_980_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cGz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_949_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cHz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_981_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cIz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_950_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cJz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_982_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cKz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_951_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cLz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_983_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cMA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_952_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cNA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_984_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cOA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_953_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cPA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_985_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cQA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_954_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cRA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_986_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cSB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_956_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cTB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_988_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cUB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_957_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cVB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_989_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cWB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_958_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cXB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_990_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cYC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_959_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cZC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_991_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c0C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_960_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c1C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_992_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c2C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_961_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c3C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_993_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c4D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_962_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c5D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_994_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c6D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_963_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c7D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_995_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c8D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_964_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c9D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_996_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2daE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_965_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dbE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_997_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dcE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_967_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2ddE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_999_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2deE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_968_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dfE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1000_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dgE' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.9 seconds. CPU system time: 0.16 seconds. Elapsed time: 2.05 seconds; current allocated memory: 3.170 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s_w14_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s_w14_RdhF' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s' is 9216 from HDL expression: (do_init_reg_1345 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 63 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 64 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 4 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s_w14_RdhF' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.85 seconds. CPU system time: 0.07 seconds. Elapsed time: 0.93 seconds; current allocated memory: 3.198 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5021' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_89' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5022' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_88' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5024' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_87' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5025' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_86' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5026' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_85' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5027' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_84' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5028' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_83' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5029' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_82' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5030' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_81' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5031' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_80' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5032' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5033' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5035' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5036' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5037' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4839' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5038' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4851' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5039' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4863' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5040' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4875' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5041' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4887' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5042' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4899' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5043' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4911' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5044' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4923' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5046' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4936' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5047' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4948' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5048' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4960' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5049' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4972' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5050' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4984' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5051' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4996' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5052' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5008' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5053' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5018' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5054' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5019' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5055' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5020' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5092' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5093' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5094' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5095' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4840' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4841' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4842' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4843' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4844' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4845' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4846' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4848' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4849' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4850' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4852' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4853' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4854' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4855' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4856' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4857' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4859' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4860' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4861' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4862' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4941' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4903' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4942' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4904' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4943' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4905' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4944' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4906' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4945' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4907' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4947' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4908' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4949' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4909' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4950' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4910' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4951' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4912' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4952' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4914' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4953' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4915' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4954' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4916' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4955' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4917' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4956' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4918' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4958' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4919' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4959' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4920' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4961' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4921' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4962' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4922' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4963' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4925' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4964' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4926' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4965' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4927' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4966' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4928' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4967' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4929' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4969' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4930' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4970' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4931' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4971' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4932' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4973' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4933' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4974' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4934' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4975' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4937' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4976' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4938' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4977' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4939' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4978' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4940' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5057' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5058' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5059' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5060' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5061' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5062' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5063' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5064' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5065' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5066' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5068' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5069' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5070' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5071' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5072' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5073' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5074' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5075' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5076' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5077' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5079' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5080' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5081' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5082' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5083' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5084' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5085' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5086' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5087' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5088' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5090' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5091' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4864' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4865' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4866' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4867' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4868' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4870' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4871' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4872' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4873' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4874' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4876' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4877' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4878' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4879' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4881' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4882' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4883' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4884' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4885' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4886' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4888' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4889' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4890' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4892' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4893' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4894' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4895' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4896' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4897' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4898' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4900' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4901' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4980' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4981' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4982' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4983' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4985' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4986' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4987' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4988' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4989' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4991' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4992' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4993' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4994' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4995' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4997' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4998' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5000' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5002' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5003' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5004' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5005' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5006' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5007' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5009' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5010' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5011' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5013' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5014' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5015' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5016' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5017' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_5' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 8.52 seconds. CPU system time: 1.01 seconds. Elapsed time: 9.55 seconds; current allocated memory: 3.241 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.27 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.29 seconds; current allocated memory: 3.247 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.26 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.27 seconds; current allocated memory: 3.250 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.21 seconds; current allocated memory: 3.253 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_diF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_djF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dkF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dlF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dmF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dnG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_doG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dpG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dqG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_drG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_21_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindsG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_20_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindtH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_19_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolinduH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_18_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindvH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_17_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindwH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_16_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindxH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_15_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindyH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_14_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindzI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_13_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindAI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_12_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindBI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_11_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindCI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_10_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindDI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindEI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindFJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindGJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindHJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindIJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindJJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindKJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindLJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindMK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindNK' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.04 seconds. CPU system time: 0.12 seconds. Elapsed time: 1.16 seconds; current allocated memory: 3.256 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'sY_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_89' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_57' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_88' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_56' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_87' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_55' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_86' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_54' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_85' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_53' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_84' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_52' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_83' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_51' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_82' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_50' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_81' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_49' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_80' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_48' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_79' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_47' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_78' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_46' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_77' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_45' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_76' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_44' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_75' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_43' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_74' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_42' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_73' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_41' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_72' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_40' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_71' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_39' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_70' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_38' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_69' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_37' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_68' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_36' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_99' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_67' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_35' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_98' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_66' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_34' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_97' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_65' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_33' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_96' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_64' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_32' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_95' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_63' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_31' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_94' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_62' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_30' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_93' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_61' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_92' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_60' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_91' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_59' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_90' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_58' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_3' is power-on initialization. +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' pipeline 'ReadInputHeight_ReadInputWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.07 seconds. CPU system time: 0.42 seconds. Elapsed time: 4.49 seconds; current allocated memory: 3.268 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.33 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.37 seconds; current allocated memory: 3.278 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 3.279 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 3.280 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 3.282 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1071_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dOK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1103_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dPK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1072_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dQK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1104_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dRK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1083_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dSL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1115_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dTL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1094_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dUL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1126_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dVL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1097_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dWL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1129_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dXL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1098_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dYM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1130_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dZM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1099_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d0M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1131_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d1M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1100_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d2M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1132_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d3M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1101_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d4N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1133_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d5N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1102_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d6N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1134_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d7N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1073_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d8N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1105_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d9N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1074_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eaO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1106_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ebO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1075_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ecO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1107_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2edO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1076_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eeO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1108_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2efO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1077_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2egO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1109_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ehP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1078_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eiP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1110_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ejP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1079_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ekP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1111_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2elP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1080_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2emP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1112_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2enQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1081_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eoQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1113_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2epQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1082_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eqQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1114_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2erQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1084_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2esQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1116_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2etR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1085_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2euR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1117_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2evR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1086_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ewR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1118_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2exR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1087_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eyR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1119_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ezS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1088_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eAS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1120_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eBS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1089_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eCS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1121_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eDS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1090_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eES' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1122_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eFT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1091_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eGT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1123_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eHT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1092_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eIT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1124_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eJT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1093_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eKT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1125_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eLT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1095_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eMU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1127_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eNU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1096_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eOU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1128_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ePU' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 2 seconds. CPU system time: 0.24 seconds. Elapsed time: 2.25 seconds; current allocated memory: 3.287 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s_w17_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s_w17_ReQU' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s' is 9216 from HDL expression: (do_init_reg_1923 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 127 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 128 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 4 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s_w17_ReQU' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.12 seconds. CPU system time: 0.09 seconds. Elapsed time: 1.21 seconds; current allocated memory: 3.330 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_69' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_68' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_67' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_66' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_65' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_64' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_63' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_62' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_61' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_60' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5402' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5414' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5426' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5438' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5450' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5462' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5436' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5437' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5439' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5440' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5442' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5403' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5443' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5404' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5444' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5405' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5445' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5406' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5446' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5407' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5447' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5409' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5448' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5410' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5449' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5411' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5451' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5412' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5453' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5413' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5454' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5415' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5455' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5416' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5456' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5417' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5457' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5418' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5458' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5420' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5459' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5421' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5460' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5422' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5461' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5423' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5464' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5424' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5465' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5425' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5466' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5427' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5467' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5428' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5468' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5429' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5469' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5431' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5432' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5433' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5434' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5435' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_10' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 9.94 seconds. CPU system time: 0.86 seconds. Elapsed time: 10.83 seconds; current allocated memory: 3.389 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.34 seconds; current allocated memory: 3.395 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.31 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.34 seconds; current allocated memory: 3.399 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.28 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.31 seconds; current allocated memory: 3.405 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.2 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.22 seconds; current allocated memory: 3.408 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.22 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.23 seconds; current allocated memory: 3.409 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.19 seconds; current allocated memory: 3.410 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1231_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eRU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1295_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eSV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1232_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eTV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1296_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eUV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1243_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eVV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1307_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eWV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1254_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eXV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1318_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eYW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1265_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eZW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1329_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e0W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1276_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e1W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1340_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e2W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1287_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e3W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1351_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e4X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1292_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e5X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1356_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e6X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1293_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e7X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1357_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e8X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1294_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e9X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1358_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2faY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1233_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fbY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1297_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fcY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1234_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fdY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1298_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2feY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1235_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ffY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1299_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fgY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1236_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fhZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1300_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fiZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1237_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fjZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1301_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fkZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1238_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2flZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1302_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fmZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1239_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fn0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1303_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fo0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1240_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fp0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1304_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fq0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1241_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fr0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1305_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fs0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1242_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ft1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1306_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fu1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1244_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fv1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1308_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fw1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1245_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fx1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1309_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fy1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1246_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fz2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1310_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fA2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1247_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fB2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1311_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fC2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1248_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fD2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1312_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fE2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1249_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fF3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1313_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fG3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1250_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fH3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1314_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fI3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1251_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fJ3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1315_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fK3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1252_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fL3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1316_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fM4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1253_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fN4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1317_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fO4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1255_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fP4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1319_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fQ4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1256_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fR4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1320_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fS5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1257_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fT5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1321_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fU5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1258_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fV5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1322_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fW5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1259_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fX5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1323_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fY6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1260_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fZ6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1324_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f06' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1261_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f16' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1325_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f26' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1262_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f36' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1326_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f47' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1263_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f57' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1327_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f67' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1264_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f77' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1328_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f87' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1266_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f97' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1330_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ga8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1267_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gb8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1331_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gc8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1268_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gd8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1332_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ge8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1269_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gf8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1333_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gg8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1270_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gh9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1334_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gi9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1271_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gj9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1335_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gk9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1272_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gl9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1336_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gm9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1273_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1337_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1274_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1338_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1275_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2grb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1339_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1277_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gtb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1341_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1278_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1342_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1279_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1343_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1280_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1344_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gAb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1281_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gBb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1345_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gCb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1282_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gDb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1346_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gEb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1283_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gFb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1347_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gGb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1284_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gHb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1348_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gIb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1285_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gJb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1349_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gKb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1286_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gLb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1350_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gMb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1288_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1352_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1289_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1353_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1290_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1354_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1291_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1355_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gUb_x' due to conflict. +INFO: [RTGEN 206-104] Estimated max fanout for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s' is 9216 from HDL expression: (1'b1 == ap_CS_fsm_state1) +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.61 seconds. CPU system time: 0.46 seconds. Elapsed time: 5.07 seconds; current allocated memory: 3.420 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s_w19_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s_w19_RgVb' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s' is 18432 from HDL expression: (do_init_reg_3761 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 256 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_33s_33_1_1': 63 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 256 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_129_6_16_1_1': 9 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s_w19_RgVb' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 2.31 seconds. CPU system time: 0.13 seconds. Elapsed time: 2.43 seconds; current allocated memory: 3.499 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_49' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_48' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_47' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_46' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_45' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_44' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_43' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_42' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_41' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_40' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6184' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6293' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6305' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6317' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6329' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6341' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6353' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6366' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6378' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6390' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6402' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6414' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6426' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6438' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6450' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6462' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6177' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6179' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6180' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6181' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6182' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6183' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6185' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6186' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6187' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6188' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6190' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6191' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6192' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6361' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6362' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6363' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6364' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6287' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6367' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6289' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6368' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6290' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6369' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6291' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6370' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6292' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6371' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6294' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6372' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6295' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6373' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6296' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6374' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6297' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6375' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6298' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6377' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6300' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6379' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6301' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6380' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6302' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6381' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6303' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6382' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6304' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6383' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6306' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6384' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6307' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6385' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6308' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6386' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6309' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6388' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6311' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6389' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6312' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6391' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6313' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6392' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6314' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6393' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6315' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6394' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6316' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6395' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6318' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6396' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6319' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6397' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6320' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6399' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6322' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6400' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6323' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6401' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6324' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6403' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6325' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6404' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6326' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6405' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6327' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6406' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6328' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6407' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6330' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6408' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6331' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6410' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6333' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6411' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6334' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6412' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6335' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6413' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6336' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6415' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6337' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6416' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6338' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6417' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6339' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6418' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6340' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6419' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6342' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6421' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6344' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6422' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6345' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6423' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6346' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6424' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6347' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6425' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6348' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6427' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6349' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6428' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6350' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6429' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6351' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6430' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6352' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6432' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6355' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6433' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6356' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6434' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6357' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6435' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6358' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6436' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6359' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6437' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6360' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6439' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6440' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6441' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6443' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6444' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6445' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6446' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6447' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6448' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6449' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6451' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6452' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6454' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6455' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6456' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6457' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6458' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6459' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6460' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6461' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6463' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6465' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6466' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6467' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6468' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6469' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_16' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 21.7 seconds. CPU system time: 2.18 seconds. Elapsed time: 23.94 seconds; current allocated memory: 3.626 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.49 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.52 seconds; current allocated memory: 3.638 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.43 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.46 seconds; current allocated memory: 3.647 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.28 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.32 seconds; current allocated memory: 3.652 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' pipeline 'ConcatLoopHeight_ConcatLoopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.26 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.28 seconds; current allocated memory: 3.660 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.21 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.23 seconds; current allocated memory: 3.661 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.24 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.26 seconds; current allocated memory: 3.662 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.25 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.27 seconds; current allocated memory: 3.662 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.26 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.28 seconds; current allocated memory: 3.664 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.2 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.23 seconds; current allocated memory: 3.665 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1407_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2gWb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_95_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2gXb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1408_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2gYb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_94_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2gZb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1419_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_83_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1430_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_72_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1441_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_61_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1452_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_50_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1463_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_39_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1474_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_28_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1485_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_17_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1496_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2heb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1409_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_93_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1410_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_92_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1411_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_91_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hlb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1412_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_90_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1413_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_89_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1414_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_88_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1415_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_87_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2htb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1416_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_86_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1417_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_85_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1418_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_84_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1420_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_82_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1421_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_81_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1422_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_80_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1423_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_79_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1424_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_78_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1425_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_77_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1426_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_76_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1427_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_75_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1428_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_74_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1429_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_73_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1431_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_71_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1432_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_70_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1433_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_69_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1434_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_68_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1435_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_67_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1436_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_66_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1437_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_65_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1438_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_64_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1439_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_63_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ibb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1440_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2icb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_62_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2idb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1442_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ieb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_60_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ifb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1443_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2igb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_59_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ihb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1444_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_58_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ijb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1445_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ikb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_57_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ilb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1446_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2imb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_56_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2inb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1447_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_55_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ipb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1448_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_54_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2irb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1449_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2isb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_53_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2itb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1450_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_52_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ivb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1451_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_51_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ixb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1453_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_49_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2izb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1454_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_48_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1455_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_47_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1456_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_46_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1457_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_45_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1458_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_44_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1459_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_43_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1460_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_42_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1461_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_41_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1462_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_40_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1464_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_38_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1465_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_37_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1466_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_36_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1467_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_35_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1468_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_34_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1469_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_33_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1470_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_32_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1471_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_31_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1472_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_30_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1473_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_29_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1475_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_27_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1476_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jeb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_26_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1477_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_25_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1478_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_24_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1479_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_23_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jlb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1480_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_22_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1481_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2job' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_21_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1482_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_20_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1483_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_19_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jtb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1484_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_18_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1486_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_16_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1487_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_15_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1488_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_14_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1489_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_13_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1490_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_12_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1491_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_11_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1492_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_10_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1493_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1494_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1495_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1497_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1498_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_99_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_98_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_97_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_96_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j1b' due to the length limit 80 +INFO: [RTGEN 206-104] Estimated max fanout for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s' is 13824 from HDL expression: (1'b1 == ap_CS_fsm_state1) +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 10.21 seconds. CPU system time: 0.97 seconds. Elapsed time: 11.19 seconds; current allocated memory: 3.674 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_w23_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_w23_Rj2b' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' is 27648 from HDL expression: (do_init_reg_3523 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 128 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_33s_33_1_1': 127 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 128 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 12 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_w23_Rj2b' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 2.38 seconds. CPU system time: 0.17 seconds. Elapsed time: 2.58 seconds; current allocated memory: 3.753 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3846' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3857' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3868' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3879' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3890' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3901' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3912' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3923' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3934' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3945' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3956' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3967' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3978' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3989' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4000' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4011' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4022' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4033' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4044' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4055' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4066' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4077' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4088' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4099' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4110' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4121' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4363' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4847' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4968' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5089' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5331' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5452' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5936' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6057' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6178' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6299' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6420' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_94' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_83' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_72' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_61' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_50' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_39' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3928' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3929' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3930' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3931' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3932' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3933' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3935' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3936' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3937' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3938' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3939' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3940' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3941' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3942' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3943' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3944' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3839' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3946' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3840' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3947' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3841' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3948' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3842' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3949' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3843' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3950' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3844' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3951' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3845' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3952' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3847' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3953' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3848' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3954' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3849' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3955' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3850' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3957' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3851' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3958' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3852' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3959' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3853' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3960' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3854' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3961' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3855' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3962' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3856' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3963' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3858' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3964' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3859' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3965' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3860' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3966' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3861' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3968' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3862' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3969' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3863' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3970' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3864' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3971' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3865' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3972' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3866' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3973' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3867' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3974' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3869' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3975' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3870' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3976' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3871' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3977' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3872' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3979' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3873' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3980' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3874' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3981' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3875' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3982' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3876' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3983' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3877' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3984' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3878' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3985' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3880' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3986' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3881' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3987' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3882' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3988' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3883' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3990' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3884' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3991' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3885' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3992' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3886' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3993' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3887' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3994' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3888' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3995' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3889' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3996' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3891' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3997' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3892' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3998' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3893' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3894' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4001' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3895' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4002' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3896' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4003' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3897' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4004' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3898' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4005' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3899' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4006' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3900' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4007' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3902' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4008' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3903' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4009' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3904' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4010' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3905' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4012' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3906' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4013' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3907' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4014' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3908' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4015' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3909' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4016' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3910' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4017' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3911' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4018' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3913' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4019' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3914' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4020' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3915' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4021' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3916' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4023' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3917' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4024' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3918' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4025' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3919' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4026' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3920' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4027' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3921' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4028' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3922' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4029' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3924' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4030' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3925' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4031' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3926' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4032' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3927' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4319' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4330' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4341' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4352' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4374' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4385' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4396' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4407' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4418' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4429' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4440' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4451' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4462' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5848' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5859' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5870' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5881' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5892' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5903' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5914' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5925' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5947' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5958' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5969' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5980' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5991' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6002' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6013' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4858' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6024' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4869' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6035' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4880' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6046' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4891' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6068' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4902' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6079' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4913' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6090' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4924' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6101' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4935' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6112' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4946' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6123' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4957' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6134' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4979' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4990' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5001' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5012' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6189' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5023' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5034' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5045' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5056' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5067' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5078' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5100' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5111' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5122' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6288' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5133' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6310' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6321' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6332' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6343' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5177' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6354' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5188' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6365' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6376' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6387' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6398' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6409' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6431' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6442' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6453' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5287' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6464' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5298' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5309' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5320' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5342' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5353' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5364' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5375' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5386' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5397' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5408' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5419' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5430' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5441' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5463' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4034' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4035' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4036' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4037' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4038' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4039' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4040' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4041' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4042' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4043' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4045' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4046' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4047' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4048' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4049' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4050' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4051' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4052' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4053' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4054' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4056' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4057' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4058' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4059' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4060' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4061' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4062' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4063' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4064' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4065' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4067' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4068' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4069' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4070' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4071' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4072' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4073' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4074' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4075' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4076' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4078' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4079' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4080' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4081' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4082' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4083' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4084' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4085' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4086' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4087' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4089' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4090' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4091' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4092' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4093' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4094' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4095' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4096' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4097' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4098' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4100' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4101' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4102' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4103' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4104' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4105' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4106' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4107' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4108' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4109' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4111' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4112' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4113' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4114' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4115' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4116' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4117' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4118' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4119' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4120' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4132' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4187' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4297' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4308' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_99' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_98' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_97' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_96' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_95' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_93' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_92' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_91' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_90' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_89' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_88' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_87' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_86' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_85' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_84' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_82' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_81' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_80' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_79' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_78' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_77' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_76' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_75' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_74' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_73' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_71' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_70' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_69' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_68' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_67' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_66' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_65' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_64' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_63' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_62' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_60' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_59' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_58' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_57' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_56' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_55' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_54' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_53' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_52' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_51' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_49' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_48' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_47' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_46' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_45' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_44' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_43' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_42' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_41' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_40' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_38' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_37' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_36' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_35' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_34' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_33' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_32' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_31' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_30' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_12' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 37.1 seconds. CPU system time: 3.61 seconds. Elapsed time: 40.76 seconds; current allocated memory: 3.889 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.63 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.68 seconds; current allocated memory: 3.907 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.48 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.54 seconds; current allocated memory: 3.920 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.34 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.37 seconds; current allocated memory: 3.926 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.29 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.33 seconds; current allocated memory: 3.929 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.33 seconds; current allocated memory: 3.931 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.25 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.27 seconds; current allocated memory: 3.932 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1007_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1039_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1008_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1040_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1019_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1051_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1030_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1062_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1033_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1065_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1034_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1066_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2keb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1035_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1067_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1036_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2khb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1068_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1037_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1069_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1038_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2klb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1070_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1009_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2knb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1041_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1010_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1042_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1011_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2krb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1043_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2ksb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1012_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2ktb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1044_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1013_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1045_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1014_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1046_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1015_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1047_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1016_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1048_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1017_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1049_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1018_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1050_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1020_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1052_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1021_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1053_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1022_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1054_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1023_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1055_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1024_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1056_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1025_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1057_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1026_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1058_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1027_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1059_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1028_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1060_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1029_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1061_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1031_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1063_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1032_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1064_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k4b' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.03 seconds. CPU system time: 0.46 seconds. Elapsed time: 4.49 seconds; current allocated memory: 3.933 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s_w25_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s_w25_Rk5b' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s' is 9216 from HDL expression: (do_init_reg_1343 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 63 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 64 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 4 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s_w25_Rk5b' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.1 seconds. CPU system time: 0.08 seconds. Elapsed time: 1.19 seconds; current allocated memory: 3.949 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5327' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_79' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5328' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_78' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5329' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_77' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5330' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_76' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5332' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_75' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5333' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_74' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5334' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_73' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5335' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_72' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5336' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_71' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5337' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_70' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5338' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5096' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5339' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5108' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5340' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5120' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5341' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5132' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5343' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5344' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5345' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5346' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5181' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5347' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5348' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5349' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5350' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5351' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5352' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5354' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5355' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5356' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5290' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5357' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5302' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5358' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5314' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5359' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5324' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5360' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5325' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5361' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5326' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5130' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5398' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5131' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5399' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5134' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5400' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5135' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5401' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5136' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5097' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5137' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5098' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5099' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5101' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5102' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5103' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5104' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5105' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5106' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5107' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5109' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5110' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5112' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5113' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5114' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5115' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5116' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5117' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5118' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5119' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5121' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5123' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5124' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5125' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5126' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5127' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5128' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5129' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5362' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5363' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5365' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5366' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5367' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5368' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5369' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5370' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5371' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5372' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5373' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5374' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5376' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5377' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5378' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5379' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5380' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5381' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5382' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5383' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5384' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5385' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5387' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5388' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5389' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5390' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5391' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5392' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5393' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5394' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5395' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5396' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5178' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5179' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5180' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5182' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5183' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5184' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5185' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5186' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5187' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5189' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5190' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5191' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5192' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5288' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5289' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5291' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5292' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5293' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5294' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5295' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5296' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5297' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5299' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5300' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5301' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5303' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5304' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5305' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5306' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5307' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5308' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5310' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5311' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5312' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5313' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5315' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5316' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5317' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5318' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5319' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5321' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5322' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5323' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_4' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 13.91 seconds. CPU system time: 1.26 seconds. Elapsed time: 15.18 seconds; current allocated memory: 3.988 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.4 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.45 seconds; current allocated memory: 3.997 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.39 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.44 seconds; current allocated memory: 4.019 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.36 seconds; current allocated memory: 4.022 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' pipeline 'ConcatLoopHeight_ConcatLoopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.33 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.37 seconds; current allocated memory: 4.027 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.28 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.29 seconds; current allocated memory: 4.029 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.31 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.33 seconds; current allocated memory: 4.029 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.34 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.37 seconds; current allocated memory: 4.030 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.34 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.36 seconds; current allocated memory: 4.032 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.26 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.3 seconds; current allocated memory: 4.034 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1135_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2k6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1183_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2k7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1136_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2k8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1184_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2k9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1147_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1195_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1158_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1206_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2ldb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1169_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2leb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1217_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1178_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1226_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1179_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1227_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2ljb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1180_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1228_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2llb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1181_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1229_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1182_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1230_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1137_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1185_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1138_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1186_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2ltb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1139_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1187_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1140_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1188_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1141_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1189_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1142_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1190_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1143_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1191_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1144_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1192_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1145_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1193_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1146_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1194_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1148_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1196_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1149_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1197_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1150_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1198_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1151_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1199_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1152_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1200_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1153_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1201_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1154_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1202_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1155_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1203_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1156_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1204_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1157_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1205_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1159_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1207_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1160_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1208_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1161_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1209_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1162_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1210_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1163_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1211_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1164_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2meb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1212_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1165_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1213_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1166_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1214_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1167_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1215_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mlb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1168_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1216_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1170_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1218_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1171_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1219_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1172_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2msb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1220_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mtb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1173_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1221_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1174_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1222_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1175_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2myb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1223_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mzc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1176_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mAc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1224_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mBc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1177_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mCc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1225_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mDc' due to the length limit 80 +INFO: [RTGEN 206-104] Estimated max fanout for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s' is 6912 from HDL expression: (1'b1 == ap_CS_fsm_state1) +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 5.79 seconds. CPU system time: 0.63 seconds. Elapsed time: 6.42 seconds; current allocated memory: 4.035 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_w29_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_w29_RmEc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' is 13824 from HDL expression: (do_init_reg_1475 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 32 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_33s_33_1_1': 31 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_8s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 32 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 6 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_w29_RmEc' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.34 seconds. CPU system time: 0.11 seconds. Elapsed time: 1.45 seconds; current allocated memory: 4.058 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6115' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_59' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6116' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_58' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6117' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_57' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6118' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_56' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6119' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_55' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6120' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_54' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6121' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_53' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6122' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_52' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6124' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_51' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6125' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_50' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6126' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6127' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6128' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6129' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6130' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6131' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6132' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6133' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6135' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6136' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6137' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5841' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5853' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5865' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5877' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5889' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5901' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5913' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5926' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5938' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5950' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5962' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5974' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5986' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5998' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6010' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6022' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6034' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6047' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6059' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6071' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6083' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6095' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6107' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6110' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6111' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6113' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6114' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5839' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5840' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5842' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5843' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5844' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5845' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5846' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5847' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5849' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5850' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5851' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5852' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5854' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5855' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5856' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5857' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5858' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5860' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5861' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5862' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5863' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5864' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5866' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5867' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5868' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5869' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5871' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5872' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5873' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5874' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5875' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5876' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5994' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5935' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5995' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5937' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5996' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5939' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5997' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5940' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5941' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6000' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5942' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6001' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5943' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6003' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5944' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6004' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5945' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6005' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5946' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6006' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5948' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6007' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5949' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6008' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5951' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6009' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5952' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6011' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5953' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6012' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5954' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6014' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5955' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6015' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5956' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6016' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5957' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6017' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5959' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6018' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5960' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6019' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5961' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6020' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5963' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6021' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5964' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6023' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5965' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6025' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5966' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6026' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5967' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6027' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5968' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6028' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5970' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6029' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5971' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6030' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5972' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6031' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5973' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6032' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5975' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6033' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5976' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6036' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5977' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6037' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5978' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6038' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5979' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6039' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5981' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6040' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5982' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6041' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5983' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6042' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5984' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6043' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5985' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6044' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5987' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6045' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5988' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6048' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5989' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6049' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5990' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6050' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5992' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6051' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5993' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5878' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5879' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5880' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5882' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5883' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5884' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5885' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5886' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5887' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5888' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5890' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5891' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5893' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5894' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5895' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5896' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5897' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5898' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5899' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5900' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5902' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5904' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5905' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5906' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5907' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5908' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5909' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5910' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5911' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5912' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5915' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5916' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5917' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5918' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5919' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5920' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5921' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5922' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5923' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5924' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5927' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5928' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5929' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5930' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5931' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5932' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5933' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5934' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6052' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6053' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6054' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6055' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6056' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6058' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6060' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6061' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6062' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6063' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6064' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6065' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6066' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6067' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6069' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6070' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6072' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6073' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6074' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6075' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6076' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6077' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6078' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6080' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6081' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6082' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6084' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6085' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6086' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6087' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6088' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6089' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6091' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6092' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6093' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6094' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6096' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6097' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6098' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6099' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6100' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6102' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6103' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6104' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6105' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6106' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6108' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6109' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_1' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 21.81 seconds. CPU system time: 2.14 seconds. Elapsed time: 23.99 seconds; current allocated memory: 4.110 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.45 seconds. CPU system time: 0.06 seconds. Elapsed time: 0.52 seconds; current allocated memory: 4.117 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.35 seconds. CPU system time: 0.06 seconds. Elapsed time: 0.42 seconds; current allocated memory: 4.140 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.37 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.38 seconds; current allocated memory: 4.143 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.34 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.38 seconds; current allocated memory: 4.145 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.35 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.39 seconds; current allocated memory: 4.147 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.3 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.32 seconds; current allocated memory: 4.149 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_831_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mFc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_847_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mGc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_832_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mHc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_848_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mIc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_839_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mJc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_855_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mKc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_840_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mLc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_856_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mMc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_841_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mNc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_857_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mOc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_842_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mPc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_858_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mQc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_843_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mRc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_859_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mSc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_844_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mTc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_860_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mUc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_845_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mVc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_861_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mWc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_846_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mXc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_862_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mYc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_833_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mZc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_849_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m0c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_834_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m1c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_850_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m2c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_835_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m3c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_851_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m4c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_836_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m5c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_852_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m6c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_837_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m7c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_853_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m8c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_838_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m9c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_854_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2nac' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.85 seconds. CPU system time: 0.17 seconds. Elapsed time: 2.02 seconds; current allocated memory: 4.150 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s_w31_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s_w31_Rnbc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 15 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 16 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 2 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s_w31_Rnbc' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.81 seconds. CPU system time: 0.07 seconds. Elapsed time: 0.89 seconds; current allocated memory: 4.154 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4324' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4325' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4326' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4327' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4328' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4329' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4331' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4332' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4333' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4334' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4335' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4336' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4337' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4293' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4338' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4305' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4339' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4317' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4340' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4323' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4377' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4359' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4378' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4360' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4379' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4361' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4380' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4362' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4381' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4364' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4382' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4365' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4383' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4366' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4384' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4367' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4386' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4368' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4387' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4369' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4388' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4370' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4389' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4371' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4390' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4372' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4391' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4373' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4392' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4375' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4393' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4376' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4412' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4413' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4287' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4414' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4288' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4415' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4289' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4290' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4291' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4292' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4294' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4295' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4296' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4298' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4299' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4300' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4301' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4302' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4342' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4343' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4344' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4345' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4346' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4347' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4348' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4349' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4350' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4351' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4353' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4354' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4355' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4356' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4357' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4358' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4394' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4395' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4397' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4398' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4399' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4400' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4401' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4402' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4403' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4404' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4405' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4406' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4408' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4409' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4410' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4411' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4303' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4304' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4306' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4307' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4309' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4310' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4311' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4312' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4313' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4314' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4315' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4316' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4318' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4320' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4321' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4322' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_2' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 7.73 seconds. CPU system time: 0.7 seconds. Elapsed time: 8.43 seconds; current allocated memory: 4.167 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.38 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.4 seconds; current allocated memory: 4.175 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.36 seconds; current allocated memory: 4.189 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.36 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.39 seconds; current allocated memory: 4.191 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' pipeline 'ConcatLoopHeight_ConcatLoopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.4 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.43 seconds; current allocated memory: 4.196 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.31 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.33 seconds; current allocated memory: 4.199 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.35 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.37 seconds; current allocated memory: 4.200 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.38 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.41 seconds; current allocated memory: 4.200 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.39 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.42 seconds; current allocated memory: 4.204 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.31 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.32 seconds; current allocated memory: 4.207 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_895_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2ncc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_919_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2ndc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_896_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nec' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_920_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nfc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_907_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2ngc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_931_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nhc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_912_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nic' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_936_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2njc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_913_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nkc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_937_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nlc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_914_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nmc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_938_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nnc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_915_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2noc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_939_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2npc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_916_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nqc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_940_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nrc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_917_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nsc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_941_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2ntc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_918_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nuc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_942_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nvc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_897_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nwc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_921_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nxc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_898_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nyc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_922_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nzc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_899_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nAc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_923_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nBc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_900_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nCc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nCc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nCc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_924_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nDc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nDc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nDc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_901_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nEc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nEc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nEc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_925_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nFc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nFc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nFc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_902_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nGc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nGc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nGc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_926_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nHc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nHc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nHc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_903_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nIc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nIc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nIc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_927_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nJc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nJc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nJc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_904_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nKc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nKc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nKc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_928_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nLc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nLc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nLc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_905_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nMc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nMc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nMc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_929_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nNc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nNc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nNc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_906_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nOc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nOc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nOc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_930_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nPc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nPc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nPc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_908_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nQc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nQc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nQc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_932_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nRc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nRc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nRc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_909_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nSc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nSc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nSc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_933_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nTc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nTc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nTc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_910_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nUc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nUc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nUc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_934_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nVc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nVc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nVc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_911_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nWc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nWc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nWc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_935_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nXc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nXc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nXc_x' due to conflict. +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 3.76 seconds. CPU system time: 0.34 seconds. Elapsed time: 4.1 seconds; current allocated memory: 4.208 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_w35_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_w35_RnYc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' is 6912 from HDL expression: (do_init_reg_739 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 8 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_33s_33_1_1': 7 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 8 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 3 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_w35_RnYc' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1 seconds. CPU system time: 0.1 seconds. Elapsed time: 1.1 seconds; current allocated memory: 4.213 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_99' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_98' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_97' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_96' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_95' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_94' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_93' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_92' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_91' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_90' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_6' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 11.59 seconds. CPU system time: 1.16 seconds. Elapsed time: 12.75 seconds; current allocated memory: 4.231 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.42 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.44 seconds; current allocated memory: 4.237 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.39 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.44 seconds; current allocated memory: 4.259 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.39 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.4 seconds; current allocated memory: 4.261 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.39 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.43 seconds; current allocated memory: 4.262 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.41 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.43 seconds; current allocated memory: 4.266 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.31 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.33 seconds; current allocated memory: 4.268 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1391_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dnZc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1399_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn0c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1392_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn1c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1400_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn2c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1393_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn3c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1401_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn4c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1394_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn5c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1402_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn6c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1395_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn7c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1403_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn8c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1396_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn9c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1404_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2doac' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1397_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dobc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1405_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2docc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1398_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dodc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1406_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2doec' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.13 seconds. CPU system time: 0.08 seconds. Elapsed time: 1.21 seconds; current allocated memory: 4.269 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s_w37_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s_w37_Rofc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_38s_38_1_1': 7 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_31s_31_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s_w37_Rofc' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.68 seconds. CPU system time: 0.07 seconds. Elapsed time: 0.75 seconds; current allocated memory: 4.272 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_14' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.28 seconds. CPU system time: 0.34 seconds. Elapsed time: 4.64 seconds; current allocated memory: 4.278 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.36 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.37 seconds; current allocated memory: 4.287 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.38 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.4 seconds; current allocated memory: 4.289 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_12s_30s_30_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_17_3_12_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_17_3_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.52 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.56 seconds; current allocated memory: 4.291 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.31 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.35 seconds; current allocated memory: 4.293 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s_sigmoid_table_ROM_AUTO_1R' to 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s_sigmoid_table_Rogc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s' pipeline 'SigmoidActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s_sigmoid_table_Rogc' using auto ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.49 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.53 seconds; current allocated memory: 4.294 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'myproject' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low. +INFO: [RTGEN 206-500] Setting interface mode on port 'myproject/x' to 'axis' (register, both mode). +INFO: [RTGEN 206-500] Setting interface mode on port 'myproject/layer40_out' to 'axis' (register, both mode). +INFO: [RTGEN 206-500] Setting interface mode on function 'myproject' to 'ap_ctrl_hs'. +INFO: [SYN 201-210] Renamed object name 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_U0' to 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4ohc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_U0' to 'start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6oic' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_U0' to 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4ojc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_U0' to 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7okc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_U0' to 'start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configolc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_U0' to 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10omc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_U0' to 'start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384onc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13ooc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15opc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_U0' to 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18oqc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_U0' to 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20orc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24osc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26otc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_U0' to 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30ouc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_U0' to 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32ovc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_U0' to 'start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3owc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_U0' to 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config5oxc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_U0' to 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37oyc' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'myproject'. +INFO: [RTMG 210-285] Implementing FIFO 'layer44_out_U(myproject_fifo_w16_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer2_out_U(myproject_fifo_w296_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer3_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer45_out_U(myproject_fifo_w128_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer4_out_U(myproject_fifo_w320_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer5_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer41_cpy1_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer41_cpy2_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer6_out_U(myproject_fifo_w128_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer46_out_U(myproject_fifo_w128_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer7_out_U(myproject_fifo_w640_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer8_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer47_out_U(myproject_fifo_w256_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer9_out_U(myproject_fifo_w656_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer10_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer42_cpy1_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer42_cpy2_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer11_out_U(myproject_fifo_w256_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer48_out_U(myproject_fifo_w256_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer12_out_U(myproject_fifo_w1312_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer13_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer49_out_U(myproject_fifo_w512_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer14_out_U(myproject_fifo_w1344_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer15_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer43_cpy1_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer43_cpy2_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer16_out_U(myproject_fifo_w512_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer50_out_U(myproject_fifo_w512_d100_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer17_out_U(myproject_fifo_w2688_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer18_out_U(myproject_fifo_w1024_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer51_out_U(myproject_fifo_w1024_d100_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer19_out_U(myproject_fifo_w2752_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer20_out_U(myproject_fifo_w1024_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer21_out_U(myproject_fifo_w1024_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer22_out_U(myproject_fifo_w1536_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer52_out_U(myproject_fifo_w1536_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer23_out_U(myproject_fifo_w1376_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer24_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer53_out_U(myproject_fifo_w512_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer25_out_U(myproject_fifo_w1344_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer26_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer27_out_U(myproject_fifo_w512_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer28_out_U(myproject_fifo_w768_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer54_out_U(myproject_fifo_w768_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer29_out_U(myproject_fifo_w672_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer30_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer55_out_U(myproject_fifo_w256_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer31_out_U(myproject_fifo_w656_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer32_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer33_out_U(myproject_fifo_w256_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer34_out_U(myproject_fifo_w384_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer56_out_U(myproject_fifo_w384_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer35_out_U(myproject_fifo_w328_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer36_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer57_out_U(myproject_fifo_w128_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer37_out_U(myproject_fifo_w320_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer38_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer39_out_U(myproject_fifo_w36_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_U0_U(myproject_start_for_conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4ohc_U(myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4ohc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_U0_U(myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0_U(myproject_start_for_clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6oic_U(myproject_start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6oic)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0_U(myproject_start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4ojc_U(myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4ojc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7okc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7okc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_U0_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configolc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configolc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10omc_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10omc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384onc_U(myproject_start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384onc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0_U(myproject_start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0_U(myproject_start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13ooc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13ooc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15opc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15opc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0_U(myproject_start_for_clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_U0_U(myproject_start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0_U(myproject_start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18oqc_U(myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18oqc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20orc_U(myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20orc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_U0_U(myproject_start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24osc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24osc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26otc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26otc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_U0_U(myproject_start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30ouc_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30ouc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32ovc_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32ovc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_U0_U(myproject_start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3owc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3owc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config5oxc_U(myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config5oxc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37oyc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37oyc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_U0_U(myproject_start_for_pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_U0_U(myproject_start_for_sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_U0)' using Shift Registers. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 7.43 seconds. CPU system time: 0.71 seconds. Elapsed time: 8.16 seconds; current allocated memory: 4.296 GB. +INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 2.26 seconds. CPU system time: 0.26 seconds. Elapsed time: 2.56 seconds; current allocated memory: 4.300 GB. +INFO: [HLS 200-111] Finished Updating report files: CPU user time: 17.88 seconds. CPU system time: 0.14 seconds. Elapsed time: 18.04 seconds; current allocated memory: 4.431 GB. +INFO: [VHDL 208-304] Generating VHDL RTL for myproject. +INFO: [VLOG 209-307] Generating Verilog RTL for myproject. +INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were NOT satisfied. +INFO: [HLS 200-789] **** Estimated Fmax: 226.71 MHz +INFO: [HLS 200-2161] Finished Command csynth_design Elapsed time: 00:18:16; Allocated memory: 4.184 GB. +***** C/RTL SYNTHESIS COMPLETED IN 0h18m16s ***** +INFO: [HLS 200-112] Total CPU user time: 1069.68 seconds. Total CPU system time: 38.58 seconds. Total elapsed time: 1100.27 seconds; peak allocated memory: 4.454 GB. +INFO: [vitis-run 60-791] Total elapsed time: 0h 18m 22s +INFO: [vitis-run 60-1662] Stopping dispatch session having empty uuid. diff --git a/logs/hls_run_tcl_184335.backup.log b/logs/hls_run_tcl_184335.backup.log new file mode 100644 index 0000000000000000000000000000000000000000..5a4df45b50fbb97940d5a06c50c38f11bf426e31 --- /dev/null +++ b/logs/hls_run_tcl_184335.backup.log @@ -0,0 +1,10260 @@ +INFO: [vitis-run 82-31] Launching vitis_hls: vitis_hls -nolog -run tcl -f /home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl -work_dir /home/ubuntu/lithobench/hls4ml_mini_unet + +****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2024.1 (64-bit) + **** SW Build 5069499 on May 21 2024 + **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 + **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 + **** Start of session at: Sat Apr 4 08:25:33 2026 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. + +source /opt/Xilinx/Vitis_HLS/2024.1/scripts/vitis_hls/hls.tcl -notrace +INFO: [HLS 200-10] For user 'ubuntu' on host 'ip-172-31-42-252.ec2.internal' (Linux_x86_64 version 5.15.0-1084-aws) on Sat Apr 04 08:25:35 UTC 2026 +INFO: [HLS 200-10] On os Ubuntu 20.04.6 LTS +INFO: [HLS 200-10] In directory '/home/ubuntu/lithobench/hls4ml_mini_unet' +Sourcing Tcl script '/home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl' +INFO: [HLS 200-1510] Running: open_project myproject_prj +INFO: [HLS 200-10] Opening project '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj'. +INFO: [HLS 200-1510] Running: set_top myproject +INFO: [HLS 200-1510] Running: add_files firmware/myproject.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding design file 'firmware/myproject.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb myproject_test.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding test bench file 'myproject_test.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb firmware/weights +INFO: [HLS 200-10] Adding test bench file 'firmware/weights' to the project +INFO: [HLS 200-1510] Running: add_files -tb tb_data +INFO: [HLS 200-10] Adding test bench file 'tb_data' to the project +INFO: [HLS 200-1510] Running: open_solution solution1 +INFO: [HLS 200-10] Opening solution '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1'. +INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. +INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 1.35ns. +INFO: [HLS 200-1611] Setting target device to 'xcvu47p-fsvh2892-2L-e' +INFO: [HLS 200-1505] Using flow_target 'vivado' +Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1505.html +INFO: [HLS 200-1464] Running solution command: config_compile -name_max_length=80 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_compile -complex-mul-dsp=0 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_compile -unsafe_math_optimizations=0 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_schedule -enable_dsp_full_reg=0 +INFO: [HLS 200-1464] Running solution command: config_array_partition -complete_threshold=4096 +INFO: [XFORM 203-102] Size-based automatic array partition enabled: cut-off elements per dimension is 4096. +INFO: [HLS 200-1510] Running: config_array_partition -maximum_size 4096 +ERROR: [HLS 200-101] config_array_partition: Unknown option '-maximum_size'. +ERROR: [HLS 200-101] config_array_partition: Unknown option '4096'. +SYNTAX + config_array_partition [OPTIONS] + -auto_partition_threshold *** DEPRECATED*** + -auto_promotion_threshold *** DEPRECATED*** + -complete_threshold + -throughput_driven + +SEE ALSO + INI: syn.array_partition.complete_threshold syn.array_partition.throughput_driven + docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1399-vitis-hls&resourceid=vyw1583260160301.html + +INFO: [HLS 200-1510] Running: config_compile -name_max_length 80 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: set_part xcvu47p-fsvh2892-2L-e +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: config_schedule -enable_dsp_full_reg=false +INFO: [HLS 200-1510] Running: create_clock -period 5 -name default +INFO: [HLS 200-1510] Running: set_clock_uncertainty 27% default +***** C/RTL SYNTHESIS ***** +INFO: [HLS 200-1510] Running: csynth_design +INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0.08 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.11 seconds; current allocated memory: 276.828 MB. +INFO: [HLS 200-10] Analyzing design file 'firmware/myproject.cpp' ... +WARNING: [HLS 207-5570] unexpected pragma argument 'softmax', expects function/operation (firmware/nnet_utils/nnet_activation.h:402:36) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:33:9) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:107:9) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:189:9) +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:234:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:234:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:240:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:240:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:250:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:250:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:256:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:256:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:266:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:266:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:272:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:272:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:282:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:282:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:288:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:288:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:298:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:298:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:304:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:304:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:314:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:314:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:320:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:320:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:330:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:330:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:336:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:336:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:340:100) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:340:105) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 200-471] Dataflow form checks found 30 issue(s) in file firmware/myproject.cpp +Resolution: For help on HLS 200-471 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-471.html +WARNING: [HLS 207-5292] unused parameter 'keep' (firmware/nnet_utils/nnet_helpers.h:285:99) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:14:36) +WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:15:36) +WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:16:44) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:24:24) +WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:25:24) +WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:26:32) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:33:30) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:33:58) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:34:51) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:35:49) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:42:30) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:42:58) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:43:51) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:44:49) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:51:29) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:51:80) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:52:50) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:53:48) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_code_gen.h:16:39) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_code_gen.h:17:38) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_code_gen.h:18:60) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_code_gen.h:19:58) +WARNING: [HLS 207-5584] there are more than one pragma inline in the function scope, ignore the pragma (/opt/Xilinx/Vitis_HLS/2024.1/common/technology/autopilot/ap_shift_reg.h:47:9) +INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 36.65 seconds. CPU system time: 2.23 seconds. Elapsed time: 39.8 seconds; current allocated memory: 287.934 MB. +INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target. +INFO: [HLS 200-1995] There were 28,092 instructions in the design after the 'Compile/Link' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 281,564 instructions in the design after the 'Unroll/Inline' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 126,649 instructions in the design after the 'Unroll/Inline (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 101,403 instructions in the design after the 'Unroll/Inline (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 52,850 instructions in the design after the 'Unroll/Inline (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 40,314 instructions in the design after the 'Array/Struct (step 1)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 38,449 instructions in the design after the 'Array/Struct (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 39,344 instructions in the design after the 'Array/Struct (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 94,283 instructions in the design after the 'Array/Struct (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 81,528 instructions in the design after the 'Array/Struct (step 5)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 83,186 instructions in the design after the 'Performance (step 1)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 193,957 instructions in the design after the 'Performance (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 191,271 instructions in the design after the 'Performance (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 191,271 instructions in the design after the 'Performance (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 152,447 instructions in the design after the 'HW Transforms' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 144,708 instructions in the design after the 'HW Transforms (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>' (firmware/nnet_utils/nnet_sepconv_stream.h:103:9) +WARNING: [HLS 214-273] In function 'void nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config58_mult::weight_t*, config58_mult::bias_t*)', Pragma conflict happens on 'INLINE' and 'FUNCTION_INSTANTIATE' pragmas: same function (firmware/nnet_utils/nnet_dense_resource.h:15:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 1u>, config2>(nnet::array, 1u>::value_type (*) [config2::n_chan], nnet::array, 1u>::value_type*)' into 'void nnet::shift_line_buffer, 1u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], nnet::array, 1u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, config2_mult::weight_t*, config2_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*) (.55)' into 'void nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config4>(nnet::array, 8u>::value_type (*) [config4::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config4_mult::weight_t*, config4_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 8u>, config4>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*) (.54)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config6>(nnet::array, 8u>::value_type (*) [config6::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::Op_max >::operator()(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>) (.36)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' (firmware/nnet_utils/nnet_common.h:44:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:15) +INFO: [HLS 214-131] Inlining function 'nnet::Op_max >::operator()(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>) (.36)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:12) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:44) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config6>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.52)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config6>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.52)' into 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 8u>::operator[](unsigned long) (.51)' into 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' into 'void nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config7>(nnet::array, 8u>::value_type (*) [config7::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config7_mult::weight_t*, config7_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 16u>, config7>(hls::stream, 8u>, 0>&, hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*) (.48)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>(hls::stream, 8u>, 0>&, hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config9>(nnet::array, 16u>::value_type (*) [config9::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config9_mult::weight_t*, config9_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 16u>, config9>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*) (.47)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config11>(nnet::array, 16u>::value_type (*) [config11::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config11>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.45)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config11>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.45)' into 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 16u>::operator[](unsigned long) (.44)' into 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' into 'void nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config12>(nnet::array, 16u>::value_type (*) [config12::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config12_mult::weight_t*, config12_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 32u>, config12>(hls::stream, 16u>, 0>&, hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*) (.41)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>(hls::stream, 16u>, 0>&, hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config14>(nnet::array, 32u>::value_type (*) [config14::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config14_mult::weight_t*, config14_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 32u>, config14>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*) (.40)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config16>(nnet::array, 32u>::value_type (*) [config16::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config16>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.34)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config16>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.34)' into 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 32u>::operator[](unsigned long) (.33)' into 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' into 'void nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config17>(nnet::array, 32u>::value_type (*) [config17::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config17_mult::weight_t*, config17_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 64u>, config17>(hls::stream, 32u>, 0>&, hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*) (.30)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>(hls::stream, 32u>, 0>&, hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 64u>, config19>(nnet::array, 64u>::value_type (*) [config19::n_chan], nnet::array, 64u>::value_type*)' into 'void nnet::shift_line_buffer, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], nnet::array, 64u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config19_mult::weight_t*, config19_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 64u>, nnet::array, 64u>, config19>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*) (.26)' into 'void nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 96u>, config23>(nnet::array, 96u>::value_type (*) [config23::n_chan], nnet::array, 96u>::value_type*)' into 'void nnet::shift_line_buffer, 96u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], nnet::array, 96u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config23_mult::weight_t*, config23_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 96u>, nnet::array, 32u>, config23>(hls::stream, 96u>, 0>&, hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*) (.23)' into 'void nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>(hls::stream, 96u>, 0>&, hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config25>(nnet::array, 32u>::value_type (*) [config25::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config25_mult::weight_t*, config25_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 32u>, config25>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*) (.19)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 48u>, config29>(nnet::array, 48u>::value_type (*) [config29::n_chan], nnet::array, 48u>::value_type*)' into 'void nnet::shift_line_buffer, 48u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], nnet::array, 48u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config29_mult::weight_t*, config29_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 48u>, nnet::array, 16u>, config29>(hls::stream, 48u>, 0>&, hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*) (.16)' into 'void nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>(hls::stream, 48u>, 0>&, hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config31>(nnet::array, 16u>::value_type (*) [config31::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config31_mult::weight_t*, config31_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 16u>, config31>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*) (.12)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 24u>, config35>(nnet::array, 24u>::value_type (*) [config35::n_chan], nnet::array, 24u>::value_type*)' into 'void nnet::shift_line_buffer, 24u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], nnet::array, 24u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config35_mult::weight_t*, config35_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 24u>, nnet::array, 8u>, config35>(hls::stream, 24u>, 0>&, hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*) (.9)' into 'void nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>(hls::stream, 24u>, 0>&, hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config37>(nnet::array, 8u>::value_type (*) [config37::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config37_mult::weight_t*, config37_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 8u>, config37>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*) (.5)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config58_mult::weight_t*, config58_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const (.4)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:100:13) +INFO: [HLS 214-131] Inlining function 'nnet::array, 1u>::operator[](unsigned long) (.2)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:110:2) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.3)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:104:2) +INFO: [HLS 214-131] Inlining function 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' into 'void nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>(hls::stream, 8u>, 0>&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv2d_stream.h:86:21) +INFO: [HLS 214-291] Loop 'SigmoidPackLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_activation_stream.h:88:9) +INFO: [HLS 214-291] Loop 'MultLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_dense_resource.h:55:9) +INFO: [HLS 214-291] Loop 'ReLUPackLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_activation_stream.h:49:9) +INFO: [HLS 214-291] Loop 'KernelPushHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:205:5) +INFO: [HLS 214-291] Loop 'KernelPushChannel' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:208:9) +INFO: [HLS 214-291] Loop 'KernelShiftWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:189:5) +INFO: [HLS 214-291] Loop 'KernelShiftHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:192:9) +INFO: [HLS 214-291] Loop 'KernelShiftChannel' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:194:13) +INFO: [HLS 214-291] Loop 'LineBufferDataIn' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:236:5) +INFO: [HLS 214-291] Loop 'LineBufferShift' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:239:9) +INFO: [HLS 214-291] Loop 'UpdateBuffer' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:228:5) +INFO: [HLS 214-291] Loop 'ConcatPackInput1' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_merge_stream.h:245:13) +INFO: [HLS 214-291] Loop 'ConcatPackInput2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_merge_stream.h:251:13) +INFO: [HLS 214-291] Loop 'ImageWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:22:9) +INFO: [HLS 214-291] Loop 'ImageChan' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:28:13) +INFO: [HLS 214-291] Loop 'ResizeHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:36:9) +INFO: [HLS 214-291] Loop 'ImageWidth2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:40:13) +INFO: [HLS 214-291] Loop 'ResizeWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:44:17) +INFO: [HLS 214-291] Loop 'ResizeChan' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:51:21) +INFO: [HLS 214-291] Loop 'FiltLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_pooling_stream.h:57:9) +INFO: [HLS 214-291] Loop 'PoolLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_pooling_stream.h:62:13) +INFO: [HLS 214-291] Loop 'ClonePack' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_stream.h:32:9) +INFO: [HLS 214-291] Loop 'MultLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_dense_resource.h:142:9) +INFO: [HLS 214-186] Unrolling loop 'SigmoidPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:88:9) in function 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>' completely with a factor of 1 (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-186] Unrolling loop 'InitData' (firmware/nnet_utils/nnet_sepconv_stream.h:98:5) in function 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>' completely with a factor of 8 (firmware/nnet_utils/nnet_sepconv2d_stream.h:58:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_sepconv_stream.h:108:5) in function 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>' completely with a factor of 1 (firmware/nnet_utils/nnet_sepconv2d_stream.h:58:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config38>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config37>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config36>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 24 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 24u>, config35>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>' completely with a factor of 24 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' completely with a factor of 16 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' completely with a factor of 8 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config32>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config31>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config30>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 96 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 48u>, config29>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>' completely with a factor of 48 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' completely with a factor of 32 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' completely with a factor of 16 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config26>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 128 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config25>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config24>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 384 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 96u>, config23>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>' completely with a factor of 96 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' completely with a factor of 64 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' completely with a factor of 32 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 8 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 64 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 8 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 64 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 64u>, nnet::array, 64u>, relu_config20>' completely with a factor of 64 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 576 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 64u>, config19>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 64u>, nnet::array, 64u>, relu_config18>' completely with a factor of 64 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 256 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config17>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config16>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>' completely with a factor of 32 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config15>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 128 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config14>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config13>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config12>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config11>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>' completely with a factor of 16 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config10>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config9>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config8>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config7>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config6>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>' completely with a factor of 8 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config5>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config4>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config3>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 1u>, config2>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>' completely with a factor of 1 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 1u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], nnet::array, 1u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(config2_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, config2_mult::weight_t*, config2_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config3>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config3>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(config4_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config4_mult::weight_t*, config4_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config5>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config5>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(config7_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config7_mult::weight_t*, config7_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config8>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config8>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(config9_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config9_mult::weight_t*, config9_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config10>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config10>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(config12_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config12_mult::weight_t*, config12_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config13>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config13>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(config14_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config14_mult::weight_t*, config14_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config15>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config15>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config18>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config18>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], nnet::array, 64u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config20>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config20>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 64u>, config21>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 96u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], nnet::array, 96u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(config23_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config23_mult::weight_t*, config23_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config24>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config24>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(config25_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config25_mult::weight_t*, config25_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config26>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config26>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 32u>, config27>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 48u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], nnet::array, 48u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(config29_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config29_mult::weight_t*, config29_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config30>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config30>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(config31_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config31_mult::weight_t*, config31_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config32>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config32>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 16u>, config33>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 24u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], nnet::array, 24u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(config35_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config35_mult::weight_t*, config35_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config36>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config36>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(config37_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config37_mult::weight_t*, config37_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config38>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config38>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(config58_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config58_mult::weight_t*, config58_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj1EEENS1_IS2_ILi37ELi17ELS3_5ELS4_3ELi0EELj8EEE7config2EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEES6_7config6EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to 'b2': Complete partitioning on dimension 1. (firmware/weights/b2.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b4': Complete partitioning on dimension 1. (firmware/weights/b4.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b7': Complete partitioning on dimension 1. (firmware/weights/b7.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b9': Complete partitioning on dimension 1. (firmware/weights/b9.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b12': Complete partitioning on dimension 1. (firmware/weights/b12.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b14': Complete partitioning on dimension 1. (firmware/weights/b14.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b17': Complete partitioning on dimension 1. (firmware/weights/b17.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b19': Complete partitioning on dimension 1. (firmware/weights/b19.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b23': Complete partitioning on dimension 1. (firmware/weights/b23.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b25': Complete partitioning on dimension 1. (firmware/weights/b25.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b29': Complete partitioning on dimension 1. (firmware/weights/b29.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b31': Complete partitioning on dimension 1. (firmware/weights/b31.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b35': Complete partitioning on dimension 1. (firmware/weights/b35.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b37': Complete partitioning on dimension 1. (firmware/weights/b37.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'w39': Complete partitioning on dimension 1. (firmware/weights/w39.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b39': Complete partitioning on dimension 1. (firmware/weights/b39.h:12:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEES6_7config6EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj1EEENS1_IS2_ILi37ELi17ELS3_5ELS4_3ELi0EELj8EEE7config2EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to 'acc': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_dense_resource.h:110:32) +INFO: [HLS 214-248] Applying array_partition to 'res_out': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:274:29) +INFO: [HLS 214-248] Applying array_partition to 'shift_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv_stream.h:224:30) +INFO: [HLS 214-248] Applying array_partition to 'data.i': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_sepconv_stream.h:88:30) +INFO: [HLS 214-248] Applying array_partition to 'res.i': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_sepconv_stream.h:91:29) +WARNING: [HLS 214-322] Unsuported scalar variable on pragma 'Resource/Bind_Storage', ignore it. (firmware/myproject.cpp:340:5) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer39_out' with compact=bit mode in 36-bits (firmware/myproject.cpp:229:35) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer38_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:226:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer57_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:220:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer36_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:217:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer46_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:85:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer6_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:82:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer41_cpy1' with compact=bit mode in 128-bits (firmware/myproject.cpp:76:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer41_cpy2' with compact=bit mode in 128-bits (firmware/myproject.cpp:79:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer5_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:73:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer45_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:67:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer3_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:64:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer37_out' with compact=bit mode in 320-bits (firmware/myproject.cpp:223:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer4_out' with compact=bit mode in 320-bits (firmware/myproject.cpp:70:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer35_out' with compact=bit mode in 328-bits (firmware/myproject.cpp:214:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer56_out' with compact=bit mode in 384-bits (firmware/myproject.cpp:211:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer34_out' with compact=bit mode in 384-bits (firmware/myproject.cpp:208:30) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer33_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:205:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer32_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:202:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer55_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:196:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer30_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:193:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer48_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:112:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer11_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:109:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer42_cpy1' with compact=bit mode in 256-bits (firmware/myproject.cpp:103:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer42_cpy2' with compact=bit mode in 256-bits (firmware/myproject.cpp:106:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer10_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:100:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer47_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:94:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer8_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:91:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer31_out' with compact=bit mode in 656-bits (firmware/myproject.cpp:199:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer9_out' with compact=bit mode in 656-bits (firmware/myproject.cpp:97:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer29_out' with compact=bit mode in 672-bits (firmware/myproject.cpp:190:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer54_out' with compact=bit mode in 768-bits (firmware/myproject.cpp:187:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer28_out' with compact=bit mode in 768-bits (firmware/myproject.cpp:184:30) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer27_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:181:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer26_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:178:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer53_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:172:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer24_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:169:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer50_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:139:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer16_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:136:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer43_cpy1' with compact=bit mode in 512-bits (firmware/myproject.cpp:130:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer43_cpy2' with compact=bit mode in 512-bits (firmware/myproject.cpp:133:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer15_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:127:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer49_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:121:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer13_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:118:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer25_out' with compact=bit mode in 1344-bits (firmware/myproject.cpp:175:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer14_out' with compact=bit mode in 1344-bits (firmware/myproject.cpp:124:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer23_out' with compact=bit mode in 1376-bits (firmware/myproject.cpp:166:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer52_out' with compact=bit mode in 1536-bits (firmware/myproject.cpp:163:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer22_out' with compact=bit mode in 1536-bits (firmware/myproject.cpp:160:28) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer21_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:157:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer20_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:154:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer51_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:148:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer18_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:145:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer19_out' with compact=bit mode in 2752-bits (firmware/myproject.cpp:151:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer17_out' with compact=bit mode in 2688-bits (firmware/myproject.cpp:142:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer12_out' with compact=bit mode in 1312-bits (firmware/myproject.cpp:115:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer7_out' with compact=bit mode in 640-bits (firmware/myproject.cpp:88:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer2_out' with compact=bit mode in 296-bits (firmware/myproject.cpp:61:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer44_out' with compact=bit mode in 16-bits (firmware/myproject.cpp:58:25) +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::conv_2d_buffer_resource_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_64' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_65' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_66' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_67' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_68' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_69' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_70' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_71' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_72' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_73' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_74' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_75' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_76' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_77' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_78' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_79' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_80' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_81' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_82' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_83' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_84' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_85' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_86' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_87' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_88' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_89' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_90' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_91' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_92' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_93' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_94' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_95' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_64' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_65' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_66' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_67' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_68' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_69' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_70' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_71' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_72' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_73' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_74' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_75' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_76' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_77' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_78' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_79' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_80' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_81' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_82' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_83' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_84' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_85' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_86' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_87' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_88' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_89' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_90' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_91' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_92' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_93' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_94' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_95' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-248] Applying array_reshape to 'w4': Block reshaping with factor 8 on dimension 1. (firmware/weights/w4.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w7': Block reshaping with factor 16 on dimension 1. (firmware/weights/w7.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w9': Block reshaping with factor 32 on dimension 1. (firmware/weights/w9.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w12': Block reshaping with factor 64 on dimension 1. (firmware/weights/w12.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w14': Block reshaping with factor 128 on dimension 1. (firmware/weights/w14.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w17': Block reshaping with factor 256 on dimension 1. (firmware/weights/w17.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w19': Block reshaping with factor 576 on dimension 1. (firmware/weights/w19.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w23': Block reshaping with factor 384 on dimension 1. (firmware/weights/w23.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w25': Block reshaping with factor 128 on dimension 1. (firmware/weights/w25.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w29': Block reshaping with factor 96 on dimension 1. (firmware/weights/w29.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w31': Block reshaping with factor 32 on dimension 1. (firmware/weights/w31.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w35': Block reshaping with factor 24 on dimension 1. (firmware/weights/w35.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w37': Block reshaping with factor 8 on dimension 1. (firmware/weights/w37.h:12:0) +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadTopWidth> at firmware/nnet_utils/nnet_padding_stream.h:53:9 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadMain> at firmware/nnet_utils/nnet_padding_stream.h:59:5 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadBottomWidth> at firmware/nnet_utils/nnet_padding_stream.h:77:9 +INFO: [HLS 214-291] Loop 'CopyMain' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_padding_stream.h:65:9) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-270] Inferring pragma 'array_partition type=complete dim=1' for array 'ref.tmp.i' due to pipeline pragma +INFO: [HLS 214-248] Applying array_partition to 'ref.tmp.i': Complete partitioning on dimension 1. +INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 280.03 seconds. CPU system time: 5.27 seconds. Elapsed time: 275.95 seconds; current allocated memory: 350.871 MB. +INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 350.941 MB. +INFO: [HLS 200-10] Starting code transformations ... +INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 27.05 seconds. CPU system time: 0.06 seconds. Elapsed time: 27.22 seconds; current allocated memory: 420.219 MB. +INFO: [HLS 200-10] Checking synthesizability ... +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 96.36 seconds. CPU system time: 0.06 seconds. Elapsed time: 96.43 seconds; current allocated memory: 538.703 MB. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-712] Applying dataflow to function 'myproject' (firmware/myproject.cpp:8), detected/extracted 56 process function(s): + 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>' + 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config3>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config5>' + 'nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>' + 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config8>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config10>' + 'nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>' + 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config13>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config15>' + 'nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>' + 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>' + 'nnet::relu, 64u>, nnet::array, 64u>, relu_config18>' + 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>' + 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>' + 'nnet::relu, 64u>, nnet::array, 64u>, relu_config20>' + 'nnet::resize_nearest, 64u>, config21>' + 'nnet::concatenate3d, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' + 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>' + 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config24>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config26>' + 'nnet::resize_nearest, 32u>, config27>' + 'nnet::concatenate3d, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' + 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>' + 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config30>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config32>' + 'nnet::resize_nearest, 16u>, config33>' + 'nnet::concatenate3d, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' + 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>' + 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config36>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config38>' + 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>' + 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>'. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_activation_stream.h:81:9) to (firmware/nnet_utils/nnet_activation_stream.h:80:5) in function 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>'... converting 3 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>'... converting 18 basic blocks. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' (firmware/nnet_utils/nnet_dense_resource.h:46:20)...384 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_mult.h:46:11)...576 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' (firmware/nnet_utils/nnet_dense_resource.h:46:5)...96 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' (firmware/nnet_utils/nnet_mult.h:46:11)...128 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_mult.h:46:11)...256 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' (firmware/nnet_utils/nnet_mult.h:46:11)...128 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' (firmware/nnet_utils/nnet_dense_resource.h:46:5)...24 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...13 expression(s) balanced. +INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 236.97 seconds. CPU system time: 0.22 seconds. Elapsed time: 237.22 seconds; current allocated memory: 886.480 MB. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_pooling_stream.h:109:5) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_pooling_stream.h:109:5) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_pooling_stream.h:109:5) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeightSerial' (firmware/nnet_utils/nnet_sepconv2d_stream.h:81:9) in function 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ConcatLoopHeight' (firmware/nnet_utils/nnet_merge_stream.h:234:5) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ConcatLoopHeight' (firmware/nnet_utils/nnet_merge_stream.h:234:5) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ConcatLoopHeight' (firmware/nnet_utils/nnet_merge_stream.h:234:5) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>'. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config23_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config19_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config29_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config25_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config17_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config14_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config9_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config35_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config31_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config12_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config7_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config4_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config37_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config58_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0,config2_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config23_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config19_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config29_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config25_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config17_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config14_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config9_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config35_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config31_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config12_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config7_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config4_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config37_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config58_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0,config2_mult>'. +INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 34.43 seconds. CPU system time: 0.67 seconds. Elapsed time: 35.11 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] Starting hardware synthesis ... +INFO: [HLS 200-10] Synthesizing 'myproject' ... +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,1u>,config44>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,1u>,config44>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config44>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,1u>,config44>' to 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 1u>, config2>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0,config2_mult>' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config2>' to 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config2>' to 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config3>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config45>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config45>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config45>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,8u>,config45>' to 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config4>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config4_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config4>' to 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config4>' to 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config5>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s'. +WARNING: [SYN 201-103] Legalizing function name 'clone_stream,array,8u>,32768>' to 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config6>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +WARNING: [SYN 201-103] Legalizing function name 'pooling2d_cl,array,8u>,config6>' to 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config46>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config46>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config46>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,8u>,config46>' to 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config7>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config7_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config7>' to 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,16u>,config7>' to 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config8>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config47>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config47>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config47>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config47>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config9>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config9_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config9>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,16u>,config9>' to 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config10>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s'. +WARNING: [SYN 201-103] Legalizing function name 'clone_stream,array,16u>,16384>' to 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config11>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +WARNING: [SYN 201-103] Legalizing function name 'pooling2d_cl,16u>,config11>' to 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config48>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config48>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config48>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config48>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config12>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config12_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config12>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config12>' to 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config13>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config49>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config49>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config49>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config49>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config14>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config14_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config14>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config14>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config15>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s'. +WARNING: [SYN 201-103] Legalizing function name 'clone_stream,array,32u>,8192>' to 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config16>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +WARNING: [SYN 201-103] Legalizing function name 'pooling2d_cl,32u>,config16>' to 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config50>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config50>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config50>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config50>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config17>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config17_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,64u>,config17>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,64u>,config17>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,64u>,relu_config18>' to 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config51>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,64u>,config51>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config51>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,64u>,config51>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 64u>, config19>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config19_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,64u>,config19>' to 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,64u>,config19>' to 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,64u>,relu_config20>' to 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s'. +WARNING: [SYN 201-103] Legalizing function name 'resize_nearest, 64u>, config21>' to 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d_2,96u>,config22>' to 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d,96u>,config22>' to 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config52>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,96u>,config52>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config52>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,96u>,config52>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 96u>, config23>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config23_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config23>' to 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config23>' to 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config24>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config53>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config53>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config53>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config53>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config25>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config25_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config25>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config25>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config26>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s'. +WARNING: [SYN 201-103] Legalizing function name 'resize_nearest, 32u>, config27>' to 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d_2,48u>,config28>' to 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d,48u>,config28>' to 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config54>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,48u>,config54>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config54>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,48u>,config54>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 48u>, config29>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config29_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config29>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,16u>,config29>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config30>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config55>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config55>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config55>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config55>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config31>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config31_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config31>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,16u>,config31>' to 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config32>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s'. +WARNING: [SYN 201-103] Legalizing function name 'resize_nearest, 16u>, config33>' to 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d_2,24u>,config34>' to 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d,24u>,config34>' to 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config56>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,24u>,config56>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config56>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,24u>,config56>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 24u>, config35>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config35_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config35>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config35>' to 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config36>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config57>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config57>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config57>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,8u>,config57>' to 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config37>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config37_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config37>' to 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config37>' to 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config38>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config58_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'pointwise_conv_2d_cl,1u>,config58>' to 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_s'. +WARNING: [SYN 201-103] Legalizing function name 'sigmoid,1u>,sigmoid_config40>' to 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s'. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 4.08 seconds. CPU system time: 0.36 seconds. Elapsed time: 4.48 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.93 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.95 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 1u>, config2>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 1u>, config2>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.411 ns) exceeds the target (target clock period: 5.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 3.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' consists of the following: + 'or' operation 1 bit ('or_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [82] (0.000 ns) + 'or' operation 1 bit ('or_ln144_2', firmware/nnet_utils/nnet_dense_resource.h:144) [84] (0.000 ns) + 'or' operation 1 bit ('or_ln144_6', firmware/nnet_utils/nnet_dense_resource.h:144) [88] (0.000 ns) + 'select' operation 37 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [89] (0.229 ns) + 'select' operation 37 bit ('acc_7', firmware/nnet_utils/nnet_dense_resource.h:144) [93] (0.229 ns) + multiplexor before 'phi' operation 37 bit ('acc') with incoming values : ('acc_7', firmware/nnet_utils/nnet_dense_resource.h:144) [33] (0.387 ns) + 'phi' operation 37 bit ('acc') with incoming values : ('acc_7', firmware/nnet_utils/nnet_dense_resource.h:144) [33] (0.000 ns) + 'sparsemux' operation 37 bit ('tmp_i', firmware/nnet_utils/nnet_dense_resource.h:144) [70] (0.584 ns) + 'add' operation 38 bit of DSP[73] ('add_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [73] (2.039 ns) + 'icmp' operation 1 bit ('icmp_ln144_7', firmware/nnet_utils/nnet_dense_resource.h:144) [81] (0.943 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.96 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.99 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config4>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config4>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.23 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.26 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'CloneLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'CloneLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config6>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config6>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReadInputHeight_ReadInputWidth'. +WARNING: [HLS 200-880] The II Violation in module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' (loop 'ReadInputHeight_ReadInputWidth'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between 'load' operation 16 bit ('void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_32', firmware/nnet_utils/nnet_pooling_stream.h:63->firmware/nnet_utils/nnet_pooling_stream.h:115) on static variable 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel' and 'call' operation 0 bit ('_ln52', firmware/nnet_utils/nnet_pooling_stream.h:52->firmware/nnet_utils/nnet_pooling_stream.h:115) to 'shift_line_buffer, 8u>, config6>'. +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 2, Depth = 3, loop 'ReadInputHeight_ReadInputWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.624 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.624 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.45 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.46 seconds; current allocated memory: 2.625 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.625 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.625 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.625 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.625 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.625 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config7>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config7>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.626 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.626 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.29 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.31 seconds; current allocated memory: 2.632 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.632 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.632 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.632 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.632 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.632 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.632 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.632 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.632 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.632 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.44 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.48 seconds; current allocated memory: 2.633 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.634 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.634 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.634 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.634 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.634 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config9>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config9>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.634 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.635 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.5 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.51 seconds; current allocated memory: 2.646 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.646 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.646 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.646 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.646 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.646 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.646 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.646 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'CloneLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'CloneLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.646 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.646 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config11>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config11>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.646 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.646 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReadInputHeight_ReadInputWidth'. +WARNING: [HLS 200-880] The II Violation in module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' (loop 'ReadInputHeight_ReadInputWidth'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between 'load' operation 16 bit ('void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_52', firmware/nnet_utils/nnet_pooling_stream.h:63->firmware/nnet_utils/nnet_pooling_stream.h:115) on static variable 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_20' and 'call' operation 0 bit ('_ln52', firmware/nnet_utils/nnet_pooling_stream.h:52->firmware/nnet_utils/nnet_pooling_stream.h:115) to 'shift_line_buffer, 16u>, config11>'. +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 2, Depth = 3, loop 'ReadInputHeight_ReadInputWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.22 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.23 seconds; current allocated memory: 2.647 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.647 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.648 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.648 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.3 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.32 seconds; current allocated memory: 2.648 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.649 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.649 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.649 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.649 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.649 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config12>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config12>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.650 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.651 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.63 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.68 seconds; current allocated memory: 2.673 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.673 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.673 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.673 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.673 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.673 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.673 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.673 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.673 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.673 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.3 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.33 seconds; current allocated memory: 2.673 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.673 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.673 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.673 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.673 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.673 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config14>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config14>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.28 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.3 seconds; current allocated memory: 2.673 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.673 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.26 seconds. CPU system time: 0.04 seconds. Elapsed time: 1.31 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.34 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.36 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.24 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.26 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'CloneLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'CloneLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config16>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config16>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReadInputHeight_ReadInputWidth'. +WARNING: [HLS 200-880] The II Violation in module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' (loop 'ReadInputHeight_ReadInputWidth'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between 'load' operation 16 bit ('void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_42', firmware/nnet_utils/nnet_pooling_stream.h:63->firmware/nnet_utils/nnet_pooling_stream.h:115) on static variable 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_19' and 'call' operation 0 bit ('_ln52', firmware/nnet_utils/nnet_pooling_stream.h:52->firmware/nnet_utils/nnet_pooling_stream.h:115) to 'shift_line_buffer, 32u>, config16>'. +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 2, Depth = 3, loop 'ReadInputHeight_ReadInputWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.3 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.33 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 7, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 9, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 10, Depth = 11, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.23 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.26 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config17>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config17>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.28 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.3 seconds; current allocated memory: 2.719 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 2.06 seconds. CPU system time: 0.04 seconds. Elapsed time: 2.1 seconds; current allocated memory: 2.781 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.58 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.61 seconds; current allocated memory: 2.781 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.34 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.36 seconds; current allocated memory: 2.781 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.781 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.781 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.781 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.24 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.26 seconds; current allocated memory: 2.781 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.781 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.781 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.781 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 7, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 9, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 10, Depth = 11, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.25 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.28 seconds; current allocated memory: 2.781 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.781 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.781 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.781 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.781 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.781 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 64u>, config19>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 64u>, config19>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.61 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.61 seconds; current allocated memory: 2.781 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.19 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.781 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 5, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 4.91 seconds. CPU system time: 0.07 seconds. Elapsed time: 4.99 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 1.92 seconds. CPU system time: 0.02 seconds. Elapsed time: 1.95 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.57 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.63 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.22 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.23 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.28 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.3 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ImageHeight'. +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_1', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_2', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_3', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_4', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 32, Depth = 32, loop 'ImageHeight' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.39 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.41 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ConcatLoopHeight_ConcatLoopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'ConcatLoopHeight_ConcatLoopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.34 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.37 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 96u>, config23>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 96u>, config23>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.05 seconds. CPU system time: 0.02 seconds. Elapsed time: 1.06 seconds; current allocated memory: 2.904 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.31 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.31 seconds; current allocated memory: 2.904 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 5, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 4.55 seconds. CPU system time: 0.06 seconds. Elapsed time: 4.62 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 1.59 seconds. CPU system time: 0.04 seconds. Elapsed time: 1.64 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.59 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.63 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.25 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.26 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.27 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.28 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.34 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.36 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config25>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config25>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.32 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.32 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.28 seconds. CPU system time: 0.02 seconds. Elapsed time: 1.3 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.35 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.38 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.26 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.28 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.21 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ImageHeight'. +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_1', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_2', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_3', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_4', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 64, Depth = 64, loop 'ImageHeight' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.69 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.71 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ConcatLoopHeight_ConcatLoopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'ConcatLoopHeight_ConcatLoopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.54 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.56 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 48u>, config29>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 48u>, config29>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.46 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.46 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 5, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.38 seconds. CPU system time: 0.03 seconds. Elapsed time: 1.41 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.42 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.43 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.29 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.31 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.53 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.57 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config31>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config31>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.22 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.23 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.52 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.53 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ImageHeight'. +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_1', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_2', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_3', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_4', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 67, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 98, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 114, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 122, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 126, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 127, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 128, Depth = 128, loop 'ImageHeight' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.72 seconds. CPU system time: 0.05 seconds. Elapsed time: 1.77 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ConcatLoopHeight_ConcatLoopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'ConcatLoopHeight_ConcatLoopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 1.16 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 24u>, config35>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 24u>, config35>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.27 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.29 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.61 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.62 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.19 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.2 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.1 seconds. CPU system time: 0.05 seconds. Elapsed time: 1.15 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config37>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config37>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.2 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.3 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.33 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'SigmoidActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 4, loop 'SigmoidActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.2 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'myproject' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +WARNING: [HLS 200-1020] Increasing the depth of FIFO start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0 (from clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0 to concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0) to 10 to improve performance and/or avoid deadlocks. +WARNING: [HLS 200-1020] Increasing the depth of FIFO start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0 (from clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_U0 to concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0) to 26 to improve performance and/or avoid deadlocks. +WARNING: [HLS 200-1020] Increasing the depth of FIFO start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0 (from clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0 to concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0) to 42 to improve performance and/or avoid deadlocks. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.41 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.44 seconds; current allocated memory: 2.967 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.35 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.36 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.75 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.79 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.967 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.969 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.969 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_cud' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.13 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.970 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_outidx_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_oudEe' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_w2_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_w2eOg' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_37s_38_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_17_3_37_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_19_4_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_oudEe' using auto ROMs. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_w2eOg' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.27 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.34 seconds; current allocated memory: 2.972 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_7' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.42 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.46 seconds; current allocated memory: 2.976 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.13 seconds. CPU system time: 0 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.977 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.978 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.980 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.982 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.985 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.985 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1375_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_fYi' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1383_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_g8j' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1376_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_hbi' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1384_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_ibs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1377_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_jbC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1385_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_kbM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1378_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_lbW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1386_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_mb6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1379_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_ncg' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1387_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_ocq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1380_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_pcA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1388_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_qcK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1381_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_rcU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1389_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_sc4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1382_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_tde' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1390_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_udo' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.44 seconds. CPU system time: 0.06 seconds. Elapsed time: 0.5 seconds; current allocated memory: 2.988 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_w4_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_w4_ROMvdy' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_38s_38_1_1': 7 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_8s_30s_30_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_w4_ROMvdy' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.35 seconds; current allocated memory: 2.993 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_13' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.85 seconds. CPU system time: 0.18 seconds. Elapsed time: 2.03 seconds; current allocated memory: 3.002 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0 seconds. Elapsed time: 0.16 seconds; current allocated memory: 3.005 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 3.006 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 3.007 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stwdI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stxdS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_styd2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stzec' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stAem' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stBew' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stCeG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stDeQ' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.28 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.32 seconds; current allocated memory: 3.010 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'sY' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX' is power-on initialization. +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' pipeline 'ReadInputHeight_ReadInputWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.94 seconds. CPU system time: 0.1 seconds. Elapsed time: 1.05 seconds; current allocated memory: 3.012 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.2 seconds; current allocated memory: 3.015 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.14 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.16 seconds; current allocated memory: 3.018 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 3.021 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.13 seconds; current allocated memory: 3.021 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1359_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Ee0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1367_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Ffa' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1360_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Gfk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1368_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Hfu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1361_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_IfE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1369_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_JfO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1362_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_KfY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1370_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Lf8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1363_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Mgi' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1371_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Ngs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1364_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_OgC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1372_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_PgM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1365_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_QgW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1373_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Rg6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1366_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Shg' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1374_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Thq' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.48 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.53 seconds; current allocated memory: 3.023 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_w7_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_w7_ROMUhA' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_38s_38_1_1': 15 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_w7_ROMUhA' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.37 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.38 seconds; current allocated memory: 3.029 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_38' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_30' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_39' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_31' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_32' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_33' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_34' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_35' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_36' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_37' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_15' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.99 seconds. CPU system time: 0.17 seconds. Elapsed time: 2.15 seconds; current allocated memory: 3.039 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.17 seconds; current allocated memory: 3.042 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 3.043 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 3.045 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 3.048 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 3.051 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 3.051 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_799_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dVhK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_815_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dWhU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_800_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dXh4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_816_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dYie' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_807_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dZio' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_823_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d0iy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_808_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d1iI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_824_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d2iS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_809_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d3i2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_825_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d4jc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_810_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d5jm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_826_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d6jw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_811_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d7jG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_827_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d8jQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_812_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d9j0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_828_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbak' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_813_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbbk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_829_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbck' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_814_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbdk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_830_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbek' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_801_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbfk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_817_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbgk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_802_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbhl' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_818_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbil' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_803_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbjl' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_819_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbkl' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_804_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbll' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_820_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbml' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_805_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbnm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_821_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbom' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_806_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbpm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_822_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbqm' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.87 seconds. CPU system time: 0.1 seconds. Elapsed time: 0.97 seconds; current allocated memory: 3.053 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbrm' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 15 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 16 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 2 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbrm' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.49 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.52 seconds; current allocated memory: 3.065 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4177' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4178' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4179' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4180' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4181' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4182' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4183' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4184' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4185' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4186' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4188' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4122' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4189' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4134' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4190' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4191' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4192' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4137' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4123' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4124' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4125' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4126' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4127' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4128' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4129' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4130' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4131' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4133' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4135' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4136' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_9' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 3.87 seconds. CPU system time: 0.38 seconds. Elapsed time: 4.25 seconds; current allocated memory: 3.084 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.2 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.21 seconds; current allocated memory: 3.088 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 3.089 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 3.091 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bsm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_btn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bun' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bvn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bwn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bxn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_byn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bzo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bAo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bBo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_27_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbCo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_26_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbDo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_25_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbEo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_24_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbFp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_23_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbGp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_22_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbHp' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.53 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.57 seconds; current allocated memory: 3.094 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'sY_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_11' is power-on initialization. +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' pipeline 'ReadInputHeight_ReadInputWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.85 seconds. CPU system time: 0.2 seconds. Elapsed time: 2.05 seconds; current allocated memory: 3.099 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.23 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.26 seconds; current allocated memory: 3.105 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 3.106 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 3.110 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 3.110 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_863_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bIp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_879_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bJp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_864_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_880_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bLp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_871_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bMq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_887_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bNq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_872_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bOq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_888_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bPq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_873_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bQq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_889_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bRq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_874_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bSr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_890_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bTr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_875_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bUr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_891_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bVr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_876_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bWr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_892_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bXr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_877_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bYs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_893_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bZs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_878_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b0s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_894_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b1s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_865_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b2s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_881_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b3s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_866_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b4t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_882_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b5t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_867_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b6t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_883_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b7t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_868_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b8t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_884_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b9t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_869_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2cau' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_885_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2cbu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_870_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2ccu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_886_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2cdu' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.93 seconds. CPU system time: 0.1 seconds. Elapsed time: 1.03 seconds; current allocated memory: 3.112 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s_w12_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s_w12_Rceu' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 31 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 32 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 2 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s_w12_Rceu' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.51 seconds. CPU system time: 0.08 seconds. Elapsed time: 0.59 seconds; current allocated memory: 3.128 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4416' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4428' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4441' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4453' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4465' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4432' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4433' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4434' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4435' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4436' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4417' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4437' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4419' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4438' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4420' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4439' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4421' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4442' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4422' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4443' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4423' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4444' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4424' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4445' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4425' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4446' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4426' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4447' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4427' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4448' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4430' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4449' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4431' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4450' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4452' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4454' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4455' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4456' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4457' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4458' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4459' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4460' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4461' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4463' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4464' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4466' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4467' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4468' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4469' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_8' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.11 seconds. CPU system time: 0.42 seconds. Elapsed time: 4.53 seconds; current allocated memory: 3.151 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.21 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.22 seconds; current allocated memory: 3.155 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.21 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.23 seconds; current allocated memory: 3.157 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.2 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.21 seconds; current allocated memory: 3.160 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.19 seconds; current allocated memory: 3.162 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 3.163 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 3.164 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_943_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cfu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_975_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cgu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_944_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2chv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_976_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2civ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_955_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cjv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_987_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2ckv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_966_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2clv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_998_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cmv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_969_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cnw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1001_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cow' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_970_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cpw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1002_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cqw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_971_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2crw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1003_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2csw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_972_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2ctx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1004_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cux' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_973_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cvx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1005_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cwx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_974_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cxx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1006_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cyx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_945_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2czy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_977_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cAy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_946_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cBy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_978_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cCy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_947_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cDy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_979_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cEy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_948_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cFz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_980_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cGz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_949_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cHz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_981_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cIz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_950_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cJz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_982_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cKz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_951_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cLz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_983_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cMA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_952_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cNA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_984_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cOA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_953_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cPA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_985_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cQA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_954_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cRA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_986_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cSB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_956_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cTB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_988_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cUB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_957_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cVB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_989_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cWB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_958_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cXB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_990_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cYC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_959_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cZC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_991_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c0C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_960_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c1C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_992_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c2C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_961_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c3C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_993_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c4D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_962_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c5D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_994_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c6D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_963_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c7D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_995_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c8D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_964_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c9D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_996_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2daE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_965_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dbE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_997_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dcE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_967_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2ddE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_999_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2deE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_968_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dfE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1000_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dgE' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.82 seconds. CPU system time: 0.19 seconds. Elapsed time: 2.01 seconds; current allocated memory: 3.170 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s_w14_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s_w14_RdhF' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s' is 9216 from HDL expression: (do_init_reg_1345 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 63 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 64 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 4 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s_w14_RdhF' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.84 seconds. CPU system time: 0.06 seconds. Elapsed time: 0.9 seconds; current allocated memory: 3.199 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5021' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_89' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5022' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_88' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5024' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_87' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5025' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_86' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5026' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_85' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5027' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_84' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5028' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_83' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5029' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_82' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5030' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_81' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5031' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_80' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5032' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5033' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5035' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5036' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5037' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4839' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5038' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4851' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5039' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4863' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5040' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4875' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5041' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4887' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5042' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4899' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5043' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4911' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5044' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4923' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5046' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4936' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5047' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4948' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5048' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4960' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5049' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4972' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5050' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4984' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5051' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4996' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5052' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5008' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5053' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5018' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5054' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5019' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5055' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5020' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5092' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5093' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5094' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5095' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4840' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4841' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4842' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4843' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4844' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4845' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4846' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4848' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4849' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4850' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4852' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4853' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4854' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4855' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4856' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4857' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4859' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4860' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4861' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4862' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4941' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4903' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4942' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4904' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4943' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4905' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4944' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4906' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4945' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4907' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4947' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4908' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4949' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4909' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4950' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4910' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4951' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4912' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4952' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4914' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4953' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4915' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4954' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4916' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4955' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4917' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4956' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4918' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4958' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4919' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4959' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4920' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4961' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4921' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4962' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4922' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4963' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4925' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4964' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4926' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4965' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4927' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4966' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4928' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4967' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4929' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4969' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4930' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4970' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4931' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4971' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4932' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4973' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4933' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4974' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4934' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4975' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4937' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4976' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4938' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4977' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4939' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4978' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4940' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5057' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5058' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5059' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5060' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5061' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5062' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5063' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5064' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5065' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5066' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5068' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5069' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5070' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5071' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5072' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5073' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5074' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5075' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5076' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5077' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5079' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5080' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5081' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5082' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5083' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5084' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5085' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5086' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5087' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5088' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5090' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5091' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4864' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4865' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4866' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4867' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4868' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4870' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4871' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4872' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4873' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4874' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4876' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4877' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4878' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4879' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4881' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4882' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4883' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4884' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4885' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4886' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4888' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4889' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4890' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4892' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4893' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4894' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4895' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4896' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4897' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4898' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4900' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4901' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4980' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4981' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4982' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4983' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4985' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4986' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4987' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4988' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4989' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4991' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4992' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4993' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4994' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4995' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4997' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4998' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5000' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5002' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5003' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5004' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5005' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5006' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5007' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5009' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5010' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5011' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5013' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5014' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5015' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5016' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5017' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_5' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 8.5 seconds. CPU system time: 0.84 seconds. Elapsed time: 9.35 seconds; current allocated memory: 3.241 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.26 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.3 seconds; current allocated memory: 3.247 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.24 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.27 seconds; current allocated memory: 3.250 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.21 seconds; current allocated memory: 3.253 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_diF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_djF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dkF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dlF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dmF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dnG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_doG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dpG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dqG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_drG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_21_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindsG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_20_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindtH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_19_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolinduH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_18_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindvH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_17_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindwH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_16_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindxH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_15_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindyH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_14_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindzI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_13_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindAI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_12_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindBI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_11_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindCI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_10_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindDI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindEI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindFJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindGJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindHJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindIJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindJJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindKJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindLJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindMK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindNK' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.05 seconds. CPU system time: 0.1 seconds. Elapsed time: 1.14 seconds; current allocated memory: 3.256 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'sY_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_89' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_57' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_88' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_56' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_87' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_55' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_86' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_54' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_85' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_53' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_84' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_52' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_83' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_51' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_82' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_50' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_81' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_49' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_80' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_48' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_79' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_47' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_78' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_46' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_77' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_45' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_76' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_44' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_75' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_43' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_74' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_42' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_73' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_41' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_72' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_40' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_71' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_39' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_70' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_38' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_69' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_37' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_68' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_36' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_99' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_67' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_35' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_98' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_66' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_34' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_97' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_65' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_33' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_96' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_64' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_32' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_95' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_63' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_31' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_94' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_62' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_30' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_93' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_61' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_92' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_60' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_91' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_59' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_90' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_58' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_3' is power-on initialization. +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' pipeline 'ReadInputHeight_ReadInputWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.01 seconds. CPU system time: 0.38 seconds. Elapsed time: 4.38 seconds; current allocated memory: 3.268 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.34 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.37 seconds; current allocated memory: 3.278 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 3.279 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.21 seconds; current allocated memory: 3.282 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 3.282 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1071_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dOK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1103_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dPK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1072_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dQK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1104_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dRK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1083_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dSL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1115_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dTL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1094_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dUL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1126_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dVL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1097_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dWL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1129_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dXL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1098_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dYM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1130_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dZM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1099_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d0M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1131_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d1M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1100_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d2M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1132_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d3M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1101_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d4N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1133_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d5N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1102_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d6N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1134_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d7N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1073_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d8N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1105_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d9N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1074_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eaO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1106_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ebO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1075_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ecO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1107_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2edO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1076_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eeO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1108_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2efO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1077_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2egO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1109_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ehP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1078_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eiP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1110_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ejP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1079_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ekP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1111_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2elP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1080_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2emP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1112_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2enQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1081_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eoQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1113_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2epQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1082_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eqQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1114_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2erQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1084_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2esQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1116_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2etR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1085_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2euR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1117_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2evR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1086_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ewR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1118_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2exR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1087_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eyR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1119_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ezS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1088_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eAS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1120_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eBS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1089_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eCS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1121_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eDS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1090_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eES' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1122_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eFT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1091_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eGT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1123_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eHT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1092_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eIT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1124_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eJT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1093_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eKT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1125_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eLT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1095_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eMU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1127_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eNU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1096_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eOU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1128_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ePU' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 2.02 seconds. CPU system time: 0.21 seconds. Elapsed time: 2.23 seconds; current allocated memory: 3.287 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s_w17_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s_w17_ReQU' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s' is 9216 from HDL expression: (do_init_reg_1923 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 127 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 128 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 4 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s_w17_ReQU' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.1 seconds. CPU system time: 0.09 seconds. Elapsed time: 1.19 seconds; current allocated memory: 3.330 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_69' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_68' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_67' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_66' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_65' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_64' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_63' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_62' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_61' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_60' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5402' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5414' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5426' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5438' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5450' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5462' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5436' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5437' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5439' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5440' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5442' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5403' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5443' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5404' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5444' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5405' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5445' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5406' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5446' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5407' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5447' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5409' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5448' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5410' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5449' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5411' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5451' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5412' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5453' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5413' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5454' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5415' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5455' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5416' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5456' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5417' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5457' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5418' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5458' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5420' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5459' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5421' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5460' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5422' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5461' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5423' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5464' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5424' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5465' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5425' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5466' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5427' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5467' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5428' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5468' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5429' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5469' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5431' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5432' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5433' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5434' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5435' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_10' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 9.7 seconds. CPU system time: 0.92 seconds. Elapsed time: 10.63 seconds; current allocated memory: 3.389 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.3 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.33 seconds; current allocated memory: 3.395 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.31 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.33 seconds; current allocated memory: 3.399 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.26 seconds. CPU system time: 0.06 seconds. Elapsed time: 0.3 seconds; current allocated memory: 3.405 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.21 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.22 seconds; current allocated memory: 3.408 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.2 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.22 seconds; current allocated memory: 3.409 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 3.410 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1231_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eRU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1295_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eSV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1232_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eTV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1296_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eUV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1243_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eVV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1307_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eWV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1254_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eXV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1318_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eYW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1265_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eZW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1329_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e0W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1276_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e1W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1340_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e2W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1287_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e3W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1351_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e4X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1292_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e5X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1356_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e6X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1293_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e7X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1357_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e8X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1294_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e9X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1358_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2faY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1233_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fbY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1297_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fcY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1234_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fdY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1298_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2feY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1235_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ffY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1299_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fgY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1236_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fhZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1300_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fiZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1237_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fjZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1301_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fkZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1238_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2flZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1302_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fmZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1239_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fn0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1303_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fo0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1240_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fp0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1304_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fq0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1241_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fr0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1305_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fs0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1242_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ft1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1306_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fu1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1244_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fv1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1308_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fw1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1245_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fx1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1309_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fy1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1246_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fz2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1310_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fA2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1247_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fB2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1311_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fC2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1248_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fD2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1312_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fE2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1249_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fF3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1313_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fG3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1250_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fH3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1314_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fI3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1251_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fJ3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1315_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fK3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1252_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fL3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1316_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fM4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1253_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fN4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1317_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fO4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1255_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fP4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1319_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fQ4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1256_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fR4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1320_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fS5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1257_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fT5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1321_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fU5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1258_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fV5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1322_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fW5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1259_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fX5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1323_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fY6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1260_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fZ6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1324_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f06' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1261_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f16' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1325_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f26' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1262_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f36' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1326_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f47' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1263_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f57' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1327_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f67' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1264_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f77' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1328_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f87' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1266_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f97' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1330_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ga8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1267_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gb8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1331_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gc8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1268_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gd8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1332_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ge8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1269_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gf8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1333_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gg8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1270_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gh9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1334_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gi9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1271_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gj9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1335_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gk9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1272_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gl9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1336_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gm9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1273_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1337_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1274_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1338_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1275_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2grb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1339_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1277_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gtb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1341_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1278_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1342_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1279_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1343_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1280_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1344_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gAb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1281_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gBb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1345_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gCb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1282_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gDb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1346_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gEb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1283_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gFb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1347_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gGb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1284_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gHb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1348_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gIb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1285_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gJb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1349_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gKb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1286_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gLb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1350_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gMb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1288_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1352_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1289_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1353_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1290_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1354_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1291_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1355_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gUb_x' due to conflict. +INFO: [RTGEN 206-104] Estimated max fanout for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s' is 9216 from HDL expression: (1'b1 == ap_CS_fsm_state1) +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.51 seconds. CPU system time: 0.42 seconds. Elapsed time: 4.93 seconds; current allocated memory: 3.420 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s_w19_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s_w19_RgVb' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s' is 18432 from HDL expression: (do_init_reg_3761 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 256 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_33s_33_1_1': 63 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 256 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_129_6_16_1_1': 9 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s_w19_RgVb' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 2.23 seconds. CPU system time: 0.14 seconds. Elapsed time: 2.37 seconds; current allocated memory: 3.500 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_49' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_48' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_47' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_46' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_45' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_44' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_43' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_42' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_41' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_40' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6184' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6293' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6305' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6317' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6329' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6341' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6353' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6366' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6378' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6390' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6402' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6414' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6426' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6438' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6450' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6462' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6177' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6179' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6180' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6181' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6182' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6183' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6185' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6186' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6187' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6188' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6190' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6191' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6192' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6361' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6362' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6363' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6364' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6287' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6367' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6289' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6368' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6290' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6369' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6291' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6370' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6292' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6371' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6294' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6372' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6295' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6373' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6296' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6374' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6297' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6375' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6298' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6377' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6300' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6379' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6301' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6380' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6302' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6381' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6303' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6382' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6304' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6383' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6306' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6384' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6307' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6385' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6308' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6386' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6309' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6388' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6311' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6389' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6312' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6391' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6313' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6392' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6314' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6393' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6315' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6394' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6316' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6395' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6318' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6396' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6319' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6397' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6320' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6399' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6322' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6400' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6323' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6401' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6324' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6403' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6325' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6404' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6326' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6405' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6327' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6406' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6328' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6407' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6330' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6408' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6331' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6410' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6333' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6411' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6334' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6412' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6335' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6413' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6336' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6415' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6337' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6416' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6338' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6417' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6339' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6418' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6340' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6419' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6342' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6421' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6344' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6422' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6345' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6423' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6346' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6424' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6347' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6425' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6348' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6427' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6349' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6428' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6350' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6429' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6351' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6430' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6352' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6432' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6355' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6433' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6356' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6434' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6357' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6435' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6358' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6436' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6359' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6437' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6360' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6439' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6440' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6441' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6443' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6444' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6445' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6446' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6447' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6448' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6449' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6451' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6452' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6454' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6455' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6456' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6457' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6458' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6459' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6460' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6461' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6463' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6465' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6466' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6467' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6468' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6469' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_16' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 21.56 seconds. CPU system time: 2 seconds. Elapsed time: 23.63 seconds; current allocated memory: 3.626 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.49 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.51 seconds; current allocated memory: 3.638 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.43 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.45 seconds; current allocated memory: 3.647 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.31 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.33 seconds; current allocated memory: 3.653 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' pipeline 'ConcatLoopHeight_ConcatLoopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.25 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.28 seconds; current allocated memory: 3.660 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.2 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.22 seconds; current allocated memory: 3.661 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.22 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.26 seconds; current allocated memory: 3.662 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.25 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.27 seconds; current allocated memory: 3.663 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.26 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.28 seconds; current allocated memory: 3.664 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.22 seconds; current allocated memory: 3.665 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1407_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2gWb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_95_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2gXb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1408_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2gYb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_94_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2gZb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1419_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_83_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1430_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_72_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1441_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_61_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1452_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_50_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1463_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_39_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1474_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_28_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1485_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_17_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1496_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2heb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1409_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_93_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1410_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_92_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1411_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_91_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hlb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1412_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_90_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1413_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_89_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1414_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_88_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1415_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_87_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2htb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1416_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_86_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1417_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_85_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1418_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_84_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1420_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_82_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1421_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_81_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1422_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_80_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1423_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_79_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1424_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_78_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1425_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_77_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1426_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_76_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1427_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_75_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1428_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_74_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1429_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_73_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1431_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_71_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1432_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_70_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1433_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_69_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1434_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_68_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1435_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_67_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1436_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_66_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1437_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_65_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1438_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_64_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1439_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_63_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ibb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1440_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2icb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_62_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2idb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1442_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ieb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_60_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ifb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1443_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2igb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_59_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ihb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1444_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_58_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ijb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1445_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ikb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_57_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ilb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1446_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2imb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_56_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2inb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1447_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_55_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ipb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1448_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_54_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2irb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1449_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2isb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_53_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2itb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1450_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_52_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ivb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1451_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_51_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ixb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1453_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_49_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2izb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1454_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_48_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1455_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_47_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1456_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_46_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1457_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_45_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1458_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_44_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1459_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_43_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1460_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_42_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1461_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_41_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1462_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_40_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1464_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_38_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1465_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_37_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1466_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_36_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1467_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_35_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1468_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_34_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1469_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_33_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1470_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_32_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1471_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_31_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1472_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_30_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1473_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_29_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1475_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_27_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1476_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jeb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_26_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1477_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_25_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1478_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_24_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1479_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_23_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jlb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1480_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_22_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1481_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2job' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_21_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1482_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_20_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1483_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_19_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jtb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1484_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_18_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1486_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_16_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1487_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_15_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1488_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_14_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1489_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_13_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1490_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_12_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1491_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_11_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1492_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_10_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1493_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1494_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1495_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1497_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1498_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_99_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_98_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_97_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_96_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j1b' due to the length limit 80 +INFO: [RTGEN 206-104] Estimated max fanout for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s' is 13824 from HDL expression: (1'b1 == ap_CS_fsm_state1) +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 10.07 seconds. CPU system time: 0.94 seconds. Elapsed time: 11 seconds; current allocated memory: 3.674 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_w23_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_w23_Rj2b' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' is 27648 from HDL expression: (do_init_reg_3523 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 128 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_33s_33_1_1': 127 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 128 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 12 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_w23_Rj2b' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 2.3 seconds. CPU system time: 0.16 seconds. Elapsed time: 2.48 seconds; current allocated memory: 3.753 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3846' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3857' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3868' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3879' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3890' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3901' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3912' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3923' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3934' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3945' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3956' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3967' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3978' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3989' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4000' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4011' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4022' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4033' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4044' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4055' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4066' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4077' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4088' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4099' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4110' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4121' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4363' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4847' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4968' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5089' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5331' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5452' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5936' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6057' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6178' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6299' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6420' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_94' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_83' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_72' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_61' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_50' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_39' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3928' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3929' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3930' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3931' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3932' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3933' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3935' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3936' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3937' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3938' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3939' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3940' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3941' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3942' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3943' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3944' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3839' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3946' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3840' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3947' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3841' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3948' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3842' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3949' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3843' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3950' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3844' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3951' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3845' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3952' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3847' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3953' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3848' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3954' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3849' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3955' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3850' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3957' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3851' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3958' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3852' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3959' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3853' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3960' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3854' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3961' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3855' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3962' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3856' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3963' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3858' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3964' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3859' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3965' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3860' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3966' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3861' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3968' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3862' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3969' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3863' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3970' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3864' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3971' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3865' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3972' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3866' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3973' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3867' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3974' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3869' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3975' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3870' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3976' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3871' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3977' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3872' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3979' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3873' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3980' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3874' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3981' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3875' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3982' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3876' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3983' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3877' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3984' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3878' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3985' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3880' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3986' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3881' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3987' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3882' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3988' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3883' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3990' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3884' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3991' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3885' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3992' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3886' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3993' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3887' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3994' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3888' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3995' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3889' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3996' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3891' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3997' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3892' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3998' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3893' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3894' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4001' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3895' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4002' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3896' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4003' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3897' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4004' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3898' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4005' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3899' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4006' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3900' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4007' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3902' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4008' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3903' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4009' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3904' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4010' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3905' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4012' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3906' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4013' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3907' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4014' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3908' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4015' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3909' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4016' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3910' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4017' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3911' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4018' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3913' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4019' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3914' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4020' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3915' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4021' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3916' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4023' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3917' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4024' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3918' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4025' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3919' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4026' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3920' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4027' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3921' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4028' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3922' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4029' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3924' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4030' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3925' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4031' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3926' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4032' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3927' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4319' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4330' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4341' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4352' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4374' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4385' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4396' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4407' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4418' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4429' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4440' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4451' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4462' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5848' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5859' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5870' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5881' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5892' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5903' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5914' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5925' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5947' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5958' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5969' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5980' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5991' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6002' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6013' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4858' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6024' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4869' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6035' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4880' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6046' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4891' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6068' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4902' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6079' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4913' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6090' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4924' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6101' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4935' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6112' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4946' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6123' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4957' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6134' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4979' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4990' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5001' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5012' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6189' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5023' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5034' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5045' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5056' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5067' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5078' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5100' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5111' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5122' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6288' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5133' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6310' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6321' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6332' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6343' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5177' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6354' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5188' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6365' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6376' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6387' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6398' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6409' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6431' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6442' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6453' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5287' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6464' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5298' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5309' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5320' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5342' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5353' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5364' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5375' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5386' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5397' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5408' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5419' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5430' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5441' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5463' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4034' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4035' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4036' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4037' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4038' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4039' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4040' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4041' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4042' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4043' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4045' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4046' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4047' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4048' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4049' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4050' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4051' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4052' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4053' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4054' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4056' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4057' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4058' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4059' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4060' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4061' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4062' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4063' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4064' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4065' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4067' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4068' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4069' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4070' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4071' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4072' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4073' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4074' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4075' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4076' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4078' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4079' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4080' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4081' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4082' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4083' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4084' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4085' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4086' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4087' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4089' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4090' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4091' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4092' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4093' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4094' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4095' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4096' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4097' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4098' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4100' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4101' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4102' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4103' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4104' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4105' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4106' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4107' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4108' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4109' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4111' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4112' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4113' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4114' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4115' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4116' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4117' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4118' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4119' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4120' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4132' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4187' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4297' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4308' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_99' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_98' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_97' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_96' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_95' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_93' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_92' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_91' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_90' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_89' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_88' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_87' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_86' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_85' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_84' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_82' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_81' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_80' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_79' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_78' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_77' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_76' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_75' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_74' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_73' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_71' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_70' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_69' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_68' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_67' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_66' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_65' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_64' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_63' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_62' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_60' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_59' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_58' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_57' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_56' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_55' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_54' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_53' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_52' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_51' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_49' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_48' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_47' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_46' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_45' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_44' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_43' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_42' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_41' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_40' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_38' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_37' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_36' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_35' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_34' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_33' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_32' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_31' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_30' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_12' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 36.36 seconds. CPU system time: 3.3 seconds. Elapsed time: 39.72 seconds; current allocated memory: 3.889 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.65 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.67 seconds; current allocated memory: 3.908 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.48 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.52 seconds; current allocated memory: 3.920 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.33 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.36 seconds; current allocated memory: 3.926 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.31 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.32 seconds; current allocated memory: 3.929 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.3 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.33 seconds; current allocated memory: 3.931 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.24 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.26 seconds; current allocated memory: 3.932 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1007_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1039_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1008_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1040_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1019_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1051_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1030_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1062_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1033_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1065_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1034_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1066_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2keb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1035_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1067_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1036_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2khb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1068_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1037_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1069_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1038_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2klb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1070_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1009_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2knb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1041_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1010_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1042_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1011_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2krb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1043_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2ksb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1012_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2ktb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1044_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1013_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1045_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1014_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1046_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1015_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1047_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1016_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1048_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1017_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1049_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1018_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1050_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1020_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1052_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1021_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1053_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1022_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1054_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1023_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1055_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1024_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1056_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1025_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1057_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1026_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1058_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1027_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1059_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1028_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1060_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1029_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1061_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1031_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1063_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1032_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1064_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k4b' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4 seconds. CPU system time: 0.35 seconds. Elapsed time: 4.35 seconds; current allocated memory: 3.933 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s_w25_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s_w25_Rk5b' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s' is 9216 from HDL expression: (do_init_reg_1343 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 63 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 64 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 4 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s_w25_Rk5b' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.08 seconds. CPU system time: 0.07 seconds. Elapsed time: 1.15 seconds; current allocated memory: 3.949 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5327' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_79' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5328' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_78' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5329' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_77' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5330' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_76' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5332' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_75' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5333' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_74' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5334' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_73' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5335' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_72' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5336' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_71' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5337' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_70' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5338' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5096' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5339' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5108' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5340' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5120' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5341' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5132' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5343' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5344' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5345' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5346' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5181' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5347' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5348' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5349' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5350' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5351' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5352' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5354' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5355' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5356' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5290' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5357' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5302' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5358' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5314' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5359' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5324' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5360' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5325' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5361' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5326' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5130' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5398' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5131' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5399' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5134' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5400' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5135' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5401' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5136' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5097' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5137' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5098' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5099' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5101' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5102' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5103' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5104' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5105' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5106' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5107' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5109' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5110' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5112' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5113' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5114' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5115' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5116' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5117' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5118' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5119' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5121' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5123' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5124' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5125' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5126' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5127' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5128' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5129' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5362' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5363' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5365' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5366' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5367' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5368' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5369' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5370' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5371' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5372' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5373' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5374' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5376' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5377' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5378' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5379' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5380' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5381' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5382' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5383' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5384' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5385' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5387' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5388' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5389' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5390' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5391' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5392' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5393' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5394' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5395' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5396' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5178' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5179' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5180' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5182' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5183' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5184' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5185' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5186' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5187' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5189' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5190' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5191' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5192' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5288' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5289' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5291' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5292' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5293' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5294' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5295' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5296' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5297' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5299' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5300' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5301' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5303' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5304' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5305' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5306' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5307' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5308' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5310' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5311' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5312' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5313' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5315' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5316' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5317' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5318' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5319' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5321' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5322' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5323' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_4' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 13.2 seconds. CPU system time: 1.22 seconds. Elapsed time: 14.42 seconds; current allocated memory: 3.988 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.39 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.44 seconds; current allocated memory: 3.998 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.38 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.42 seconds; current allocated memory: 4.019 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.34 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.36 seconds; current allocated memory: 4.022 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' pipeline 'ConcatLoopHeight_ConcatLoopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.34 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.36 seconds; current allocated memory: 4.027 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.26 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.3 seconds; current allocated memory: 4.029 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.31 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.34 seconds; current allocated memory: 4.030 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.33 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.36 seconds; current allocated memory: 4.030 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.33 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.36 seconds; current allocated memory: 4.032 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.27 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.29 seconds; current allocated memory: 4.034 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1135_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2k6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1183_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2k7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1136_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2k8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1184_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2k9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1147_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1195_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1158_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1206_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2ldb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1169_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2leb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1217_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1178_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1226_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1179_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1227_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2ljb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1180_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1228_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2llb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1181_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1229_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1182_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1230_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1137_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1185_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1138_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1186_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2ltb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1139_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1187_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1140_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1188_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1141_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1189_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1142_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1190_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1143_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1191_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1144_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1192_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1145_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1193_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1146_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1194_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1148_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1196_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1149_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1197_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1150_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1198_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1151_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1199_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1152_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1200_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1153_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1201_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1154_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1202_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1155_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1203_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1156_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1204_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1157_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1205_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1159_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1207_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1160_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1208_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1161_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1209_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1162_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1210_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1163_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1211_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1164_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2meb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1212_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1165_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1213_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1166_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1214_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1167_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1215_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mlb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1168_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1216_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1170_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1218_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1171_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1219_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1172_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2msb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1220_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mtb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1173_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1221_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1174_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1222_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1175_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2myb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1223_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mzc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1176_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mAc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1224_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mBc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1177_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mCc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1225_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mDc' due to the length limit 80 +INFO: [RTGEN 206-104] Estimated max fanout for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s' is 6912 from HDL expression: (1'b1 == ap_CS_fsm_state1) +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 5.78 seconds. CPU system time: 0.49 seconds. Elapsed time: 6.27 seconds; current allocated memory: 4.035 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_w29_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_w29_RmEc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' is 13824 from HDL expression: (do_init_reg_1475 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 32 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_33s_33_1_1': 31 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_8s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 32 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 6 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_w29_RmEc' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.29 seconds. CPU system time: 0.13 seconds. Elapsed time: 1.42 seconds; current allocated memory: 4.058 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6115' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_59' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6116' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_58' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6117' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_57' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6118' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_56' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6119' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_55' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6120' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_54' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6121' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_53' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6122' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_52' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6124' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_51' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6125' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_50' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6126' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6127' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6128' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6129' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6130' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6131' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6132' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6133' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6135' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6136' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6137' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5841' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5853' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5865' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5877' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5889' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5901' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5913' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5926' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5938' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5950' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5962' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5974' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5986' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5998' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6010' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6022' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6034' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6047' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6059' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6071' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6083' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6095' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6107' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6110' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6111' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6113' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6114' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5839' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5840' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5842' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5843' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5844' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5845' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5846' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5847' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5849' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5850' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5851' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5852' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5854' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5855' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5856' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5857' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5858' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5860' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5861' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5862' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5863' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5864' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5866' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5867' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5868' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5869' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5871' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5872' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5873' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5874' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5875' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5876' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5994' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5935' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5995' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5937' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5996' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5939' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5997' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5940' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5941' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6000' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5942' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6001' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5943' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6003' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5944' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6004' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5945' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6005' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5946' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6006' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5948' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6007' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5949' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6008' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5951' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6009' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5952' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6011' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5953' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6012' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5954' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6014' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5955' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6015' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5956' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6016' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5957' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6017' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5959' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6018' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5960' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6019' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5961' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6020' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5963' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6021' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5964' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6023' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5965' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6025' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5966' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6026' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5967' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6027' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5968' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6028' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5970' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6029' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5971' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6030' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5972' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6031' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5973' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6032' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5975' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6033' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5976' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6036' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5977' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6037' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5978' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6038' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5979' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6039' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5981' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6040' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5982' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6041' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5983' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6042' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5984' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6043' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5985' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6044' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5987' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6045' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5988' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6048' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5989' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6049' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5990' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6050' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5992' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6051' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5993' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5878' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5879' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5880' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5882' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5883' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5884' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5885' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5886' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5887' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5888' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5890' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5891' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5893' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5894' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5895' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5896' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5897' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5898' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5899' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5900' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5902' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5904' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5905' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5906' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5907' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5908' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5909' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5910' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5911' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5912' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5915' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5916' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5917' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5918' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5919' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5920' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5921' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5922' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5923' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5924' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5927' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5928' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5929' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5930' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5931' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5932' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5933' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5934' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6052' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6053' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6054' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6055' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6056' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6058' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6060' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6061' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6062' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6063' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6064' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6065' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6066' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6067' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6069' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6070' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6072' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6073' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6074' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6075' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6076' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6077' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6078' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6080' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6081' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6082' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6084' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6085' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6086' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6087' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6088' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6089' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6091' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6092' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6093' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6094' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6096' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6097' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6098' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6099' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6100' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6102' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6103' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6104' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6105' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6106' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6108' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6109' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_1' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 20.86 seconds. CPU system time: 1.86 seconds. Elapsed time: 22.73 seconds; current allocated memory: 4.110 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.46 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.51 seconds; current allocated memory: 4.117 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.38 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.41 seconds; current allocated memory: 4.140 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.38 seconds; current allocated memory: 4.143 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.35 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.38 seconds; current allocated memory: 4.145 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.34 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.38 seconds; current allocated memory: 4.147 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.27 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.3 seconds; current allocated memory: 4.149 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_831_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mFc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_847_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mGc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_832_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mHc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_848_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mIc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_839_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mJc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_855_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mKc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_840_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mLc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_856_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mMc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_841_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mNc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_857_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mOc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_842_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mPc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_858_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mQc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_843_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mRc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_859_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mSc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_844_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mTc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_860_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mUc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_845_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mVc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_861_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mWc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_846_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mXc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_862_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mYc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_833_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mZc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_849_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m0c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_834_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m1c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_850_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m2c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_835_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m3c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_851_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m4c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_836_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m5c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_852_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m6c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_837_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m7c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_853_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m8c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_838_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m9c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_854_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2nac' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.79 seconds. CPU system time: 0.15 seconds. Elapsed time: 1.95 seconds; current allocated memory: 4.150 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s_w31_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s_w31_Rnbc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 15 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 16 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 2 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s_w31_Rnbc' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.8 seconds. CPU system time: 0.06 seconds. Elapsed time: 0.86 seconds; current allocated memory: 4.154 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4324' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4325' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4326' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4327' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4328' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4329' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4331' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4332' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4333' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4334' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4335' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4336' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4337' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4293' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4338' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4305' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4339' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4317' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4340' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4323' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4377' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4359' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4378' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4360' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4379' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4361' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4380' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4362' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4381' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4364' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4382' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4365' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4383' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4366' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4384' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4367' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4386' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4368' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4387' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4369' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4388' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4370' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4389' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4371' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4390' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4372' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4391' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4373' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4392' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4375' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4393' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4376' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4412' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4413' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4287' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4414' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4288' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4415' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4289' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4290' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4291' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4292' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4294' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4295' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4296' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4298' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4299' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4300' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4301' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4302' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4342' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4343' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4344' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4345' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4346' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4347' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4348' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4349' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4350' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4351' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4353' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4354' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4355' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4356' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4357' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4358' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4394' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4395' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4397' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4398' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4399' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4400' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4401' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4402' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4403' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4404' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4405' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4406' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4408' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4409' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4410' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4411' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4303' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4304' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4306' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4307' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4309' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4310' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4311' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4312' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4313' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4314' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4315' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4316' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4318' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4320' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4321' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4322' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_2' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 7.49 seconds. CPU system time: 0.71 seconds. Elapsed time: 8.2 seconds; current allocated memory: 4.167 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.36 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.39 seconds; current allocated memory: 4.175 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.3 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.36 seconds; current allocated memory: 4.189 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.35 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.39 seconds; current allocated memory: 4.191 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' pipeline 'ConcatLoopHeight_ConcatLoopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.37 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.42 seconds; current allocated memory: 4.196 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.28 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.31 seconds; current allocated memory: 4.199 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.34 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.36 seconds; current allocated memory: 4.200 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.4 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.41 seconds; current allocated memory: 4.201 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.39 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.42 seconds; current allocated memory: 4.204 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.29 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.31 seconds; current allocated memory: 4.207 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_895_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2ncc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_919_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2ndc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_896_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nec' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_920_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nfc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_907_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2ngc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_931_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nhc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_912_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nic' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_936_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2njc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_913_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nkc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_937_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nlc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_914_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nmc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_938_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nnc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_915_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2noc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_939_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2npc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_916_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nqc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_940_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nrc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_917_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nsc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_941_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2ntc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_918_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nuc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_942_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nvc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_897_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nwc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_921_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nxc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_898_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nyc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_922_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nzc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_899_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nAc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_923_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nBc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_900_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nCc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nCc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nCc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_924_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nDc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nDc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nDc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_901_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nEc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nEc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nEc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_925_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nFc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nFc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nFc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_902_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nGc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nGc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nGc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_926_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nHc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nHc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nHc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_903_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nIc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nIc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nIc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_927_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nJc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nJc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nJc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_904_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nKc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nKc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nKc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_928_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nLc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nLc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nLc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_905_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nMc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nMc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nMc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_929_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nNc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nNc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nNc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_906_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nOc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nOc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nOc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_930_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nPc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nPc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nPc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_908_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nQc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nQc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nQc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_932_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nRc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nRc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nRc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_909_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nSc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nSc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nSc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_933_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nTc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nTc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nTc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_910_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nUc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nUc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nUc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_934_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nVc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nVc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nVc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_911_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nWc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nWc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nWc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_935_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nXc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nXc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nXc_x' due to conflict. +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 3.69 seconds. CPU system time: 0.34 seconds. Elapsed time: 4.03 seconds; current allocated memory: 4.208 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_w35_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_w35_RnYc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' is 6912 from HDL expression: (do_init_reg_739 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 8 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_33s_33_1_1': 7 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 8 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 3 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_w35_RnYc' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1 seconds. CPU system time: 0.08 seconds. Elapsed time: 1.1 seconds; current allocated memory: 4.214 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_99' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_98' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_97' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_96' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_95' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_94' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_93' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_92' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_91' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_90' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_6' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 11.46 seconds. CPU system time: 1.15 seconds. Elapsed time: 12.61 seconds; current allocated memory: 4.231 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.39 seconds. CPU system time: 0.06 seconds. Elapsed time: 0.44 seconds; current allocated memory: 4.237 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.41 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.44 seconds; current allocated memory: 4.259 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.36 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.39 seconds; current allocated memory: 4.261 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.39 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.43 seconds; current allocated memory: 4.262 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.38 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.43 seconds; current allocated memory: 4.266 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.29 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.33 seconds; current allocated memory: 4.268 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1391_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dnZc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1399_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn0c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1392_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn1c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1400_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn2c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1393_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn3c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1401_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn4c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1394_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn5c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1402_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn6c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1395_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn7c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1403_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn8c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1396_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn9c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1404_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2doac' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1397_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dobc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1405_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2docc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1398_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dodc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1406_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2doec' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.08 seconds. CPU system time: 0.12 seconds. Elapsed time: 1.21 seconds; current allocated memory: 4.269 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s_w37_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s_w37_Rofc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_38s_38_1_1': 7 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_31s_31_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s_w37_Rofc' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.65 seconds. CPU system time: 0.09 seconds. Elapsed time: 0.74 seconds; current allocated memory: 4.272 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_14' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.27 seconds. CPU system time: 0.35 seconds. Elapsed time: 4.62 seconds; current allocated memory: 4.278 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.34 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.37 seconds; current allocated memory: 4.287 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.38 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.41 seconds; current allocated memory: 4.289 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_12s_30s_30_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_17_3_12_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_17_3_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.49 seconds. CPU system time: 0.07 seconds. Elapsed time: 0.58 seconds; current allocated memory: 4.291 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.35 seconds; current allocated memory: 4.293 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s_sigmoid_table_ROM_AUTO_1R' to 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s_sigmoid_table_Rogc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s' pipeline 'SigmoidActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s_sigmoid_table_Rogc' using auto ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.47 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.51 seconds; current allocated memory: 4.295 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'myproject' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low. +INFO: [RTGEN 206-500] Setting interface mode on port 'myproject/x' to 'axis' (register, both mode). +INFO: [RTGEN 206-500] Setting interface mode on port 'myproject/layer40_out' to 'axis' (register, both mode). +INFO: [RTGEN 206-500] Setting interface mode on function 'myproject' to 'ap_ctrl_hs'. +INFO: [SYN 201-210] Renamed object name 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_U0' to 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4ohc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_U0' to 'start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6oic' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_U0' to 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4ojc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_U0' to 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7okc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_U0' to 'start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configolc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_U0' to 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10omc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_U0' to 'start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384onc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13ooc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15opc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_U0' to 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18oqc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_U0' to 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20orc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24osc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26otc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_U0' to 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30ouc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_U0' to 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32ovc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_U0' to 'start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3owc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_U0' to 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config5oxc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_U0' to 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37oyc' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'myproject'. +INFO: [RTMG 210-285] Implementing FIFO 'layer44_out_U(myproject_fifo_w16_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer2_out_U(myproject_fifo_w296_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer3_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer45_out_U(myproject_fifo_w128_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer4_out_U(myproject_fifo_w320_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer5_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer41_cpy1_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer41_cpy2_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer6_out_U(myproject_fifo_w128_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer46_out_U(myproject_fifo_w128_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer7_out_U(myproject_fifo_w640_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer8_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer47_out_U(myproject_fifo_w256_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer9_out_U(myproject_fifo_w656_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer10_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer42_cpy1_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer42_cpy2_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer11_out_U(myproject_fifo_w256_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer48_out_U(myproject_fifo_w256_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer12_out_U(myproject_fifo_w1312_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer13_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer49_out_U(myproject_fifo_w512_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer14_out_U(myproject_fifo_w1344_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer15_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer43_cpy1_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer43_cpy2_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer16_out_U(myproject_fifo_w512_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer50_out_U(myproject_fifo_w512_d100_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer17_out_U(myproject_fifo_w2688_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer18_out_U(myproject_fifo_w1024_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer51_out_U(myproject_fifo_w1024_d100_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer19_out_U(myproject_fifo_w2752_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer20_out_U(myproject_fifo_w1024_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer21_out_U(myproject_fifo_w1024_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer22_out_U(myproject_fifo_w1536_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer52_out_U(myproject_fifo_w1536_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer23_out_U(myproject_fifo_w1376_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer24_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer53_out_U(myproject_fifo_w512_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer25_out_U(myproject_fifo_w1344_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer26_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer27_out_U(myproject_fifo_w512_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer28_out_U(myproject_fifo_w768_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer54_out_U(myproject_fifo_w768_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer29_out_U(myproject_fifo_w672_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer30_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer55_out_U(myproject_fifo_w256_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer31_out_U(myproject_fifo_w656_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer32_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer33_out_U(myproject_fifo_w256_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer34_out_U(myproject_fifo_w384_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer56_out_U(myproject_fifo_w384_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer35_out_U(myproject_fifo_w328_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer36_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer57_out_U(myproject_fifo_w128_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer37_out_U(myproject_fifo_w320_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer38_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer39_out_U(myproject_fifo_w36_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_U0_U(myproject_start_for_conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4ohc_U(myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4ohc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_U0_U(myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0_U(myproject_start_for_clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6oic_U(myproject_start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6oic)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0_U(myproject_start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4ojc_U(myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4ojc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7okc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7okc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_U0_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configolc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configolc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10omc_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10omc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384onc_U(myproject_start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384onc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0_U(myproject_start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0_U(myproject_start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13ooc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13ooc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15opc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15opc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0_U(myproject_start_for_clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_U0_U(myproject_start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0_U(myproject_start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18oqc_U(myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18oqc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20orc_U(myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20orc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_U0_U(myproject_start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24osc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24osc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26otc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26otc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_U0_U(myproject_start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30ouc_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30ouc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32ovc_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32ovc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_U0_U(myproject_start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3owc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3owc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config5oxc_U(myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config5oxc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37oyc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37oyc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_U0_U(myproject_start_for_pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_U0_U(myproject_start_for_sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_U0)' using Shift Registers. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 7.13 seconds. CPU system time: 0.69 seconds. Elapsed time: 7.83 seconds; current allocated memory: 4.296 GB. +INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 2.27 seconds. CPU system time: 0.23 seconds. Elapsed time: 2.58 seconds; current allocated memory: 4.300 GB. +INFO: [HLS 200-111] Finished Updating report files: CPU user time: 17.07 seconds. CPU system time: 0.12 seconds. Elapsed time: 17.25 seconds; current allocated memory: 4.432 GB. +INFO: [VHDL 208-304] Generating VHDL RTL for myproject. +INFO: [VLOG 209-307] Generating Verilog RTL for myproject. +INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were NOT satisfied. +INFO: [HLS 200-789] **** Estimated Fmax: 226.71 MHz +INFO: [HLS 200-2161] Finished Command csynth_design Elapsed time: 00:18:03; Allocated memory: 4.184 GB. +***** C/RTL SYNTHESIS COMPLETED IN 0h18m3s ***** +INFO: [HLS 200-112] Total CPU user time: 1057.04 seconds. Total CPU system time: 37.31 seconds. Total elapsed time: 1087.08 seconds; peak allocated memory: 4.454 GB. +INFO: [vitis-run 60-791] Total elapsed time: 0h 18m 8s +INFO: [vitis-run 60-1662] Stopping dispatch session having empty uuid. diff --git a/logs/hls_run_tcl_185829.backup.log b/logs/hls_run_tcl_185829.backup.log new file mode 100644 index 0000000000000000000000000000000000000000..a8627b440db15d355a61bb0066d8621f0e357635 --- /dev/null +++ b/logs/hls_run_tcl_185829.backup.log @@ -0,0 +1,1817 @@ +INFO: [vitis-run 82-31] Launching vitis_hls: vitis_hls -nolog -run tcl -f /home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl -work_dir /home/ubuntu/lithobench/hls4ml_mini_unet + +****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2024.1 (64-bit) + **** SW Build 5069499 on May 21 2024 + **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 + **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 + **** Start of session at: Sat Apr 4 08:49:58 2026 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. + +source /opt/Xilinx/Vitis_HLS/2024.1/scripts/vitis_hls/hls.tcl -notrace +INFO: [HLS 200-10] For user 'ubuntu' on host 'ip-172-31-42-252.ec2.internal' (Linux_x86_64 version 5.15.0-1084-aws) on Sat Apr 04 08:50:00 UTC 2026 +INFO: [HLS 200-10] On os Ubuntu 20.04.6 LTS +INFO: [HLS 200-10] In directory '/home/ubuntu/lithobench/hls4ml_mini_unet' +Sourcing Tcl script '/home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl' +INFO: [HLS 200-1510] Running: open_project myproject_prj +INFO: [HLS 200-10] Opening project '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj'. +INFO: [HLS 200-1510] Running: set_top myproject +INFO: [HLS 200-1510] Running: add_files firmware/myproject.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding design file 'firmware/myproject.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb myproject_test.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding test bench file 'myproject_test.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb firmware/weights +INFO: [HLS 200-10] Adding test bench file 'firmware/weights' to the project +INFO: [HLS 200-1510] Running: add_files -tb tb_data +INFO: [HLS 200-10] Adding test bench file 'tb_data' to the project +INFO: [HLS 200-1510] Running: open_solution solution1 +INFO: [HLS 200-10] Opening solution '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1'. +INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. +INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 1.35ns. +INFO: [HLS 200-1611] Setting target device to 'xcvu47p-fsvh2892-2L-e' +INFO: [HLS 200-1505] Using flow_target 'vivado' +Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1505.html +INFO: [HLS 200-1464] Running solution command: config_compile -name_max_length=80 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_compile -complex-mul-dsp=0 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_compile -unsafe_math_optimizations=0 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_schedule -enable_dsp_full_reg=0 +INFO: [HLS 200-1464] Running solution command: config_array_partition -complete_threshold=4096 +INFO: [XFORM 203-102] Size-based automatic array partition enabled: cut-off elements per dimension is 4096. +INFO: [HLS 200-1510] Running: config_array_partition -maximum_size 4096 +ERROR: [HLS 200-101] config_array_partition: Unknown option '-maximum_size'. +ERROR: [HLS 200-101] config_array_partition: Unknown option '4096'. +SYNTAX + config_array_partition [OPTIONS] + -auto_partition_threshold *** DEPRECATED*** + -auto_promotion_threshold *** DEPRECATED*** + -complete_threshold + -throughput_driven + +SEE ALSO + INI: syn.array_partition.complete_threshold syn.array_partition.throughput_driven + docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1399-vitis-hls&resourceid=vyw1583260160301.html + +INFO: [HLS 200-1510] Running: config_compile -name_max_length 80 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: set_part xcvu47p-fsvh2892-2L-e +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: config_schedule -enable_dsp_full_reg=false +INFO: [HLS 200-1510] Running: create_clock -period 5 -name default +INFO: [HLS 200-1510] Running: set_clock_uncertainty 27% default +***** C/RTL SYNTHESIS ***** +INFO: [HLS 200-1510] Running: csynth_design +INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0.07 seconds. CPU system time: 0.06 seconds. Elapsed time: 0.14 seconds; current allocated memory: 276.809 MB. +INFO: [HLS 200-10] Analyzing design file 'firmware/myproject.cpp' ... +WARNING: [HLS 207-5570] unexpected pragma argument 'softmax', expects function/operation (firmware/nnet_utils/nnet_activation.h:402:36) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:33:9) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:107:9) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:189:9) +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:234:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:234:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:240:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:240:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:250:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:250:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:256:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:256:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:266:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:266:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:272:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:272:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:282:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:282:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:288:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:288:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:298:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:298:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:304:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:304:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:314:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:314:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:320:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:320:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:330:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:330:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:336:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:336:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:340:100) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:340:105) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 200-471] Dataflow form checks found 30 issue(s) in file firmware/myproject.cpp +Resolution: For help on HLS 200-471 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-471.html +WARNING: [HLS 207-5292] unused parameter 'keep' (firmware/nnet_utils/nnet_helpers.h:285:99) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:14:36) +WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:15:36) +WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:16:44) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:24:24) +WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:25:24) +WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:26:32) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:33:30) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:33:58) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:34:51) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:35:49) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:42:30) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:42:58) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:43:51) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:44:49) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:51:29) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:51:80) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:52:50) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:53:48) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_code_gen.h:16:39) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_code_gen.h:17:38) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_code_gen.h:18:60) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_code_gen.h:19:58) +WARNING: [HLS 207-5584] there are more than one pragma inline in the function scope, ignore the pragma (/opt/Xilinx/Vitis_HLS/2024.1/common/technology/autopilot/ap_shift_reg.h:47:9) +INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 36.21 seconds. CPU system time: 2.2 seconds. Elapsed time: 38.42 seconds; current allocated memory: 287.910 MB. +INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target. +INFO: [HLS 200-1995] There were 28,230 instructions in the design after the 'Compile/Link' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 187,691 instructions in the design after the 'Unroll/Inline (step 1)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 95,617 instructions in the design after the 'Unroll/Inline (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 81,669 instructions in the design after the 'Unroll/Inline (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 37,140 instructions in the design after the 'Unroll/Inline (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 36,213 instructions in the design after the 'Array/Struct' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 31,788 instructions in the design after the 'Array/Struct (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 32,683 instructions in the design after the 'Array/Struct (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 80,744 instructions in the design after the 'Array/Struct (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 77,235 instructions in the design after the 'Array/Struct (step 5)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 78,881 instructions in the design after the 'Performance' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 189,652 instructions in the design after the 'Performance (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 186,966 instructions in the design after the 'Performance (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 186,966 instructions in the design after the 'Performance (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 148,142 instructions in the design after the 'HW Transforms' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 140,432 instructions in the design after the 'HW Transforms (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>' (firmware/nnet_utils/nnet_sepconv_stream.h:103:9) +WARNING: [HLS 214-273] In function 'void nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config58_mult::weight_t*, config58_mult::bias_t*)', Pragma conflict happens on 'INLINE' and 'FUNCTION_INSTANTIATE' pragmas: same function (firmware/nnet_utils/nnet_dense_resource.h:15:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 1u>, config2>(nnet::array, 1u>::value_type (*) [config2::n_chan], nnet::array, 1u>::value_type*)' into 'void nnet::shift_line_buffer, 1u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], nnet::array, 1u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, config2_mult::weight_t*, config2_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*) (.55)' into 'void nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config4>(nnet::array, 8u>::value_type (*) [config4::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config4_mult::weight_t*, config4_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 8u>, config4>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*) (.54)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config6>(nnet::array, 8u>::value_type (*) [config6::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::Op_max >::operator()(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>) (.36)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' (firmware/nnet_utils/nnet_common.h:44:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:15) +INFO: [HLS 214-131] Inlining function 'nnet::Op_max >::operator()(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>) (.36)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:12) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:44) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config6>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.52)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config6>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.52)' into 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 8u>::operator[](unsigned long) (.51)' into 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' into 'void nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config7>(nnet::array, 8u>::value_type (*) [config7::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config7_mult::weight_t*, config7_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 16u>, config7>(hls::stream, 8u>, 0>&, hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*) (.48)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>(hls::stream, 8u>, 0>&, hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config9>(nnet::array, 16u>::value_type (*) [config9::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config9_mult::weight_t*, config9_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 16u>, config9>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*) (.47)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config11>(nnet::array, 16u>::value_type (*) [config11::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config11>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.45)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config11>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.45)' into 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 16u>::operator[](unsigned long) (.44)' into 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' into 'void nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config12>(nnet::array, 16u>::value_type (*) [config12::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config12_mult::weight_t*, config12_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 32u>, config12>(hls::stream, 16u>, 0>&, hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*) (.41)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>(hls::stream, 16u>, 0>&, hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config14>(nnet::array, 32u>::value_type (*) [config14::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config14_mult::weight_t*, config14_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 32u>, config14>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*) (.40)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config16>(nnet::array, 32u>::value_type (*) [config16::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config16>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.34)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config16>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.34)' into 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 32u>::operator[](unsigned long) (.33)' into 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' into 'void nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config17>(nnet::array, 32u>::value_type (*) [config17::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config17_mult::weight_t*, config17_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 64u>, config17>(hls::stream, 32u>, 0>&, hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*) (.30)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>(hls::stream, 32u>, 0>&, hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 64u>, config19>(nnet::array, 64u>::value_type (*) [config19::n_chan], nnet::array, 64u>::value_type*)' into 'void nnet::shift_line_buffer, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], nnet::array, 64u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config19_mult::weight_t*, config19_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 64u>, nnet::array, 64u>, config19>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*) (.26)' into 'void nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 96u>, config23>(nnet::array, 96u>::value_type (*) [config23::n_chan], nnet::array, 96u>::value_type*)' into 'void nnet::shift_line_buffer, 96u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], nnet::array, 96u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config23_mult::weight_t*, config23_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 96u>, nnet::array, 32u>, config23>(hls::stream, 96u>, 0>&, hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*) (.23)' into 'void nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>(hls::stream, 96u>, 0>&, hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config25>(nnet::array, 32u>::value_type (*) [config25::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config25_mult::weight_t*, config25_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 32u>, config25>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*) (.19)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 48u>, config29>(nnet::array, 48u>::value_type (*) [config29::n_chan], nnet::array, 48u>::value_type*)' into 'void nnet::shift_line_buffer, 48u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], nnet::array, 48u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config29_mult::weight_t*, config29_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 48u>, nnet::array, 16u>, config29>(hls::stream, 48u>, 0>&, hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*) (.16)' into 'void nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>(hls::stream, 48u>, 0>&, hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config31>(nnet::array, 16u>::value_type (*) [config31::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config31_mult::weight_t*, config31_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 16u>, config31>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*) (.12)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 24u>, config35>(nnet::array, 24u>::value_type (*) [config35::n_chan], nnet::array, 24u>::value_type*)' into 'void nnet::shift_line_buffer, 24u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], nnet::array, 24u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config35_mult::weight_t*, config35_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 24u>, nnet::array, 8u>, config35>(hls::stream, 24u>, 0>&, hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*) (.9)' into 'void nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>(hls::stream, 24u>, 0>&, hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config37>(nnet::array, 8u>::value_type (*) [config37::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config37_mult::weight_t*, config37_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 8u>, config37>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*) (.5)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config58_mult::weight_t*, config58_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const (.4)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:100:13) +INFO: [HLS 214-131] Inlining function 'nnet::array, 1u>::operator[](unsigned long) (.2)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:110:2) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.3)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:104:2) +INFO: [HLS 214-131] Inlining function 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' into 'void nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>(hls::stream, 8u>, 0>&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv2d_stream.h:86:21) +INFO: [HLS 214-291] Loop 'SigmoidPackLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_activation_stream.h:88:9) +INFO: [HLS 214-291] Loop 'MultLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_dense_resource.h:55:9) +INFO: [HLS 214-291] Loop 'ReLUPackLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_activation_stream.h:49:9) +INFO: [HLS 214-291] Loop 'MultLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_dense_resource.h:142:9) +INFO: [HLS 214-291] Loop 'KernelPushHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:205:5) +INFO: [HLS 214-291] Loop 'KernelPushChannel' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:208:9) +INFO: [HLS 214-291] Loop 'KernelShiftWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:189:5) +INFO: [HLS 214-291] Loop 'KernelShiftHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:192:9) +INFO: [HLS 214-291] Loop 'KernelShiftChannel' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:194:13) +INFO: [HLS 214-291] Loop 'LineBufferDataIn' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:236:5) +INFO: [HLS 214-291] Loop 'LineBufferShift' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:239:9) +INFO: [HLS 214-291] Loop 'UpdateBuffer' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:228:5) +INFO: [HLS 214-291] Loop 'ConcatPackInput1' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_merge_stream.h:245:13) +INFO: [HLS 214-291] Loop 'ConcatPackInput2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_merge_stream.h:251:13) +INFO: [HLS 214-291] Loop 'ImageWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:22:9) +INFO: [HLS 214-291] Loop 'ImageChan' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:28:13) +INFO: [HLS 214-291] Loop 'ResizeHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:36:9) +INFO: [HLS 214-291] Loop 'ImageWidth2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:40:13) +INFO: [HLS 214-291] Loop 'ResizeWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:44:17) +INFO: [HLS 214-291] Loop 'ResizeChan' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:51:21) +INFO: [HLS 214-291] Loop 'FiltLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_pooling_stream.h:57:9) +INFO: [HLS 214-291] Loop 'PoolLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_pooling_stream.h:62:13) +INFO: [HLS 214-291] Loop 'ClonePack' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_stream.h:32:9) +INFO: [HLS 214-186] Unrolling loop 'SigmoidPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:88:9) in function 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>' completely with a factor of 1 (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-186] Unrolling loop 'InitData' (firmware/nnet_utils/nnet_sepconv_stream.h:98:5) in function 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>' completely with a factor of 8 (firmware/nnet_utils/nnet_sepconv2d_stream.h:58:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_sepconv_stream.h:108:5) in function 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>' completely with a factor of 1 (firmware/nnet_utils/nnet_sepconv2d_stream.h:58:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config38>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 2 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config37>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config36>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 24u>, config35>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>' completely with a factor of 24 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' completely with a factor of 16 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' completely with a factor of 8 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config32>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config31>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config30>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 48u>, config29>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>' completely with a factor of 48 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' completely with a factor of 32 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' completely with a factor of 16 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config26>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config25>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config24>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 96 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 96u>, config23>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>' completely with a factor of 96 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' completely with a factor of 64 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' completely with a factor of 32 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 8 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 64 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 8 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 64 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 64u>, nnet::array, 64u>, relu_config20>' completely with a factor of 64 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 128 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 64u>, config19>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 64u>, nnet::array, 64u>, relu_config18>' completely with a factor of 64 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config17>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config16>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>' completely with a factor of 32 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config15>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config14>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config13>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config12>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config11>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>' completely with a factor of 16 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config10>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config9>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config8>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 4 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config7>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config6>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>' completely with a factor of 8 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config5>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 2 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config4>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config3>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 1u>, config2>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>' completely with a factor of 1 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 1u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], nnet::array, 1u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(config2_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, config2_mult::weight_t*, config2_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config3>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config3>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(config4_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config4_mult::weight_t*, config4_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config5>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config5>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(config7_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config7_mult::weight_t*, config7_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config8>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config8>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(config9_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config9_mult::weight_t*, config9_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config10>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config10>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(config12_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config12_mult::weight_t*, config12_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config13>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config13>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(config14_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config14_mult::weight_t*, config14_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config15>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config15>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config18>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config18>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], nnet::array, 64u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config20>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config20>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 64u>, config21>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 96u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], nnet::array, 96u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(config23_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config23_mult::weight_t*, config23_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config24>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config24>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(config25_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config25_mult::weight_t*, config25_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config26>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config26>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 32u>, config27>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 48u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], nnet::array, 48u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(config29_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config29_mult::weight_t*, config29_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config30>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config30>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(config31_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config31_mult::weight_t*, config31_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config32>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config32>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 16u>, config33>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 24u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], nnet::array, 24u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(config35_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config35_mult::weight_t*, config35_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config36>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config36>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(config37_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config37_mult::weight_t*, config37_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config38>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config38>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(config58_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config58_mult::weight_t*, config58_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj1EEENS1_IS2_ILi37ELi17ELS3_5ELS4_3ELi0EELj8EEE7config2EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEES6_7config6EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to 'b2': Complete partitioning on dimension 1. (firmware/weights/b2.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b4': Complete partitioning on dimension 1. (firmware/weights/b4.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b7': Complete partitioning on dimension 1. (firmware/weights/b7.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b9': Complete partitioning on dimension 1. (firmware/weights/b9.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b12': Complete partitioning on dimension 1. (firmware/weights/b12.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b14': Complete partitioning on dimension 1. (firmware/weights/b14.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b17': Complete partitioning on dimension 1. (firmware/weights/b17.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b19': Complete partitioning on dimension 1. (firmware/weights/b19.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b23': Complete partitioning on dimension 1. (firmware/weights/b23.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b25': Complete partitioning on dimension 1. (firmware/weights/b25.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b29': Complete partitioning on dimension 1. (firmware/weights/b29.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b31': Complete partitioning on dimension 1. (firmware/weights/b31.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b35': Complete partitioning on dimension 1. (firmware/weights/b35.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b37': Complete partitioning on dimension 1. (firmware/weights/b37.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'w39': Complete partitioning on dimension 1. (firmware/weights/w39.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b39': Complete partitioning on dimension 1. (firmware/weights/b39.h:12:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEES6_7config6EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj1EEENS1_IS2_ILi37ELi17ELS3_5ELS4_3ELi0EELj8EEE7config2EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to 'acc': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_dense_resource.h:110:32) +INFO: [HLS 214-248] Applying array_partition to 'res_out': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:274:29) +INFO: [HLS 214-248] Applying array_partition to 'shift_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv_stream.h:224:30) +INFO: [HLS 214-248] Applying array_partition to 'data.i': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_sepconv_stream.h:88:30) +INFO: [HLS 214-248] Applying array_partition to 'res.i': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_sepconv_stream.h:91:29) +WARNING: [HLS 214-322] Unsuported scalar variable on pragma 'Resource/Bind_Storage', ignore it. (firmware/myproject.cpp:340:5) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer39_out' with compact=bit mode in 36-bits (firmware/myproject.cpp:229:35) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer38_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:226:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer57_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:220:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer36_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:217:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer46_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:85:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer6_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:82:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer41_cpy1' with compact=bit mode in 128-bits (firmware/myproject.cpp:76:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer41_cpy2' with compact=bit mode in 128-bits (firmware/myproject.cpp:79:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer5_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:73:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer45_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:67:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer3_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:64:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer37_out' with compact=bit mode in 320-bits (firmware/myproject.cpp:223:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer4_out' with compact=bit mode in 320-bits (firmware/myproject.cpp:70:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer35_out' with compact=bit mode in 328-bits (firmware/myproject.cpp:214:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer56_out' with compact=bit mode in 384-bits (firmware/myproject.cpp:211:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer34_out' with compact=bit mode in 384-bits (firmware/myproject.cpp:208:30) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer33_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:205:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer32_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:202:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer55_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:196:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer30_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:193:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer48_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:112:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer11_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:109:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer42_cpy1' with compact=bit mode in 256-bits (firmware/myproject.cpp:103:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer42_cpy2' with compact=bit mode in 256-bits (firmware/myproject.cpp:106:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer10_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:100:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer47_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:94:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer8_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:91:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer31_out' with compact=bit mode in 656-bits (firmware/myproject.cpp:199:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer9_out' with compact=bit mode in 656-bits (firmware/myproject.cpp:97:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer29_out' with compact=bit mode in 672-bits (firmware/myproject.cpp:190:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer54_out' with compact=bit mode in 768-bits (firmware/myproject.cpp:187:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer28_out' with compact=bit mode in 768-bits (firmware/myproject.cpp:184:30) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer27_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:181:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer26_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:178:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer53_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:172:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer24_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:169:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer50_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:139:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer16_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:136:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer43_cpy1' with compact=bit mode in 512-bits (firmware/myproject.cpp:130:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer43_cpy2' with compact=bit mode in 512-bits (firmware/myproject.cpp:133:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer15_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:127:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer49_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:121:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer13_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:118:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer25_out' with compact=bit mode in 1344-bits (firmware/myproject.cpp:175:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer14_out' with compact=bit mode in 1344-bits (firmware/myproject.cpp:124:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer23_out' with compact=bit mode in 1376-bits (firmware/myproject.cpp:166:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer52_out' with compact=bit mode in 1536-bits (firmware/myproject.cpp:163:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer22_out' with compact=bit mode in 1536-bits (firmware/myproject.cpp:160:28) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer21_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:157:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer20_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:154:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer51_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:148:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer18_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:145:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer19_out' with compact=bit mode in 2752-bits (firmware/myproject.cpp:151:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer17_out' with compact=bit mode in 2688-bits (firmware/myproject.cpp:142:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer12_out' with compact=bit mode in 1312-bits (firmware/myproject.cpp:115:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer7_out' with compact=bit mode in 640-bits (firmware/myproject.cpp:88:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer2_out' with compact=bit mode in 296-bits (firmware/myproject.cpp:61:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer44_out' with compact=bit mode in 16-bits (firmware/myproject.cpp:58:25) +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::conv_2d_buffer_resource_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_64' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_65' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_66' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_67' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_68' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_69' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_70' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_71' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_72' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_73' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_74' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_75' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_76' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_77' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_78' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_79' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_80' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_81' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_82' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_83' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_84' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_85' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_86' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_87' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_88' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_89' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_90' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_91' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_92' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_93' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_94' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_95' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_64' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_65' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_66' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_67' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_68' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_69' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_70' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_71' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_72' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_73' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_74' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_75' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_76' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_77' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_78' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_79' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_80' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_81' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_82' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_83' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_84' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_85' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_86' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_87' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_88' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_89' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_90' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_91' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_92' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_93' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_94' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_95' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-248] Applying array_reshape to 'w4': Block reshaping with factor 2 on dimension 1. (firmware/weights/w4.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w7': Block reshaping with factor 4 on dimension 1. (firmware/weights/w7.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w9': Block reshaping with factor 8 on dimension 1. (firmware/weights/w9.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w12': Block reshaping with factor 16 on dimension 1. (firmware/weights/w12.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w14': Block reshaping with factor 32 on dimension 1. (firmware/weights/w14.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w17': Block reshaping with factor 64 on dimension 1. (firmware/weights/w17.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w19': Block reshaping with factor 128 on dimension 1. (firmware/weights/w19.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w23': Block reshaping with factor 96 on dimension 1. (firmware/weights/w23.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w25': Block reshaping with factor 32 on dimension 1. (firmware/weights/w25.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w29': Block reshaping with factor 32 on dimension 1. (firmware/weights/w29.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w31': Block reshaping with factor 8 on dimension 1. (firmware/weights/w31.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w35': Block reshaping with factor 8 on dimension 1. (firmware/weights/w35.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w37': Block reshaping with factor 2 on dimension 1. (firmware/weights/w37.h:12:0) +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadTopWidth> at firmware/nnet_utils/nnet_padding_stream.h:53:9 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadMain> at firmware/nnet_utils/nnet_padding_stream.h:59:5 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadBottomWidth> at firmware/nnet_utils/nnet_padding_stream.h:77:9 +INFO: [HLS 214-291] Loop 'CopyMain' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_padding_stream.h:65:9) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-270] Inferring pragma 'array_partition type=complete dim=1' for array 'ref.tmp.i' due to pipeline pragma +INFO: [HLS 214-248] Applying array_partition to 'ref.tmp.i': Complete partitioning on dimension 1. +INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 265.42 seconds. CPU system time: 5.18 seconds. Elapsed time: 260.69 seconds; current allocated memory: 350.953 MB. +INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 351.023 MB. +INFO: [HLS 200-10] Starting code transformations ... +INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 27.56 seconds. CPU system time: 0.05 seconds. Elapsed time: 27.62 seconds; current allocated memory: 417.805 MB. +INFO: [HLS 200-10] Checking synthesizability ... +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 97.14 seconds. CPU system time: 0.06 seconds. Elapsed time: 97.2 seconds; current allocated memory: 512.848 MB. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-712] Applying dataflow to function 'myproject' (firmware/myproject.cpp:8), detected/extracted 56 process function(s): + 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>' + 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config3>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config5>' + 'nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>' + 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config8>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config10>' + 'nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>' + 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config13>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config15>' + 'nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>' + 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>' + 'nnet::relu, 64u>, nnet::array, 64u>, relu_config18>' + 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>' + 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>' + 'nnet::relu, 64u>, nnet::array, 64u>, relu_config20>' + 'nnet::resize_nearest, 64u>, config21>' + 'nnet::concatenate3d, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' + 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>' + 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config24>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config26>' + 'nnet::resize_nearest, 32u>, config27>' + 'nnet::concatenate3d, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' + 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>' + 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config30>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config32>' + 'nnet::resize_nearest, 16u>, config33>' + 'nnet::concatenate3d, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' + 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>' + 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config36>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config38>' + 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>' + 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>'. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_activation_stream.h:81:9) to (firmware/nnet_utils/nnet_activation_stream.h:80:5) in function 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>'... converting 3 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>'... converting 17 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>'... converting 17 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>'... converting 33 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>'... converting 37 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>'... converting 19 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>'... converting 19 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>'... converting 18 basic blocks. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' (firmware/nnet_utils/nnet_dense_resource.h:46:5)...96 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...12 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...6 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...6 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...13 expression(s) balanced. +/opt/Xilinx/Vitis_HLS/2024.1/bin/rdiArgs.sh: line 387: 184383 Segmentation fault (core dumped) "$RDI_PROG" "$@" +segfault in /opt/Xilinx/Vitis_HLS/2024.1/bin/unwrapped/lnx64.o/vitis_hls -exec vitis_hls -nolog -run tcl -f /home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl -work_dir /home/ubuntu/lithobench/hls4ml_mini_unet, exiting... +INFO: [vitis-run 60-1662] Stopping dispatch session having empty uuid. diff --git a/logs/hls_run_tcl_20622.backup.log b/logs/hls_run_tcl_20622.backup.log new file mode 100644 index 0000000000000000000000000000000000000000..9e8358007f3f236e784d60f833083673aa9df1e8 --- /dev/null +++ b/logs/hls_run_tcl_20622.backup.log @@ -0,0 +1,170 @@ +INFO: [vitis-run 82-31] Launching vitis_hls: vitis_hls -nolog -run tcl -f /home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl -work_dir /home/ubuntu/lithobench/hls4ml_mini_unet + +****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2024.1 (64-bit) + **** SW Build 5069499 on May 21 2024 + **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 + **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 + **** Start of session at: Mon Mar 30 15:20:26 2026 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. + +source /opt/Xilinx/Vitis_HLS/2024.1/scripts/vitis_hls/hls.tcl -notrace +INFO: [HLS 200-10] For user 'ubuntu' on host 'ip-172-31-42-252.ec2.internal' (Linux_x86_64 version 5.15.0-1084-aws) on Mon Mar 30 15:20:28 UTC 2026 +INFO: [HLS 200-10] On os Ubuntu 20.04.6 LTS +INFO: [HLS 200-10] In directory '/home/ubuntu/lithobench/hls4ml_mini_unet' +Sourcing Tcl script '/home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl' +INFO: [HLS 200-1510] Running: open_project myproject_prj +INFO: [HLS 200-10] Opening project '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj'. +INFO: [HLS 200-1510] Running: set_top myproject +INFO: [HLS 200-1510] Running: add_files firmware/myproject.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding design file 'firmware/myproject.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb myproject_test.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding test bench file 'myproject_test.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb firmware/weights +INFO: [HLS 200-10] Adding test bench file 'firmware/weights' to the project +INFO: [HLS 200-1510] Running: add_files -tb tb_data +INFO: [HLS 200-10] Adding test bench file 'tb_data' to the project +INFO: [HLS 200-1510] Running: open_solution solution1 +INFO: [HLS 200-10] Opening solution '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1'. +INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. +INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 1.35ns. +INFO: [HLS 200-1611] Setting target device to 'xcvu47p-fsvh2892-2L-e' +INFO: [HLS 200-1505] Using flow_target 'vivado' +Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1505.html +INFO: [HLS 200-1464] Running solution command: config_compile -name_max_length=80 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_compile -complex-mul-dsp=0 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_compile -unsafe_math_optimizations=0 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_schedule -enable_dsp_full_reg=0 +INFO: [HLS 200-1464] Running solution command: config_array_partition -complete_threshold=4096 +INFO: [XFORM 203-102] Size-based automatic array partition enabled: cut-off elements per dimension is 4096. +INFO: [HLS 200-1510] Running: config_array_partition -maximum_size 4096 +ERROR: [HLS 200-101] config_array_partition: Unknown option '-maximum_size'. +ERROR: [HLS 200-101] config_array_partition: Unknown option '4096'. +SYNTAX + config_array_partition [OPTIONS] + -auto_partition_threshold *** DEPRECATED*** + -auto_promotion_threshold *** DEPRECATED*** + -complete_threshold + -throughput_driven + +SEE ALSO + INI: syn.array_partition.complete_threshold syn.array_partition.throughput_driven + docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1399-vitis-hls&resourceid=vyw1583260160301.html + +INFO: [HLS 200-1510] Running: config_compile -name_max_length 80 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: set_part xcvu47p-fsvh2892-2L-e +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: config_schedule -enable_dsp_full_reg=false +INFO: [HLS 200-1510] Running: create_clock -period 5 -name default +INFO: [HLS 200-1510] Running: set_clock_uncertainty 27% default +***** C/RTL SYNTHESIS ***** +INFO: [HLS 200-1510] Running: csynth_design +INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 276.859 MB. +INFO: [HLS 200-10] Analyzing design file 'firmware/myproject.cpp' ... +WARNING: [HLS 207-5570] unexpected pragma argument 'softmax', expects function/operation (firmware/nnet_utils/nnet_activation.h:402:36) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:33:9) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:107:9) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:189:9) +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:242:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:242:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:248:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:248:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:258:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:258:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:264:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:264:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:274:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:274:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:280:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:280:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:290:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:290:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:296:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:296:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:306:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:306:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:312:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:312:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:322:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:322:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:328:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:328:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:338:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:338:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:344:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:344:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:348:100) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:348:105) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 200-471] Dataflow form checks found 30 issue(s) in file firmware/myproject.cpp +Resolution: For help on HLS 200-471 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-471.html +WARNING: [HLS 207-5292] unused parameter 'keep' (firmware/nnet_utils/nnet_helpers.h:285:99) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:14:36) +WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:15:36) +WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:16:44) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:24:24) +WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:25:24) +WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:26:32) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:33:30) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:33:58) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:34:51) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:35:49) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:42:30) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:42:58) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:43:51) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:44:49) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:51:29) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:51:80) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:52:50) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:53:48) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_code_gen.h:16:39) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_code_gen.h:17:38) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_code_gen.h:18:60) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_code_gen.h:19:58) +WARNING: [HLS 207-5584] there are more than one pragma inline in the function scope, ignore the pragma (/opt/Xilinx/Vitis_HLS/2024.1/common/technology/autopilot/ap_shift_reg.h:47:9) +INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 36.43 seconds. CPU system time: 2.15 seconds. Elapsed time: 38.64 seconds; current allocated memory: 287.945 MB. +INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target. +INFO: [HLS 200-1995] There were 28,390 instructions in the design after the 'Compile/Link' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 282,347 instructions in the design after the 'Unroll/Inline' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 127,448 instructions in the design after the 'Unroll/Inline (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 102,013 instructions in the design after the 'Unroll/Inline (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 53,117 instructions in the design after the 'Unroll/Inline (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 69,335 instructions in the design after the 'Array/Struct' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 50,968 instructions in the design after the 'Array/Struct (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 51,867 instructions in the design after the 'Array/Struct (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 106,651 instructions in the design after the 'Array/Struct (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 97,860 instructions in the design after the 'Array/Struct (step 5)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 99,568 instructions in the design after the 'Performance' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt diff --git a/logs/hls_run_tcl_21278.backup.log b/logs/hls_run_tcl_21278.backup.log new file mode 100644 index 0000000000000000000000000000000000000000..3258c4fb43735ef061efb08d520c04e7758834f4 --- /dev/null +++ b/logs/hls_run_tcl_21278.backup.log @@ -0,0 +1,104 @@ +INFO: [vitis-run 82-31] Launching vitis_hls: vitis_hls -nolog -run tcl -f /home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl -work_dir /home/ubuntu/lithobench/hls4ml_mini_unet + +****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2024.1 (64-bit) + **** SW Build 5069499 on May 21 2024 + **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 + **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 + **** Start of session at: Mon Mar 30 15:35:30 2026 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. + +source /opt/Xilinx/Vitis_HLS/2024.1/scripts/vitis_hls/hls.tcl -notrace +INFO: [HLS 200-10] For user 'ubuntu' on host 'ip-172-31-42-252.ec2.internal' (Linux_x86_64 version 5.15.0-1084-aws) on Mon Mar 30 15:35:32 UTC 2026 +INFO: [HLS 200-10] On os Ubuntu 20.04.6 LTS +INFO: [HLS 200-10] In directory '/home/ubuntu/lithobench/hls4ml_mini_unet' +Sourcing Tcl script '/home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl' +INFO: [HLS 200-1510] Running: open_project myproject_prj +INFO: [HLS 200-10] Opening project '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj'. +INFO: [HLS 200-1510] Running: set_top myproject +INFO: [HLS 200-1510] Running: add_files firmware/myproject.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding design file 'firmware/myproject.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb myproject_test.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding test bench file 'myproject_test.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb firmware/weights +INFO: [HLS 200-10] Adding test bench file 'firmware/weights' to the project +INFO: [HLS 200-1510] Running: add_files -tb tb_data +INFO: [HLS 200-10] Adding test bench file 'tb_data' to the project +INFO: [HLS 200-1510] Running: open_solution solution1 +INFO: [HLS 200-10] Opening solution '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1'. +INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. +INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 1.35ns. +INFO: [HLS 200-1611] Setting target device to 'xcvu47p-fsvh2892-2L-e' +INFO: [HLS 200-1505] Using flow_target 'vivado' +Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1505.html +INFO: [HLS 200-1464] Running solution command: config_compile -name_max_length=80 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_compile -complex-mul-dsp=0 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_compile -unsafe_math_optimizations=0 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_schedule -enable_dsp_full_reg=0 +INFO: [HLS 200-1464] Running solution command: config_array_partition -complete_threshold=4096 +INFO: [XFORM 203-102] Size-based automatic array partition enabled: cut-off elements per dimension is 4096. +INFO: [HLS 200-1510] Running: config_array_partition -maximum_size 4096 +ERROR: [HLS 200-101] config_array_partition: Unknown option '-maximum_size'. +ERROR: [HLS 200-101] config_array_partition: Unknown option '4096'. +SYNTAX + config_array_partition [OPTIONS] + -auto_partition_threshold *** DEPRECATED*** + -auto_promotion_threshold *** DEPRECATED*** + -complete_threshold + -throughput_driven + +SEE ALSO + INI: syn.array_partition.complete_threshold syn.array_partition.throughput_driven + docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1399-vitis-hls&resourceid=vyw1583260160301.html + +INFO: [HLS 200-1510] Running: config_compile -name_max_length 80 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: set_part xcvu47p-fsvh2892-2L-e +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: config_schedule -enable_dsp_full_reg=false +INFO: [HLS 200-1510] Running: create_clock -period 5 -name default +INFO: [HLS 200-1510] Running: set_clock_uncertainty 27% default +***** C/RTL SYNTHESIS ***** +INFO: [HLS 200-1510] Running: config_compile -expression_balance off +ERROR: [HLS 200-101] config_compile: Unknown option '-expression_balance'. +ERROR: [HLS 200-101] config_compile: Unknown option 'off'. +SYNTAX + config_compile [OPTIONS] + -design_size_maximum_warning + -enable_auto_rewind [=false|*true*] + -ignore_long_run_time [=true|*false*] + -name_max_length + -no_signed_zeros [=true|*false*] + -pipeline_flush_in_task + -pipeline_loops + -pipeline_style + -pragma_strict_mode [=true|*false*] + -pre_tcl + -unsafe_math_optimizations [=true|*false*] + +SEE ALSO + INI: syn.compile.* + docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1399-vitis-hls&resourceid=vyw1583260160301.html + + + invoked from within +"config_compile -expression_balance off" + invoked from within +"if {$opt(synth)} { + puts "***** C/RTL SYNTHESIS *****" + + set time_start [clock clicks -milliseconds] + config_compile -expression_balance off +..." + (file "/home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl" line 165) + invoked from within +"source /home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl" + ("uplevel" body line 1) + invoked from within +"uplevel \#0 [list source $tclfile] " + +INFO: [HLS 200-112] Total CPU user time: 2.3 seconds. Total CPU system time: 0.34 seconds. Total elapsed time: 2.46 seconds; peak allocated memory: 276.859 MB. +INFO: [vitis-run 60-1662] Stopping dispatch session having empty uuid. diff --git a/logs/hls_run_tcl_450811.backup.log b/logs/hls_run_tcl_450811.backup.log new file mode 100644 index 0000000000000000000000000000000000000000..1af4ea8ab8a971bc176bff1b4208a9e3049c243f --- /dev/null +++ b/logs/hls_run_tcl_450811.backup.log @@ -0,0 +1,10389 @@ +INFO: [vitis-run 82-31] Launching vitis_hls: vitis_hls -nolog -run tcl -f /home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl -work_dir /home/ubuntu/lithobench/hls4ml_mini_unet + +****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2024.1 (64-bit) + **** SW Build 5069499 on May 21 2024 + **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 + **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 + **** Start of session at: Sat Apr 4 21:27:53 2026 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. + +source /opt/Xilinx/Vitis_HLS/2024.1/scripts/vitis_hls/hls.tcl -notrace +INFO: [HLS 200-10] For user 'ubuntu' on host 'ip-172-31-42-252.ec2.internal' (Linux_x86_64 version 5.15.0-1084-aws) on Sat Apr 04 21:27:55 UTC 2026 +INFO: [HLS 200-10] On os Ubuntu 20.04.6 LTS +INFO: [HLS 200-10] In directory '/home/ubuntu/lithobench/hls4ml_mini_unet' +Sourcing Tcl script '/home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl' +INFO: [HLS 200-1510] Running: open_project myproject_prj +INFO: [HLS 200-10] Opening project '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj'. +INFO: [HLS 200-1510] Running: set_top myproject +INFO: [HLS 200-1510] Running: add_files firmware/myproject.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding design file 'firmware/myproject.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb myproject_test.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding test bench file 'myproject_test.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb firmware/weights +INFO: [HLS 200-10] Adding test bench file 'firmware/weights' to the project +INFO: [HLS 200-1510] Running: add_files -tb tb_data +INFO: [HLS 200-10] Adding test bench file 'tb_data' to the project +INFO: [HLS 200-1510] Running: open_solution solution1 +INFO: [HLS 200-10] Opening solution '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1'. +INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. +INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 1.35ns. +INFO: [HLS 200-1611] Setting target device to 'xcvu47p-fsvh2892-2L-e' +INFO: [HLS 200-1505] Using flow_target 'vivado' +Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1505.html +INFO: [HLS 200-1464] Running solution command: config_compile -name_max_length=80 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_compile -complex-mul-dsp=0 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_compile -unsafe_math_optimizations=0 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_schedule -enable_dsp_full_reg=0 +INFO: [HLS 200-1464] Running solution command: config_array_partition -complete_threshold=4096 +INFO: [XFORM 203-102] Size-based automatic array partition enabled: cut-off elements per dimension is 4096. +INFO: [HLS 200-1510] Running: config_array_partition -maximum_size 4096 +ERROR: [HLS 200-101] config_array_partition: Unknown option '-maximum_size'. +ERROR: [HLS 200-101] config_array_partition: Unknown option '4096'. +SYNTAX + config_array_partition [OPTIONS] + -auto_partition_threshold *** DEPRECATED*** + -auto_promotion_threshold *** DEPRECATED*** + -complete_threshold + -throughput_driven + +SEE ALSO + INI: syn.array_partition.complete_threshold syn.array_partition.throughput_driven + docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1399-vitis-hls&resourceid=vyw1583260160301.html + +INFO: [HLS 200-1510] Running: config_compile -name_max_length 80 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: set_part xcvu47p-fsvh2892-2L-e +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: config_schedule -enable_dsp_full_reg=false +INFO: [HLS 200-1510] Running: create_clock -period 5 -name default +INFO: [HLS 200-1510] Running: set_clock_uncertainty 27% default +***** C/RTL SYNTHESIS ***** +INFO: [HLS 200-1510] Running: csynth_design +INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0.08 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.21 seconds; current allocated memory: 276.809 MB. +INFO: [HLS 200-10] Analyzing design file 'firmware/myproject.cpp' ... +WARNING: [HLS 207-5570] unexpected pragma argument 'softmax', expects function/operation (firmware/nnet_utils/nnet_activation.h:402:36) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:33:9) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:107:9) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:189:9) +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:234:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:234:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:240:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:240:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:250:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:250:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:256:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:256:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:266:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:266:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:272:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:272:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:282:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:282:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:288:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:288:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:298:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:298:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:304:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:304:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:314:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:314:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:320:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:320:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:330:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:330:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:336:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:336:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:340:100) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:340:105) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 200-471] Dataflow form checks found 30 issue(s) in file firmware/myproject.cpp +Resolution: For help on HLS 200-471 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-471.html +WARNING: [HLS 207-5292] unused parameter 'keep' (firmware/nnet_utils/nnet_helpers.h:285:99) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:14:36) +WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:15:36) +WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:16:44) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:24:24) +WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:25:24) +WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:26:32) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:33:30) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:33:58) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:34:51) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:35:49) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:42:30) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:42:58) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:43:51) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:44:49) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:51:29) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:51:80) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:52:50) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:53:48) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_code_gen.h:16:39) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_code_gen.h:17:38) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_code_gen.h:18:60) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_code_gen.h:19:58) +WARNING: [HLS 207-5584] there are more than one pragma inline in the function scope, ignore the pragma (/opt/Xilinx/Vitis_HLS/2024.1/common/technology/autopilot/ap_shift_reg.h:47:9) +INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 37.03 seconds. CPU system time: 2.34 seconds. Elapsed time: 40.27 seconds; current allocated memory: 287.910 MB. +INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target. +INFO: [HLS 200-1995] There were 28,299 instructions in the design after the 'Compile/Link' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 169,202 instructions in the design after the 'Unroll/Inline' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 90,029 instructions in the design after the 'Unroll/Inline (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 78,923 instructions in the design after the 'Unroll/Inline (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 35,354 instructions in the design after the 'Unroll/Inline (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 53,132 instructions in the design after the 'Array/Struct' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 39,560 instructions in the design after the 'Array/Struct (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 40,455 instructions in the design after the 'Array/Struct (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 85,724 instructions in the design after the 'Array/Struct (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 83,664 instructions in the design after the 'Array/Struct (step 5)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 85,310 instructions in the design after the 'Performance' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 196,081 instructions in the design after the 'Performance (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 193,395 instructions in the design after the 'Performance (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 193,395 instructions in the design after the 'Performance (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 154,571 instructions in the design after the 'HW Transforms' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 146,893 instructions in the design after the 'HW Transforms (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>' (firmware/nnet_utils/nnet_sepconv_stream.h:103:9) +WARNING: [HLS 214-273] In function 'void nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config58_mult::weight_t*, config58_mult::bias_t*)', Pragma conflict happens on 'INLINE' and 'FUNCTION_INSTANTIATE' pragmas: same function (firmware/nnet_utils/nnet_dense_resource.h:15:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config44>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 1u>, config2>(nnet::array, 1u>::value_type (*) [config2::n_chan], nnet::array, 1u>::value_type*)' into 'void nnet::shift_line_buffer, 1u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], nnet::array, 1u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, config2_mult::weight_t*, config2_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*) (.55)' into 'void nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config45>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config4>(nnet::array, 8u>::value_type (*) [config4::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config4_mult::weight_t*, config4_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 8u>, config4>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*) (.54)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config6>(nnet::array, 8u>::value_type (*) [config6::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::Op_max >::operator()(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>) (.36)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' (firmware/nnet_utils/nnet_common.h:44:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:15) +INFO: [HLS 214-131] Inlining function 'nnet::Op_max >::operator()(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>) (.36)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:12) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:44) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config6>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.52)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config6>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.52)' into 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 8u>::operator[](unsigned long) (.51)' into 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' into 'void nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config46>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config7>(nnet::array, 8u>::value_type (*) [config7::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config7_mult::weight_t*, config7_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 16u>, config7>(hls::stream, 8u>, 0>&, hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*) (.48)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>(hls::stream, 8u>, 0>&, hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config47>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config9>(nnet::array, 16u>::value_type (*) [config9::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config9_mult::weight_t*, config9_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 16u>, config9>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*) (.47)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config11>(nnet::array, 16u>::value_type (*) [config11::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config11>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.45)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config11>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.45)' into 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 16u>::operator[](unsigned long) (.44)' into 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' into 'void nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config48>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config12>(nnet::array, 16u>::value_type (*) [config12::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config12_mult::weight_t*, config12_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 32u>, config12>(hls::stream, 16u>, 0>&, hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*) (.41)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>(hls::stream, 16u>, 0>&, hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config49>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config14>(nnet::array, 32u>::value_type (*) [config14::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config14_mult::weight_t*, config14_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 32u>, config14>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*) (.40)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config16>(nnet::array, 32u>::value_type (*) [config16::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config16>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.34)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config16>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.34)' into 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 32u>::operator[](unsigned long) (.33)' into 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' into 'void nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config50>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config17>(nnet::array, 32u>::value_type (*) [config17::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config17_mult::weight_t*, config17_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 64u>, config17>(hls::stream, 32u>, 0>&, hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*) (.30)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>(hls::stream, 32u>, 0>&, hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config51>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 64u>, config19>(nnet::array, 64u>::value_type (*) [config19::n_chan], nnet::array, 64u>::value_type*)' into 'void nnet::shift_line_buffer, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], nnet::array, 64u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config19_mult::weight_t*, config19_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 64u>, nnet::array, 64u>, config19>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*) (.26)' into 'void nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config52>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 96u>, config23>(nnet::array, 96u>::value_type (*) [config23::n_chan], nnet::array, 96u>::value_type*)' into 'void nnet::shift_line_buffer, 96u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], nnet::array, 96u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config23_mult::weight_t*, config23_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 96u>, nnet::array, 32u>, config23>(hls::stream, 96u>, 0>&, hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*) (.23)' into 'void nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>(hls::stream, 96u>, 0>&, hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config53>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config25>(nnet::array, 32u>::value_type (*) [config25::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config25_mult::weight_t*, config25_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 32u>, config25>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*) (.19)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config54>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 48u>, config29>(nnet::array, 48u>::value_type (*) [config29::n_chan], nnet::array, 48u>::value_type*)' into 'void nnet::shift_line_buffer, 48u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], nnet::array, 48u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config29_mult::weight_t*, config29_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 48u>, nnet::array, 16u>, config29>(hls::stream, 48u>, 0>&, hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*) (.16)' into 'void nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>(hls::stream, 48u>, 0>&, hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config55>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config31>(nnet::array, 16u>::value_type (*) [config31::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config31_mult::weight_t*, config31_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 16u>, config31>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*) (.12)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config56>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 24u>, config35>(nnet::array, 24u>::value_type (*) [config35::n_chan], nnet::array, 24u>::value_type*)' into 'void nnet::shift_line_buffer, 24u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], nnet::array, 24u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config35_mult::weight_t*, config35_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 24u>, nnet::array, 8u>, config35>(hls::stream, 24u>, 0>&, hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*) (.9)' into 'void nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>(hls::stream, 24u>, 0>&, hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config57>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config37>(nnet::array, 8u>::value_type (*) [config37::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config37_mult::weight_t*, config37_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 8u>, config37>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*) (.5)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config58_mult::weight_t*, config58_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const (.4)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:100:13) +INFO: [HLS 214-131] Inlining function 'nnet::array, 1u>::operator[](unsigned long) (.2)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:110:2) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.3)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:104:2) +INFO: [HLS 214-131] Inlining function 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config58>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' into 'void nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>(hls::stream, 8u>, 0>&, hls::stream, 1u>, 0>&, config58::weight_t*, config58::bias_t*)' (firmware/nnet_utils/nnet_sepconv2d_stream.h:86:21) +INFO: [HLS 214-291] Loop 'SigmoidPackLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_activation_stream.h:88:9) +INFO: [HLS 214-291] Loop 'MultLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_dense_resource.h:55:9) +INFO: [HLS 214-291] Loop 'ReLUPackLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_activation_stream.h:49:9) +INFO: [HLS 214-291] Loop 'MultLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_dense_resource.h:142:9) +INFO: [HLS 214-291] Loop 'KernelPushHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:205:5) +INFO: [HLS 214-291] Loop 'KernelPushChannel' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:208:9) +INFO: [HLS 214-291] Loop 'KernelShiftWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:189:5) +INFO: [HLS 214-291] Loop 'KernelShiftHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:192:9) +INFO: [HLS 214-291] Loop 'KernelShiftChannel' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:194:13) +INFO: [HLS 214-291] Loop 'LineBufferDataIn' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:236:5) +INFO: [HLS 214-291] Loop 'LineBufferShift' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:239:9) +INFO: [HLS 214-291] Loop 'UpdateBuffer' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:228:5) +INFO: [HLS 214-291] Loop 'ConcatPackInput1' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_merge_stream.h:245:13) +INFO: [HLS 214-291] Loop 'ConcatPackInput2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_merge_stream.h:251:13) +INFO: [HLS 214-291] Loop 'ImageWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:22:9) +INFO: [HLS 214-291] Loop 'ImageChan' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:28:13) +INFO: [HLS 214-291] Loop 'ResizeHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:36:9) +INFO: [HLS 214-291] Loop 'ImageWidth2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:40:13) +INFO: [HLS 214-291] Loop 'ResizeWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:44:17) +INFO: [HLS 214-291] Loop 'ResizeChan' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:51:21) +INFO: [HLS 214-291] Loop 'FiltLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_pooling_stream.h:57:9) +INFO: [HLS 214-291] Loop 'PoolLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_pooling_stream.h:62:13) +INFO: [HLS 214-291] Loop 'ClonePack' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_stream.h:32:9) +INFO: [HLS 214-186] Unrolling loop 'SigmoidPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:88:9) in function 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>' completely with a factor of 1 (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-186] Unrolling loop 'InitData' (firmware/nnet_utils/nnet_sepconv_stream.h:98:5) in function 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>' completely with a factor of 8 (firmware/nnet_utils/nnet_sepconv2d_stream.h:58:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_sepconv_stream.h:108:5) in function 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>' completely with a factor of 1 (firmware/nnet_utils/nnet_sepconv2d_stream.h:58:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config38>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 2 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config37>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config36>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 24u>, config35>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>' completely with a factor of 24 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' completely with a factor of 16 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' completely with a factor of 8 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config32>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 4 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config31>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config30>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 48u>, config29>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>' completely with a factor of 48 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' completely with a factor of 32 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' completely with a factor of 16 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config26>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config25>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config24>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 96u>, config23>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>' completely with a factor of 96 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' completely with a factor of 64 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' completely with a factor of 32 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 8 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 64 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 8 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 64 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 64u>, nnet::array, 64u>, relu_config20>' completely with a factor of 64 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 64u>, config19>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 64u>, nnet::array, 64u>, relu_config18>' completely with a factor of 64 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config17>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config16>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>' completely with a factor of 32 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config15>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config14>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config13>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config12>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config11>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>' completely with a factor of 16 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config10>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config9>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config8>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config7>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config6>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>' completely with a factor of 8 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config5>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 4 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config4>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config3>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 1u>, config2>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>' completely with a factor of 1 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 1u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], nnet::array, 1u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(config2_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, config2_mult::weight_t*, config2_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config3>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config3>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(config4_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config4_mult::weight_t*, config4_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config5>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config5>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(config7_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config7_mult::weight_t*, config7_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config8>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config8>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(config9_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config9_mult::weight_t*, config9_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config10>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config10>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(config12_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config12_mult::weight_t*, config12_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config13>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config13>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(config14_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config14_mult::weight_t*, config14_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config15>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config15>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config18>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config18>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], nnet::array, 64u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config20>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config20>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 64u>, config21>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 96u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], nnet::array, 96u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(config23_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config23_mult::weight_t*, config23_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config24>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config24>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(config25_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config25_mult::weight_t*, config25_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config26>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config26>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 32u>, config27>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 48u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], nnet::array, 48u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(config29_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config29_mult::weight_t*, config29_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config30>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config30>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(config31_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config31_mult::weight_t*, config31_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config32>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config32>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 16u>, config33>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 24u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], nnet::array, 24u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(config35_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config35_mult::weight_t*, config35_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config36>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config36>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(config37_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config37_mult::weight_t*, config37_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config38>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config38>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(config58_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config58_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config58_mult::weight_t*, config58_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj1EEENS1_IS2_ILi37ELi17ELS3_5ELS4_3ELi0EELj8EEE7config2EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEES6_7config6EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to 'b2': Complete partitioning on dimension 1. (firmware/weights/b2.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b4': Complete partitioning on dimension 1. (firmware/weights/b4.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b7': Complete partitioning on dimension 1. (firmware/weights/b7.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b9': Complete partitioning on dimension 1. (firmware/weights/b9.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b12': Complete partitioning on dimension 1. (firmware/weights/b12.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b14': Complete partitioning on dimension 1. (firmware/weights/b14.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b17': Complete partitioning on dimension 1. (firmware/weights/b17.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b19': Complete partitioning on dimension 1. (firmware/weights/b19.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b23': Complete partitioning on dimension 1. (firmware/weights/b23.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b25': Complete partitioning on dimension 1. (firmware/weights/b25.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b29': Complete partitioning on dimension 1. (firmware/weights/b29.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b31': Complete partitioning on dimension 1. (firmware/weights/b31.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b35': Complete partitioning on dimension 1. (firmware/weights/b35.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b37': Complete partitioning on dimension 1. (firmware/weights/b37.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'w39': Complete partitioning on dimension 1. (firmware/weights/w39.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b39': Complete partitioning on dimension 1. (firmware/weights/b39.h:12:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEES6_7config6EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj1EEENS1_IS2_ILi37ELi17ELS3_5ELS4_3ELi0EELj8EEE7config2EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to 'acc': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_dense_resource.h:110:32) +INFO: [HLS 214-248] Applying array_partition to 'res_out': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:274:29) +INFO: [HLS 214-248] Applying array_partition to 'shift_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv_stream.h:224:30) +INFO: [HLS 214-248] Applying array_partition to 'data.i': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_sepconv_stream.h:88:30) +INFO: [HLS 214-248] Applying array_partition to 'res.i': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_sepconv_stream.h:91:29) +WARNING: [HLS 214-322] Unsuported scalar variable on pragma 'Resource/Bind_Storage', ignore it. (firmware/myproject.cpp:340:5) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer39_out' with compact=bit mode in 36-bits (firmware/myproject.cpp:229:35) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer38_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:226:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer57_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:220:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer36_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:217:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer46_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:85:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer6_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:82:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer41_cpy1' with compact=bit mode in 128-bits (firmware/myproject.cpp:76:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer41_cpy2' with compact=bit mode in 128-bits (firmware/myproject.cpp:79:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer5_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:73:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer45_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:67:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer3_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:64:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer37_out' with compact=bit mode in 320-bits (firmware/myproject.cpp:223:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer4_out' with compact=bit mode in 320-bits (firmware/myproject.cpp:70:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer35_out' with compact=bit mode in 328-bits (firmware/myproject.cpp:214:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer56_out' with compact=bit mode in 384-bits (firmware/myproject.cpp:211:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer34_out' with compact=bit mode in 384-bits (firmware/myproject.cpp:208:30) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer33_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:205:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer32_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:202:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer55_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:196:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer30_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:193:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer48_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:112:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer11_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:109:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer42_cpy1' with compact=bit mode in 256-bits (firmware/myproject.cpp:103:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer42_cpy2' with compact=bit mode in 256-bits (firmware/myproject.cpp:106:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer10_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:100:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer47_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:94:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer8_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:91:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer31_out' with compact=bit mode in 656-bits (firmware/myproject.cpp:199:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer9_out' with compact=bit mode in 656-bits (firmware/myproject.cpp:97:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer29_out' with compact=bit mode in 672-bits (firmware/myproject.cpp:190:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer54_out' with compact=bit mode in 768-bits (firmware/myproject.cpp:187:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer28_out' with compact=bit mode in 768-bits (firmware/myproject.cpp:184:30) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer27_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:181:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer26_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:178:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer53_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:172:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer24_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:169:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer50_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:139:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer16_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:136:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer43_cpy1' with compact=bit mode in 512-bits (firmware/myproject.cpp:130:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer43_cpy2' with compact=bit mode in 512-bits (firmware/myproject.cpp:133:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer15_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:127:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer49_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:121:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer13_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:118:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer25_out' with compact=bit mode in 1344-bits (firmware/myproject.cpp:175:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer14_out' with compact=bit mode in 1344-bits (firmware/myproject.cpp:124:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer23_out' with compact=bit mode in 1376-bits (firmware/myproject.cpp:166:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer52_out' with compact=bit mode in 1536-bits (firmware/myproject.cpp:163:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer22_out' with compact=bit mode in 1536-bits (firmware/myproject.cpp:160:28) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer21_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:157:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer20_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:154:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer51_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:148:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer18_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:145:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer19_out' with compact=bit mode in 2752-bits (firmware/myproject.cpp:151:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer17_out' with compact=bit mode in 2688-bits (firmware/myproject.cpp:142:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer12_out' with compact=bit mode in 1312-bits (firmware/myproject.cpp:115:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer7_out' with compact=bit mode in 640-bits (firmware/myproject.cpp:88:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer2_out' with compact=bit mode in 296-bits (firmware/myproject.cpp:61:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer44_out' with compact=bit mode in 16-bits (firmware/myproject.cpp:58:25) +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::conv_2d_buffer_resource_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_64' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_65' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_66' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_67' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_68' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_69' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_70' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_71' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_72' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_73' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_74' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_75' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_76' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_77' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_78' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_79' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_80' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_81' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_82' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_83' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_84' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_85' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_86' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_87' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_88' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_89' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_90' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_91' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_92' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_93' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_94' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_95' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_64' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_65' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_66' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_67' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_68' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_69' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_70' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_71' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_72' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_73' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_74' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_75' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_76' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_77' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_78' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_79' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_80' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_81' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_82' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_83' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_84' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_85' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_86' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_87' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_88' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_89' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_90' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_91' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_92' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_93' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_94' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_95' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-248] Applying array_reshape to 'w4': Block reshaping with factor 4 on dimension 1. (firmware/weights/w4.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w7': Block reshaping with factor 8 on dimension 1. (firmware/weights/w7.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w9': Block reshaping with factor 16 on dimension 1. (firmware/weights/w9.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w12': Block reshaping with factor 8 on dimension 1. (firmware/weights/w12.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w14': Block reshaping with factor 16 on dimension 1. (firmware/weights/w14.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w17': Block reshaping with factor 16 on dimension 1. (firmware/weights/w17.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w19': Block reshaping with factor 32 on dimension 1. (firmware/weights/w19.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w23': Block reshaping with factor 32 on dimension 1. (firmware/weights/w23.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w25': Block reshaping with factor 8 on dimension 1. (firmware/weights/w25.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w29': Block reshaping with factor 16 on dimension 1. (firmware/weights/w29.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w31': Block reshaping with factor 4 on dimension 1. (firmware/weights/w31.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w35': Block reshaping with factor 8 on dimension 1. (firmware/weights/w35.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w37': Block reshaping with factor 2 on dimension 1. (firmware/weights/w37.h:12:0) +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadTopWidth> at firmware/nnet_utils/nnet_padding_stream.h:53:9 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadMain> at firmware/nnet_utils/nnet_padding_stream.h:59:5 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadBottomWidth> at firmware/nnet_utils/nnet_padding_stream.h:77:9 +INFO: [HLS 214-291] Loop 'CopyMain' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_padding_stream.h:65:9) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-270] Inferring pragma 'array_partition type=complete dim=1' for array 'ref.tmp.i' due to pipeline pragma +INFO: [HLS 214-248] Applying array_partition to 'ref.tmp.i': Complete partitioning on dimension 1. +INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 297.86 seconds. CPU system time: 5.5 seconds. Elapsed time: 292.33 seconds; current allocated memory: 351.375 MB. +INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 351.445 MB. +INFO: [HLS 200-10] Starting code transformations ... +INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 28.62 seconds. CPU system time: 0.08 seconds. Elapsed time: 28.8 seconds; current allocated memory: 430.660 MB. +INFO: [HLS 200-10] Checking synthesizability ... +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' into 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_dense_resource.h:164) automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' into 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_dense_resource.h:164) automatically. +INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 101.72 seconds. CPU system time: 0.07 seconds. Elapsed time: 101.81 seconds; current allocated memory: 552.094 MB. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' into 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_dense_resource.h:164) automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' into 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_dense_resource.h:164) automatically. +INFO: [XFORM 203-712] Applying dataflow to function 'myproject' (firmware/myproject.cpp:8), detected/extracted 56 process function(s): + 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config44>' + 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config3>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config45>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config5>' + 'nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>' + 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config46>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config8>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config47>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config10>' + 'nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>' + 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config48>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config13>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config49>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config15>' + 'nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>' + 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config50>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>' + 'nnet::relu, 64u>, nnet::array, 64u>, relu_config18>' + 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config51>' + 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>' + 'nnet::relu, 64u>, nnet::array, 64u>, relu_config20>' + 'nnet::resize_nearest, 64u>, config21>' + 'nnet::concatenate3d, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' + 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config52>' + 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config24>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config53>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config26>' + 'nnet::resize_nearest, 32u>, config27>' + 'nnet::concatenate3d, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' + 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config54>' + 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config30>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config55>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config32>' + 'nnet::resize_nearest, 16u>, config33>' + 'nnet::concatenate3d, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' + 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config56>' + 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config36>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config57>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config38>' + 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>' + 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>'. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_activation_stream.h:81:9) to (firmware/nnet_utils/nnet_activation_stream.h:80:5) in function 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>'... converting 3 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>'... converting 65 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>'... converting 73 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>'... converting 145 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>'... converting 33 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>'... converting 37 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>'... converting 73 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>'... converting 17 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>'... converting 9 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>'... converting 19 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>'... converting 18 basic blocks. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...24 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...48 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...12 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...24 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...6 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...13 expression(s) balanced. +INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 246.14 seconds. CPU system time: 0.15 seconds. Elapsed time: 246.31 seconds; current allocated memory: 683.594 MB. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_pooling_stream.h:109:5) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_pooling_stream.h:109:5) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_pooling_stream.h:109:5) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeightSerial' (firmware/nnet_utils/nnet_sepconv2d_stream.h:81:9) in function 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config58>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ConcatLoopHeight' (firmware/nnet_utils/nnet_merge_stream.h:234:5) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ConcatLoopHeight' (firmware/nnet_utils/nnet_merge_stream.h:234:5) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ConcatLoopHeight' (firmware/nnet_utils/nnet_merge_stream.h:234:5) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>'. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config23_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config29_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config9_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config35_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config58_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0,config7_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0,config4_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0,config2_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config23_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config29_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config9_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config35_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config58_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0,config7_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0,config4_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0,config2_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0'. +INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 34.49 seconds. CPU system time: 0.65 seconds. Elapsed time: 35.15 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] Starting hardware synthesis ... +INFO: [HLS 200-10] Synthesizing 'myproject' ... +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,1u>,config44>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,1u>,config44>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config44>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,1u>,config44>' to 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 1u>, config2>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0,config2_mult>' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config2>' to 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config2>' to 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config3>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config45>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config45>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config45>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,8u>,config45>' to 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config4>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0,config4_mult>' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config4>' to 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config4>' to 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config5>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s'. +WARNING: [SYN 201-103] Legalizing function name 'clone_stream,array,8u>,32768>' to 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config6>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +WARNING: [SYN 201-103] Legalizing function name 'pooling2d_cl,array,8u>,config6>' to 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config46>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config46>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config46>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,8u>,config46>' to 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config7>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0,config7_mult>' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config7>' to 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,16u>,config7>' to 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config8>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config47>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config47>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config47>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config47>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config9>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config9_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config9>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,16u>,config9>' to 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config10>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s'. +WARNING: [SYN 201-103] Legalizing function name 'clone_stream,array,16u>,16384>' to 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config11>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +WARNING: [SYN 201-103] Legalizing function name 'pooling2d_cl,16u>,config11>' to 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config48>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config48>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config48>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config48>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config12>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config12>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config12>' to 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config13>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config49>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config49>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config49>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config49>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config14>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config14>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config14>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config15>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s'. +WARNING: [SYN 201-103] Legalizing function name 'clone_stream,array,32u>,8192>' to 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config16>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +WARNING: [SYN 201-103] Legalizing function name 'pooling2d_cl,32u>,config16>' to 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config50>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config50>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config50>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config50>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config17>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,64u>,config17>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,64u>,config17>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,64u>,relu_config18>' to 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config51>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,64u>,config51>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config51>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,64u>,config51>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 64u>, config19>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,64u>,config19>' to 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,64u>,config19>' to 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,64u>,relu_config20>' to 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s'. +WARNING: [SYN 201-103] Legalizing function name 'resize_nearest, 64u>, config21>' to 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d_2,96u>,config22>' to 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d,96u>,config22>' to 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config52>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,96u>,config52>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config52>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,96u>,config52>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 96u>, config23>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config23_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config23>' to 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config23>' to 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config24>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config53>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config53>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config53>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config53>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config25>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config25>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config25>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config26>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s'. +WARNING: [SYN 201-103] Legalizing function name 'resize_nearest, 32u>, config27>' to 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d_2,48u>,config28>' to 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d,48u>,config28>' to 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config54>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,48u>,config54>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config54>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,48u>,config54>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 48u>, config29>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config29_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config29>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,16u>,config29>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config30>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config55>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config55>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config55>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config55>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config31>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config31>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,16u>,config31>' to 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config32>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s'. +WARNING: [SYN 201-103] Legalizing function name 'resize_nearest, 16u>, config33>' to 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d_2,24u>,config34>' to 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d,24u>,config34>' to 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config56>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,24u>,config56>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config56>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,24u>,config56>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 24u>, config35>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config35_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config35>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config35>' to 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config36>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config57>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config57>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config57>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,8u>,config57>' to 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config37>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config37>' to 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config37>' to 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config38>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config58_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'pointwise_conv_2d_cl,1u>,config58>' to 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_s'. +WARNING: [SYN 201-103] Legalizing function name 'sigmoid,1u>,sigmoid_config40>' to 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s'. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 4.08 seconds. CPU system time: 0.36 seconds. Elapsed time: 4.48 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer44_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer44_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.95 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.97 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.06 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 1u>, config2>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 1u>, config2>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.411 ns) exceeds the target (target clock period: 5.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 3.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' consists of the following: + 'or' operation 1 bit ('or_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [82] (0.000 ns) + 'or' operation 1 bit ('or_ln144_2', firmware/nnet_utils/nnet_dense_resource.h:144) [84] (0.000 ns) + 'or' operation 1 bit ('or_ln144_6', firmware/nnet_utils/nnet_dense_resource.h:144) [88] (0.000 ns) + 'select' operation 37 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [89] (0.229 ns) + 'select' operation 37 bit ('acc_87', firmware/nnet_utils/nnet_dense_resource.h:144) [93] (0.229 ns) + multiplexor before 'phi' operation 37 bit ('acc') with incoming values : ('acc_87', firmware/nnet_utils/nnet_dense_resource.h:144) [33] (0.387 ns) + 'phi' operation 37 bit ('acc') with incoming values : ('acc_87', firmware/nnet_utils/nnet_dense_resource.h:144) [33] (0.000 ns) + 'sparsemux' operation 37 bit ('tmp_i', firmware/nnet_utils/nnet_dense_resource.h:144) [70] (0.584 ns) + 'add' operation 38 bit of DSP[73] ('add_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [73] (2.039 ns) + 'icmp' operation 1 bit ('icmp_ln144_17', firmware/nnet_utils/nnet_dense_resource.h:144) [81] (0.943 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer45_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer45_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.96 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.99 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config4>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config4>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.309 ns) exceeds the target (target clock period: 5.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 3.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s' consists of the following: + 'select' operation 40 bit ('select_ln144_40', firmware/nnet_utils/nnet_dense_resource.h:144) [329] (0.230 ns) + 'select' operation 40 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [331] (0.230 ns) + 'select' operation 40 bit ('acc_74', firmware/nnet_utils/nnet_dense_resource.h:144) [338] (0.230 ns) + multiplexor before 'phi' operation 40 bit ('acc') with incoming values : ('acc_74', firmware/nnet_utils/nnet_dense_resource.h:144) [153] (0.387 ns) + 'phi' operation 40 bit ('acc') with incoming values : ('acc_74', firmware/nnet_utils/nnet_dense_resource.h:144) [153] (0.000 ns) + 'select' operation 40 bit ('select_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [324] (0.230 ns) + 'add' operation 41 bit of DSP[327] ('add_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [327] (2.039 ns) + 'icmp' operation 1 bit ('icmp_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [328] (0.963 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.28 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.3 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'CloneLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'CloneLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config6>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config6>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReadInputHeight_ReadInputWidth'. +WARNING: [HLS 200-880] The II Violation in module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' (loop 'ReadInputHeight_ReadInputWidth'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between 'load' operation 16 bit ('void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_32', firmware/nnet_utils/nnet_pooling_stream.h:63->firmware/nnet_utils/nnet_pooling_stream.h:115) on static variable 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel' and 'call' operation 0 bit ('_ln52', firmware/nnet_utils/nnet_pooling_stream.h:52->firmware/nnet_utils/nnet_pooling_stream.h:115) to 'shift_line_buffer, 8u>, config6>'. +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 2, Depth = 3, loop 'ReadInputHeight_ReadInputWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.44 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.47 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config7>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config7>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.238 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.238 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.309 ns) exceeds the target (target clock period: 5.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 3.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s' consists of the following: + 'select' operation 40 bit ('select_ln144_1', firmware/nnet_utils/nnet_dense_resource.h:144) [337] (0.230 ns) + 'select' operation 40 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [339] (0.230 ns) + 'select' operation 40 bit ('acc_40', firmware/nnet_utils/nnet_dense_resource.h:144) [346] (0.230 ns) + multiplexor before 'phi' operation 40 bit ('acc') with incoming values : ('acc_40', firmware/nnet_utils/nnet_dense_resource.h:144) [153] (0.387 ns) + 'phi' operation 40 bit ('acc') with incoming values : ('acc_40', firmware/nnet_utils/nnet_dense_resource.h:144) [153] (0.000 ns) + 'select' operation 40 bit ('select_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [332] (0.230 ns) + 'add' operation 41 bit of DSP[335] ('add_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [335] (2.039 ns) + 'icmp' operation 1 bit ('icmp_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [336] (0.963 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.34 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.34 seconds; current allocated memory: 2.242 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.242 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.242 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.242 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.242 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.242 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.242 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.243 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.243 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.243 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.45 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.48 seconds; current allocated memory: 2.244 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.245 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.245 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.08 seconds; current allocated memory: 2.245 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.245 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.245 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config9>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config9>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.245 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.245 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.47 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.5 seconds; current allocated memory: 2.261 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.261 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.261 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.261 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.261 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.261 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.261 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.261 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'CloneLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'CloneLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.261 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.261 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config11>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config11>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.261 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.261 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReadInputHeight_ReadInputWidth'. +WARNING: [HLS 200-880] The II Violation in module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' (loop 'ReadInputHeight_ReadInputWidth'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between 'load' operation 16 bit ('void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_52', firmware/nnet_utils/nnet_pooling_stream.h:63->firmware/nnet_utils/nnet_pooling_stream.h:115) on static variable 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_20' and 'call' operation 0 bit ('_ln52', firmware/nnet_utils/nnet_pooling_stream.h:52->firmware/nnet_utils/nnet_pooling_stream.h:115) to 'shift_line_buffer, 16u>, config11>'. +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 2, Depth = 3, loop 'ReadInputHeight_ReadInputWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.21 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.23 seconds; current allocated memory: 2.261 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.261 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.261 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.261 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.28 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.32 seconds; current allocated memory: 2.261 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.261 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.261 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.261 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.261 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.261 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config12>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config12>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.261 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.261 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.437 ns) exceeds the target (target clock period: 5.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 3.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s' consists of the following: + 'or' operation 1 bit ('or_ln144_76', firmware/nnet_utils/nnet_dense_resource.h:144) [695] (0.122 ns) + 'or' operation 1 bit ('or_ln144_77', firmware/nnet_utils/nnet_dense_resource.h:144) [696] (0.000 ns) + 'select' operation 41 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [697] (0.237 ns) + 'select' operation 41 bit ('acc_568', firmware/nnet_utils/nnet_dense_resource.h:144) [707] (0.237 ns) + multiplexor before 'phi' operation 41 bit ('acc') with incoming values : ('acc_568', firmware/nnet_utils/nnet_dense_resource.h:144) [308] (0.387 ns) + 'phi' operation 41 bit ('acc') with incoming values : ('acc_568', firmware/nnet_utils/nnet_dense_resource.h:144) [308] (0.000 ns) + 'sparsemux' operation 41 bit ('tmp_26_i', firmware/nnet_utils/nnet_dense_resource.h:144) [685] (0.453 ns) + 'add' operation 42 bit of DSP[692] ('add_ln144_64', firmware/nnet_utils/nnet_dense_resource.h:144) [692] (2.039 ns) + 'icmp' operation 1 bit ('icmp_ln144_74', firmware/nnet_utils/nnet_dense_resource.h:144) [693] (0.962 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.5 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.53 seconds; current allocated memory: 2.272 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.272 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.272 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.272 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.272 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.272 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.272 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.272 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.272 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.272 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.31 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.33 seconds; current allocated memory: 2.273 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.273 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.273 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.273 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.273 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.273 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config14>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config14>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.28 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.3 seconds; current allocated memory: 2.278 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.279 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.362 ns) exceeds the target (target clock period: 5.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 3.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s' consists of the following: + 'select' operation 42 bit ('select_ln144_160', firmware/nnet_utils/nnet_dense_resource.h:144) [1217] (0.243 ns) + 'select' operation 42 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [1219] (0.243 ns) + 'select' operation 42 bit ('acc_526', firmware/nnet_utils/nnet_dense_resource.h:144) [1226] (0.243 ns) + multiplexor before 'phi' operation 42 bit ('acc') with incoming values : ('acc_526', firmware/nnet_utils/nnet_dense_resource.h:144) [585] (0.387 ns) + 'phi' operation 42 bit ('acc') with incoming values : ('acc_526', firmware/nnet_utils/nnet_dense_resource.h:144) [585] (0.000 ns) + 'select' operation 42 bit ('select_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [1212] (0.243 ns) + 'add' operation 43 bit of DSP[1215] ('add_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [1215] (2.039 ns) + 'icmp' operation 1 bit ('icmp_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [1216] (0.962 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.98 seconds. CPU system time: 0.03 seconds. Elapsed time: 1.01 seconds; current allocated memory: 2.311 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.23 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.26 seconds; current allocated memory: 2.311 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.2 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.23 seconds; current allocated memory: 2.311 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.311 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.311 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.311 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.311 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.311 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'CloneLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'CloneLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.311 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.311 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config16>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config16>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.311 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.311 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReadInputHeight_ReadInputWidth'. +WARNING: [HLS 200-880] The II Violation in module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' (loop 'ReadInputHeight_ReadInputWidth'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between 'load' operation 16 bit ('void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_42', firmware/nnet_utils/nnet_pooling_stream.h:63->firmware/nnet_utils/nnet_pooling_stream.h:115) on static variable 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_19' and 'call' operation 0 bit ('_ln52', firmware/nnet_utils/nnet_pooling_stream.h:52->firmware/nnet_utils/nnet_pooling_stream.h:115) to 'shift_line_buffer, 32u>, config16>'. +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 2, Depth = 3, loop 'ReadInputHeight_ReadInputWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.31 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.33 seconds; current allocated memory: 2.311 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.311 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.311 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.311 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 7, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 9, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 10, Depth = 11, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.25 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.27 seconds; current allocated memory: 2.311 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.311 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.311 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 2.311 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.311 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.311 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config17>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config17>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.3 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.31 seconds; current allocated memory: 2.311 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.15 seconds. CPU system time: 0 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.311 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.328 ns) exceeds the target (target clock period: 5.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 3.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s' consists of the following: + 'or' operation 1 bit ('or_ln144_30', firmware/nnet_utils/nnet_dense_resource.h:144) [1253] (0.122 ns) + 'or' operation 1 bit ('or_ln144_32', firmware/nnet_utils/nnet_dense_resource.h:144) [1264] (0.122 ns) + 'select' operation 42 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [1265] (0.243 ns) + multiplexor before 'phi' operation 42 bit ('acc') with incoming values : ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [584] (0.387 ns) + 'phi' operation 42 bit ('acc') with incoming values : ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [584] (0.000 ns) + 'sparsemux' operation 42 bit ('tmp_i', firmware/nnet_utils/nnet_dense_resource.h:144) [1244] (0.453 ns) + 'add' operation 43 bit of DSP[1247] ('add_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [1247] (2.039 ns) + 'icmp' operation 1 bit ('icmp_ln144_43', firmware/nnet_utils/nnet_dense_resource.h:144) [1251] (0.962 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.04 seconds. CPU system time: 0.04 seconds. Elapsed time: 1.08 seconds; current allocated memory: 2.350 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.27 seconds. CPU system time: 0 seconds. Elapsed time: 0.28 seconds; current allocated memory: 2.350 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.24 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.26 seconds; current allocated memory: 2.350 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.350 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.350 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.350 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.24 seconds. CPU system time: 0 seconds. Elapsed time: 0.25 seconds; current allocated memory: 2.350 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.350 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.350 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.350 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 7, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 9, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 10, Depth = 11, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.27 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.29 seconds; current allocated memory: 2.350 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.350 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.350 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.350 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.350 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.350 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 64u>, config19>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 64u>, config19>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.6 seconds. CPU system time: 0 seconds. Elapsed time: 0.6 seconds; current allocated memory: 2.350 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.21 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.350 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.388 ns) exceeds the target (target clock period: 5.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 3.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s' consists of the following: + 'select' operation 43 bit ('select_ln144_1', firmware/nnet_utils/nnet_dense_resource.h:144) [2401] (0.250 ns) + 'select' operation 43 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [2403] (0.250 ns) + 'select' operation 43 bit ('acc_288', firmware/nnet_utils/nnet_dense_resource.h:144) [2410] (0.250 ns) + multiplexor before 'phi' operation 43 bit ('acc') with incoming values : ('acc_288', firmware/nnet_utils/nnet_dense_resource.h:144) [1161] (0.387 ns) + 'phi' operation 43 bit ('acc') with incoming values : ('acc_288', firmware/nnet_utils/nnet_dense_resource.h:144) [1161] (0.000 ns) + 'select' operation 43 bit ('select_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [2396] (0.250 ns) + 'add' operation 44 bit of DSP[2399] ('add_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [2399] (2.039 ns) + 'icmp' operation 1 bit ('icmp_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [2400] (0.961 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.69 seconds. CPU system time: 0.06 seconds. Elapsed time: 1.75 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.54 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.59 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.37 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.39 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.28 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.29 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ImageHeight'. +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_1', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_2', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_3', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_4', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 32, Depth = 32, loop 'ImageHeight' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.4 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.41 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ConcatLoopHeight_ConcatLoopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'ConcatLoopHeight_ConcatLoopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.34 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.37 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.378 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 96u>, config23>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 96u>, config23>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.05 seconds. CPU system time: 0.01 seconds. Elapsed time: 1.07 seconds; current allocated memory: 2.380 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.3 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.32 seconds; current allocated memory: 2.385 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 2.1 seconds. CPU system time: 0.08 seconds. Elapsed time: 2.18 seconds; current allocated memory: 2.439 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.84 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.86 seconds; current allocated memory: 2.439 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.4 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.47 seconds; current allocated memory: 2.439 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.439 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.23 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.26 seconds; current allocated memory: 2.439 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.439 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.24 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.27 seconds; current allocated memory: 2.439 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.439 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.439 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.439 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.35 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.36 seconds; current allocated memory: 2.439 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.439 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.439 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.439 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.439 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 2.439 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config25>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config25>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.31 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.33 seconds; current allocated memory: 2.439 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.439 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.449 ns) exceeds the target (target clock period: 5.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 3.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s' consists of the following: + 'or' operation 1 bit ('or_ln144_12', firmware/nnet_utils/nnet_dense_resource.h:144) [1271] (0.122 ns) + 'or' operation 1 bit ('or_ln144_13', firmware/nnet_utils/nnet_dense_resource.h:144) [1272] (0.000 ns) + 'select' operation 42 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [1273] (0.243 ns) + 'select' operation 42 bit ('acc_137', firmware/nnet_utils/nnet_dense_resource.h:144) [1283] (0.243 ns) + multiplexor before 'phi' operation 42 bit ('acc') with incoming values : ('acc_137', firmware/nnet_utils/nnet_dense_resource.h:144) [596] (0.387 ns) + 'phi' operation 42 bit ('acc') with incoming values : ('acc_137', firmware/nnet_utils/nnet_dense_resource.h:144) [596] (0.000 ns) + 'sparsemux' operation 42 bit ('tmp_4_i', firmware/nnet_utils/nnet_dense_resource.h:144) [1261] (0.453 ns) + 'add' operation 43 bit of DSP[1268] ('add_ln144_17', firmware/nnet_utils/nnet_dense_resource.h:144) [1268] (2.039 ns) + 'icmp' operation 1 bit ('icmp_ln144_35', firmware/nnet_utils/nnet_dense_resource.h:144) [1269] (0.962 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.82 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.87 seconds; current allocated memory: 2.454 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.23 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.26 seconds; current allocated memory: 2.454 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.22 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.24 seconds; current allocated memory: 2.454 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.454 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.454 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.454 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.21 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.23 seconds; current allocated memory: 2.454 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.454 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ImageHeight'. +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_1', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_2', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_3', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_4', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 64, Depth = 64, loop 'ImageHeight' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.68 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.71 seconds; current allocated memory: 2.454 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.454 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ConcatLoopHeight_ConcatLoopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'ConcatLoopHeight_ConcatLoopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.454 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.454 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.454 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.454 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.454 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.454 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.53 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.56 seconds; current allocated memory: 2.454 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.454 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.454 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.454 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.454 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.454 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 48u>, config29>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 48u>, config29>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.46 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.46 seconds; current allocated memory: 2.454 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.16 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.454 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.95 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.98 seconds; current allocated memory: 2.475 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.35 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.37 seconds; current allocated memory: 2.475 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.25 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.28 seconds; current allocated memory: 2.475 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.475 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.475 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.475 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.21 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.475 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.475 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.475 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.475 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.54 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.56 seconds; current allocated memory: 2.475 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.476 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.476 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.476 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.476 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.11 seconds; current allocated memory: 2.476 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config31>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config31>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.23 seconds. CPU system time: 0 seconds. Elapsed time: 0.23 seconds; current allocated memory: 2.476 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.477 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.322 ns) exceeds the target (target clock period: 5.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 3.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s' consists of the following: + 'or' operation 1 bit ('or_ln144_17', firmware/nnet_utils/nnet_dense_resource.h:144) [629] (0.122 ns) + 'or' operation 1 bit ('or_ln144_19', firmware/nnet_utils/nnet_dense_resource.h:144) [640] (0.122 ns) + 'select' operation 41 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [641] (0.237 ns) + multiplexor before 'phi' operation 41 bit ('acc') with incoming values : ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [296] (0.387 ns) + 'phi' operation 41 bit ('acc') with incoming values : ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [296] (0.000 ns) + 'sparsemux' operation 41 bit ('tmp_i', firmware/nnet_utils/nnet_dense_resource.h:144) [620] (0.453 ns) + 'add' operation 42 bit of DSP[623] ('add_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [623] (2.039 ns) + 'icmp' operation 1 bit ('icmp_ln144_25', firmware/nnet_utils/nnet_dense_resource.h:144) [627] (0.962 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.48 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.51 seconds; current allocated memory: 2.485 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.485 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.485 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.485 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.485 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.487 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.487 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.487 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ImageHeight'. +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_1', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_2', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_3', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_4', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 67, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 98, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 114, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 122, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 126, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 127, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 128, Depth = 128, loop 'ImageHeight' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.73 seconds. CPU system time: 0.05 seconds. Elapsed time: 1.78 seconds; current allocated memory: 2.503 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.503 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ConcatLoopHeight_ConcatLoopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'ConcatLoopHeight_ConcatLoopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.503 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.503 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.503 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.503 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.503 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.503 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.12 seconds. CPU system time: 0.03 seconds. Elapsed time: 1.16 seconds; current allocated memory: 2.503 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.503 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.503 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.503 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.503 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.503 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 24u>, config35>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 24u>, config35>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.27 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.29 seconds; current allocated memory: 2.503 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.503 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.58 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.61 seconds; current allocated memory: 2.506 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.21 seconds. CPU system time: 0 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.506 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.21 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.506 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.506 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.506 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.506 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.506 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.506 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.506 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.506 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 1.16 seconds; current allocated memory: 2.510 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.510 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.510 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.510 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.510 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.510 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config37>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config37>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.510 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.510 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.424 ns) exceeds the target (target clock period: 5.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 3.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s' consists of the following: + 'or' operation 1 bit ('or_ln144_9', firmware/nnet_utils/nnet_dense_resource.h:144) [333] (0.122 ns) + 'or' operation 1 bit ('or_ln144_10', firmware/nnet_utils/nnet_dense_resource.h:144) [334] (0.000 ns) + 'select' operation 40 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [335] (0.230 ns) + 'select' operation 40 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [345] (0.230 ns) + multiplexor before 'phi' operation 40 bit ('acc') with incoming values : ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [152] (0.387 ns) + 'phi' operation 40 bit ('acc') with incoming values : ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [152] (0.000 ns) + 'sparsemux' operation 40 bit ('tmp_i', firmware/nnet_utils/nnet_dense_resource.h:144) [324] (0.453 ns) + 'add' operation 41 bit of DSP[327] ('add_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [327] (2.039 ns) + 'icmp' operation 1 bit ('icmp_ln144_20', firmware/nnet_utils/nnet_dense_resource.h:144) [331] (0.963 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.34 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.38 seconds; current allocated memory: 2.510 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.510 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.510 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.512 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.512 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.512 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.512 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.512 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.512 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.512 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.512 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.512 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'SigmoidActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 4, loop 'SigmoidActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.2 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.513 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.513 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'myproject' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +WARNING: [HLS 200-1020] Increasing the depth of FIFO start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0 (from clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0 to concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0) to 10 to improve performance and/or avoid deadlocks. +WARNING: [HLS 200-1020] Increasing the depth of FIFO start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0 (from clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_U0 to concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0) to 26 to improve performance and/or avoid deadlocks. +WARNING: [HLS 200-1020] Increasing the depth of FIFO start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0 (from clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0 to concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0) to 42 to improve performance and/or avoid deadlocks. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.42 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.45 seconds; current allocated memory: 2.514 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.36 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.37 seconds; current allocated memory: 2.524 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.73 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.77 seconds; current allocated memory: 2.525 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.529 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.531 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.532 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_cud' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.532 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_outidx_1_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_oudEe' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_w2_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_w2eOg' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_37s_38_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_17_3_37_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_19_4_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_oudEe' using auto ROMs. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_w2eOg' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.28 seconds. CPU system time: 0.06 seconds. Elapsed time: 0.34 seconds; current allocated memory: 2.536 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_7' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.43 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.47 seconds; current allocated memory: 2.538 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.539 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.540 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.542 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.545 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 2.547 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.549 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1375_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_fYi' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1383_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_g8j' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1376_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_hbi' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1384_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_ibs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1377_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_jbC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1385_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_kbM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1378_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_lbW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1386_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_mb6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1379_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_ncg' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1387_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_ocq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1380_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_pcA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1388_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_qcK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1381_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_rcU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1389_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_sc4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1382_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_tde' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1390_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_udo' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.46 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.52 seconds; current allocated memory: 2.550 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_outidx_2_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_ouvdy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_w4_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_w4wdI' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_40s_41_1_1': 3 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_40s_41_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_ouvdy' using auto ROMs. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_w4wdI' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.36 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.42 seconds; current allocated memory: 2.557 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_13' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.92 seconds. CPU system time: 0.18 seconds. Elapsed time: 2.11 seconds; current allocated memory: 2.565 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.568 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.569 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.571 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stxdS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_styd2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stzec' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stAem' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stBew' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stCeG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stDeQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stEe0' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0 seconds. Elapsed time: 0.33 seconds; current allocated memory: 2.573 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'sY' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX' is power-on initialization. +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' pipeline 'ReadInputHeight_ReadInputWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1 seconds. CPU system time: 0.08 seconds. Elapsed time: 1.08 seconds; current allocated memory: 2.575 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.2 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.578 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.580 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.584 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 2.584 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1359_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Ffa' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1367_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Gfk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1360_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Hfu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1368_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_IfE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1361_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_JfO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1369_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_KfY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1362_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Lf8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1370_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Mgi' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1363_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Ngs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1371_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_OgC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1364_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_PgM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1372_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_QgW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1365_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Rg6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1373_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Shg' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1366_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Thq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1374_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_UhA' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.5 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.54 seconds; current allocated memory: 2.585 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_outidx_3_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_ouVhK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_w7_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_w7WhU' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_11s_40s_41_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_40s_41_1_1': 7 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_w7WhU' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.37 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.43 seconds; current allocated memory: 2.593 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_38' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_30' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_39' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_31' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_32' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_33' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_34' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_35' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_36' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_37' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_15' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.98 seconds. CPU system time: 0.21 seconds. Elapsed time: 2.19 seconds; current allocated memory: 2.603 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.605 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.607 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.609 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.612 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.614 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 2.614 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_799_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dXh4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_815_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dYie' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_800_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dZio' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_816_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d0iy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_807_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d1iI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_823_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d2iS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_808_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d3i2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_824_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d4jc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_809_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d5jm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_825_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d6jw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_810_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d7jG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_826_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d8jQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_811_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d9j0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_827_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbak' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_812_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbbk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_828_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbck' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_813_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbdk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_829_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbek' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_814_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbfk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_830_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbgk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_801_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbhl' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_817_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbil' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_802_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbjl' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_818_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbkl' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_803_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbll' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_819_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbml' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_804_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbnm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_820_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbom' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_805_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbpm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_821_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbqm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_806_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbrm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_822_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbsm' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.91 seconds. CPU system time: 0.06 seconds. Elapsed time: 0.97 seconds; current allocated memory: 2.617 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbtn' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_11s_34s_34_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_39s_39_1_1': 15 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_289_8_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbtn' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.43 seconds. CPU system time: 0.06 seconds. Elapsed time: 0.48 seconds; current allocated memory: 2.628 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4177' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4178' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4179' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4180' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4181' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4182' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4183' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4184' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4185' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4186' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4188' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4122' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4189' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4134' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4190' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4191' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4192' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4137' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4123' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4124' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4125' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4126' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4127' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4128' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4129' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4130' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4131' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4133' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4135' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4136' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_9' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 3.84 seconds. CPU system time: 0.38 seconds. Elapsed time: 4.23 seconds; current allocated memory: 2.646 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.2 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.649 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.651 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 2.653 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bun' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bvn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bwn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bxn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_byn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bzo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bAo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bBo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bCo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bDo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_27_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbEo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_26_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbFp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_25_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbGp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_24_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbHp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_23_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbIp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_22_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbJp' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.54 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.58 seconds; current allocated memory: 2.656 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'sY_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_11' is power-on initialization. +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' pipeline 'ReadInputHeight_ReadInputWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.88 seconds. CPU system time: 0.18 seconds. Elapsed time: 2.06 seconds; current allocated memory: 2.661 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.23 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.27 seconds; current allocated memory: 2.667 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.668 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.671 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 2.671 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_863_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_879_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bLp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_864_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bMq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_880_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bNq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_871_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bOq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_887_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bPq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_872_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bQq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_888_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bRq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_873_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bSr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_889_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bTr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_874_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bUr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_890_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bVr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_875_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bWr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_891_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bXr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_876_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bYs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_892_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bZs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_877_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b0s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_893_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b1s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_878_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b2s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_894_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b3s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_865_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b4t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_881_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b5t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_866_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b6t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_882_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b7t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_867_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b8t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_883_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b9t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_868_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2cau' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_884_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2cbu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_869_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2ccu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_885_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2cdu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_870_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2ceu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_886_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2cfu' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.97 seconds. CPU system time: 0.08 seconds. Elapsed time: 1.05 seconds; current allocated memory: 2.673 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s_outidx_4_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s_outidx_4_ROM_cgu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s_w12_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s_w12_ROM_NP_BRchv' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_41s_42_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_41s_42_1_1': 7 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_289_8_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_9_2_41_1_1': 8 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s_outidx_4_ROM_cgu' using auto ROMs. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s_w12_ROM_NP_BRchv' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.6 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.64 seconds; current allocated memory: 2.688 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4416' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4428' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4441' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4453' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4465' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4432' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4433' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4434' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4435' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4436' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4417' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4437' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4419' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4438' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4420' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4439' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4421' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4442' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4422' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4443' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4423' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4444' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4424' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4445' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4425' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4446' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4426' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4447' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4427' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4448' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4430' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4449' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4431' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4450' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4452' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4454' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4455' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4456' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4457' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4458' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4459' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4460' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4461' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4463' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4464' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4466' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4467' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4468' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4469' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_8' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.09 seconds. CPU system time: 0.45 seconds. Elapsed time: 4.53 seconds; current allocated memory: 2.709 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.21 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.712 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.21 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.23 seconds; current allocated memory: 2.715 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.23 seconds; current allocated memory: 2.718 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.719 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 2.720 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 2.721 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_943_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2civ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_975_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cjv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_944_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2ckv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_976_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2clv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_955_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cmv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_987_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cnw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_966_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cow' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_998_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cpw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_969_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cqw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1001_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2crw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_970_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2csw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1002_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2ctx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_971_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cux' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1003_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cvx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_972_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cwx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1004_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cxx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_973_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cyx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1005_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2czy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_974_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cAy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1006_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cBy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_945_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cCy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_977_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cDy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_946_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cEy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_978_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cFz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_947_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cGz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_979_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cHz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_948_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cIz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_980_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cJz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_949_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cKz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_981_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cLz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_950_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cMA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_982_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cNA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_951_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cOA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_983_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cPA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_952_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cQA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_984_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cRA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_953_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cSB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_985_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cTB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_954_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cUB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_986_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cVB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_956_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cWB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_988_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cXB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_957_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cYC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_989_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cZC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_958_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c0C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_990_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c1C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_959_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c2C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_991_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c3C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_960_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c4D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_992_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c5D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_961_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c6D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_993_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c7D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_962_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c8D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_994_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c9D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_963_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2daE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_995_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dbE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_964_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dcE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_996_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2ddE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_965_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2deE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_997_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dfE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_967_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dgE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_999_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dhF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_968_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2diF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1000_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2djF' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.88 seconds. CPU system time: 0.16 seconds. Elapsed time: 2.05 seconds; current allocated memory: 2.728 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_outidx_5_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_outidx_5_ROM_dkF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_w14_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_w14_ROM_NP_BRdlF' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s' is 9216 from HDL expression: (do_init_reg_1356 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_42s_43_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_42s_43_1_1': 15 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_577_9_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_outidx_5_ROM_dkF' using auto ROMs. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_w14_ROM_NP_BRdlF' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.78 seconds. CPU system time: 0.09 seconds. Elapsed time: 0.87 seconds; current allocated memory: 2.753 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5021' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_89' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5022' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_88' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5024' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_87' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5025' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_86' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5026' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_85' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5027' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_84' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5028' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_83' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5029' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_82' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5030' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_81' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5031' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_80' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5032' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5033' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5035' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5036' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5037' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4839' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5038' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4851' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5039' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4863' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5040' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4875' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5041' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4887' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5042' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4899' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5043' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4911' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5044' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4923' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5046' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4936' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5047' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4948' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5048' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4960' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5049' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4972' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5050' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4984' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5051' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4996' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5052' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5008' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5053' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5018' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5054' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5019' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5055' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5020' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5092' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5093' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5094' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5095' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4840' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4841' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4842' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4843' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4844' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4845' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4846' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4848' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4849' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4850' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4852' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4853' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4854' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4855' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4856' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4857' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4859' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4860' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4861' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4862' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4941' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4903' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4942' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4904' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4943' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4905' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4944' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4906' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4945' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4907' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4947' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4908' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4949' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4909' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4950' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4910' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4951' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4912' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4952' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4914' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4953' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4915' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4954' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4916' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4955' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4917' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4956' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4918' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4958' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4919' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4959' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4920' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4961' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4921' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4962' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4922' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4963' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4925' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4964' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4926' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4965' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4927' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4966' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4928' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4967' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4929' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4969' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4930' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4970' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4931' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4971' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4932' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4973' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4933' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4974' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4934' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4975' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4937' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4976' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4938' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4977' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4939' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4978' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4940' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5057' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5058' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5059' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5060' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5061' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5062' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5063' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5064' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5065' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5066' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5068' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5069' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5070' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5071' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5072' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5073' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5074' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5075' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5076' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5077' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5079' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5080' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5081' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5082' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5083' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5084' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5085' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5086' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5087' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5088' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5090' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5091' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4864' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4865' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4866' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4867' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4868' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4870' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4871' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4872' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4873' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4874' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4876' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4877' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4878' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4879' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4881' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4882' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4883' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4884' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4885' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4886' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4888' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4889' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4890' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4892' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4893' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4894' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4895' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4896' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4897' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4898' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4900' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4901' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4980' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4981' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4982' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4983' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4985' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4986' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4987' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4988' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4989' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4991' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4992' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4993' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4994' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4995' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4997' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4998' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5000' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5002' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5003' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5004' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5005' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5006' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5007' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5009' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5010' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5011' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5013' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5014' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5015' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5016' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5017' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_5' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 8.61 seconds. CPU system time: 0.85 seconds. Elapsed time: 9.46 seconds; current allocated memory: 2.791 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.27 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.3 seconds; current allocated memory: 2.796 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.25 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.28 seconds; current allocated memory: 2.800 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.803 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dmF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dnG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_doG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dpG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dqG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_drG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dsG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dtH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_duH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dvH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_21_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindwH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_20_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindxH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_19_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindyH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_18_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindzI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_17_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindAI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_16_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindBI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_15_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindCI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_14_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindDI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_13_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindEI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_12_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindFJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_11_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindGJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_10_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindHJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindIJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindJJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindKJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindLJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindMK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindNK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindOK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindPK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindQK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindRK' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.08 seconds. CPU system time: 0.11 seconds. Elapsed time: 1.19 seconds; current allocated memory: 2.806 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'sY_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_89' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_57' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_88' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_56' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_87' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_55' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_86' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_54' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_85' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_53' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_84' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_52' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_83' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_51' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_82' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_50' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_81' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_49' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_80' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_48' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_79' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_47' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_78' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_46' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_77' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_45' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_76' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_44' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_75' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_43' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_74' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_42' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_73' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_41' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_72' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_40' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_71' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_39' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_70' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_38' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_69' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_37' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_68' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_36' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_99' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_67' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_35' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_98' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_66' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_34' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_97' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_65' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_33' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_96' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_64' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_32' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_95' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_63' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_31' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_94' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_62' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_30' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_93' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_61' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_92' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_60' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_91' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_59' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_90' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_58' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_3' is power-on initialization. +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' pipeline 'ReadInputHeight_ReadInputWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.11 seconds. CPU system time: 0.4 seconds. Elapsed time: 4.51 seconds; current allocated memory: 2.817 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.35 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.39 seconds; current allocated memory: 2.828 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.829 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.830 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 2.831 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1071_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dSL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1103_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dTL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1072_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dUL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1104_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dVL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1083_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dWL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1115_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dXL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1094_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dYM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1126_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dZM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1097_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d0M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1129_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d1M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1098_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d2M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1130_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d3M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1099_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d4N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1131_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d5N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1100_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d6N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1132_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d7N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1101_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d8N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1133_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d9N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1102_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eaO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1134_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ebO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1073_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ecO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1105_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2edO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1074_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eeO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1106_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2efO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1075_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2egO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1107_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ehP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1076_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eiP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1108_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ejP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1077_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ekP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1109_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2elP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1078_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2emP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1110_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2enQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1079_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eoQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1111_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2epQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1080_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eqQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1112_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2erQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1081_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2esQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1113_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2etR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1082_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2euR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1114_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2evR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1084_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ewR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1116_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2exR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1085_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eyR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1117_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ezS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1086_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eAS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1118_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eBS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1087_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eCS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1119_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eDS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1088_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eES' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1120_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eFT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1089_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eGT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1121_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eHT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1090_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eIT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1122_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eJT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1091_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eKT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1123_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eLT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1092_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eMU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1124_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eNU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1093_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eOU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1125_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ePU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1095_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eQU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1127_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eRU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1096_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eSV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1128_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eTV' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 2.1 seconds. CPU system time: 0.17 seconds. Elapsed time: 2.27 seconds; current allocated memory: 2.837 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s_outidx_6_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s_outidx_6_ROM_eUV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s_w17_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s_w17_ROM_NP_BReVV' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s' is 9216 from HDL expression: (do_init_reg_1434 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_42s_43_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_42s_43_1_1': 15 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_577_9_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_9_2_42_1_1': 16 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s_outidx_6_ROM_eUV' using auto ROMs. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s_w17_ROM_NP_BReVV' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.99 seconds. CPU system time: 0.07 seconds. Elapsed time: 1.05 seconds; current allocated memory: 2.872 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_69' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_68' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_67' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_66' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_65' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_64' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_63' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_62' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_61' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_60' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5402' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5414' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5426' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5438' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5450' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5462' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5436' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5437' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5439' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5440' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5442' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5403' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5443' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5404' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5444' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5405' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5445' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5406' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5446' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5407' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5447' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5409' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5448' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5410' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5449' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5411' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5451' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5412' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5453' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5413' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5454' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5415' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5455' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5416' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5456' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5417' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5457' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5418' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5458' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5420' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5459' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5421' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5460' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5422' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5461' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5423' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5464' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5424' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5465' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5425' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5466' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5427' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5467' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5428' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5468' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5429' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5469' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5431' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5432' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5433' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5434' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5435' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_10' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 9.34 seconds. CPU system time: 1.02 seconds. Elapsed time: 10.38 seconds; current allocated memory: 2.913 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.29 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.33 seconds; current allocated memory: 2.919 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.29 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.33 seconds; current allocated memory: 2.923 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.28 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.3 seconds; current allocated memory: 2.929 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.21 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.21 seconds; current allocated memory: 2.930 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.21 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.22 seconds; current allocated memory: 2.931 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 2.932 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1231_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eWV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1295_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eXV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1232_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eYW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1296_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eZW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1243_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e0W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1307_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e1W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1254_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e2W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1318_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e3W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1265_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e4X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1329_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e5X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1276_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e6X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1340_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e7X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1287_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e8X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1351_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e9X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1292_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2faY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1356_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fbY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1293_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fcY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1357_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fdY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1294_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2feY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1358_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ffY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1233_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fgY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1297_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fhZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1234_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fiZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1298_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fjZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1235_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fkZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1299_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2flZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1236_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fmZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1300_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fn0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1237_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fo0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1301_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fp0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1238_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fq0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1302_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fr0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1239_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fs0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1303_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ft1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1240_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fu1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1304_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fv1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1241_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fw1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1305_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fx1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1242_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fy1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1306_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fz2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1244_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fA2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1308_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fB2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1245_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fC2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1309_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fD2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1246_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fE2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1310_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fF3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1247_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fG3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1311_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fH3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1248_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fI3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1312_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fJ3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1249_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fK3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1313_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fL3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1250_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fM4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1314_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fN4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1251_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fO4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1315_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fP4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1252_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fQ4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1316_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fR4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1253_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fS5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1317_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fT5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1255_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fU5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1319_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fV5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1256_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fW5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1320_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fX5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1257_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fY6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1321_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fZ6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1258_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f06' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1322_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f16' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1259_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f26' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1323_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f36' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1260_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f47' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1324_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f57' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1261_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f67' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1325_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f77' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1262_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f87' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1326_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f97' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1263_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ga8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1327_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gb8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1264_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gc8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1328_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gd8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1266_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ge8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1330_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gf8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1267_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gg8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1331_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gh9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1268_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gi9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1332_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gj9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1269_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gk9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1333_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gl9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1270_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gm9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1334_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1271_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1335_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1272_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1336_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2grb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1273_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1337_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gtb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1274_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1338_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1275_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1339_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1277_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1341_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1278_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gAb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1342_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gBb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1279_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gCb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1343_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gDb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1280_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gEb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1344_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gFb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1281_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gGb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1345_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gHb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1282_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gIb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1346_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gJb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1283_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gKb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1347_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gLb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1284_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gMb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1348_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1285_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1349_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1286_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1350_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1288_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1352_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1289_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1353_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1290_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1354_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1291_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1355_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gZb_x' due to conflict. +INFO: [RTGEN 206-104] Estimated max fanout for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s' is 9216 from HDL expression: (1'b1 == ap_CS_fsm_state1) +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.64 seconds. CPU system time: 0.54 seconds. Elapsed time: 5.19 seconds; current allocated memory: 2.944 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s_outidx_7_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s_outidx_7_ROM_g0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s_w19_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s_w19_ROM_NP_BRg1b' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s' is 18432 from HDL expression: (do_init_reg_2636 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_43s_44_1_1': 31 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_43s_44_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_1153_10_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s_outidx_7_ROM_g0b' using auto ROMs. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s_w19_ROM_NP_BRg1b' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.49 seconds. CPU system time: 0.11 seconds. Elapsed time: 1.6 seconds; current allocated memory: 3.000 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_49' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_48' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_47' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_46' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_45' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_44' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_43' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_42' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_41' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_40' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6184' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6293' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6305' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6317' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6329' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6341' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6353' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6366' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6378' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6390' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6402' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6414' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6426' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6438' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6450' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6462' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6177' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6179' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6180' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6181' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6182' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6183' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6185' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6186' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6187' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6188' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6190' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6191' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6192' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6361' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6362' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6363' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6364' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6287' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6367' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6289' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6368' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6290' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6369' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6291' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6370' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6292' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6371' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6294' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6372' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6295' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6373' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6296' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6374' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6297' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6375' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6298' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6377' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6300' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6379' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6301' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6380' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6302' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6381' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6303' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6382' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6304' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6383' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6306' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6384' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6307' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6385' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6308' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6386' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6309' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6388' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6311' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6389' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6312' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6391' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6313' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6392' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6314' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6393' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6315' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6394' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6316' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6395' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6318' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6396' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6319' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6397' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6320' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6399' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6322' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6400' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6323' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6401' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6324' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6403' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6325' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6404' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6326' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6405' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6327' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6406' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6328' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6407' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6330' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6408' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6331' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6410' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6333' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6411' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6334' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6412' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6335' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6413' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6336' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6415' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6337' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6416' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6338' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6417' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6339' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6418' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6340' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6419' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6342' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6421' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6344' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6422' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6345' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6423' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6346' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6424' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6347' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6425' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6348' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6427' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6349' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6428' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6350' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6429' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6351' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6430' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6352' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6432' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6355' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6433' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6356' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6434' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6357' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6435' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6358' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6436' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6359' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6437' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6360' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6439' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6440' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6441' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6443' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6444' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6445' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6446' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6447' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6448' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6449' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6451' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6452' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6454' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6455' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6456' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6457' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6458' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6459' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6460' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6461' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6463' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6465' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6466' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6467' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6468' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6469' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_16' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 20.94 seconds. CPU system time: 1.95 seconds. Elapsed time: 22.92 seconds; current allocated memory: 3.073 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.42 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.48 seconds; current allocated memory: 3.083 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.4 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.41 seconds; current allocated memory: 3.088 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.28 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.31 seconds; current allocated memory: 3.095 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' pipeline 'ConcatLoopHeight_ConcatLoopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.22 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.26 seconds; current allocated memory: 3.096 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 3.097 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.22 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.24 seconds; current allocated memory: 3.098 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.21 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.26 seconds; current allocated memory: 3.099 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.22 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.26 seconds; current allocated memory: 3.100 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.21 seconds; current allocated memory: 3.101 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1407_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_95_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1408_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_94_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1419_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_83_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1430_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_72_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1441_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_61_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1452_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_50_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1463_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2heb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_39_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1474_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_28_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1485_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_17_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1496_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hlb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1409_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_93_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1410_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_92_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1411_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_91_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1412_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_90_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2htb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1413_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_89_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1414_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_88_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1415_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_87_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1416_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_86_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1417_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_85_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1418_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_84_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1420_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_82_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1421_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_81_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1422_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_80_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1423_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_79_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1424_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_78_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1425_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_77_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1426_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_76_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1427_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_75_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1428_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_74_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1429_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_73_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1431_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_71_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1432_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_70_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1433_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_69_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1434_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_68_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1435_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_67_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1436_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_66_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ibb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1437_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2icb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_65_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2idb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1438_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ieb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_64_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ifb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1439_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2igb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_63_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ihb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1440_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_62_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ijb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1442_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ikb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_60_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ilb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1443_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2imb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_59_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2inb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1444_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_58_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ipb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1445_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_57_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2irb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1446_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2isb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_56_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2itb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1447_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_55_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ivb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1448_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_54_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ixb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1449_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_53_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2izb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1450_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_52_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1451_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_51_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1453_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_49_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1454_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_48_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1455_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_47_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1456_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_46_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1457_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_45_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1458_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_44_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1459_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_43_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1460_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_42_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1461_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_41_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1462_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_40_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1464_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_38_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1465_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_37_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1466_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_36_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1467_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_35_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1468_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_34_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1469_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_33_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1470_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_32_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1471_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_31_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1472_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jeb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_30_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1473_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_29_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1475_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_27_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1476_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_26_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jlb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1477_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_25_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1478_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2job' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_24_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1479_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_23_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1480_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_22_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jtb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1481_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_21_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1482_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_20_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1483_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_19_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1484_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_18_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1486_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_16_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1487_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_15_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1488_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_14_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1489_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_13_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1490_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_12_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1491_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_11_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1492_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_10_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1493_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1494_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1495_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1497_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1498_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_99_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_98_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_97_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_96_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j7b' due to the length limit 80 +INFO: [RTGEN 206-104] Estimated max fanout for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s' is 13824 from HDL expression: (1'b1 == ap_CS_fsm_state1) +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 10.2 seconds. CPU system time: 1.08 seconds. Elapsed time: 11.3 seconds; current allocated memory: 3.122 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_w23_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_w23_Rj8b' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' is 27648 from HDL expression: (do_init_reg_3699 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_41s_41_1_1': 31 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_34s_34_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_1729_10_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_w23_Rj8b' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.79 seconds. CPU system time: 0.15 seconds. Elapsed time: 1.94 seconds; current allocated memory: 3.187 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3846' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3857' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3868' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3879' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3890' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3901' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3912' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3923' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3934' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3945' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3956' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3967' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3978' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3989' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4000' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4011' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4022' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4033' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4044' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4055' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4066' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4077' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4088' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4099' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4110' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4121' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4363' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4847' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4968' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5089' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5331' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5452' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5936' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6057' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6178' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6299' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6420' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_94' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_83' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_72' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_61' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_50' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_39' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3928' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3929' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3930' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3931' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3932' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3933' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3935' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3936' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3937' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3938' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3939' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3940' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3941' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3942' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3943' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3944' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3839' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3946' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3840' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3947' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3841' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3948' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3842' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3949' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3843' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3950' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3844' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3951' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3845' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3952' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3847' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3953' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3848' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3954' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3849' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3955' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3850' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3957' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3851' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3958' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3852' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3959' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3853' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3960' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3854' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3961' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3855' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3962' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3856' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3963' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3858' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3964' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3859' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3965' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3860' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3966' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3861' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3968' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3862' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3969' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3863' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3970' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3864' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3971' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3865' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3972' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3866' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3973' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3867' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3974' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3869' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3975' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3870' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3976' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3871' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3977' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3872' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3979' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3873' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3980' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3874' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3981' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3875' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3982' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3876' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3983' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3877' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3984' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3878' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3985' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3880' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3986' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3881' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3987' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3882' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3988' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3883' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3990' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3884' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3991' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3885' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3992' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3886' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3993' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3887' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3994' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3888' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3995' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3889' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3996' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3891' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3997' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3892' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3998' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3893' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3894' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4001' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3895' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4002' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3896' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4003' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3897' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4004' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3898' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4005' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3899' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4006' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3900' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4007' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3902' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4008' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3903' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4009' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3904' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4010' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3905' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4012' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3906' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4013' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3907' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4014' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3908' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4015' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3909' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4016' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3910' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4017' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3911' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4018' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3913' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4019' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3914' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4020' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3915' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4021' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3916' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4023' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3917' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4024' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3918' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4025' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3919' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4026' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3920' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4027' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3921' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4028' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3922' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4029' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3924' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4030' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3925' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4031' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3926' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4032' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3927' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4319' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4330' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4341' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4352' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4374' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4385' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4396' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4407' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4418' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4429' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4440' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4451' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4462' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5848' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5859' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5870' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5881' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5892' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5903' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5914' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5925' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5947' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5958' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5969' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5980' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5991' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6002' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6013' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4858' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6024' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4869' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6035' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4880' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6046' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4891' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6068' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4902' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6079' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4913' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6090' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4924' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6101' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4935' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6112' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4946' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6123' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4957' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6134' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4979' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4990' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5001' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5012' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6189' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5023' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5034' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5045' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5056' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5067' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5078' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5100' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5111' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5122' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6288' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5133' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6310' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6321' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6332' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6343' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5177' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6354' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5188' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6365' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6376' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6387' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6398' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6409' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6431' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6442' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6453' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5287' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6464' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5298' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5309' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5320' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5342' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5353' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5364' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5375' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5386' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5397' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5408' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5419' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5430' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5441' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5463' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4034' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4035' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4036' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4037' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4038' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4039' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4040' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4041' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4042' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4043' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4045' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4046' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4047' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4048' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4049' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4050' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4051' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4052' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4053' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4054' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4056' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4057' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4058' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4059' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4060' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4061' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4062' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4063' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4064' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4065' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4067' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4068' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4069' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4070' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4071' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4072' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4073' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4074' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4075' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4076' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4078' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4079' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4080' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4081' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4082' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4083' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4084' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4085' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4086' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4087' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4089' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4090' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4091' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4092' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4093' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4094' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4095' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4096' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4097' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4098' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4100' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4101' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4102' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4103' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4104' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4105' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4106' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4107' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4108' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4109' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4111' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4112' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4113' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4114' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4115' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4116' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4117' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4118' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4119' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4120' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4132' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4187' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4297' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4308' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_99' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_98' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_97' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_96' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_95' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_93' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_92' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_91' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_90' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_89' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_88' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_87' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_86' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_85' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_84' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_82' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_81' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_80' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_79' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_78' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_77' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_76' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_75' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_74' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_73' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_71' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_70' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_69' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_68' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_67' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_66' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_65' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_64' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_63' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_62' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_60' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_59' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_58' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_57' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_56' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_55' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_54' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_53' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_52' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_51' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_49' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_48' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_47' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_46' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_45' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_44' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_43' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_42' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_41' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_40' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_38' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_37' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_36' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_35' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_34' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_33' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_32' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_31' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_30' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_12' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 36.81 seconds. CPU system time: 3.51 seconds. Elapsed time: 40.38 seconds; current allocated memory: 3.287 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.59 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.65 seconds; current allocated memory: 3.300 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.46 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.48 seconds; current allocated memory: 3.305 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.3 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.33 seconds; current allocated memory: 3.308 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.29 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.31 seconds; current allocated memory: 3.312 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.27 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.3 seconds; current allocated memory: 3.313 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.23 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.24 seconds; current allocated memory: 3.315 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1007_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1039_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1008_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1040_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1019_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1051_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2keb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1030_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1062_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1033_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2khb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1065_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1034_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1066_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1035_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2klb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1067_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1036_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2knb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1068_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1037_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1069_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1038_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2krb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1070_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2ksb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1009_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2ktb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1041_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1010_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1042_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1011_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1043_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1012_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1044_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1013_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1045_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1014_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1046_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1015_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1047_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1016_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1048_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1017_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1049_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1018_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1050_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1020_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1052_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1021_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1053_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1022_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1054_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1023_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1055_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1024_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1056_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1025_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1057_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1026_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1058_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1027_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1059_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1028_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1060_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1029_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1061_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1031_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1063_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1032_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1064_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2lab' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.05 seconds. CPU system time: 0.4 seconds. Elapsed time: 4.45 seconds; current allocated memory: 3.318 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s_outidx_8_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s_outidx_8_ROM_lbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s_w25_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s_w25_ROM_NP_BRlcb' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s' is 9216 from HDL expression: (do_init_reg_1334 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_11s_42s_43_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_42s_43_1_1': 7 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_577_9_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_9_2_42_1_1': 8 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s_w25_ROM_NP_BRlcb' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.01 seconds. CPU system time: 0.11 seconds. Elapsed time: 1.12 seconds; current allocated memory: 3.344 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5327' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_79' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5328' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_78' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5329' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_77' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5330' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_76' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5332' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_75' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5333' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_74' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5334' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_73' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5335' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_72' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5336' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_71' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5337' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_70' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5338' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5096' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5339' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5108' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5340' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5120' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5341' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5132' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5343' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5344' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5345' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5346' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5181' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5347' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5348' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5349' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5350' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5351' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5352' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5354' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5355' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5356' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5290' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5357' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5302' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5358' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5314' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5359' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5324' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5360' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5325' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5361' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5326' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5130' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5398' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5131' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5399' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5134' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5400' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5135' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5401' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5136' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5097' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5137' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5098' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5099' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5101' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5102' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5103' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5104' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5105' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5106' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5107' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5109' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5110' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5112' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5113' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5114' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5115' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5116' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5117' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5118' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5119' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5121' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5123' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5124' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5125' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5126' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5127' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5128' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5129' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5362' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5363' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5365' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5366' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5367' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5368' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5369' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5370' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5371' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5372' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5373' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5374' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5376' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5377' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5378' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5379' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5380' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5381' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5382' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5383' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5384' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5385' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5387' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5388' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5389' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5390' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5391' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5392' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5393' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5394' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5395' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5396' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5178' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5179' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5180' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5182' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5183' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5184' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5185' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5186' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5187' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5189' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5190' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5191' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5192' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5288' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5289' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5291' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5292' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5293' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5294' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5295' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5296' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5297' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5299' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5300' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5301' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5303' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5304' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5305' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5306' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5307' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5308' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5310' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5311' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5312' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5313' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5315' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5316' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5317' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5318' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5319' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5321' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5322' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5323' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_4' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 13.28 seconds. CPU system time: 1.49 seconds. Elapsed time: 14.77 seconds; current allocated memory: 3.378 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.37 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.4 seconds; current allocated memory: 3.384 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.35 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.38 seconds; current allocated memory: 3.387 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.31 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.33 seconds; current allocated memory: 3.388 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' pipeline 'ConcatLoopHeight_ConcatLoopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.31 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.33 seconds; current allocated memory: 3.393 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.24 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.26 seconds; current allocated memory: 3.394 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.29 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.32 seconds; current allocated memory: 3.397 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.31 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.32 seconds; current allocated memory: 3.400 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.26 seconds. CPU system time: 0.06 seconds. Elapsed time: 0.33 seconds; current allocated memory: 3.402 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.23 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.26 seconds; current allocated memory: 3.402 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1135_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2ldb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1183_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2leb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1136_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1184_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1147_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1195_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1158_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2ljb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1206_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1169_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2llb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1217_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1178_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1226_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1179_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1227_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1180_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1228_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1181_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2ltb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1229_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1182_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1230_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1137_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1185_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1138_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1186_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lAb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1139_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lBb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1187_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lCb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1140_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1188_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1141_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1189_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1142_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1190_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1143_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1191_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1144_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1192_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1145_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1193_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1146_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1194_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1148_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1196_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1149_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1197_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1150_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1198_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1151_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1199_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1152_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1200_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1153_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1201_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1154_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1202_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1155_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1203_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1156_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1204_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1157_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1205_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1159_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1207_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1160_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1208_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2meb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1161_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1209_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1162_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1210_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1163_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1211_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1164_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mlb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1212_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1165_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1213_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1166_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1214_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1167_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1215_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2msb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1168_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mtb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1216_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1170_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1218_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1171_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1219_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2myb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1172_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mzc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1220_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mAc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1173_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mBc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1221_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mCc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1174_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mDc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1222_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mEc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1175_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mFc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1223_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mGc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1176_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mHc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1224_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mIc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1177_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mJc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1225_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mKc' due to the length limit 80 +INFO: [RTGEN 206-104] Estimated max fanout for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s' is 6912 from HDL expression: (1'b1 == ap_CS_fsm_state1) +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 5.79 seconds. CPU system time: 0.59 seconds. Elapsed time: 6.38 seconds; current allocated memory: 3.409 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_w29_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_w29_RmLc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' is 13824 from HDL expression: (do_init_reg_1875 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_40s_40_1_1': 15 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_33s_33_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_865_9_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_w29_RmLc' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.16 seconds. CPU system time: 0.1 seconds. Elapsed time: 1.27 seconds; current allocated memory: 3.441 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6115' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_59' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6116' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_58' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6117' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_57' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6118' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_56' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6119' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_55' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6120' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_54' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6121' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_53' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6122' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_52' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6124' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_51' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6125' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_50' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6126' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6127' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6128' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6129' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6130' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6131' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6132' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6133' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6135' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6136' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6137' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5841' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5853' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5865' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5877' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5889' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5901' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5913' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5926' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5938' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5950' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5962' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5974' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5986' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5998' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6010' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6022' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6034' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6047' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6059' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6071' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6083' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6095' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6107' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6110' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6111' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6113' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6114' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5839' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5840' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5842' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5843' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5844' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5845' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5846' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5847' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5849' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5850' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5851' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5852' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5854' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5855' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5856' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5857' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5858' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5860' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5861' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5862' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5863' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5864' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5866' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5867' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5868' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5869' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5871' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5872' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5873' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5874' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5875' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5876' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5994' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5935' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5995' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5937' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5996' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5939' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5997' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5940' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5941' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6000' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5942' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6001' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5943' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6003' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5944' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6004' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5945' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6005' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5946' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6006' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5948' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6007' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5949' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6008' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5951' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6009' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5952' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6011' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5953' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6012' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5954' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6014' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5955' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6015' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5956' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6016' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5957' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6017' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5959' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6018' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5960' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6019' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5961' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6020' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5963' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6021' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5964' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6023' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5965' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6025' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5966' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6026' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5967' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6027' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5968' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6028' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5970' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6029' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5971' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6030' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5972' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6031' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5973' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6032' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5975' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6033' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5976' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6036' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5977' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6037' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5978' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6038' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5979' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6039' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5981' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6040' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5982' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6041' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5983' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6042' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5984' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6043' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5985' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6044' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5987' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6045' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5988' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6048' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5989' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6049' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5990' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6050' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5992' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6051' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5993' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5878' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5879' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5880' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5882' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5883' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5884' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5885' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5886' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5887' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5888' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5890' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5891' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5893' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5894' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5895' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5896' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5897' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5898' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5899' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5900' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5902' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5904' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5905' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5906' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5907' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5908' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5909' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5910' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5911' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5912' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5915' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5916' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5917' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5918' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5919' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5920' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5921' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5922' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5923' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5924' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5927' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5928' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5929' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5930' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5931' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5932' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5933' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5934' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6052' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6053' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6054' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6055' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6056' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6058' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6060' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6061' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6062' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6063' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6064' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6065' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6066' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6067' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6069' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6070' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6072' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6073' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6074' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6075' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6076' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6077' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6078' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6080' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6081' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6082' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6084' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6085' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6086' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6087' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6088' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6089' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6091' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6092' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6093' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6094' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6096' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6097' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6098' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6099' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6100' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6102' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6103' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6104' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6105' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6106' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6108' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6109' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_1' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 21.58 seconds. CPU system time: 2.1 seconds. Elapsed time: 23.7 seconds; current allocated memory: 3.488 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.45 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.48 seconds; current allocated memory: 3.495 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.06 seconds. Elapsed time: 0.38 seconds; current allocated memory: 3.498 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.35 seconds; current allocated memory: 3.500 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.3 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.34 seconds; current allocated memory: 3.505 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.33 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.36 seconds; current allocated memory: 3.506 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.27 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.28 seconds; current allocated memory: 3.506 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_831_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mMc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_847_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mNc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_832_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mOc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_848_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mPc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_839_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mQc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_855_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mRc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_840_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mSc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_856_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mTc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_841_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mUc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_857_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mVc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_842_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mWc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_858_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mXc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_843_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mYc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_859_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mZc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_844_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m0c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_860_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m1c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_845_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m2c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_861_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m3c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_846_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m4c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_862_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m5c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_833_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m6c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_849_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m7c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_834_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m8c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_850_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m9c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_835_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2nac' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_851_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2nbc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_836_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2ncc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_852_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2ndc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_837_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2nec' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_853_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2nfc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_838_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2ngc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_854_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2nhc' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.84 seconds. CPU system time: 0.16 seconds. Elapsed time: 2.01 seconds; current allocated memory: 3.509 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s_outidx_9_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s_outidx_9_ROM_nic' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s_w31_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s_w31_ROM_NP_BRnjc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_41s_42_1_1': 3 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_41s_42_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_289_8_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_9_2_41_1_1': 4 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s_w31_ROM_NP_BRnjc' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.83 seconds. CPU system time: 0.1 seconds. Elapsed time: 0.94 seconds; current allocated memory: 3.520 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4324' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4325' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4326' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4327' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4328' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4329' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4331' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4332' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4333' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4334' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4335' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4336' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4337' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4293' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4338' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4305' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4339' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4317' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4340' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4323' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4377' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4359' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4378' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4360' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4379' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4361' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4380' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4362' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4381' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4364' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4382' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4365' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4383' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4366' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4384' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4367' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4386' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4368' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4387' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4369' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4388' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4370' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4389' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4371' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4390' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4372' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4391' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4373' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4392' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4375' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4393' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4376' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4412' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4413' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4287' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4414' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4288' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4415' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4289' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4290' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4291' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4292' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4294' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4295' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4296' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4298' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4299' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4300' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4301' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4302' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4342' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4343' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4344' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4345' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4346' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4347' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4348' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4349' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4350' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4351' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4353' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4354' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4355' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4356' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4357' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4358' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4394' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4395' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4397' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4398' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4399' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4400' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4401' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4402' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4403' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4404' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4405' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4406' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4408' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4409' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4410' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4411' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4303' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4304' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4306' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4307' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4309' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4310' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4311' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4312' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4313' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4314' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4315' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4316' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4318' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4320' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4321' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4322' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_2' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 7.78 seconds. CPU system time: 0.76 seconds. Elapsed time: 8.55 seconds; current allocated memory: 3.538 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.35 seconds; current allocated memory: 3.541 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.28 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.32 seconds; current allocated memory: 3.543 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.33 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.36 seconds; current allocated memory: 3.548 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' pipeline 'ConcatLoopHeight_ConcatLoopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.36 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.39 seconds; current allocated memory: 3.551 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.25 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.28 seconds; current allocated memory: 3.552 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.31 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.34 seconds; current allocated memory: 3.553 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.37 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.38 seconds; current allocated memory: 3.558 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.36 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.39 seconds; current allocated memory: 3.561 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.25 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.28 seconds; current allocated memory: 3.562 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_895_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nkc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_919_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nlc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_896_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nmc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_920_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nnc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_907_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2noc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_931_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2npc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_912_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nqc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_936_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nrc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_913_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nsc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_937_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2ntc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_914_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nuc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_938_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nvc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_915_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nwc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_939_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nxc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_916_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nyc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_940_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nzc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_917_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nAc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_941_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nBc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_918_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nCc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_942_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nDc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_897_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nEc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_921_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nFc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_898_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nGc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_922_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nHc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_899_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nIc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_923_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nJc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_900_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nKc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nKc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nKc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_924_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nLc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nLc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nLc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_901_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nMc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nMc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nMc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_925_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nNc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nNc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nNc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_902_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nOc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nOc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nOc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_926_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nPc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nPc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nPc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_903_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nQc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nQc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nQc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_927_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nRc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nRc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nRc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_904_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nSc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nSc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nSc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_928_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nTc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nTc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nTc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_905_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nUc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nUc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nUc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_929_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nVc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nVc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nVc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_906_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nWc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nWc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nWc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_930_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nXc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nXc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nXc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_908_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nYc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nYc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nYc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_932_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nZc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nZc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nZc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_909_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2n0c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_933_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2n1c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_910_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2n2c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_934_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2n3c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_911_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2n4c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_935_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2n5c' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 3.53 seconds. CPU system time: 0.37 seconds. Elapsed time: 3.9 seconds; current allocated memory: 3.566 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_w35_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_w35_Rn6c' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' is 6912 from HDL expression: (do_init_reg_963 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_33s_33_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_39s_39_1_1': 7 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_433_8_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_w35_Rn6c' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.87 seconds. CPU system time: 0.09 seconds. Elapsed time: 0.96 seconds; current allocated memory: 3.581 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_99' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_98' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_97' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_96' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_95' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_94' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_93' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_92' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_91' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_90' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_6' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 12 seconds. CPU system time: 1.18 seconds. Elapsed time: 13.19 seconds; current allocated memory: 3.605 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.37 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.39 seconds; current allocated memory: 3.609 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.35 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.39 seconds; current allocated memory: 3.611 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.33 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.37 seconds; current allocated memory: 3.615 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.38 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.42 seconds; current allocated memory: 3.617 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.38 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.42 seconds; current allocated memory: 3.619 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.25 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.28 seconds; current allocated memory: 3.622 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1391_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn7c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1399_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn8c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1392_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn9c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1400_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2doac' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1393_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dobc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1401_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2docc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1394_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dodc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1402_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2doec' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1395_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dofc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1403_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dogc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1396_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dohc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1404_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2doic' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1397_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dojc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1405_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dokc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1398_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dolc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1406_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2domc' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.1 seconds. CPU system time: 0.11 seconds. Elapsed time: 1.21 seconds; current allocated memory: 3.625 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s_outidx_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s_outidx_ROM_AUonc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s_w37_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s_w37_ROM_NP_BRooc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_11s_40s_41_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_40s_41_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_9_2_40_1_1': 2 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s_outidx_ROM_AUonc' using auto ROMs. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s_w37_ROM_NP_BRooc' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.82 seconds. CPU system time: 0.08 seconds. Elapsed time: 0.9 seconds; current allocated memory: 3.631 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_14' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.42 seconds. CPU system time: 0.45 seconds. Elapsed time: 4.87 seconds; current allocated memory: 3.638 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.35 seconds; current allocated memory: 3.640 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.34 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.39 seconds; current allocated memory: 3.642 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_12s_30s_30_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_17_3_12_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_17_3_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.51 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.55 seconds; current allocated memory: 3.644 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.28 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.31 seconds; current allocated memory: 3.645 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s_sigmoid_table_ROM_AUTO_1R' to 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s_sigmoid_table_Ropc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s' pipeline 'SigmoidActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s_sigmoid_table_Ropc' using auto ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.43 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.48 seconds; current allocated memory: 3.649 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'myproject' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low. +INFO: [RTGEN 206-500] Setting interface mode on port 'myproject/x' to 'axis' (register, both mode). +INFO: [RTGEN 206-500] Setting interface mode on port 'myproject/layer40_out' to 'axis' (register, both mode). +INFO: [RTGEN 206-500] Setting interface mode on function 'myproject' to 'ap_ctrl_hs'. +INFO: [SYN 201-210] Renamed object name 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_U0' to 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4oqc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_U0' to 'start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6orc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_U0' to 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4osc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_U0' to 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7otc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_U0' to 'start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configouc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_U0' to 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10ovc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_U0' to 'start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384owc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13oxc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15oyc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_U0' to 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18ozc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_U0' to 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20oAc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24oBc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26oCc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_U0' to 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30oDc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_U0' to 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32oEc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_U0' to 'start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3oFc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_U0' to 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config5oGc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_U0' to 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37oHc' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'myproject'. +INFO: [RTMG 210-285] Implementing FIFO 'layer44_out_U(myproject_fifo_w16_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer2_out_U(myproject_fifo_w296_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer3_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer45_out_U(myproject_fifo_w128_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer4_out_U(myproject_fifo_w320_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer5_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer41_cpy1_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer41_cpy2_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer6_out_U(myproject_fifo_w128_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer46_out_U(myproject_fifo_w128_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer7_out_U(myproject_fifo_w640_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer8_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer47_out_U(myproject_fifo_w256_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer9_out_U(myproject_fifo_w656_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer10_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer42_cpy1_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer42_cpy2_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer11_out_U(myproject_fifo_w256_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer48_out_U(myproject_fifo_w256_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer12_out_U(myproject_fifo_w1312_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer13_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer49_out_U(myproject_fifo_w512_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer14_out_U(myproject_fifo_w1344_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer15_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer43_cpy1_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer43_cpy2_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer16_out_U(myproject_fifo_w512_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer50_out_U(myproject_fifo_w512_d100_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer17_out_U(myproject_fifo_w2688_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer18_out_U(myproject_fifo_w1024_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer51_out_U(myproject_fifo_w1024_d100_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer19_out_U(myproject_fifo_w2752_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer20_out_U(myproject_fifo_w1024_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer21_out_U(myproject_fifo_w1024_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer22_out_U(myproject_fifo_w1536_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer52_out_U(myproject_fifo_w1536_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer23_out_U(myproject_fifo_w1376_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer24_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer53_out_U(myproject_fifo_w512_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer25_out_U(myproject_fifo_w1344_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer26_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer27_out_U(myproject_fifo_w512_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer28_out_U(myproject_fifo_w768_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer54_out_U(myproject_fifo_w768_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer29_out_U(myproject_fifo_w672_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer30_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer55_out_U(myproject_fifo_w256_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer31_out_U(myproject_fifo_w656_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer32_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer33_out_U(myproject_fifo_w256_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer34_out_U(myproject_fifo_w384_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer56_out_U(myproject_fifo_w384_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer35_out_U(myproject_fifo_w328_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer36_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer57_out_U(myproject_fifo_w128_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer37_out_U(myproject_fifo_w320_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer38_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer39_out_U(myproject_fifo_w36_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_U0_U(myproject_start_for_conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4oqc_U(myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4oqc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_U0_U(myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0_U(myproject_start_for_clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6orc_U(myproject_start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6orc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0_U(myproject_start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4osc_U(myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4osc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7otc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7otc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_U0_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configouc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configouc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10ovc_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10ovc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384owc_U(myproject_start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384owc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0_U(myproject_start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0_U(myproject_start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13oxc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13oxc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15oyc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15oyc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0_U(myproject_start_for_clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_U0_U(myproject_start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0_U(myproject_start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18ozc_U(myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18ozc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20oAc_U(myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20oAc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_U0_U(myproject_start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24oBc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24oBc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26oCc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26oCc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_U0_U(myproject_start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30oDc_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30oDc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32oEc_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32oEc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_U0_U(myproject_start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3oFc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3oFc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config5oGc_U(myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config5oGc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37oHc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37oHc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_U0_U(myproject_start_for_pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_U0_U(myproject_start_for_sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_U0)' using Shift Registers. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 7.53 seconds. CPU system time: 0.76 seconds. Elapsed time: 8.31 seconds; current allocated memory: 3.658 GB. +INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 2.02 seconds. CPU system time: 0.37 seconds. Elapsed time: 2.63 seconds; current allocated memory: 3.667 GB. +INFO: [HLS 200-111] Finished Updating report files: CPU user time: 14.39 seconds. CPU system time: 0.14 seconds. Elapsed time: 14.59 seconds; current allocated memory: 3.759 GB. +INFO: [VHDL 208-304] Generating VHDL RTL for myproject. +INFO: [VLOG 209-307] Generating Verilog RTL for myproject. +INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were NOT satisfied. +INFO: [HLS 200-789] **** Estimated Fmax: 224.75 MHz +INFO: [HLS 200-2161] Finished Command csynth_design Elapsed time: 00:18:23; Allocated memory: 3.512 GB. +***** C/RTL SYNTHESIS COMPLETED IN 0h18m24s ***** +INFO: [HLS 200-112] Total CPU user time: 1077.97 seconds. Total CPU system time: 39.22 seconds. Total elapsed time: 1108.37 seconds; peak allocated memory: 3.759 GB. +INFO: [vitis-run 60-791] Total elapsed time: 0h 18m 30s +INFO: [vitis-run 60-1662] Stopping dispatch session having empty uuid. diff --git a/logs/hls_run_tcl_4666.backup.log b/logs/hls_run_tcl_4666.backup.log new file mode 100644 index 0000000000000000000000000000000000000000..4808adb3ab8dd98bcaeeb6f572de549e4a02fae1 --- /dev/null +++ b/logs/hls_run_tcl_4666.backup.log @@ -0,0 +1,1821 @@ +INFO: [vitis-run 82-31] Launching vitis_hls: vitis_hls -nolog -run tcl -f /home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl -work_dir /home/ubuntu/lithobench/hls4ml_mini_unet + +****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2024.1 (64-bit) + **** SW Build 5069499 on May 21 2024 + **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 + **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 + **** Start of session at: Sat Mar 28 14:47:06 2026 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. + +source /opt/Xilinx/Vitis_HLS/2024.1/scripts/vitis_hls/hls.tcl -notrace +INFO: [HLS 200-10] For user 'ubuntu' on host 'ip-172-31-42-252.ec2.internal' (Linux_x86_64 version 5.15.0-1084-aws) on Sat Mar 28 14:47:08 UTC 2026 +INFO: [HLS 200-10] On os Ubuntu 20.04.6 LTS +INFO: [HLS 200-10] In directory '/home/ubuntu/lithobench/hls4ml_mini_unet' +Sourcing Tcl script '/home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl' +INFO: [HLS 200-1510] Running: open_project myproject_prj +INFO: [HLS 200-10] Creating and opening project '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj'. +INFO: [HLS 200-1510] Running: set_top myproject +INFO: [HLS 200-1510] Running: add_files firmware/myproject.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding design file 'firmware/myproject.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb myproject_test.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding test bench file 'myproject_test.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb firmware/weights +INFO: [HLS 200-10] Adding test bench file 'firmware/weights' to the project +INFO: [HLS 200-1510] Running: add_files -tb tb_data +INFO: [HLS 200-10] Adding test bench file 'tb_data' to the project +INFO: [HLS 200-1510] Running: open_solution solution1 +INFO: [HLS 200-10] Creating and opening solution '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1'. +INFO: [HLS 200-1505] Using default flow_target 'vivado' +Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1505.html +INFO: [HLS 200-1510] Running: config_array_partition -maximum_size 4096 +ERROR: [HLS 200-101] config_array_partition: Unknown option '-maximum_size'. +ERROR: [HLS 200-101] config_array_partition: Unknown option '4096'. +SYNTAX + config_array_partition [OPTIONS] + -auto_partition_threshold *** DEPRECATED*** + -auto_promotion_threshold *** DEPRECATED*** + -complete_threshold + -throughput_driven + +SEE ALSO + INI: syn.array_partition.complete_threshold syn.array_partition.throughput_driven + docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1399-vitis-hls&resourceid=vyw1583260160301.html + +INFO: [HLS 200-1510] Running: config_compile -name_max_length 80 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: set_part xcvu47p-fsvh2892-2L-e +INFO: [HLS 200-1611] Setting target device to 'xcvu47p-fsvh2892-2L-e' +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: config_schedule -enable_dsp_full_reg=false +INFO: [HLS 200-1510] Running: create_clock -period 5 -name default +INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. +INFO: [HLS 200-1510] Running: set_clock_uncertainty 27% default +INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 1.35ns. +***** C/RTL SYNTHESIS ***** +INFO: [HLS 200-1510] Running: csynth_design +INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 223.766 MB. +INFO: [HLS 200-10] Analyzing design file 'firmware/myproject.cpp' ... +WARNING: [HLS 207-5570] unexpected pragma argument 'softmax', expects function/operation (firmware/nnet_utils/nnet_activation.h:402:36) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:33:9) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:107:9) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:189:9) +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:242:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:242:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:248:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:248:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:258:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:258:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:264:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:264:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:274:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:274:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:280:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:280:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:290:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:290:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:296:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:296:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:306:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:306:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:312:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:312:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:322:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:322:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:328:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:328:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:338:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:338:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:344:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:344:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:348:100) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:348:105) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 200-471] Dataflow form checks found 30 issue(s) in file firmware/myproject.cpp +Resolution: For help on HLS 200-471 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-471.html +WARNING: [HLS 207-5292] unused parameter 'keep' (firmware/nnet_utils/nnet_helpers.h:285:99) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:14:36) +WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:15:36) +WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:16:44) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:24:24) +WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:25:24) +WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:26:32) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:33:30) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:33:58) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:34:51) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:35:49) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:42:30) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:42:58) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:43:51) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:44:49) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:51:29) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:51:80) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:52:50) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:53:48) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_code_gen.h:16:39) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_code_gen.h:17:38) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_code_gen.h:18:60) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_code_gen.h:19:58) +WARNING: [HLS 207-5584] there are more than one pragma inline in the function scope, ignore the pragma (/opt/Xilinx/Vitis_HLS/2024.1/common/technology/autopilot/ap_shift_reg.h:47:9) +INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 36.8 seconds. CPU system time: 2.27 seconds. Elapsed time: 39.92 seconds; current allocated memory: 235.973 MB. +INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target. +INFO: [HLS 200-1995] There were 28,528 instructions in the design after the 'Compile/Link' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 188,474 instructions in the design after the 'Unroll/Inline' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 96,416 instructions in the design after the 'Unroll/Inline (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 82,279 instructions in the design after the 'Unroll/Inline (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 37,407 instructions in the design after the 'Unroll/Inline (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 65,234 instructions in the design after the 'Array/Struct' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 44,307 instructions in the design after the 'Array/Struct (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 45,206 instructions in the design after the 'Array/Struct (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 93,112 instructions in the design after the 'Array/Struct (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 93,567 instructions in the design after the 'Array/Struct (step 5)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 95,263 instructions in the design after the 'Performance' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 202,374 instructions in the design after the 'Performance (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 199,687 instructions in the design after the 'Performance (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 199,687 instructions in the design after the 'Performance (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 160,662 instructions in the design after the 'HW Transforms' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 152,727 instructions in the design after the 'HW Transforms (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config60>' (firmware/nnet_utils/nnet_sepconv_stream.h:103:9) +WARNING: [HLS 214-273] In function 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config60_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config60_mult::weight_t*, config60_mult::bias_t*)', Pragma conflict happens on 'INLINE' and 'FUNCTION_INSTANTIATE' pragmas: same function (firmware/nnet_utils/nnet_dense_resource.h:89:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config46>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config46>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config46>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config46>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 1u>, config2>(nnet::array, 1u>::value_type (*) [config2::n_chan], nnet::array, 1u>::value_type*)' into 'void nnet::shift_line_buffer, 1u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], nnet::array, 1u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, config2_mult::weight_t*, config2_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*) (.55)' into 'void nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config47>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config47>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config47>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config47>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config4>(nnet::array, 8u>::value_type (*) [config4::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config4_mult::weight_t*, config4_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 8u>, config4>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*) (.54)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config6>(nnet::array, 8u>::value_type (*) [config6::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::Op_max >::operator()(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>) (.36)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' (firmware/nnet_utils/nnet_common.h:44:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:15) +INFO: [HLS 214-131] Inlining function 'nnet::Op_max >::operator()(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>) (.36)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:12) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:44) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config6>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.52)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config6>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.52)' into 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 8u>::operator[](unsigned long) (.51)' into 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' into 'void nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config48>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config48>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config48>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config48>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config7>(nnet::array, 8u>::value_type (*) [config7::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config7_mult::weight_t*, config7_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 16u>, config7>(hls::stream, 8u>, 0>&, hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*) (.48)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>(hls::stream, 8u>, 0>&, hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config49>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config49>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config49>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config49>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config9>(nnet::array, 16u>::value_type (*) [config9::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config9_mult::weight_t*, config9_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 16u>, config9>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*) (.47)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config11>(nnet::array, 16u>::value_type (*) [config11::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config11>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.45)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config11>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.45)' into 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 16u>::operator[](unsigned long) (.44)' into 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' into 'void nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config50>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config50>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config50>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config50>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config12>(nnet::array, 16u>::value_type (*) [config12::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config12_mult::weight_t*, config12_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 32u>, config12>(hls::stream, 16u>, 0>&, hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*) (.41)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>(hls::stream, 16u>, 0>&, hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config51>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config51>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config51>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config51>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config14>(nnet::array, 32u>::value_type (*) [config14::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config14_mult::weight_t*, config14_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 32u>, config14>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*) (.40)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config16>(nnet::array, 32u>::value_type (*) [config16::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config16>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.34)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config16>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.34)' into 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 32u>::operator[](unsigned long) (.33)' into 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' into 'void nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config52>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config52>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config52>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config52>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config17>(nnet::array, 32u>::value_type (*) [config17::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config17_mult::weight_t*, config17_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 64u>, config17>(hls::stream, 32u>, 0>&, hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*) (.30)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>(hls::stream, 32u>, 0>&, hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config53>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config53>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config53>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config53>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 64u>, config19>(nnet::array, 64u>::value_type (*) [config19::n_chan], nnet::array, 64u>::value_type*)' into 'void nnet::shift_line_buffer, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], nnet::array, 64u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config19_mult::weight_t*, config19_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 64u>, nnet::array, 64u>, config19>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*) (.26)' into 'void nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config54>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config54>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config54>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config54>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 96u>, config23>(nnet::array, 96u>::value_type (*) [config23::n_chan], nnet::array, 96u>::value_type*)' into 'void nnet::shift_line_buffer, 96u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], nnet::array, 96u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config23_mult::weight_t*, config23_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 96u>, nnet::array, 32u>, config23>(hls::stream, 96u>, 0>&, hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*) (.23)' into 'void nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>(hls::stream, 96u>, 0>&, hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config55>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config55>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config55>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config55>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config25>(nnet::array, 32u>::value_type (*) [config25::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config25_mult::weight_t*, config25_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 32u>, config25>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*) (.19)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config56>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config56>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config56>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config56>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 48u>, config29>(nnet::array, 48u>::value_type (*) [config29::n_chan], nnet::array, 48u>::value_type*)' into 'void nnet::shift_line_buffer, 48u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], nnet::array, 48u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config29_mult::weight_t*, config29_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 48u>, nnet::array, 16u>, config29>(hls::stream, 48u>, 0>&, hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*) (.16)' into 'void nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>(hls::stream, 48u>, 0>&, hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config57>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config57>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config57>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config57>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config31>(nnet::array, 16u>::value_type (*) [config31::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config31_mult::weight_t*, config31_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 16u>, config31>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*) (.12)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config58>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config58>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config58>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config58>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 24u>, config35>(nnet::array, 24u>::value_type (*) [config35::n_chan], nnet::array, 24u>::value_type*)' into 'void nnet::shift_line_buffer, 24u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], nnet::array, 24u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config35_mult::weight_t*, config35_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 24u>, nnet::array, 8u>, config35>(hls::stream, 24u>, 0>&, hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*) (.9)' into 'void nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>(hls::stream, 24u>, 0>&, hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config59>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config59>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config59>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config59>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config37>(nnet::array, 8u>::value_type (*) [config37::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config37_mult::weight_t*, config37_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 8u>, config37>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*) (.5)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config60_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config60_mult::weight_t*, config60_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const (.4)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config60>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config60::weight_t*, config60::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:100:13) +INFO: [HLS 214-131] Inlining function 'nnet::array, 1u>::operator[](unsigned long) (.2)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config60>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config60::weight_t*, config60::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:110:2) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config60_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.3)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config60>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config60::weight_t*, config60::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:104:2) +INFO: [HLS 214-131] Inlining function 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config60>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config60::weight_t*, config60::bias_t*)' into 'void nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config60>(hls::stream, 8u>, 0>&, hls::stream, 1u>, 0>&, config60::weight_t*, config60::bias_t*)' (firmware/nnet_utils/nnet_sepconv2d_stream.h:86:21) +INFO: [HLS 214-291] Loop 'VITIS_LOOP_58_4' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_transpose_stream.h:58:26) +INFO: [HLS 214-291] Loop 'VITIS_LOOP_48_2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_transpose_stream.h:48:26) +INFO: [HLS 214-291] Loop 'VITIS_LOOP_21_1' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_transpose.h:21:22) +INFO: [HLS 214-291] Loop 'SigmoidPackLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_activation_stream.h:88:9) +INFO: [HLS 214-291] Loop 'ReLUPackLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_activation_stream.h:49:9) +INFO: [HLS 214-291] Loop 'MultLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_dense_resource.h:142:9) +INFO: [HLS 214-291] Loop 'KernelPushHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:205:5) +INFO: [HLS 214-291] Loop 'KernelPushChannel' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:208:9) +INFO: [HLS 214-291] Loop 'KernelShiftWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:189:5) +INFO: [HLS 214-291] Loop 'KernelShiftHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:192:9) +INFO: [HLS 214-291] Loop 'KernelShiftChannel' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:194:13) +INFO: [HLS 214-291] Loop 'LineBufferDataIn' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:236:5) +INFO: [HLS 214-291] Loop 'LineBufferShift' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:239:9) +INFO: [HLS 214-291] Loop 'UpdateBuffer' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:228:5) +INFO: [HLS 214-291] Loop 'MultLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_dense_resource.h:55:9) +INFO: [HLS 214-291] Loop 'ConcatPackInput1' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_merge_stream.h:245:13) +INFO: [HLS 214-291] Loop 'ConcatPackInput2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_merge_stream.h:251:13) +INFO: [HLS 214-291] Loop 'ImageWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:22:9) +INFO: [HLS 214-291] Loop 'ImageChan' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:28:13) +INFO: [HLS 214-291] Loop 'ResizeHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:36:9) +INFO: [HLS 214-291] Loop 'ImageWidth2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:40:13) +INFO: [HLS 214-291] Loop 'ResizeWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:44:17) +INFO: [HLS 214-291] Loop 'ResizeChan' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:51:21) +INFO: [HLS 214-291] Loop 'FiltLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_pooling_stream.h:57:9) +INFO: [HLS 214-291] Loop 'PoolLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_pooling_stream.h:62:13) +INFO: [HLS 214-291] Loop 'ClonePack' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_stream.h:32:9) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_58_4' (firmware/nnet_utils/nnet_transpose_stream.h:58:26) in function 'nnet::transpose, 1u>, nnet::array, 1u>, config42>' completely with a factor of 1 (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_48_2' (firmware/nnet_utils/nnet_transpose_stream.h:48:26) in function 'nnet::transpose, 1u>, nnet::array, 1u>, config42>' completely with a factor of 1 (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_21_1' (firmware/nnet_utils/nnet_transpose.h:21:22) in function 'nnet::transfer_idx' completely with a factor of 3 (firmware/nnet_utils/nnet_transpose.h:18:0) +INFO: [HLS 214-186] Unrolling loop 'SigmoidPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:88:9) in function 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>' completely with a factor of 1 (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-186] Unrolling loop 'InitData' (firmware/nnet_utils/nnet_sepconv_stream.h:98:5) in function 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config60>' completely with a factor of 8 (firmware/nnet_utils/nnet_sepconv2d_stream.h:58:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config38>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 2 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config37>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config36>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 24u>, config35>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>' completely with a factor of 24 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' completely with a factor of 16 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' completely with a factor of 8 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config32>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config31>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config30>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 48u>, config29>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>' completely with a factor of 48 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' completely with a factor of 32 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' completely with a factor of 16 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config26>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config25>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config24>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 96 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 96u>, config23>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>' completely with a factor of 96 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' completely with a factor of 64 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' completely with a factor of 32 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 8 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 64 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 8 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 64 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 64u>, nnet::array, 64u>, relu_config20>' completely with a factor of 64 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 128 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 64u>, config19>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 64u>, nnet::array, 64u>, relu_config18>' completely with a factor of 64 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config17>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config16>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>' completely with a factor of 32 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config15>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config14>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config13>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config12>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config11>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>' completely with a factor of 16 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config10>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config9>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config8>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 4 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config7>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config6>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>' completely with a factor of 8 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config5>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 2 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config4>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config3>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 1u>, config2>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>' completely with a factor of 1 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_58_4' (firmware/nnet_utils/nnet_transpose_stream.h:58:26) in function 'nnet::transpose, 64u>, nnet::array, 1u>, config41>' completely with a factor of 1 (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_48_2' (firmware/nnet_utils/nnet_transpose_stream.h:48:26) in function 'nnet::transpose, 64u>, nnet::array, 1u>, config41>' completely with a factor of 64 (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_21_1' (firmware/nnet_utils/nnet_transpose.h:21:22) in function 'nnet::transfer_idx' completely with a factor of 4 (firmware/nnet_utils/nnet_transpose.h:18:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'std::enable_if<(config41::dims) != (2), void>::type nnet::transpose, 64u>, nnet::array, 1u>, config41>(hls::stream, 64u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'std::enable_if<(config41::dims) != (2), void>::type nnet::transpose, 64u>, nnet::array, 1u>, config41>(hls::stream, 64u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-178] Inlining function 'unsigned int nnet::transfer_idx(int)' into 'std::enable_if<(config41::dims) != (2), void>::type nnet::transpose, 64u>, nnet::array, 1u>, config41>(hls::stream, 64u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 1u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], nnet::array, 1u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(config2_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, config2_mult::weight_t*, config2_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config3>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config3>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(config4_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config4_mult::weight_t*, config4_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config5>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config5>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(config7_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config7_mult::weight_t*, config7_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config8>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config8>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(config9_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config9_mult::weight_t*, config9_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config10>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config10>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(config12_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config12_mult::weight_t*, config12_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config13>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config13>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(config14_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config14_mult::weight_t*, config14_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config15>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config15>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config18>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config18>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], nnet::array, 64u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config20>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config20>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 64u>, config21>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 96u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], nnet::array, 96u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(config23_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config23_mult::weight_t*, config23_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config24>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config24>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(config25_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config25_mult::weight_t*, config25_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config26>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config26>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 32u>, config27>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 48u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], nnet::array, 48u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(config29_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config29_mult::weight_t*, config29_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config30>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config30>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(config31_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config31_mult::weight_t*, config31_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config32>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config32>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 16u>, config33>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 24u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], nnet::array, 24u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(config35_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config35_mult::weight_t*, config35_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config36>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config36>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(config37_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config37_mult::weight_t*, config37_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config38>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config38>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'std::enable_if<(config42::dims) != (2), void>::type nnet::transpose, 1u>, nnet::array, 1u>, config42>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-178] Inlining function 'unsigned int nnet::transfer_idx(int)' into 'std::enable_if<(config42::dims) != (2), void>::type nnet::transpose, 1u>, nnet::array, 1u>, config42>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj1EEENS1_IS2_ILi37ELi17ELS3_5ELS4_3ELi0EELj8EEE7config2EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEES6_7config6EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to 'b2': Complete partitioning on dimension 1. (firmware/weights/b2.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b4': Complete partitioning on dimension 1. (firmware/weights/b4.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b7': Complete partitioning on dimension 1. (firmware/weights/b7.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b9': Complete partitioning on dimension 1. (firmware/weights/b9.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b12': Complete partitioning on dimension 1. (firmware/weights/b12.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b14': Complete partitioning on dimension 1. (firmware/weights/b14.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b17': Complete partitioning on dimension 1. (firmware/weights/b17.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b19': Complete partitioning on dimension 1. (firmware/weights/b19.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b23': Complete partitioning on dimension 1. (firmware/weights/b23.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b25': Complete partitioning on dimension 1. (firmware/weights/b25.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b29': Complete partitioning on dimension 1. (firmware/weights/b29.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b31': Complete partitioning on dimension 1. (firmware/weights/b31.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b35': Complete partitioning on dimension 1. (firmware/weights/b35.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b37': Complete partitioning on dimension 1. (firmware/weights/b37.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'w39': Complete partitioning on dimension 1. (firmware/weights/w39.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b39': Complete partitioning on dimension 1. (firmware/weights/b39.h:12:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEES6_7config6EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj1EEENS1_IS2_ILi37ELi17ELS3_5ELS4_3ELi0EELj8EEE7config2EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to 'data_array': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_transpose_stream.h:42:33) +INFO: [HLS 214-248] Applying array_partition to 'acc': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_dense_resource.h:110:32) +INFO: [HLS 214-248] Applying array_partition to 'res_out': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:274:29) +INFO: [HLS 214-248] Applying array_partition to 'shift_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv_stream.h:224:30) +WARNING: [HLS 214-322] Unsuported scalar variable on pragma 'Resource/Bind_Storage', ignore it. (firmware/myproject.cpp:348:5) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer40_out' with compact=bit mode in 16-bits (firmware/myproject.cpp:235:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer46_out' with compact=bit mode in 16-bits (firmware/myproject.cpp:61:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer41_out' with compact=bit mode in 16-bits (firmware/myproject.cpp:58:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer39_out' with compact=bit mode in 36-bits (firmware/myproject.cpp:232:35) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer38_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:229:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer59_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:223:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer36_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:220:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer48_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:88:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer6_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:85:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer43_cpy1' with compact=bit mode in 128-bits (firmware/myproject.cpp:79:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer43_cpy2' with compact=bit mode in 128-bits (firmware/myproject.cpp:82:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer5_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:76:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer47_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:70:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer3_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:67:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer37_out' with compact=bit mode in 320-bits (firmware/myproject.cpp:226:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer4_out' with compact=bit mode in 320-bits (firmware/myproject.cpp:73:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer35_out' with compact=bit mode in 328-bits (firmware/myproject.cpp:217:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer58_out' with compact=bit mode in 384-bits (firmware/myproject.cpp:214:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer34_out' with compact=bit mode in 384-bits (firmware/myproject.cpp:211:30) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer33_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:208:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer32_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:205:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer57_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:199:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer30_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:196:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer50_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:115:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer11_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:112:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer44_cpy1' with compact=bit mode in 256-bits (firmware/myproject.cpp:106:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer44_cpy2' with compact=bit mode in 256-bits (firmware/myproject.cpp:109:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer10_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:103:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer49_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:97:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer8_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:94:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer31_out' with compact=bit mode in 656-bits (firmware/myproject.cpp:202:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer9_out' with compact=bit mode in 656-bits (firmware/myproject.cpp:100:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer29_out' with compact=bit mode in 672-bits (firmware/myproject.cpp:193:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer56_out' with compact=bit mode in 768-bits (firmware/myproject.cpp:190:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer28_out' with compact=bit mode in 768-bits (firmware/myproject.cpp:187:30) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer27_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:184:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer26_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:181:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer55_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:175:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer24_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:172:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer52_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:142:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer16_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:139:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer45_cpy1' with compact=bit mode in 512-bits (firmware/myproject.cpp:133:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer45_cpy2' with compact=bit mode in 512-bits (firmware/myproject.cpp:136:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer15_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:130:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer51_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:124:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer13_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:121:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer25_out' with compact=bit mode in 1344-bits (firmware/myproject.cpp:178:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer14_out' with compact=bit mode in 1344-bits (firmware/myproject.cpp:127:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer23_out' with compact=bit mode in 1376-bits (firmware/myproject.cpp:169:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer54_out' with compact=bit mode in 1536-bits (firmware/myproject.cpp:166:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer22_out' with compact=bit mode in 1536-bits (firmware/myproject.cpp:163:28) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer21_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:160:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer20_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:157:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer53_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:151:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer18_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:148:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer19_out' with compact=bit mode in 2752-bits (firmware/myproject.cpp:154:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer17_out' with compact=bit mode in 2688-bits (firmware/myproject.cpp:145:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer12_out' with compact=bit mode in 1312-bits (firmware/myproject.cpp:118:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer7_out' with compact=bit mode in 640-bits (firmware/myproject.cpp:91:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer2_out' with compact=bit mode in 296-bits (firmware/myproject.cpp:64:32) +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::conv_2d_buffer_resource_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_64' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_65' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_66' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_67' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_68' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_69' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_70' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_71' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_72' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_73' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_74' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_75' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_76' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_77' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_78' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_79' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_80' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_81' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_82' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_83' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_84' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_85' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_86' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_87' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_88' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_89' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_90' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_91' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_92' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_93' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_94' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_95' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_64' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_65' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_66' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_67' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_68' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_69' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_70' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_71' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_72' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_73' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_74' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_75' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_76' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_77' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_78' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_79' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_80' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_81' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_82' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_83' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_84' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_85' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_86' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_87' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_88' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_89' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_90' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_91' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_92' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_93' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_94' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_95' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-248] Applying array_reshape to 'w4': Block reshaping with factor 2 on dimension 1. (firmware/weights/w4.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w7': Block reshaping with factor 4 on dimension 1. (firmware/weights/w7.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w9': Block reshaping with factor 8 on dimension 1. (firmware/weights/w9.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w12': Block reshaping with factor 16 on dimension 1. (firmware/weights/w12.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w14': Block reshaping with factor 32 on dimension 1. (firmware/weights/w14.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w17': Block reshaping with factor 64 on dimension 1. (firmware/weights/w17.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w19': Block reshaping with factor 128 on dimension 1. (firmware/weights/w19.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w23': Block reshaping with factor 96 on dimension 1. (firmware/weights/w23.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w25': Block reshaping with factor 32 on dimension 1. (firmware/weights/w25.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w29': Block reshaping with factor 32 on dimension 1. (firmware/weights/w29.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w31': Block reshaping with factor 8 on dimension 1. (firmware/weights/w31.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w35': Block reshaping with factor 8 on dimension 1. (firmware/weights/w35.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w37': Block reshaping with factor 2 on dimension 1. (firmware/weights/w37.h:12:0) +INFO: [HLS 214-376] automatically set the pipeline for Loop< ReadInputWidthSerial> at firmware/nnet_utils/nnet_sepconv2d_stream.h:83:13 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadTopWidth> at firmware/nnet_utils/nnet_padding_stream.h:53:9 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadMain> at firmware/nnet_utils/nnet_padding_stream.h:59:5 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadBottomWidth> at firmware/nnet_utils/nnet_padding_stream.h:77:9 +INFO: [HLS 214-291] Loop 'CopyMain' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_padding_stream.h:65:9) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-270] Inferring pragma 'array_partition type=complete dim=1' for array 'ref.tmp.i' due to pipeline pragma +INFO: [HLS 214-248] Applying array_partition to 'ref.tmp.i': Complete partitioning on dimension 1. +INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 36136.2 seconds. CPU system time: 7.28 seconds. Elapsed time: 36131.2 seconds; current allocated memory: 301.129 MB. +INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 301.129 MB. +INFO: [HLS 200-10] Starting code transformations ... +INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 165.35 seconds. CPU system time: 0.45 seconds. Elapsed time: 165.91 seconds; current allocated memory: 946.934 MB. +INFO: [HLS 200-10] Checking synthesizability ... +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 142.84 seconds. CPU system time: 0.61 seconds. Elapsed time: 143.46 seconds; current allocated memory: 1.979 GB. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-712] Applying dataflow to function 'myproject' (firmware/myproject.cpp:8), detected/extracted 58 process function(s): + 'nnet::transpose, 64u>, nnet::array, 1u>, config41>' + 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>' + 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config3>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config5>' + 'nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>' + 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config8>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config10>' + 'nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>' + 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config13>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config15>' + 'nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>' + 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>' + 'nnet::relu, 64u>, nnet::array, 64u>, relu_config18>' + 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>' + 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>' + 'nnet::relu, 64u>, nnet::array, 64u>, relu_config20>' + 'nnet::resize_nearest, 64u>, config21>' + 'nnet::concatenate3d, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' + 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>' + 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config24>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config26>' + 'nnet::resize_nearest, 32u>, config27>' + 'nnet::concatenate3d, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' + 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>' + 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config30>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config32>' + 'nnet::resize_nearest, 16u>, config33>' + 'nnet::concatenate3d, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' + 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>' + 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config36>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config38>' + 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config60>' + 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>' + 'nnet::transpose, 1u>, nnet::array, 1u>, config42>'. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_activation_stream.h:81:9) to (firmware/nnet_utils/nnet_activation_stream.h:80:5) in function 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>'... converting 3 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>'... converting 17 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>'... converting 17 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>'... converting 33 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>'... converting 37 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>'... converting 19 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>'... converting 19 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>'... converting 18 basic blocks. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' (firmware/nnet_utils/nnet_dense_resource.h:46:5)...96 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...12 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...6 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...6 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...13 expression(s) balanced. +/opt/Xilinx/Vitis_HLS/2024.1/bin/rdiArgs.sh: line 387: 3027 Segmentation fault (core dumped) "$RDI_PROG" "$@" +segfault in /opt/Xilinx/Vitis_HLS/2024.1/bin/unwrapped/lnx64.o/vitis_hls -exec vitis_hls -nolog -run tcl -f /home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl -work_dir /home/ubuntu/lithobench/hls4ml_mini_unet, exiting... +INFO: [vitis-run 60-1662] Stopping dispatch session having empty uuid. diff --git a/logs/hls_run_tcl_6671.backup.log b/logs/hls_run_tcl_6671.backup.log new file mode 100644 index 0000000000000000000000000000000000000000..d0903d75818e083f822e1365bf8a7fa047fe20b5 --- /dev/null +++ b/logs/hls_run_tcl_6671.backup.log @@ -0,0 +1,1824 @@ +INFO: [vitis-run 82-31] Launching vitis_hls: vitis_hls -nolog -run tcl -f /home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl -work_dir /home/ubuntu/lithobench/hls4ml_mini_unet + +****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2024.1 (64-bit) + **** SW Build 5069499 on May 21 2024 + **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 + **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 + **** Start of session at: Sun Mar 29 01:33:03 2026 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. + +source /opt/Xilinx/Vitis_HLS/2024.1/scripts/vitis_hls/hls.tcl -notrace +INFO: [HLS 200-10] For user 'ubuntu' on host 'ip-172-31-42-252.ec2.internal' (Linux_x86_64 version 5.15.0-1084-aws) on Sun Mar 29 01:33:05 UTC 2026 +INFO: [HLS 200-10] On os Ubuntu 20.04.6 LTS +INFO: [HLS 200-10] In directory '/home/ubuntu/lithobench/hls4ml_mini_unet' +Sourcing Tcl script '/home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl' +INFO: [HLS 200-1510] Running: open_project myproject_prj +INFO: [HLS 200-10] Opening project '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj'. +INFO: [HLS 200-1510] Running: set_top myproject +INFO: [HLS 200-1510] Running: add_files firmware/myproject.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding design file 'firmware/myproject.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb myproject_test.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding test bench file 'myproject_test.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb firmware/weights +INFO: [HLS 200-10] Adding test bench file 'firmware/weights' to the project +INFO: [HLS 200-1510] Running: add_files -tb tb_data +INFO: [HLS 200-10] Adding test bench file 'tb_data' to the project +INFO: [HLS 200-1510] Running: open_solution solution1 +INFO: [HLS 200-10] Opening solution '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1'. +INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. +INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 1.35ns. +INFO: [HLS 200-1611] Setting target device to 'xcvu47p-fsvh2892-2L-e' +INFO: [HLS 200-1505] Using flow_target 'vivado' +Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1505.html +INFO: [HLS 200-1464] Running solution command: config_compile -name_max_length=80 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_schedule -enable_dsp_full_reg=0 +INFO: [HLS 200-1510] Running: config_array_partition -maximum_size 4096 +ERROR: [HLS 200-101] config_array_partition: Unknown option '-maximum_size'. +ERROR: [HLS 200-101] config_array_partition: Unknown option '4096'. +SYNTAX + config_array_partition [OPTIONS] + -auto_partition_threshold *** DEPRECATED*** + -auto_promotion_threshold *** DEPRECATED*** + -complete_threshold + -throughput_driven + +SEE ALSO + INI: syn.array_partition.complete_threshold syn.array_partition.throughput_driven + docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1399-vitis-hls&resourceid=vyw1583260160301.html + +INFO: [HLS 200-1510] Running: config_compile -name_max_length 80 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: set_part xcvu47p-fsvh2892-2L-e +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: config_schedule -enable_dsp_full_reg=false +INFO: [HLS 200-1510] Running: create_clock -period 5 -name default +INFO: [HLS 200-1510] Running: set_clock_uncertainty 27% default +***** C/RTL SYNTHESIS ***** +INFO: [HLS 200-1510] Running: csynth_design +INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 264.785 MB. +INFO: [HLS 200-10] Analyzing design file 'firmware/myproject.cpp' ... +WARNING: [HLS 207-5570] unexpected pragma argument 'softmax', expects function/operation (firmware/nnet_utils/nnet_activation.h:402:36) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:33:9) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:107:9) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:189:9) +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:242:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:242:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:248:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:248:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:258:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:258:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:264:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:264:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:274:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:274:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:280:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:280:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:290:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:290:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:296:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:296:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:306:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:306:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:312:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:312:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:322:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:322:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:328:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:328:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:338:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:338:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:344:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:344:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:348:100) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:348:105) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 200-471] Dataflow form checks found 30 issue(s) in file firmware/myproject.cpp +Resolution: For help on HLS 200-471 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-471.html +WARNING: [HLS 207-5292] unused parameter 'keep' (firmware/nnet_utils/nnet_helpers.h:285:99) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:14:36) +WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:15:36) +WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:16:44) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:24:24) +WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:25:24) +WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:26:32) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:33:30) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:33:58) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:34:51) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:35:49) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:42:30) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:42:58) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:43:51) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:44:49) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:51:29) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:51:80) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:52:50) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:53:48) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_code_gen.h:16:39) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_code_gen.h:17:38) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_code_gen.h:18:60) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_code_gen.h:19:58) +WARNING: [HLS 207-5584] there are more than one pragma inline in the function scope, ignore the pragma (/opt/Xilinx/Vitis_HLS/2024.1/common/technology/autopilot/ap_shift_reg.h:47:9) +INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 36.75 seconds. CPU system time: 2.25 seconds. Elapsed time: 39.05 seconds; current allocated memory: 275.797 MB. +INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target. +INFO: [HLS 200-1995] There were 28,528 instructions in the design after the 'Compile/Link' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 188,474 instructions in the design after the 'Unroll/Inline (step 1)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 96,416 instructions in the design after the 'Unroll/Inline (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 82,279 instructions in the design after the 'Unroll/Inline (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 37,407 instructions in the design after the 'Unroll/Inline (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 65,234 instructions in the design after the 'Array/Struct' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 44,307 instructions in the design after the 'Array/Struct (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 45,206 instructions in the design after the 'Array/Struct (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 93,112 instructions in the design after the 'Array/Struct (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 93,567 instructions in the design after the 'Array/Struct (step 5)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 95,263 instructions in the design after the 'Performance' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 202,374 instructions in the design after the 'Performance (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 199,687 instructions in the design after the 'Performance (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 199,687 instructions in the design after the 'Performance (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 160,662 instructions in the design after the 'HW Transforms' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 152,727 instructions in the design after the 'HW Transforms (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config60>' (firmware/nnet_utils/nnet_sepconv_stream.h:103:9) +WARNING: [HLS 214-273] In function 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config60_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config60_mult::weight_t*, config60_mult::bias_t*)', Pragma conflict happens on 'INLINE' and 'FUNCTION_INSTANTIATE' pragmas: same function (firmware/nnet_utils/nnet_dense_resource.h:89:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config46>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config46>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config46>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config46>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 1u>, config2>(nnet::array, 1u>::value_type (*) [config2::n_chan], nnet::array, 1u>::value_type*)' into 'void nnet::shift_line_buffer, 1u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], nnet::array, 1u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, config2_mult::weight_t*, config2_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*) (.55)' into 'void nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config47>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config47>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config47>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config47>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config4>(nnet::array, 8u>::value_type (*) [config4::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config4_mult::weight_t*, config4_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 8u>, config4>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*) (.54)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config6>(nnet::array, 8u>::value_type (*) [config6::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::Op_max >::operator()(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>) (.36)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' (firmware/nnet_utils/nnet_common.h:44:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:15) +INFO: [HLS 214-131] Inlining function 'nnet::Op_max >::operator()(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>) (.36)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:12) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:44) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config6>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.52)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config6>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.52)' into 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 8u>::operator[](unsigned long) (.51)' into 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' into 'void nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config48>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config48>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config48>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config48>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config7>(nnet::array, 8u>::value_type (*) [config7::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config7_mult::weight_t*, config7_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 16u>, config7>(hls::stream, 8u>, 0>&, hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*) (.48)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>(hls::stream, 8u>, 0>&, hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config49>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config49>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config49>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config49>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config9>(nnet::array, 16u>::value_type (*) [config9::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config9_mult::weight_t*, config9_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 16u>, config9>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*) (.47)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config11>(nnet::array, 16u>::value_type (*) [config11::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config11>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.45)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config11>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.45)' into 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 16u>::operator[](unsigned long) (.44)' into 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' into 'void nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config50>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config50>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config50>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config50>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config12>(nnet::array, 16u>::value_type (*) [config12::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config12_mult::weight_t*, config12_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 32u>, config12>(hls::stream, 16u>, 0>&, hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*) (.41)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>(hls::stream, 16u>, 0>&, hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config51>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config51>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config51>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config51>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config14>(nnet::array, 32u>::value_type (*) [config14::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config14_mult::weight_t*, config14_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 32u>, config14>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*) (.40)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config16>(nnet::array, 32u>::value_type (*) [config16::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config16>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.34)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config16>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.34)' into 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 32u>::operator[](unsigned long) (.33)' into 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' into 'void nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config52>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config52>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config52>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config52>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config17>(nnet::array, 32u>::value_type (*) [config17::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config17_mult::weight_t*, config17_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 64u>, config17>(hls::stream, 32u>, 0>&, hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*) (.30)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>(hls::stream, 32u>, 0>&, hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config53>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config53>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config53>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config53>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 64u>, config19>(nnet::array, 64u>::value_type (*) [config19::n_chan], nnet::array, 64u>::value_type*)' into 'void nnet::shift_line_buffer, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], nnet::array, 64u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config19_mult::weight_t*, config19_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 64u>, nnet::array, 64u>, config19>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*) (.26)' into 'void nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config54>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config54>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config54>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config54>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 96u>, config23>(nnet::array, 96u>::value_type (*) [config23::n_chan], nnet::array, 96u>::value_type*)' into 'void nnet::shift_line_buffer, 96u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], nnet::array, 96u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config23_mult::weight_t*, config23_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 96u>, nnet::array, 32u>, config23>(hls::stream, 96u>, 0>&, hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*) (.23)' into 'void nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>(hls::stream, 96u>, 0>&, hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config55>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config55>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config55>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config55>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config25>(nnet::array, 32u>::value_type (*) [config25::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config25_mult::weight_t*, config25_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 32u>, config25>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*) (.19)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config56>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config56>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config56>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config56>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 48u>, config29>(nnet::array, 48u>::value_type (*) [config29::n_chan], nnet::array, 48u>::value_type*)' into 'void nnet::shift_line_buffer, 48u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], nnet::array, 48u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config29_mult::weight_t*, config29_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 48u>, nnet::array, 16u>, config29>(hls::stream, 48u>, 0>&, hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*) (.16)' into 'void nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>(hls::stream, 48u>, 0>&, hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config57>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config57>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config57>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config57>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config31>(nnet::array, 16u>::value_type (*) [config31::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config31_mult::weight_t*, config31_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 16u>, config31>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*) (.12)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config58>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config58>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config58>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config58>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 24u>, config35>(nnet::array, 24u>::value_type (*) [config35::n_chan], nnet::array, 24u>::value_type*)' into 'void nnet::shift_line_buffer, 24u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], nnet::array, 24u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config35_mult::weight_t*, config35_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 24u>, nnet::array, 8u>, config35>(hls::stream, 24u>, 0>&, hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*) (.9)' into 'void nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>(hls::stream, 24u>, 0>&, hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config59>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config59>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config59>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config59>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config37>(nnet::array, 8u>::value_type (*) [config37::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config37_mult::weight_t*, config37_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 8u>, config37>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*) (.5)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config60_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config60_mult::weight_t*, config60_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const (.4)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config60>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config60::weight_t*, config60::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:100:13) +INFO: [HLS 214-131] Inlining function 'nnet::array, 1u>::operator[](unsigned long) (.2)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config60>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config60::weight_t*, config60::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:110:2) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config60_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.3)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config60>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config60::weight_t*, config60::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:104:2) +INFO: [HLS 214-131] Inlining function 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config60>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config60::weight_t*, config60::bias_t*)' into 'void nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config60>(hls::stream, 8u>, 0>&, hls::stream, 1u>, 0>&, config60::weight_t*, config60::bias_t*)' (firmware/nnet_utils/nnet_sepconv2d_stream.h:86:21) +INFO: [HLS 214-291] Loop 'VITIS_LOOP_58_4' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_transpose_stream.h:58:26) +INFO: [HLS 214-291] Loop 'VITIS_LOOP_48_2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_transpose_stream.h:48:26) +INFO: [HLS 214-291] Loop 'VITIS_LOOP_21_1' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_transpose.h:21:22) +INFO: [HLS 214-291] Loop 'SigmoidPackLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_activation_stream.h:88:9) +INFO: [HLS 214-291] Loop 'ReLUPackLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_activation_stream.h:49:9) +INFO: [HLS 214-291] Loop 'MultLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_dense_resource.h:142:9) +INFO: [HLS 214-291] Loop 'KernelPushHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:205:5) +INFO: [HLS 214-291] Loop 'KernelPushChannel' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:208:9) +INFO: [HLS 214-291] Loop 'KernelShiftWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:189:5) +INFO: [HLS 214-291] Loop 'KernelShiftHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:192:9) +INFO: [HLS 214-291] Loop 'KernelShiftChannel' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:194:13) +INFO: [HLS 214-291] Loop 'LineBufferDataIn' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:236:5) +INFO: [HLS 214-291] Loop 'LineBufferShift' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:239:9) +INFO: [HLS 214-291] Loop 'UpdateBuffer' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:228:5) +INFO: [HLS 214-291] Loop 'MultLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_dense_resource.h:55:9) +INFO: [HLS 214-291] Loop 'ConcatPackInput1' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_merge_stream.h:245:13) +INFO: [HLS 214-291] Loop 'ConcatPackInput2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_merge_stream.h:251:13) +INFO: [HLS 214-291] Loop 'ImageWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:22:9) +INFO: [HLS 214-291] Loop 'ImageChan' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:28:13) +INFO: [HLS 214-291] Loop 'ResizeHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:36:9) +INFO: [HLS 214-291] Loop 'ImageWidth2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:40:13) +INFO: [HLS 214-291] Loop 'ResizeWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:44:17) +INFO: [HLS 214-291] Loop 'ResizeChan' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:51:21) +INFO: [HLS 214-291] Loop 'FiltLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_pooling_stream.h:57:9) +INFO: [HLS 214-291] Loop 'PoolLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_pooling_stream.h:62:13) +INFO: [HLS 214-291] Loop 'ClonePack' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_stream.h:32:9) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_58_4' (firmware/nnet_utils/nnet_transpose_stream.h:58:26) in function 'nnet::transpose, 1u>, nnet::array, 1u>, config42>' completely with a factor of 1 (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_48_2' (firmware/nnet_utils/nnet_transpose_stream.h:48:26) in function 'nnet::transpose, 1u>, nnet::array, 1u>, config42>' completely with a factor of 1 (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_21_1' (firmware/nnet_utils/nnet_transpose.h:21:22) in function 'nnet::transfer_idx' completely with a factor of 3 (firmware/nnet_utils/nnet_transpose.h:18:0) +INFO: [HLS 214-186] Unrolling loop 'SigmoidPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:88:9) in function 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>' completely with a factor of 1 (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-186] Unrolling loop 'InitData' (firmware/nnet_utils/nnet_sepconv_stream.h:98:5) in function 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config60>' completely with a factor of 8 (firmware/nnet_utils/nnet_sepconv2d_stream.h:58:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config38>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 2 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config37>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config36>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 24u>, config35>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>' completely with a factor of 24 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' completely with a factor of 16 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' completely with a factor of 8 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config32>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config31>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config30>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 48u>, config29>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>' completely with a factor of 48 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' completely with a factor of 32 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' completely with a factor of 16 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config26>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config25>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config24>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 96 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 96u>, config23>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>' completely with a factor of 96 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' completely with a factor of 64 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' completely with a factor of 32 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 8 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 64 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 8 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 64 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 64u>, nnet::array, 64u>, relu_config20>' completely with a factor of 64 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 128 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 64u>, config19>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 64u>, nnet::array, 64u>, relu_config18>' completely with a factor of 64 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config17>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config16>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>' completely with a factor of 32 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config15>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config14>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config13>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config12>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config11>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>' completely with a factor of 16 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config10>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config9>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config8>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 4 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config7>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config6>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>' completely with a factor of 8 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config5>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 2 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config4>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config3>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 1u>, config2>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>' completely with a factor of 1 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_58_4' (firmware/nnet_utils/nnet_transpose_stream.h:58:26) in function 'nnet::transpose, 64u>, nnet::array, 1u>, config41>' completely with a factor of 1 (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_48_2' (firmware/nnet_utils/nnet_transpose_stream.h:48:26) in function 'nnet::transpose, 64u>, nnet::array, 1u>, config41>' completely with a factor of 64 (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_21_1' (firmware/nnet_utils/nnet_transpose.h:21:22) in function 'nnet::transfer_idx' completely with a factor of 4 (firmware/nnet_utils/nnet_transpose.h:18:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'std::enable_if<(config41::dims) != (2), void>::type nnet::transpose, 64u>, nnet::array, 1u>, config41>(hls::stream, 64u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'std::enable_if<(config41::dims) != (2), void>::type nnet::transpose, 64u>, nnet::array, 1u>, config41>(hls::stream, 64u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-178] Inlining function 'unsigned int nnet::transfer_idx(int)' into 'std::enable_if<(config41::dims) != (2), void>::type nnet::transpose, 64u>, nnet::array, 1u>, config41>(hls::stream, 64u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 1u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], nnet::array, 1u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(config2_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, config2_mult::weight_t*, config2_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config3>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config3>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(config4_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config4_mult::weight_t*, config4_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config5>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config5>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(config7_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config7_mult::weight_t*, config7_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config8>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config8>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(config9_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config9_mult::weight_t*, config9_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config10>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config10>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(config12_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config12_mult::weight_t*, config12_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config13>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config13>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(config14_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config14_mult::weight_t*, config14_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config15>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config15>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config18>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config18>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], nnet::array, 64u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config20>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config20>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 64u>, config21>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 96u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], nnet::array, 96u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(config23_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config23_mult::weight_t*, config23_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config24>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config24>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(config25_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config25_mult::weight_t*, config25_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config26>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config26>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 32u>, config27>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 48u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], nnet::array, 48u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(config29_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config29_mult::weight_t*, config29_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config30>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config30>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(config31_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config31_mult::weight_t*, config31_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config32>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config32>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 16u>, config33>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 24u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], nnet::array, 24u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(config35_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config35_mult::weight_t*, config35_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config36>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config36>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(config37_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config37_mult::weight_t*, config37_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config38>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config38>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'std::enable_if<(config42::dims) != (2), void>::type nnet::transpose, 1u>, nnet::array, 1u>, config42>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-178] Inlining function 'unsigned int nnet::transfer_idx(int)' into 'std::enable_if<(config42::dims) != (2), void>::type nnet::transpose, 1u>, nnet::array, 1u>, config42>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj1EEENS1_IS2_ILi37ELi17ELS3_5ELS4_3ELi0EELj8EEE7config2EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEES6_7config6EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to 'b2': Complete partitioning on dimension 1. (firmware/weights/b2.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b4': Complete partitioning on dimension 1. (firmware/weights/b4.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b7': Complete partitioning on dimension 1. (firmware/weights/b7.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b9': Complete partitioning on dimension 1. (firmware/weights/b9.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b12': Complete partitioning on dimension 1. (firmware/weights/b12.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b14': Complete partitioning on dimension 1. (firmware/weights/b14.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b17': Complete partitioning on dimension 1. (firmware/weights/b17.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b19': Complete partitioning on dimension 1. (firmware/weights/b19.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b23': Complete partitioning on dimension 1. (firmware/weights/b23.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b25': Complete partitioning on dimension 1. (firmware/weights/b25.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b29': Complete partitioning on dimension 1. (firmware/weights/b29.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b31': Complete partitioning on dimension 1. (firmware/weights/b31.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b35': Complete partitioning on dimension 1. (firmware/weights/b35.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b37': Complete partitioning on dimension 1. (firmware/weights/b37.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'w39': Complete partitioning on dimension 1. (firmware/weights/w39.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b39': Complete partitioning on dimension 1. (firmware/weights/b39.h:12:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEES6_7config6EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj1EEENS1_IS2_ILi37ELi17ELS3_5ELS4_3ELi0EELj8EEE7config2EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to 'data_array': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_transpose_stream.h:42:33) +INFO: [HLS 214-248] Applying array_partition to 'acc': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_dense_resource.h:110:32) +INFO: [HLS 214-248] Applying array_partition to 'res_out': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:274:29) +INFO: [HLS 214-248] Applying array_partition to 'shift_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv_stream.h:224:30) +WARNING: [HLS 214-322] Unsuported scalar variable on pragma 'Resource/Bind_Storage', ignore it. (firmware/myproject.cpp:348:5) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer40_out' with compact=bit mode in 16-bits (firmware/myproject.cpp:235:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer46_out' with compact=bit mode in 16-bits (firmware/myproject.cpp:61:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer41_out' with compact=bit mode in 16-bits (firmware/myproject.cpp:58:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer39_out' with compact=bit mode in 36-bits (firmware/myproject.cpp:232:35) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer38_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:229:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer59_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:223:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer36_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:220:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer48_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:88:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer6_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:85:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer43_cpy1' with compact=bit mode in 128-bits (firmware/myproject.cpp:79:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer43_cpy2' with compact=bit mode in 128-bits (firmware/myproject.cpp:82:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer5_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:76:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer47_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:70:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer3_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:67:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer37_out' with compact=bit mode in 320-bits (firmware/myproject.cpp:226:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer4_out' with compact=bit mode in 320-bits (firmware/myproject.cpp:73:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer35_out' with compact=bit mode in 328-bits (firmware/myproject.cpp:217:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer58_out' with compact=bit mode in 384-bits (firmware/myproject.cpp:214:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer34_out' with compact=bit mode in 384-bits (firmware/myproject.cpp:211:30) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer33_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:208:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer32_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:205:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer57_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:199:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer30_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:196:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer50_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:115:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer11_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:112:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer44_cpy1' with compact=bit mode in 256-bits (firmware/myproject.cpp:106:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer44_cpy2' with compact=bit mode in 256-bits (firmware/myproject.cpp:109:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer10_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:103:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer49_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:97:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer8_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:94:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer31_out' with compact=bit mode in 656-bits (firmware/myproject.cpp:202:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer9_out' with compact=bit mode in 656-bits (firmware/myproject.cpp:100:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer29_out' with compact=bit mode in 672-bits (firmware/myproject.cpp:193:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer56_out' with compact=bit mode in 768-bits (firmware/myproject.cpp:190:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer28_out' with compact=bit mode in 768-bits (firmware/myproject.cpp:187:30) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer27_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:184:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer26_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:181:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer55_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:175:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer24_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:172:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer52_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:142:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer16_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:139:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer45_cpy1' with compact=bit mode in 512-bits (firmware/myproject.cpp:133:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer45_cpy2' with compact=bit mode in 512-bits (firmware/myproject.cpp:136:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer15_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:130:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer51_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:124:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer13_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:121:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer25_out' with compact=bit mode in 1344-bits (firmware/myproject.cpp:178:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer14_out' with compact=bit mode in 1344-bits (firmware/myproject.cpp:127:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer23_out' with compact=bit mode in 1376-bits (firmware/myproject.cpp:169:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer54_out' with compact=bit mode in 1536-bits (firmware/myproject.cpp:166:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer22_out' with compact=bit mode in 1536-bits (firmware/myproject.cpp:163:28) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer21_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:160:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer20_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:157:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer53_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:151:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer18_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:148:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer19_out' with compact=bit mode in 2752-bits (firmware/myproject.cpp:154:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer17_out' with compact=bit mode in 2688-bits (firmware/myproject.cpp:145:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer12_out' with compact=bit mode in 1312-bits (firmware/myproject.cpp:118:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer7_out' with compact=bit mode in 640-bits (firmware/myproject.cpp:91:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer2_out' with compact=bit mode in 296-bits (firmware/myproject.cpp:64:32) +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::conv_2d_buffer_resource_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_64' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_65' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_66' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_67' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_68' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_69' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_70' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_71' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_72' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_73' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_74' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_75' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_76' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_77' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_78' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_79' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_80' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_81' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_82' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_83' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_84' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_85' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_86' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_87' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_88' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_89' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_90' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_91' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_92' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_93' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_94' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_95' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_64' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_65' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_66' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_67' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_68' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_69' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_70' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_71' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_72' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_73' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_74' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_75' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_76' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_77' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_78' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_79' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_80' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_81' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_82' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_83' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_84' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_85' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_86' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_87' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_88' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_89' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_90' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_91' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_92' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_93' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_94' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_95' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-248] Applying array_reshape to 'w4': Block reshaping with factor 2 on dimension 1. (firmware/weights/w4.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w7': Block reshaping with factor 4 on dimension 1. (firmware/weights/w7.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w9': Block reshaping with factor 8 on dimension 1. (firmware/weights/w9.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w12': Block reshaping with factor 16 on dimension 1. (firmware/weights/w12.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w14': Block reshaping with factor 32 on dimension 1. (firmware/weights/w14.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w17': Block reshaping with factor 64 on dimension 1. (firmware/weights/w17.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w19': Block reshaping with factor 128 on dimension 1. (firmware/weights/w19.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w23': Block reshaping with factor 96 on dimension 1. (firmware/weights/w23.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w25': Block reshaping with factor 32 on dimension 1. (firmware/weights/w25.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w29': Block reshaping with factor 32 on dimension 1. (firmware/weights/w29.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w31': Block reshaping with factor 8 on dimension 1. (firmware/weights/w31.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w35': Block reshaping with factor 8 on dimension 1. (firmware/weights/w35.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w37': Block reshaping with factor 2 on dimension 1. (firmware/weights/w37.h:12:0) +INFO: [HLS 214-376] automatically set the pipeline for Loop< ReadInputWidthSerial> at firmware/nnet_utils/nnet_sepconv2d_stream.h:83:13 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadTopWidth> at firmware/nnet_utils/nnet_padding_stream.h:53:9 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadMain> at firmware/nnet_utils/nnet_padding_stream.h:59:5 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadBottomWidth> at firmware/nnet_utils/nnet_padding_stream.h:77:9 +INFO: [HLS 214-291] Loop 'CopyMain' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_padding_stream.h:65:9) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-270] Inferring pragma 'array_partition type=complete dim=1' for array 'ref.tmp.i' due to pipeline pragma +INFO: [HLS 214-248] Applying array_partition to 'ref.tmp.i': Complete partitioning on dimension 1. +INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 36313.3 seconds. CPU system time: 7.3 seconds. Elapsed time: 36306.1 seconds; current allocated memory: 334.344 MB. +INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 334.344 MB. +INFO: [HLS 200-10] Starting code transformations ... +INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 165.5 seconds. CPU system time: 0.52 seconds. Elapsed time: 166.13 seconds; current allocated memory: 980.168 MB. +INFO: [HLS 200-10] Checking synthesizability ... +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 142.54 seconds. CPU system time: 0.65 seconds. Elapsed time: 143.39 seconds; current allocated memory: 2.028 GB. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-712] Applying dataflow to function 'myproject' (firmware/myproject.cpp:8), detected/extracted 58 process function(s): + 'nnet::transpose, 64u>, nnet::array, 1u>, config41>' + 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>' + 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config3>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config5>' + 'nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>' + 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config8>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config10>' + 'nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>' + 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config13>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config15>' + 'nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>' + 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>' + 'nnet::relu, 64u>, nnet::array, 64u>, relu_config18>' + 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>' + 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>' + 'nnet::relu, 64u>, nnet::array, 64u>, relu_config20>' + 'nnet::resize_nearest, 64u>, config21>' + 'nnet::concatenate3d, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' + 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>' + 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config24>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config26>' + 'nnet::resize_nearest, 32u>, config27>' + 'nnet::concatenate3d, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' + 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>' + 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config30>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config32>' + 'nnet::resize_nearest, 16u>, config33>' + 'nnet::concatenate3d, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' + 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>' + 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config36>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config38>' + 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config60>' + 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>' + 'nnet::transpose, 1u>, nnet::array, 1u>, config42>'. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_activation_stream.h:81:9) to (firmware/nnet_utils/nnet_activation_stream.h:80:5) in function 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>'... converting 3 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>'... converting 17 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>'... converting 17 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>'... converting 33 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>'... converting 37 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>'... converting 19 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>'... converting 19 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>'... converting 18 basic blocks. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' (firmware/nnet_utils/nnet_dense_resource.h:46:5)...96 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...12 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...6 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...6 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...13 expression(s) balanced. +/opt/Xilinx/Vitis_HLS/2024.1/bin/rdiArgs.sh: line 387: 4714 Segmentation fault (core dumped) "$RDI_PROG" "$@" +segfault in /opt/Xilinx/Vitis_HLS/2024.1/bin/unwrapped/lnx64.o/vitis_hls -exec vitis_hls -nolog -run tcl -f /home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl -work_dir /home/ubuntu/lithobench/hls4ml_mini_unet, exiting... +INFO: [vitis-run 60-1662] Stopping dispatch session having empty uuid. diff --git a/logs/hls_run_tcl_7008.backup.log b/logs/hls_run_tcl_7008.backup.log new file mode 100644 index 0000000000000000000000000000000000000000..077bfa965ffcaa65b667042f080096194bbcbb38 --- /dev/null +++ b/logs/hls_run_tcl_7008.backup.log @@ -0,0 +1,10379 @@ +INFO: [vitis-run 82-31] Launching vitis_hls: vitis_hls -nolog -run tcl -f /home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl -work_dir /home/ubuntu/lithobench/hls4ml_mini_unet + +****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2024.1 (64-bit) + **** SW Build 5069499 on May 21 2024 + **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 + **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 + **** Start of session at: Mon Mar 30 15:40:13 2026 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. + +source /opt/Xilinx/Vitis_HLS/2024.1/scripts/vitis_hls/hls.tcl -notrace +INFO: [HLS 200-10] For user 'ubuntu' on host 'ip-172-31-42-252.ec2.internal' (Linux_x86_64 version 5.15.0-1084-aws) on Mon Mar 30 15:40:15 UTC 2026 +INFO: [HLS 200-10] On os Ubuntu 20.04.6 LTS +INFO: [HLS 200-10] In directory '/home/ubuntu/lithobench/hls4ml_mini_unet' +Sourcing Tcl script '/home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl' +INFO: [HLS 200-1510] Running: open_project myproject_prj +INFO: [HLS 200-10] Opening project '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj'. +INFO: [HLS 200-1510] Running: set_top myproject +INFO: [HLS 200-1510] Running: add_files firmware/myproject.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding design file 'firmware/myproject.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb myproject_test.cpp -cflags -std=c++0x +INFO: [HLS 200-10] Adding test bench file 'myproject_test.cpp' to the project +INFO: [HLS 200-1510] Running: add_files -tb firmware/weights +INFO: [HLS 200-10] Adding test bench file 'firmware/weights' to the project +INFO: [HLS 200-1510] Running: add_files -tb tb_data +INFO: [HLS 200-10] Adding test bench file 'tb_data' to the project +INFO: [HLS 200-1510] Running: open_solution solution1 +INFO: [HLS 200-10] Opening solution '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1'. +INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. +INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 1.35ns. +INFO: [HLS 200-1611] Setting target device to 'xcvu47p-fsvh2892-2L-e' +INFO: [HLS 200-1505] Using flow_target 'vivado' +Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1505.html +INFO: [HLS 200-1464] Running solution command: config_compile -name_max_length=80 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_compile -complex-mul-dsp=0 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_compile -unsafe_math_optimizations=0 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1464] Running solution command: config_schedule -enable_dsp_full_reg=0 +INFO: [HLS 200-1464] Running solution command: config_array_partition -complete_threshold=4096 +INFO: [XFORM 203-102] Size-based automatic array partition enabled: cut-off elements per dimension is 4096. +INFO: [HLS 200-1510] Running: config_array_partition -maximum_size 4096 +ERROR: [HLS 200-101] config_array_partition: Unknown option '-maximum_size'. +ERROR: [HLS 200-101] config_array_partition: Unknown option '4096'. +SYNTAX + config_array_partition [OPTIONS] + -auto_partition_threshold *** DEPRECATED*** + -auto_promotion_threshold *** DEPRECATED*** + -complete_threshold + -throughput_driven + +SEE ALSO + INI: syn.array_partition.complete_threshold syn.array_partition.throughput_driven + docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1399-vitis-hls&resourceid=vyw1583260160301.html + +INFO: [HLS 200-1510] Running: config_compile -name_max_length 80 +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: set_part xcvu47p-fsvh2892-2L-e +INFO: [XFORM 203-1161] The maximum of name length is set to 80. +INFO: [HLS 200-1510] Running: config_schedule -enable_dsp_full_reg=false +INFO: [HLS 200-1510] Running: create_clock -period 5 -name default +INFO: [HLS 200-1510] Running: set_clock_uncertainty 27% default +***** C/RTL SYNTHESIS ***** +INFO: [HLS 200-1510] Running: csynth_design +INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0.06 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.08 seconds; current allocated memory: 276.859 MB. +INFO: [HLS 200-10] Analyzing design file 'firmware/myproject.cpp' ... +WARNING: [HLS 207-5570] unexpected pragma argument 'softmax', expects function/operation (firmware/nnet_utils/nnet_activation.h:402:36) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:33:9) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:107:9) +WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:189:9) +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:242:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:242:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:248:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:248:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:258:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:258:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:264:85) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:264:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:274:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:274:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:280:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:280:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:290:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:290:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:296:87) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:296:92) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:306:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:306:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:312:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:312:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:322:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:322:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:328:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:328:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:338:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:338:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:344:89) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:344:94) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:348:100) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:348:105) +Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html +WARNING: [HLS 200-471] Dataflow form checks found 30 issue(s) in file firmware/myproject.cpp +Resolution: For help on HLS 200-471 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-471.html +WARNING: [HLS 207-5292] unused parameter 'keep' (firmware/nnet_utils/nnet_helpers.h:285:99) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:14:36) +WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:15:36) +WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:16:44) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:24:24) +WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:25:24) +WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:26:32) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:33:30) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:33:58) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:34:51) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:35:49) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:42:30) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:42:58) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:43:51) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:44:49) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:51:29) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:51:80) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:52:50) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:53:48) +WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_code_gen.h:16:39) +WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_code_gen.h:17:38) +WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_code_gen.h:18:60) +WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_code_gen.h:19:58) +WARNING: [HLS 207-5584] there are more than one pragma inline in the function scope, ignore the pragma (/opt/Xilinx/Vitis_HLS/2024.1/common/technology/autopilot/ap_shift_reg.h:47:9) +INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 37.05 seconds. CPU system time: 2.07 seconds. Elapsed time: 39.17 seconds; current allocated memory: 287.895 MB. +INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target. +INFO: [HLS 200-1995] There were 28,390 instructions in the design after the 'Compile/Link' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 282,347 instructions in the design after the 'Unroll/Inline' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 127,448 instructions in the design after the 'Unroll/Inline (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 102,013 instructions in the design after the 'Unroll/Inline (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 53,117 instructions in the design after the 'Unroll/Inline (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 69,335 instructions in the design after the 'Array/Struct' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 50,968 instructions in the design after the 'Array/Struct (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 51,867 instructions in the design after the 'Array/Struct (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 106,651 instructions in the design after the 'Array/Struct (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 97,860 instructions in the design after the 'Array/Struct (step 5)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 200-1995] There were 99,568 instructions in the design after the 'Performance' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 206,679 instructions in the design after the 'Performance (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 203,992 instructions in the design after the 'Performance (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 203,992 instructions in the design after the 'Performance (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 164,967 instructions in the design after the 'HW Transforms' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +WARNING: [HLS 200-1995] There were 157,003 instructions in the design after the 'HW Transforms (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' (firmware/nnet_utils/nnet_pooling_stream.h:100:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>' (firmware/nnet_utils/nnet_conv2d_stream.h:74:9) +INFO: [HLS 214-415] Performing recursive inline in function 'nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config60>' (firmware/nnet_utils/nnet_sepconv_stream.h:103:9) +WARNING: [HLS 214-273] In function 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config60_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config60_mult::weight_t*, config60_mult::bias_t*)', Pragma conflict happens on 'INLINE' and 'FUNCTION_INSTANTIATE' pragmas: same function (firmware/nnet_utils/nnet_dense_resource.h:89:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-273] In function 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)', Pragma conflict happens on 'INLINE' and 'PIPELINE' pragmas: same function (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config46>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config46>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config46>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 1u>, config46>(hls::stream, 1u>, 0>&)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 1u>, config2>(nnet::array, 1u>::value_type (*) [config2::n_chan], nnet::array, 1u>::value_type*)' into 'void nnet::shift_line_buffer, 1u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], nnet::array, 1u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, config2_mult::weight_t*, config2_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*) (.55)' into 'void nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config47>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config47>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config47>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config47>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config4>(nnet::array, 8u>::value_type (*) [config4::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config4_mult::weight_t*, config4_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 8u>, config4>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*) (.54)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config6>(nnet::array, 8u>::value_type (*) [config6::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::Op_max >::operator()(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>) (.36)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' (firmware/nnet_utils/nnet_common.h:44:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:15) +INFO: [HLS 214-131] Inlining function 'nnet::Op_max >::operator()(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>) (.36)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:12) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 2, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.38)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' (firmware/nnet_utils/nnet_common.h:46:44) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config6>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.52)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config6>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.52)' into 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 8u>::operator[](unsigned long) (.51)' into 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 8u>, nnet::array, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_filt], hls::stream, 8u>, 0>&) (.49)' into 'void nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config48>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config48>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config48>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config48>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config7>(nnet::array, 8u>::value_type (*) [config7::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config7_mult::weight_t*, config7_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 16u>, config7>(hls::stream, 8u>, 0>&, hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*) (.48)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>(hls::stream, 8u>, 0>&, hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config49>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config49>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config49>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config49>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config9>(nnet::array, 16u>::value_type (*) [config9::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config9_mult::weight_t*, config9_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 16u>, config9>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*) (.47)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config11>(nnet::array, 16u>::value_type (*) [config11::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config11>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.45)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config11>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.45)' into 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 16u>::operator[](unsigned long) (.44)' into 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 16u>, nnet::array, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_filt], hls::stream, 16u>, 0>&) (.42)' into 'void nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config50>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config50>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config50>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config50>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config12>(nnet::array, 16u>::value_type (*) [config12::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config12_mult::weight_t*, config12_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 32u>, config12>(hls::stream, 16u>, 0>&, hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*) (.41)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>(hls::stream, 16u>, 0>&, hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config51>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config51>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config51>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config51>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config14>(nnet::array, 32u>::value_type (*) [config14::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config14_mult::weight_t*, config14_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 32u>, config14>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*) (.40)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config16>(nnet::array, 32u>::value_type (*) [config16::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce, 4, nnet::Op_max > >(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> const*, nnet::Op_max >) (.35)' into 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config16>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.34)' (firmware/nnet_utils/nnet_pooling_stream.h:21:16) +INFO: [HLS 214-131] Inlining function 'ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> nnet::reduce_pool, 4, config16>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.34)' into 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' (firmware/nnet_utils/nnet_pooling_stream.h:68:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 32u>::operator[](unsigned long) (.33)' into 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' (firmware/nnet_utils/nnet_pooling_stream.h:67:13) +INFO: [HLS 214-131] Inlining function 'void nnet::compute_pool_buffer_2d, 32u>, nnet::array, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_filt], hls::stream, 32u>, 0>&) (.31)' into 'void nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_pooling_stream.h:115:2) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config52>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config52>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config52>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config52>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config17>(nnet::array, 32u>::value_type (*) [config17::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config17_mult::weight_t*, config17_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 64u>, config17>(hls::stream, 32u>, 0>&, hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*) (.30)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>(hls::stream, 32u>, 0>&, hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config53>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config53>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config53>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 64u>, config53>(hls::stream, 64u>, 0>&)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 64u>, config19>(nnet::array, 64u>::value_type (*) [config19::n_chan], nnet::array, 64u>::value_type*)' into 'void nnet::shift_line_buffer, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], nnet::array, 64u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config19_mult::weight_t*, config19_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 64u>, nnet::array, 64u>, config19>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*) (.26)' into 'void nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config54>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config54>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config54>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 96u>, config54>(hls::stream, 96u>, 0>&)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 96u>, config23>(nnet::array, 96u>::value_type (*) [config23::n_chan], nnet::array, 96u>::value_type*)' into 'void nnet::shift_line_buffer, 96u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], nnet::array, 96u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config23_mult::weight_t*, config23_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 96u>, nnet::array, 32u>, config23>(hls::stream, 96u>, 0>&, hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*) (.23)' into 'void nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>(hls::stream, 96u>, 0>&, hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config55>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config55>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config55>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 32u>, config55>(hls::stream, 32u>, 0>&)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 32u>, config25>(nnet::array, 32u>::value_type (*) [config25::n_chan], nnet::array, 32u>::value_type*)' into 'void nnet::shift_line_buffer, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config25_mult::weight_t*, config25_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 32u>, nnet::array, 32u>, config25>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*) (.19)' into 'void nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config56>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config56>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config56>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 48u>, config56>(hls::stream, 48u>, 0>&)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 48u>, config29>(nnet::array, 48u>::value_type (*) [config29::n_chan], nnet::array, 48u>::value_type*)' into 'void nnet::shift_line_buffer, 48u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], nnet::array, 48u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config29_mult::weight_t*, config29_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 48u>, nnet::array, 16u>, config29>(hls::stream, 48u>, 0>&, hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*) (.16)' into 'void nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>(hls::stream, 48u>, 0>&, hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config57>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config57>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config57>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 16u>, config57>(hls::stream, 16u>, 0>&)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 16u>, config31>(nnet::array, 16u>::value_type (*) [config31::n_chan], nnet::array, 16u>::value_type*)' into 'void nnet::shift_line_buffer, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config31_mult::weight_t*, config31_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 16u>, nnet::array, 16u>, config31>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*) (.12)' into 'void nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config58>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config58>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config58>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 24u>, config58>(hls::stream, 24u>, 0>&)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 24u>, config35>(nnet::array, 24u>::value_type (*) [config35::n_chan], nnet::array, 24u>::value_type*)' into 'void nnet::shift_line_buffer, 24u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], nnet::array, 24u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config35_mult::weight_t*, config35_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 24u>, nnet::array, 8u>, config35>(hls::stream, 24u>, 0>&, hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*) (.9)' into 'void nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>(hls::stream, 24u>, 0>&, hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config59>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:54:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config59>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:62:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_data, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:66:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config59>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:70:13) +INFO: [HLS 214-131] Inlining function 'void nnet::fill_zero, 8u>, config59>(hls::stream, 8u>, 0>&)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:78:13) +INFO: [HLS 214-131] Inlining function 'void nnet::kernel_shift_2d, 8u>, config37>(nnet::array, 8u>::value_type (*) [config37::n_chan], nnet::array, 8u>::value_type*)' into 'void nnet::shift_line_buffer, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:247:5) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config37_mult::weight_t*, config37_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:59:17) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:288:9) +INFO: [HLS 214-131] Inlining function 'void nnet::conv_2d_buffer_resource_cl, 8u>, nnet::array, 8u>, config37>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*) (.5)' into 'void nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv2d_stream.h:78:9) +INFO: [HLS 214-131] Inlining function 'nnet::product::mult, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0> >::product(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config60_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, config60_mult::weight_t*, config60_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:145:17) +INFO: [HLS 214-131] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const (.4)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config60>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config60::weight_t*, config60::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:100:13) +INFO: [HLS 214-131] Inlining function 'nnet::array, 1u>::operator[](unsigned long) (.2)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config60>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config60::weight_t*, config60::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:110:2) +INFO: [HLS 214-131] Inlining function 'nnet::DenseResource_rf_gt_nin_rem0, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>, config60_mult>::dense(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<36, 16, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*) (.3)' into 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config60>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config60::weight_t*, config60::bias_t*)' (firmware/nnet_utils/nnet_sepconv_stream.h:104:2) +INFO: [HLS 214-131] Inlining function 'void nnet::pointwise_mult_buffer, 8u>, nnet::array, 1u>, config60>(nnet::array, 8u> const&, hls::stream, 1u>, 0>&, config60::weight_t*, config60::bias_t*)' into 'void nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config60>(hls::stream, 8u>, 0>&, hls::stream, 1u>, 0>&, config60::weight_t*, config60::bias_t*)' (firmware/nnet_utils/nnet_sepconv2d_stream.h:86:21) +INFO: [HLS 214-291] Loop 'VITIS_LOOP_58_4' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_transpose_stream.h:58:26) +INFO: [HLS 214-291] Loop 'VITIS_LOOP_48_2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_transpose_stream.h:48:26) +INFO: [HLS 214-291] Loop 'VITIS_LOOP_21_1' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_transpose.h:21:22) +INFO: [HLS 214-291] Loop 'SigmoidPackLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_activation_stream.h:88:9) +INFO: [HLS 214-291] Loop 'ReLUPackLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_activation_stream.h:49:9) +INFO: [HLS 214-291] Loop 'MultLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_dense_resource.h:55:9) +INFO: [HLS 214-291] Loop 'KernelPushHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:205:5) +INFO: [HLS 214-291] Loop 'KernelPushChannel' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:208:9) +INFO: [HLS 214-291] Loop 'KernelShiftWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:189:5) +INFO: [HLS 214-291] Loop 'KernelShiftHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:192:9) +INFO: [HLS 214-291] Loop 'KernelShiftChannel' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:194:13) +INFO: [HLS 214-291] Loop 'LineBufferDataIn' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:236:5) +INFO: [HLS 214-291] Loop 'LineBufferShift' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:239:9) +INFO: [HLS 214-291] Loop 'UpdateBuffer' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_conv_stream.h:228:5) +INFO: [HLS 214-291] Loop 'ConcatPackInput1' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_merge_stream.h:245:13) +INFO: [HLS 214-291] Loop 'ConcatPackInput2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_merge_stream.h:251:13) +INFO: [HLS 214-291] Loop 'ImageWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:22:9) +INFO: [HLS 214-291] Loop 'ImageChan' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:28:13) +INFO: [HLS 214-291] Loop 'ResizeHeight' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:36:9) +INFO: [HLS 214-291] Loop 'ImageWidth2' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:40:13) +INFO: [HLS 214-291] Loop 'ResizeWidth' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:44:17) +INFO: [HLS 214-291] Loop 'ResizeChan' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_image_stream.h:51:21) +INFO: [HLS 214-291] Loop 'FiltLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_pooling_stream.h:57:9) +INFO: [HLS 214-291] Loop 'PoolLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_pooling_stream.h:62:13) +INFO: [HLS 214-291] Loop 'ClonePack' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_stream.h:32:9) +INFO: [HLS 214-291] Loop 'MultLoop' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_dense_resource.h:142:9) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_58_4' (firmware/nnet_utils/nnet_transpose_stream.h:58:26) in function 'nnet::transpose, 1u>, nnet::array, 1u>, config42>' completely with a factor of 1 (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_48_2' (firmware/nnet_utils/nnet_transpose_stream.h:48:26) in function 'nnet::transpose, 1u>, nnet::array, 1u>, config42>' completely with a factor of 1 (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_21_1' (firmware/nnet_utils/nnet_transpose.h:21:22) in function 'nnet::transfer_idx' completely with a factor of 3 (firmware/nnet_utils/nnet_transpose.h:18:0) +INFO: [HLS 214-186] Unrolling loop 'SigmoidPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:88:9) in function 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>' completely with a factor of 1 (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-186] Unrolling loop 'InitData' (firmware/nnet_utils/nnet_sepconv_stream.h:98:5) in function 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config60>' completely with a factor of 8 (firmware/nnet_utils/nnet_sepconv2d_stream.h:58:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config38>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config37>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config37>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config36>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 24 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 24u>, config35>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 24u>, config35>' completely with a factor of 24 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>' completely with a factor of 24 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' completely with a factor of 16 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' completely with a factor of 8 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 16u>, config33>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config32>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config31>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config31>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config30>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 96 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 48u>, config29>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 48u>, config29>' completely with a factor of 48 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>' completely with a factor of 48 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' completely with a factor of 32 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' completely with a factor of 16 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 16 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 32u>, config27>' completely with a factor of 32 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config26>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 128 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config25>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config25>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config24>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 384 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 96u>, config23>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 96u>, config23>' completely with a factor of 96 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>' completely with a factor of 96 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput1' (firmware/nnet_utils/nnet_merge_stream.h:245:13) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' completely with a factor of 64 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ConcatPackInput2' (firmware/nnet_utils/nnet_merge_stream.h:251:13) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' completely with a factor of 32 (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth' (firmware/nnet_utils/nnet_image_stream.h:22:9) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 8 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageChan' (firmware/nnet_utils/nnet_image_stream.h:28:13) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 64 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeHeight' (firmware/nnet_utils/nnet_image_stream.h:36:9) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ImageWidth2' (firmware/nnet_utils/nnet_image_stream.h:40:13) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 8 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeWidth' (firmware/nnet_utils/nnet_image_stream.h:44:17) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 2 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ResizeChan' (firmware/nnet_utils/nnet_image_stream.h:51:21) in function 'nnet::resize_nearest, 64u>, config21>' completely with a factor of 64 (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 64u>, nnet::array, 64u>, relu_config20>' completely with a factor of 64 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 576 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 64u>, config19>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 64u>, config19>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 64u>, nnet::array, 64u>, relu_config18>' completely with a factor of 64 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>' completely with a factor of 64 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 256 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config17>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config17>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config16>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config16>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>' completely with a factor of 32 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config15>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 128 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 32u>, config14>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 32u>, config14>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 32u>, nnet::array, 32u>, relu_config13>' completely with a factor of 32 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>' completely with a factor of 32 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 64 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config12>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config12>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config11>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config11>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>' completely with a factor of 16 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config10>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 32 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 16u>, config9>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 16u>, config9>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 16u>, nnet::array, 16u>, relu_config8>' completely with a factor of 16 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>' completely with a factor of 16 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>' completely with a factor of 16 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config7>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config7>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'FiltLoop' (firmware/nnet_utils/nnet_pooling_stream.h:57:9) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'PoolLoop' (firmware/nnet_utils/nnet_pooling_stream.h:62:13) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' completely with a factor of 4 (firmware/nnet_utils/nnet_pooling_stream.h:96:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config6>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config6>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'ClonePack' (firmware/nnet_utils/nnet_stream.h:32:9) in function 'nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>' completely with a factor of 8 (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config5>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:80:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:55:9) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:40:5) in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 8u>, config4>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 8u>, config4>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'ReLUPackLoop' (firmware/nnet_utils/nnet_activation_stream.h:49:9) in function 'nnet::relu, 8u>, nnet::array, 8u>, relu_config3>' completely with a factor of 8 (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-186] Unrolling loop 'CastLoop' (firmware/nnet_utils/nnet_conv_stream.h:293:9) in function 'nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>' completely with a factor of 8 (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-186] Unrolling loop 'Result' (firmware/nnet_utils/nnet_dense_resource.h:162:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'MultLoop' (firmware/nnet_utils/nnet_dense_resource.h:142:9) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 1 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'InitAccum' (firmware/nnet_utils/nnet_dense_resource.h:114:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' completely with a factor of 8 (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushHeight' (firmware/nnet_utils/nnet_conv_stream.h:205:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelPushChannel' (firmware/nnet_utils/nnet_conv_stream.h:208:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +WARNING: [HLS 214-189] Pipeline directive for loop 'KernelShiftWidth' (firmware/nnet_utils/nnet_conv_stream.h:189:5) in function 'nnet::shift_line_buffer, 1u>, config2>' has been removed because the loop is unrolled completely (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftHeight' (firmware/nnet_utils/nnet_conv_stream.h:192:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 3 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'KernelShiftChannel' (firmware/nnet_utils/nnet_conv_stream.h:194:13) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferDataIn' (firmware/nnet_utils/nnet_conv_stream.h:236:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'LineBufferShift' (firmware/nnet_utils/nnet_conv_stream.h:239:9) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 2 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'UpdateBuffer' (firmware/nnet_utils/nnet_conv_stream.h:228:5) in function 'nnet::shift_line_buffer, 1u>, config2>' completely with a factor of 1 (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_22_1' (firmware/nnet_utils/nnet_padding_stream.h:22:22) in function 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>' completely with a factor of 1 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_58_4' (firmware/nnet_utils/nnet_transpose_stream.h:58:26) in function 'nnet::transpose, 64u>, nnet::array, 1u>, config41>' completely with a factor of 1 (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_48_2' (firmware/nnet_utils/nnet_transpose_stream.h:48:26) in function 'nnet::transpose, 64u>, nnet::array, 1u>, config41>' completely with a factor of 64 (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_21_1' (firmware/nnet_utils/nnet_transpose.h:21:22) in function 'nnet::transfer_idx' completely with a factor of 4 (firmware/nnet_utils/nnet_transpose.h:18:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'std::enable_if<(config41::dims) != (2), void>::type nnet::transpose, 64u>, nnet::array, 1u>, config41>(hls::stream, 64u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'std::enable_if<(config41::dims) != (2), void>::type nnet::transpose, 64u>, nnet::array, 1u>, config41>(hls::stream, 64u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-178] Inlining function 'unsigned int nnet::transfer_idx(int)' into 'std::enable_if<(config41::dims) != (2), void>::type nnet::transpose, 64u>, nnet::array, 1u>, config41>(hls::stream, 64u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 1u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], nnet::array, 1u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(config2_mult::accum_t)' into 'void nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>*, config2_mult::weight_t*, config2_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:89:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 1u>, nnet::array, 8u>, config2>(nnet::array, 1u> const&, ap_shift_reg, 1u>::value_type, config2::in_width> (*) [config2::n_chan], hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config3>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config3>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(config4_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config4_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config4_mult::weight_t*, config4_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config4>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config4::in_width> (*) [config4::n_chan], hls::stream, 8u>, 0>&, config4::weight_t*, config4::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config5>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config5>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config6>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config6::in_width> (*) [config6::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(config7_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config7_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config7_mult::weight_t*, config7_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 16u>, config7>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config7::in_width> (*) [config7::n_chan], hls::stream, 16u>, 0>&, config7::weight_t*, config7::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config8>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config8>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(config9_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config9_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config9_mult::weight_t*, config9_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config9>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config9::in_width> (*) [config9::n_chan], hls::stream, 16u>, 0>&, config9::weight_t*, config9::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config10>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config10>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config11>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config11::in_width> (*) [config11::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(config12_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config12_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config12_mult::weight_t*, config12_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 32u>, config12>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config12::in_width> (*) [config12::n_chan], hls::stream, 32u>, 0>&, config12::weight_t*, config12::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config13>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config13>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(config14_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config14_mult::weight_t*, config14_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config14>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config14::in_width> (*) [config14::n_chan], hls::stream, 32u>, 0>&, config14::weight_t*, config14::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config15>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config15>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_stream.h:20:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config16>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config16::in_width> (*) [config16::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 64u>, config17>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config17::in_width> (*) [config17::n_chan], hls::stream, 64u>, 0>&, config17::weight_t*, config17::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config18>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config18>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], nnet::array, 64u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 64u>, nnet::array, 64u>, config19>(nnet::array, 64u> const&, ap_shift_reg, 64u>::value_type, config19::in_width> (*) [config19::n_chan], hls::stream, 64u>, 0>&, config19::weight_t*, config19::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config20>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::relu, 64u>, nnet::array, 64u>, relu_config20>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 64u>, config21>(hls::stream, 64u>, 0>&, hls::stream, 64u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 64u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>(hls::stream, 64u>, 0>&, hls::stream, 32u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>(hls::stream, 96u>, 0>&, hls::stream, 96u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 96u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 96u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], nnet::array, 96u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(config23_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>*, config23_mult::weight_t*, config23_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 96u>, nnet::array, 32u>, config23>(nnet::array, 96u> const&, ap_shift_reg, 96u>::value_type, config23::in_width> (*) [config23::n_chan], hls::stream, 32u>, 0>&, config23::weight_t*, config23::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config24>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config24>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], nnet::array, 32u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(config25_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config25_mult::weight_t*, config25_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 32u>, nnet::array, 32u>, config25>(nnet::array, 32u> const&, ap_shift_reg, 32u>::value_type, config25::in_width> (*) [config25::n_chan], hls::stream, 32u>, 0>&, config25::weight_t*, config25::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config26>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::relu, 32u>, nnet::array, 32u>, relu_config26>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 32u>, config27>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 32u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>(hls::stream, 32u>, 0>&, hls::stream, 16u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>(hls::stream, 48u>, 0>&, hls::stream, 48u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 48u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 48u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], nnet::array, 48u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(config29_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>*, config29_mult::weight_t*, config29_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 48u>, nnet::array, 16u>, config29>(nnet::array, 48u> const&, ap_shift_reg, 48u>::value_type, config29::in_width> (*) [config29::n_chan], hls::stream, 16u>, 0>&, config29::weight_t*, config29::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config30>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config30>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], nnet::array, 16u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(config31_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config31_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config31_mult::weight_t*, config31_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 16u>, nnet::array, 16u>, config31>(nnet::array, 16u> const&, ap_shift_reg, 16u>::value_type, config31::in_width> (*) [config31::n_chan], hls::stream, 16u>, 0>&, config31::weight_t*, config31::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config32>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::relu, 16u>, nnet::array, 16u>, relu_config32>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::resize_nearest, 16u>, config33>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)' (firmware/nnet_utils/nnet_image_stream.h:9:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 16u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>(hls::stream, 16u>, 0>&, hls::stream, 8u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_merge_stream.h:232:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>(hls::stream, 24u>, 0>&, hls::stream, 24u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 24u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 24u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], nnet::array, 24u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(config35_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>*, config35_mult::weight_t*, config35_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 24u>, nnet::array, 8u>, config35>(nnet::array, 24u> const&, ap_shift_reg, 24u>::value_type, config35::in_width> (*) [config35::n_chan], hls::stream, 8u>, 0>&, config35::weight_t*, config35::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config36>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config36>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long) const' into 'void nnet::shift_line_buffer, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], nnet::array, 8u>::value_type*)' (firmware/nnet_utils/nnet_conv_stream.h:219:0) +INFO: [HLS 214-178] Inlining function 'std::enable_if, ap_uint<1> >::value), ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >::type nnet::cast, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(config37_mult::accum_t)' into 'void nnet::dense_resource_rf_leq_nin, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, config37_mult>(ap_fixed<16, 6, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<40, 20, (ap_q_mode)5, (ap_o_mode)3, 0>*, config37_mult::weight_t*, config37_mult::bias_t*)' (firmware/nnet_utils/nnet_dense_resource.h:15:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::compute_output_buffer_2d, 8u>, nnet::array, 8u>, config37>(nnet::array, 8u> const&, ap_shift_reg, 8u>::value_type, config37::in_width> (*) [config37::n_chan], hls::stream, 8u>, 0>&, config37::weight_t*, config37::bias_t*)' (firmware/nnet_utils/nnet_conv_stream.h:257:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config38>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 8u>::operator[](unsigned long)' into 'void nnet::relu, 8u>, nnet::array, 8u>, relu_config38>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:39:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'void nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_activation_stream.h:65:0) +INFO: [HLS 214-178] Inlining function 'nnet::array, 1u>::operator[](unsigned long)' into 'std::enable_if<(config42::dims) != (2), void>::type nnet::transpose, 1u>, nnet::array, 1u>, config42>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-178] Inlining function 'unsigned int nnet::transfer_idx(int)' into 'std::enable_if<(config42::dims) != (2), void>::type nnet::transpose, 1u>, nnet::array, 1u>, config42>(hls::stream, 1u>, 0>&, hls::stream, 1u>, 0>&)' (firmware/nnet_utils/nnet_transpose_stream.h:40:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj1EEENS1_IS2_ILi37ELi17ELS3_5ELS4_3ELi0EELj8EEE7config2EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEES6_7config6EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_pooling_stream.h:104:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv2d_stream.h:47:0) +INFO: [HLS 214-248] Applying array_partition to 'b2': Complete partitioning on dimension 1. (firmware/weights/b2.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b4': Complete partitioning on dimension 1. (firmware/weights/b4.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b7': Complete partitioning on dimension 1. (firmware/weights/b7.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b9': Complete partitioning on dimension 1. (firmware/weights/b9.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b12': Complete partitioning on dimension 1. (firmware/weights/b12.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b14': Complete partitioning on dimension 1. (firmware/weights/b14.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b17': Complete partitioning on dimension 1. (firmware/weights/b17.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b19': Complete partitioning on dimension 1. (firmware/weights/b19.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b23': Complete partitioning on dimension 1. (firmware/weights/b23.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b25': Complete partitioning on dimension 1. (firmware/weights/b25.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b29': Complete partitioning on dimension 1. (firmware/weights/b29.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b31': Complete partitioning on dimension 1. (firmware/weights/b31.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b35': Complete partitioning on dimension 1. (firmware/weights/b35.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b37': Complete partitioning on dimension 1. (firmware/weights/b37.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'w39': Complete partitioning on dimension 1. (firmware/weights/w39.h:12:0) +INFO: [HLS 214-248] Applying array_partition to 'b39': Complete partitioning on dimension 1. (firmware/weights/b39.h:12:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEES6_7config6EEvRKT_PAsrT1_6n_filt_12ap_shift_regINS8_10value_typeEXsrSB_8in_widthEERN3hls6streamIT0_Li0EEEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_pooling_stream.h:45:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to '_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj1EEENS1_IS2_ILi37ELi17ELS3_5ELS4_3ELi0EELj8EEE7config2EEvRKT_PAsrT1_6n_chan_12ap_shift_regINSA_10value_typeEXsrSD_8in_widthEERN3hls6streamIT0_Li0EEEPNSD_8weight_tEPNSD_6bias_tEE11kernel_data': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:271:0) +INFO: [HLS 214-248] Applying array_partition to 'data_array': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_transpose_stream.h:42:33) +INFO: [HLS 214-248] Applying array_partition to 'acc': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_dense_resource.h:110:32) +INFO: [HLS 214-248] Applying array_partition to 'res_out': Complete partitioning on dimension 1. (firmware/nnet_utils/nnet_conv_stream.h:274:29) +INFO: [HLS 214-248] Applying array_partition to 'shift_buffer': Complete partitioning on dimension 1. Complete partitioning on dimension 2. (firmware/nnet_utils/nnet_conv_stream.h:224:30) +WARNING: [HLS 214-322] Unsuported scalar variable on pragma 'Resource/Bind_Storage', ignore it. (firmware/myproject.cpp:348:5) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer40_out' with compact=bit mode in 16-bits (firmware/myproject.cpp:235:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer46_out' with compact=bit mode in 16-bits (firmware/myproject.cpp:61:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer41_out' with compact=bit mode in 16-bits (firmware/myproject.cpp:58:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer39_out' with compact=bit mode in 36-bits (firmware/myproject.cpp:232:35) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer38_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:229:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer59_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:223:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer36_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:220:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer48_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:88:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer6_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:85:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer43_cpy1' with compact=bit mode in 128-bits (firmware/myproject.cpp:79:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer43_cpy2' with compact=bit mode in 128-bits (firmware/myproject.cpp:82:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer5_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:76:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer47_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:70:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer3_out' with compact=bit mode in 128-bits (firmware/myproject.cpp:67:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer37_out' with compact=bit mode in 320-bits (firmware/myproject.cpp:226:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer4_out' with compact=bit mode in 320-bits (firmware/myproject.cpp:73:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer35_out' with compact=bit mode in 328-bits (firmware/myproject.cpp:217:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer58_out' with compact=bit mode in 384-bits (firmware/myproject.cpp:214:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer34_out' with compact=bit mode in 384-bits (firmware/myproject.cpp:211:30) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer33_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:208:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer32_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:205:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer57_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:199:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer30_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:196:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer50_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:115:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer11_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:112:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer44_cpy1' with compact=bit mode in 256-bits (firmware/myproject.cpp:106:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer44_cpy2' with compact=bit mode in 256-bits (firmware/myproject.cpp:109:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer10_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:103:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer49_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:97:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer8_out' with compact=bit mode in 256-bits (firmware/myproject.cpp:94:24) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer31_out' with compact=bit mode in 656-bits (firmware/myproject.cpp:202:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer9_out' with compact=bit mode in 656-bits (firmware/myproject.cpp:100:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer29_out' with compact=bit mode in 672-bits (firmware/myproject.cpp:193:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer56_out' with compact=bit mode in 768-bits (firmware/myproject.cpp:190:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer28_out' with compact=bit mode in 768-bits (firmware/myproject.cpp:187:30) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer27_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:184:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer26_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:181:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer55_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:175:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer24_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:172:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer52_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:142:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer16_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:139:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer45_cpy1' with compact=bit mode in 512-bits (firmware/myproject.cpp:133:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer45_cpy2' with compact=bit mode in 512-bits (firmware/myproject.cpp:136:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer15_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:130:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer51_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:124:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer13_out' with compact=bit mode in 512-bits (firmware/myproject.cpp:121:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer25_out' with compact=bit mode in 1344-bits (firmware/myproject.cpp:178:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer14_out' with compact=bit mode in 1344-bits (firmware/myproject.cpp:127:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer23_out' with compact=bit mode in 1376-bits (firmware/myproject.cpp:169:34) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer54_out' with compact=bit mode in 1536-bits (firmware/myproject.cpp:166:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer22_out' with compact=bit mode in 1536-bits (firmware/myproject.cpp:163:28) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer21_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:160:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer20_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:157:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer53_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:151:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer18_out' with compact=bit mode in 1024-bits (firmware/myproject.cpp:148:25) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer19_out' with compact=bit mode in 2752-bits (firmware/myproject.cpp:154:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer17_out' with compact=bit mode in 2688-bits (firmware/myproject.cpp:145:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer12_out' with compact=bit mode in 1312-bits (firmware/myproject.cpp:118:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer7_out' with compact=bit mode in 640-bits (firmware/myproject.cpp:91:32) +INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'layer2_out' with compact=bit mode in 296-bits (firmware/myproject.cpp:64:32) +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::conv_2d_buffer_resource_cl, 1u>, nnet::array, 8u>, config2>(hls::stream, 1u>, 0>&, hls::stream, 8u>, 0>&, config2::weight_t*, config2::bias_t*)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE7config4EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>(hls::stream, 8u>, 0>&, hls::stream, 8u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj16EEE7config7EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE7config9EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>(hls::stream, 16u>, 0>&, hls::stream, 16u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEES6_8config11EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj32EEE8config12EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config14EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable 'void nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>(hls::stream, 32u>, 0>&, hls::stream, 32u>, 0>&)::line_buffer' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEES6_8config16EEvRN3hls6streamIT_Li0EEERNS9_IT0_Li0EEEE11line_buffer_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj64EEE8config17EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj64EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj64EEE8config19EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_64' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_65' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_66' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_67' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_68' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_69' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_70' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_71' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_72' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_73' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_74' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_75' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_76' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_77' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_78' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_79' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_80' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_81' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_82' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_83' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_84' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_85' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_86' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_87' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_88' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_89' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_90' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_91' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_92' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_93' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_94' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_95' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_48' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_49' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_50' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_51' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_52' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_53' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_54' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_55' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_56' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_57' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_58' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_59' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_60' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_61' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_62' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_63' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_64' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_65' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_66' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_67' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_68' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_69' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_70' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_71' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_72' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_73' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_74' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_75' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_76' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_77' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_78' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_79' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_80' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_81' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_82' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_83' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_84' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_85' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_86' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_87' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_88' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_89' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_90' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_91' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_92' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_93' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_94' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj96EEENS1_IS2_ILi43ELi23ELS3_5ELS4_3ELi0EELj32EEE8config23EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_95' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj32EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj32EEE8config25EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_24' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_25' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_26' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_27' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_28' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_29' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_30' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_31' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_32' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_33' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_34' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_35' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_36' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_37' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_38' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_39' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_40' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_41' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_42' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_43' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_44' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_45' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_46' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj48EEENS1_IS2_ILi42ELi22ELS3_5ELS4_3ELi0EELj16EEE8config29EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_47' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj16EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj16EEE8config31EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_8' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_9' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_10' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_11' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_12' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_13' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_14' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_15' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_16' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_17' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_18' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_19' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_20' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_21' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_22' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj24EEENS1_IS2_ILi41ELi21ELS3_5ELS4_3ELi0EELj8EEE8config35EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_23' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_0_7' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_0' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_1' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_2' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_3' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_4' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_5' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_6' with compact=bit mode in 16-bits +INFO: [HLS 214-241] Aggregating bram variable '_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3ELi0EELj8EEENS1_IS2_ILi40ELi20ELS3_5ELS4_3ELi0EELj8EEE8config37EEvRN3hls6streamIT_Li0EEERNSB_IT0_Li0EEEPNT1_8weight_tEPNSI_6bias_tEE11line_buffer_1_7' with compact=bit mode in 16-bits +INFO: [HLS 214-248] Applying array_reshape to 'w4': Block reshaping with factor 8 on dimension 1. (firmware/weights/w4.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w7': Block reshaping with factor 16 on dimension 1. (firmware/weights/w7.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w9': Block reshaping with factor 32 on dimension 1. (firmware/weights/w9.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w12': Block reshaping with factor 64 on dimension 1. (firmware/weights/w12.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w14': Block reshaping with factor 128 on dimension 1. (firmware/weights/w14.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w17': Block reshaping with factor 256 on dimension 1. (firmware/weights/w17.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w19': Block reshaping with factor 576 on dimension 1. (firmware/weights/w19.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w23': Block reshaping with factor 384 on dimension 1. (firmware/weights/w23.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w25': Block reshaping with factor 128 on dimension 1. (firmware/weights/w25.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w29': Block reshaping with factor 96 on dimension 1. (firmware/weights/w29.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w31': Block reshaping with factor 32 on dimension 1. (firmware/weights/w31.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w35': Block reshaping with factor 24 on dimension 1. (firmware/weights/w35.h:12:0) +INFO: [HLS 214-248] Applying array_reshape to 'w37': Block reshaping with factor 8 on dimension 1. (firmware/weights/w37.h:12:0) +INFO: [HLS 214-376] automatically set the pipeline for Loop< ReadInputWidthSerial> at firmware/nnet_utils/nnet_sepconv2d_stream.h:83:13 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadTopWidth> at firmware/nnet_utils/nnet_padding_stream.h:53:9 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadMain> at firmware/nnet_utils/nnet_padding_stream.h:59:5 +INFO: [HLS 214-376] automatically set the pipeline for Loop< PadBottomWidth> at firmware/nnet_utils/nnet_padding_stream.h:77:9 +INFO: [HLS 214-291] Loop 'CopyMain' is marked as complete unroll implied by the pipeline pragma (firmware/nnet_utils/nnet_padding_stream.h:65:9) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>' completely with a factor of 8 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>' completely with a factor of 16 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>' completely with a factor of 32 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-186] Unrolling loop 'CopyMain' (firmware/nnet_utils/nnet_padding_stream.h:65:9) in function 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>' completely with a factor of 64 (firmware/nnet_utils/nnet_padding_stream.h:48:0) +INFO: [HLS 214-270] Inferring pragma 'array_partition type=complete dim=1' for array 'ref.tmp.i' due to pipeline pragma +INFO: [HLS 214-248] Applying array_partition to 'ref.tmp.i': Complete partitioning on dimension 1. +INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 36481.4 seconds. CPU system time: 7.55 seconds. Elapsed time: 36476.2 seconds; current allocated memory: 352.531 MB. +INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 352.531 MB. +INFO: [HLS 200-10] Starting code transformations ... +INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 165.63 seconds. CPU system time: 0.56 seconds. Elapsed time: 166.3 seconds; current allocated memory: 1001.887 MB. +INFO: [HLS 200-10] Checking synthesizability ... +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 140.82 seconds. CPU system time: 0.73 seconds. Elapsed time: 141.74 seconds; current allocated memory: 2.077 GB. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-102] Partitioning array 'in_elem' automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-602] Inlining function 'nnet::cast, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' into 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_dense_resource.h:82) automatically. +INFO: [XFORM 203-712] Applying dataflow to function 'myproject' (firmware/myproject.cpp:8), detected/extracted 58 process function(s): + 'nnet::transpose, 64u>, nnet::array, 1u>, config41>' + 'nnet::zeropad2d_cl, 1u>, nnet::array, 1u>, config46>' + 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config3>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config47>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config5>' + 'nnet::clone_stream, 8u>, nnet::array, 8u>, 32768>' + 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config48>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config8>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config49>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config10>' + 'nnet::clone_stream, 16u>, nnet::array, 16u>, 16384>' + 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config50>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config13>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config51>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config15>' + 'nnet::clone_stream, 32u>, nnet::array, 32u>, 8192>' + 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config52>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>' + 'nnet::relu, 64u>, nnet::array, 64u>, relu_config18>' + 'nnet::zeropad2d_cl, 64u>, nnet::array, 64u>, config53>' + 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>' + 'nnet::relu, 64u>, nnet::array, 64u>, relu_config20>' + 'nnet::resize_nearest, 64u>, config21>' + 'nnet::concatenate3d, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>' + 'nnet::zeropad2d_cl, 96u>, nnet::array, 96u>, config54>' + 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config24>' + 'nnet::zeropad2d_cl, 32u>, nnet::array, 32u>, config55>' + 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>' + 'nnet::relu, 32u>, nnet::array, 32u>, relu_config26>' + 'nnet::resize_nearest, 32u>, config27>' + 'nnet::concatenate3d, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>' + 'nnet::zeropad2d_cl, 48u>, nnet::array, 48u>, config56>' + 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config30>' + 'nnet::zeropad2d_cl, 16u>, nnet::array, 16u>, config57>' + 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>' + 'nnet::relu, 16u>, nnet::array, 16u>, relu_config32>' + 'nnet::resize_nearest, 16u>, config33>' + 'nnet::concatenate3d, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>' + 'nnet::zeropad2d_cl, 24u>, nnet::array, 24u>, config58>' + 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config36>' + 'nnet::zeropad2d_cl, 8u>, nnet::array, 8u>, config59>' + 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>' + 'nnet::relu, 8u>, nnet::array, 8u>, relu_config38>' + 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config60>' + 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>' + 'nnet::transpose, 1u>, nnet::array, 1u>, config42>'. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_activation_stream.h:81:9) to (firmware/nnet_utils/nnet_activation_stream.h:80:5) in function 'nnet::sigmoid, 1u>, nnet::array, 1u>, sigmoid_config40>'... converting 3 basic blocks. +INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (firmware/nnet_utils/nnet_dense_resource.h:135:25) to (firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>'... converting 18 basic blocks. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config23_mult>' (firmware/nnet_utils/nnet_dense_resource.h:46:20)...384 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<43, 23, (ap_q_mode)5, (ap_o_mode)3, 0>, config19_mult>' (firmware/nnet_utils/nnet_mult.h:46:11)...576 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config29_mult>' (firmware/nnet_utils/nnet_dense_resource.h:46:5)...96 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config25_mult>' (firmware/nnet_utils/nnet_mult.h:46:11)...128 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config17_mult>' (firmware/nnet_utils/nnet_mult.h:46:11)...256 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<42, 22, (ap_q_mode)5, (ap_o_mode)3, 0>, config14_mult>' (firmware/nnet_utils/nnet_mult.h:46:11)...128 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_leq_nin, ap_fixed<41, 21, (ap_q_mode)5, (ap_o_mode)3, 0>, config35_mult>' (firmware/nnet_utils/nnet_dense_resource.h:46:5)...24 expression(s) balanced. +INFO: [XFORM 203-11] Balancing expressions in function 'nnet::dense_resource_rf_gt_nin_rem0, ap_fixed<37, 17, (ap_q_mode)5, (ap_o_mode)3, 0>, config2_mult>' (firmware/nnet_utils/nnet_dense_resource.h:73:5)...13 expression(s) balanced. +INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 1174.8 seconds. CPU system time: 1.13 seconds. Elapsed time: 1176.14 seconds; current allocated memory: 3.941 GB. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_pooling_stream.h:109:5) in function 'nnet::pooling2d_cl, 8u>, nnet::array, 8u>, config6>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_pooling_stream.h:109:5) in function 'nnet::pooling2d_cl, 32u>, nnet::array, 32u>, config16>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_pooling_stream.h:109:5) in function 'nnet::pooling2d_cl, 16u>, nnet::array, 16u>, config11>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeightSerial' (firmware/nnet_utils/nnet_sepconv2d_stream.h:81:9) in function 'nnet::pointwise_conv_2d_cl, 8u>, nnet::array, 1u>, config60>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 96u>, nnet::array, 32u>, config23>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config4>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 8u>, nnet::array, 8u>, config37>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 8u>, nnet::array, 16u>, config7>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 64u>, nnet::array, 64u>, config19>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 48u>, nnet::array, 16u>, config29>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 32u>, nnet::array, 64u>, config17>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config25>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 32u>, nnet::array, 32u>, config14>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 24u>, nnet::array, 8u>, config35>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 1u>, nnet::array, 8u>, config2>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 16u>, nnet::array, 32u>, config12>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config9>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ReadInputHeight' (firmware/nnet_utils/nnet_conv2d_stream.h:52:5) in function 'nnet::conv_2d_cl, 16u>, nnet::array, 16u>, config31>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ConcatLoopHeight' (firmware/nnet_utils/nnet_merge_stream.h:234:5) in function 'nnet::concatenate3d_2, 64u>, nnet::array, 32u>, nnet::array, 96u>, config22>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ConcatLoopHeight' (firmware/nnet_utils/nnet_merge_stream.h:234:5) in function 'nnet::concatenate3d_2, 32u>, nnet::array, 16u>, nnet::array, 48u>, config28>'. +INFO: [XFORM 203-541] Flattening a loop nest 'ConcatLoopHeight' (firmware/nnet_utils/nnet_merge_stream.h:234:5) in function 'nnet::concatenate3d_2, 16u>, nnet::array, 8u>, nnet::array, 24u>, config34>'. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config23_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config19_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config29_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config25_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config17_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config14_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config9_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config35_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config31_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config12_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config7_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config4_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:46:5) in function 'dense_resource_rf_leq_nin,config37_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +WARNING: [HLS 200-1992] Performance of loop 'ReuseLoop'(firmware/nnet_utils/nnet_dense_resource.h:135:5) in function 'dense_resource_rf_gt_nin_rem0,config2_mult>' can be improved with loop rewind inference if the loop is called from a region that can be executed in overlapped fashion such as a dataflow region or the top function. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config23_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config19_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config29_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config25_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config17_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config14_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config9_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config35_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config31_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config12_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config7_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config4_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:46) in function 'dense_resource_rf_leq_nin,config37_mult>'. +INFO: [XFORM 203-531] Rewinding loop 'ReuseLoop' (firmware/nnet_utils/nnet_dense_resource.h:135) in function 'dense_resource_rf_gt_nin_rem0,config2_mult>'. +INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 4265.31 seconds. CPU system time: 0.76 seconds. Elapsed time: 4266.3 seconds; current allocated memory: 5.563 GB. +INFO: [HLS 200-10] Starting hardware synthesis ... +INFO: [HLS 200-10] Synthesizing 'myproject' ... +WARNING: [SYN 201-103] Legalizing function name 'transpose,config41>_Pipeline_VITIS_LOOP_45_1' to 'transpose_array_array_ap_fixed_1u_config41_Pipeline_VITIS_LOOP_45_1'. +WARNING: [SYN 201-103] Legalizing function name 'transpose,config41>_Pipeline_VITIS_LOOP_54_3' to 'transpose_array_array_ap_fixed_1u_config41_Pipeline_VITIS_LOOP_54_3'. +WARNING: [SYN 201-103] Legalizing function name 'transpose,array,1u>,config41>' to 'transpose_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_1u_config41_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,1u>,config46>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config46_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,1u>,config46>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config46_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config46>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_1u_config46_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,1u>,config46>' to 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config46_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 1u>, config2>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_gt_nin_rem0,config2_mult>' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config2>' to 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config2>' to 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config3>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config47>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config47>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config47>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,8u>,config47>' to 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config47_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config4>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config4_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config4>' to 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config4>' to 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config5>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s'. +WARNING: [SYN 201-103] Legalizing function name 'clone_stream,array,8u>,32768>' to 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config6>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +WARNING: [SYN 201-103] Legalizing function name 'pooling2d_cl,array,8u>,config6>' to 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config48>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config48>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config48>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,8u>,config48>' to 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config48_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config7>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config7_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config7>' to 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,16u>,config7>' to 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config8>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config49>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config49_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config49>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config49_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config49>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config49_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config49>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config49_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config9>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config9_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config9>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,16u>,config9>' to 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config10>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s'. +WARNING: [SYN 201-103] Legalizing function name 'clone_stream,array,16u>,16384>' to 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config11>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +WARNING: [SYN 201-103] Legalizing function name 'pooling2d_cl,16u>,config11>' to 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config50>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config50_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config50>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config50_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config50>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config50_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config50>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config50_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config12>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config12_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config12>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config12>' to 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config13>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config51>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config51_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config51>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config51_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config51>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config51_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config51>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config51_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config14>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config14_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config14>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config14>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config15>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s'. +WARNING: [SYN 201-103] Legalizing function name 'clone_stream,array,32u>,8192>' to 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config16>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +WARNING: [SYN 201-103] Legalizing function name 'pooling2d_cl,32u>,config16>' to 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config52>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config52_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config52>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config52>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config52_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config52>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config17>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config17_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,64u>,config17>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,64u>,config17>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,64u>,relu_config18>' to 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config53>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_64u_config53_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,64u>,config53>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config53>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_64u_config53_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,64u>,config53>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 64u>, config19>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config19_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,64u>,config19>' to 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,64u>,config19>' to 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,64u>,relu_config20>' to 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s'. +WARNING: [SYN 201-103] Legalizing function name 'resize_nearest, 64u>, config21>' to 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d_2,96u>,config22>' to 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d,96u>,config22>' to 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config54>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_96u_config54_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,96u>,config54>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config54>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_96u_config54_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,96u>,config54>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 96u>, config23>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config23_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config23>' to 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config23>' to 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config24>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config55>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config55_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config55>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config55_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config55>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_32u_config55_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,32u>,config55>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config55_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 32u>, config25>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config25_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,32u>,config25>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,32u>,config25>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,32u>,relu_config26>' to 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s'. +WARNING: [SYN 201-103] Legalizing function name 'resize_nearest, 32u>, config27>' to 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d_2,48u>,config28>' to 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d,48u>,config28>' to 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config56>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_48u_config56_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,48u>,config56>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config56>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_48u_config56_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,48u>,config56>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 48u>, config29>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config29_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config29>' to 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,16u>,config29>' to 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config30>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config57>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config57_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config57>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config57_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config57>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_16u_config57_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,16u>,config57>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config57_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 16u>, config31>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config31_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,16u>,config31>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,16u>,config31>' to 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,16u>,relu_config32>' to 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s'. +WARNING: [SYN 201-103] Legalizing function name 'resize_nearest, 16u>, config33>' to 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d_2,24u>,config34>' to 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +WARNING: [SYN 201-103] Legalizing function name 'concatenate3d,24u>,config34>' to 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config58>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_24u_config58_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,24u>,config58>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config58_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config58>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_24u_config58_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,24u>,config58>' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config58_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 24u>, config35>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config35_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config35>' to 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config35>' to 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config36>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config59>_Pipeline_PadTopWidth' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config59_Pipeline_PadTopWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,8u>,config59>_Pipeline_PadMain' to 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config59_Pipeline_PadMain'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,config59>_Pipeline_PadBottomWidth' to 'zeropad2d_cl_array_array_ap_fixed_8u_config59_Pipeline_PadBottomWidth'. +WARNING: [SYN 201-103] Legalizing function name 'zeropad2d_cl,array,8u>,config59>' to 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config59_s'. +WARNING: [SYN 201-103] Legalizing function name 'shift_line_buffer, 8u>, config37>' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s'. +WARNING: [SYN 201-103] Legalizing function name 'dense_resource_rf_leq_nin,config37_mult>' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s'. +WARNING: [SYN 201-103] Legalizing function name 'compute_output_buffer_2d,8u>,config37>' to 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +WARNING: [SYN 201-103] Legalizing function name 'conv_2d_cl,array,8u>,config37>' to 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +WARNING: [SYN 201-103] Legalizing function name 'relu,array,8u>,relu_config38>' to 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s'. +WARNING: [SYN 201-103] Legalizing function name 'pointwise_conv_2d_cl,1u>,config60>' to 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config60_s'. +WARNING: [SYN 201-103] Legalizing function name 'sigmoid,1u>,sigmoid_config40>' to 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s'. +WARNING: [SYN 201-103] Legalizing function name 'transpose,config42>_Pipeline_VITIS_LOOP_45_1' to 'transpose_array_array_ap_fixed_1u_config42_Pipeline_VITIS_LOOP_45_1'. +WARNING: [SYN 201-103] Legalizing function name 'transpose,config42>_Pipeline_VITIS_LOOP_54_3' to 'transpose_array_array_ap_fixed_1u_config42_Pipeline_VITIS_LOOP_54_3'. +WARNING: [SYN 201-103] Legalizing function name 'transpose,array,1u>,config42>' to 'transpose_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config42_s'. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'transpose_array_array_ap_fixed_1u_config41_Pipeline_VITIS_LOOP_45_1' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'VITIS_LOOP_45_1'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'VITIS_LOOP_45_1' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 71.57 seconds. CPU system time: 0.49 seconds. Elapsed time: 72.09 seconds; current allocated memory: 5.563 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.07 seconds; current allocated memory: 5.563 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'transpose_array_array_ap_fixed_1u_config41_Pipeline_VITIS_LOOP_54_3' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'VITIS_LOOP_54_3'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'VITIS_LOOP_54_3' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.563 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.07 seconds; current allocated memory: 5.563 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'transpose_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_1u_config41_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 5.563 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 5.563 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config46_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.563 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.05 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 5.563 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config46_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config46_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer46_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer46_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.94 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.99 seconds; current allocated memory: 5.563 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.563 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_1u_config46_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.563 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 5.563 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config46_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 5.563 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 5.563 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 1u>, config2>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 1u>, config2>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.563 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 5.563 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +WARNING: [HLS 200-871] Estimated clock period (4.411 ns) exceeds the target (target clock period: 5.000 ns, clock uncertainty: 1.350 ns, effective delay budget: 3.650 ns). +Resolution: For help on HLS 200-871 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-871.html +WARNING: [HLS 200-1016] The critical path in module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' consists of the following: + 'or' operation 1 bit ('or_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [82] (0.000 ns) + 'or' operation 1 bit ('or_ln144_2', firmware/nnet_utils/nnet_dense_resource.h:144) [84] (0.000 ns) + 'or' operation 1 bit ('or_ln144_6', firmware/nnet_utils/nnet_dense_resource.h:144) [88] (0.000 ns) + 'select' operation 37 bit ('acc', firmware/nnet_utils/nnet_dense_resource.h:144) [89] (0.229 ns) + 'select' operation 37 bit ('acc_7', firmware/nnet_utils/nnet_dense_resource.h:144) [93] (0.229 ns) + multiplexor before 'phi' operation 37 bit ('acc') with incoming values : ('acc_7', firmware/nnet_utils/nnet_dense_resource.h:144) [33] (0.387 ns) + 'phi' operation 37 bit ('acc') with incoming values : ('acc_7', firmware/nnet_utils/nnet_dense_resource.h:144) [33] (0.000 ns) + 'sparsemux' operation 37 bit ('tmp_i', firmware/nnet_utils/nnet_dense_resource.h:144) [70] (0.584 ns) + 'add' operation 38 bit of DSP[73] ('add_ln144', firmware/nnet_utils/nnet_dense_resource.h:144) [73] (2.039 ns) + 'icmp' operation 1 bit ('icmp_ln144_7', firmware/nnet_utils/nnet_dense_resource.h:144) [81] (0.943 ns) + +Resolution: For help on HLS 200-1016 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1016.html +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 5.563 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 5.563 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 5.563 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 5.563 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 5.563 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.08 seconds; current allocated memory: 5.563 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.563 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 5.563 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.563 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 5.563 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer47_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer47_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.98 seconds. CPU system time: 0.03 seconds. Elapsed time: 1 seconds; current allocated memory: 5.564 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.564 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.564 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 5.564 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config47_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.564 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.08 seconds; current allocated memory: 5.564 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config4>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config4>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 5.564 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.08 seconds; current allocated memory: 5.564 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.24 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.26 seconds; current allocated memory: 5.564 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 5.564 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.564 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 5.564 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.564 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.564 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.14 seconds; current allocated memory: 5.564 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.564 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'CloneLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'CloneLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.564 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.564 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config6>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config6>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.564 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.564 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReadInputHeight_ReadInputWidth'. +WARNING: [HLS 200-880] The II Violation in module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' (loop 'ReadInputHeight_ReadInputWidth'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between 'load' operation 16 bit ('void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_32', firmware/nnet_utils/nnet_pooling_stream.h:63->firmware/nnet_utils/nnet_pooling_stream.h:115) on static variable 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel' and 'call' operation 0 bit ('_ln52', firmware/nnet_utils/nnet_pooling_stream.h:52->firmware/nnet_utils/nnet_pooling_stream.h:115) to 'shift_line_buffer, 8u>, config6>'. +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 2, Depth = 3, loop 'ReadInputHeight_ReadInputWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 5.564 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 5.564 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.564 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 5.564 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer48_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer48_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.46 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.48 seconds; current allocated memory: 5.565 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.565 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.565 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.08 seconds; current allocated memory: 5.565 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config48_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.565 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 5.565 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config7>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config7>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 5.566 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 5.566 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.29 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.31 seconds; current allocated memory: 5.573 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.573 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.573 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.573 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.573 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.573 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0 seconds. Elapsed time: 0.16 seconds; current allocated memory: 5.573 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.573 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config49_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.573 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 5.573 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config49_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config49_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer49_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer49_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.47 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.49 seconds; current allocated memory: 5.574 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.574 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config49_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.574 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.574 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config49_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.574 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 5.574 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config9>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config9>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0 seconds. Elapsed time: 0.2 seconds; current allocated memory: 5.574 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.575 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.51 seconds. CPU system time: 0 seconds. Elapsed time: 0.51 seconds; current allocated memory: 5.586 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 5.586 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 5.586 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.586 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.586 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.586 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 5.586 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.586 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'CloneLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'CloneLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.586 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 5.586 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config11>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config11>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 5.586 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.586 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReadInputHeight_ReadInputWidth'. +WARNING: [HLS 200-880] The II Violation in module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' (loop 'ReadInputHeight_ReadInputWidth'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between 'load' operation 16 bit ('void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_52', firmware/nnet_utils/nnet_pooling_stream.h:63->firmware/nnet_utils/nnet_pooling_stream.h:115) on static variable 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_20' and 'call' operation 0 bit ('_ln52', firmware/nnet_utils/nnet_pooling_stream.h:52->firmware/nnet_utils/nnet_pooling_stream.h:115) to 'shift_line_buffer, 16u>, config11>'. +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 2, Depth = 3, loop 'ReadInputHeight_ReadInputWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.22 seconds. CPU system time: 0 seconds. Elapsed time: 0.23 seconds; current allocated memory: 5.586 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.587 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config50_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0 seconds. Elapsed time: 0.15 seconds; current allocated memory: 5.588 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.588 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config50_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config50_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer50_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer50_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.29 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.32 seconds; current allocated memory: 5.589 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.589 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config50_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.589 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.589 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config50_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.589 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.589 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config12>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config12>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 5.590 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.591 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.66 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.68 seconds; current allocated memory: 5.612 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.19 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 5.612 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.2 seconds; current allocated memory: 5.612 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 5.612 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.612 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.612 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 5.612 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 5.612 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config51_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 5.612 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.612 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config51_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config51_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer51_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer51_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.3 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.33 seconds; current allocated memory: 5.612 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.612 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config51_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0 seconds. Elapsed time: 0.14 seconds; current allocated memory: 5.612 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 5.612 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config51_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 5.612 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.612 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config14>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config14>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.28 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.31 seconds; current allocated memory: 5.612 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 5.612 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.31 seconds. CPU system time: 0.02 seconds. Elapsed time: 1.33 seconds; current allocated memory: 5.647 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.34 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.37 seconds; current allocated memory: 5.647 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.25 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.27 seconds; current allocated memory: 5.647 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.647 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0 seconds. Elapsed time: 0.15 seconds; current allocated memory: 5.647 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 5.647 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.21 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.21 seconds; current allocated memory: 5.647 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.647 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'CloneLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'CloneLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 5.647 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.647 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config16>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config16>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.19 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 5.647 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.647 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReadInputHeight_ReadInputWidth'. +WARNING: [HLS 200-880] The II Violation in module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' (loop 'ReadInputHeight_ReadInputWidth'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between 'load' operation 16 bit ('void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_42', firmware/nnet_utils/nnet_pooling_stream.h:63->firmware/nnet_utils/nnet_pooling_stream.h:115) on static variable 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_19' and 'call' operation 0 bit ('_ln52', firmware/nnet_utils/nnet_pooling_stream.h:52->firmware/nnet_utils/nnet_pooling_stream.h:115) to 'shift_line_buffer, 32u>, config16>'. +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 2, Depth = 3, loop 'ReadInputHeight_ReadInputWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.3 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.33 seconds; current allocated memory: 5.647 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 5.647 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config52_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 5.647 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 5.647 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 7, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 9, distance = 1, offset = 1) between fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer52_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer52_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 10, Depth = 11, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.25 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.26 seconds; current allocated memory: 5.647 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 5.647 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config52_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.647 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 5.647 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 5.647 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 5.647 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config17>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config17>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.3 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.31 seconds; current allocated memory: 5.647 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 5.647 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 2.1 seconds. CPU system time: 0.04 seconds. Elapsed time: 2.16 seconds; current allocated memory: 5.711 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.58 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.61 seconds; current allocated memory: 5.711 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.32 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.36 seconds; current allocated memory: 5.711 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.711 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 5.711 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.711 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.24 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.25 seconds; current allocated memory: 5.711 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.711 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_64u_config53_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 5.711 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 5.711 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 7, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 9, distance = 1, offset = 1) between fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer53_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer53_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 10, Depth = 11, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.25 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.28 seconds; current allocated memory: 5.711 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 5.711 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_64u_config53_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0 seconds. Elapsed time: 0.14 seconds; current allocated memory: 5.711 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 5.711 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.711 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 5.711 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 64u>, config19>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 64u>, config19>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.61 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.62 seconds; current allocated memory: 5.711 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.19 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.22 seconds; current allocated memory: 5.711 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 5, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 5.06 seconds. CPU system time: 0.08 seconds. Elapsed time: 5.14 seconds; current allocated memory: 5.835 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 1.92 seconds. CPU system time: 0.05 seconds. Elapsed time: 1.97 seconds; current allocated memory: 5.835 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.56 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.61 seconds; current allocated memory: 5.835 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 5.835 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.2 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.22 seconds; current allocated memory: 5.835 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 5.835 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.28 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.3 seconds; current allocated memory: 5.835 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.835 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ImageHeight'. +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_1', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_2', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_3', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo read operation ('layer20_out_read_4', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer20_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer20_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer21_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer21_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 32, Depth = 32, loop 'ImageHeight' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.39 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.41 seconds; current allocated memory: 5.835 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 5.835 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ConcatLoopHeight_ConcatLoopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'ConcatLoopHeight_ConcatLoopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 5.835 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 5.835 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 5.835 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.835 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_96u_config54_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 5.835 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 5.835 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer54_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer54_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.34 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.36 seconds; current allocated memory: 5.835 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.835 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_96u_config54_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0 seconds. Elapsed time: 0.16 seconds; current allocated memory: 5.835 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 5.835 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.835 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.835 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 96u>, config23>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 96u>, config23>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.04 seconds. CPU system time: 0.02 seconds. Elapsed time: 1.07 seconds; current allocated memory: 5.835 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.29 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.31 seconds; current allocated memory: 5.835 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 5, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 4.53 seconds. CPU system time: 0.04 seconds. Elapsed time: 4.57 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 1.62 seconds. CPU system time: 0.03 seconds. Elapsed time: 1.66 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.58 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.62 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.26 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.27 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.16 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.25 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.28 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config55_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config55_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 11, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 15, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config55_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 17, distance = 1, offset = 1) between fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer55_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer55_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 18, Depth = 19, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.36 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.37 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_32u_config55_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.16 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config55_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 32u>, config25>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 32u>, config25>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.31 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.32 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.28 seconds. CPU system time: 0.02 seconds. Elapsed time: 1.31 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.36 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.38 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.27 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.29 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.2 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.22 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ImageHeight'. +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_1', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_2', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_3', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo read operation ('layer26_out_read_4', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer26_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer26_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer27_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer27_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 64, Depth = 64, loop 'ImageHeight' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.69 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.72 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ConcatLoopHeight_ConcatLoopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'ConcatLoopHeight_ConcatLoopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.17 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.1 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_48u_config56_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer56_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer56_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.53 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.56 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_48u_config56_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 48u>, config29>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 48u>, config29>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.44 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.47 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 5, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.4 seconds. CPU system time: 0.03 seconds. Elapsed time: 1.43 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.42 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.45 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.3 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.31 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.21 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.22 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config57_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.17 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config57_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config57_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 33, distance = 1, offset = 1) between fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer57_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer57_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 34, Depth = 35, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.54 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.58 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16u_config57_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.17 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config57_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.11 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 16u>, config31>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 16u>, config31>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.21 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.23 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.52 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.54 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.13 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ImageHeight'. +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_1', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_2', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_3', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo read operation ('layer32_out_read_4', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25) and fifo read operation ('layer32_out_read', firmware/nnet_utils/nnet_image_stream.h:25) on port 'layer32_out' (firmware/nnet_utils/nnet_image_stream.h:25). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 67, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 98, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 114, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 122, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 126, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' (loop 'ImageHeight'): Unable to enforce a carried dependence constraint (II = 127, distance = 1, offset = 1) between fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57) and fifo write operation ('layer33_out_write_ln57', firmware/nnet_utils/nnet_image_stream.h:57) on port 'layer33_out' (firmware/nnet_utils/nnet_image_stream.h:57). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 128, Depth = 128, loop 'ImageHeight' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.73 seconds. CPU system time: 0.04 seconds. Elapsed time: 1.78 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.14 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ConcatLoopHeight_ConcatLoopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'ConcatLoopHeight_ConcatLoopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_24u_config58_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config58_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config58_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer58_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer58_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer58_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer58_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config58_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer58_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer58_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer58_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer58_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config58_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer58_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer58_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer58_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer58_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config58_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer58_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer58_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer58_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer58_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config58_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer58_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer58_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer58_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer58_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config58_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer58_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer58_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer58_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer58_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config58_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer58_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer58_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer58_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer58_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config58_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer58_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer58_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer58_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer58_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config58_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer58_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer58_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer58_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer58_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.12 seconds. CPU system time: 0.04 seconds. Elapsed time: 1.16 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_24u_config58_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config58_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 24u>, config35>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 24u>, config35>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.28 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.29 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.58 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.62 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.2 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.22 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.21 seconds. CPU system time: 0 seconds. Elapsed time: 0.21 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.2 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config59_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadTopWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadTopWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config59_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadMain'. +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config59_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between fifo write operation ('layer59_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer59_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer59_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer59_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config59_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1) between fifo write operation ('layer59_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer59_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer59_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer59_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config59_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1) between fifo write operation ('layer59_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer59_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer59_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer59_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config59_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1) between fifo write operation ('layer59_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer59_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer59_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer59_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config59_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 35, distance = 1, offset = 1) between fifo write operation ('layer59_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer59_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer59_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer59_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config59_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 51, distance = 1, offset = 1) between fifo write operation ('layer59_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer59_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer59_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer59_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config59_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 59, distance = 1, offset = 1) between fifo write operation ('layer59_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer59_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer59_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer59_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config59_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 63, distance = 1, offset = 1) between fifo write operation ('layer59_out_write_ln26', firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) on port 'layer59_out' (firmware/nnet_utils/nnet_padding_stream.h:26->firmware/nnet_utils/nnet_padding_stream.h:66) and fifo write operation ('layer59_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer59_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +WARNING: [HLS 200-880] The II Violation in module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config59_Pipeline_PadMain' (loop 'PadMain'): Unable to enforce a carried dependence constraint (II = 65, distance = 1, offset = 1) between fifo write operation ('layer59_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) on port 'layer59_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:70) and fifo write operation ('layer59_out_write_ln15', firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62) on port 'layer59_out' (firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:62). +Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-880.html +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 66, Depth = 67, loop 'PadMain' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 1.12 seconds. CPU system time: 0.03 seconds. Elapsed time: 1.16 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_array_ap_fixed_8u_config59_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'PadBottomWidth'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'PadBottomWidth' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.16 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config59_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.12 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining function 'shift_line_buffer, 8u>, config37>'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, function 'shift_line_buffer, 8u>, config37>' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.18 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.2 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReuseLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'ReuseLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.31 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.32 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.12 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.14 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.12 seconds. CPU system time: 0 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReLUActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'ReLUActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.2 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config60_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'ReadInputHeightSerial_ReadInputWidthSerial'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 1, loop 'ReadInputHeightSerial_ReadInputWidthSerial' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'SigmoidActLoop'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 3, loop 'SigmoidActLoop' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.2 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.21 seconds; current allocated memory: 5.894 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 5.894 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'transpose_array_array_ap_fixed_1u_config42_Pipeline_VITIS_LOOP_45_1' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'VITIS_LOOP_45_1'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'VITIS_LOOP_45_1' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 267.76 seconds. CPU system time: 0.15 seconds. Elapsed time: 267.93 seconds; current allocated memory: 6.036 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 11.15 seconds. CPU system time: 0.08 seconds. Elapsed time: 11.23 seconds; current allocated memory: 6.036 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'transpose_array_array_ap_fixed_1u_config42_Pipeline_VITIS_LOOP_54_3' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-61] Pipelining loop 'VITIS_LOOP_54_3'. +INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'VITIS_LOOP_54_3' +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 11.13 seconds. CPU system time: 0.2 seconds. Elapsed time: 11.33 seconds; current allocated memory: 6.056 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.58 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.63 seconds; current allocated memory: 6.074 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'transpose_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config42_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 65.33 seconds. CPU system time: 0.1 seconds. Elapsed time: 65.43 seconds; current allocated memory: 6.122 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 7.78 seconds. CPU system time: 0.03 seconds. Elapsed time: 7.81 seconds; current allocated memory: 6.122 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-42] -- Implementing module 'myproject' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SCHED 204-11] Starting scheduling ... +INFO: [SCHED 204-11] Finished scheduling. +WARNING: [HLS 200-1020] Increasing the depth of FIFO start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0 (from clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0 to concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0) to 10 to improve performance and/or avoid deadlocks. +WARNING: [HLS 200-1020] Increasing the depth of FIFO start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0 (from clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_U0 to concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0) to 26 to improve performance and/or avoid deadlocks. +WARNING: [HLS 200-1020] Increasing the depth of FIFO start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0 (from clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0 to concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0) to 42 to improve performance and/or avoid deadlocks. +INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.83 seconds. CPU system time: 0.07 seconds. Elapsed time: 0.9 seconds; current allocated memory: 6.125 GB. +INFO: [BIND 205-100] Starting micro-architecture generation ... +INFO: [BIND 205-101] Performing variable lifetime analysis. +INFO: [BIND 205-101] Exploring resource sharing. +INFO: [BIND 205-101] Binding ... +INFO: [BIND 205-100] Finished micro-architecture generation. +INFO: [HLS 200-111] Finished Binding: CPU user time: 0.4 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.42 seconds; current allocated memory: 6.136 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'transpose_array_array_ap_fixed_1u_config41_Pipeline_VITIS_LOOP_45_1' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'transpose_array_array_ap_fixed_1u_config41_Pipeline_VITIS_LOOP_45_1'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.95 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.97 seconds; current allocated memory: 6.137 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'transpose_array_array_ap_fixed_1u_config41_Pipeline_VITIS_LOOP_54_3' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'transpose_array_array_ap_fixed_1u_config41_Pipeline_VITIS_LOOP_54_3' pipeline 'VITIS_LOOP_54_3' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'transpose_array_array_ap_fixed_1u_config41_Pipeline_VITIS_LOOP_54_3'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 6.138 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'transpose_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_1u_config41_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'transpose_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_1u_config41_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 6.139 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config46_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config46_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config46_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.13 seconds. CPU system time: 0 seconds. Elapsed time: 0.15 seconds; current allocated memory: 6.139 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config46_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config46_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config46_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 6.143 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_1u_config46_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_1u_config46_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_1u_config46_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 6.146 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config46_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config46_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.12 seconds; current allocated memory: 6.146 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_cud' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.17 seconds; current allocated memory: 6.147 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_outidx_ROM_AUTO_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_oudEe' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_w2_ROM_NP_BRAM_1R' to 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_w2eOg' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_37s_38_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_17_3_37_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_19_4_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_oudEe' using auto ROMs. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_w2eOg' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.29 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.35 seconds; current allocated memory: 6.151 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_7' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.42 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.47 seconds; current allocated memory: 6.153 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 6.153 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.12 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.13 seconds; current allocated memory: 6.153 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 6.156 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.19 seconds; current allocated memory: 6.159 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 6.162 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config47_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config47_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.1 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 6.162 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1375_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_fYi' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1383_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_g8j' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1376_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_hbi' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1384_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_ibs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1377_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_jbC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1385_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_kbM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1378_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_lbW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1386_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_mb6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1379_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_ncg' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1387_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_ocq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1380_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_pcA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1388_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_qcK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1381_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_rcU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1389_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_sc4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1382_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_tde' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1390_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_p_ZZN4nnet26conv_2d_udo' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.46 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.52 seconds; current allocated memory: 6.166 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_w4_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_w4_ROMvdy' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_38s_38_1_1': 7 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_8s_30s_30_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_w4_ROMvdy' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.33 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.37 seconds; current allocated memory: 6.170 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_13' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.89 seconds. CPU system time: 0.19 seconds. Elapsed time: 2.08 seconds; current allocated memory: 6.180 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.17 seconds; current allocated memory: 6.182 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.14 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.16 seconds; current allocated memory: 6.184 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.13 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.14 seconds; current allocated memory: 6.184 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stwdI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stxdS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_styd2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stzec' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stAem' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stBew' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stCeG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_void_pooling2d_cl_stDeQ' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.29 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.33 seconds; current allocated memory: 6.186 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'sY' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX' is power-on initialization. +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s' pipeline 'ReadInputHeight_ReadInputWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.97 seconds. CPU system time: 0.11 seconds. Elapsed time: 1.08 seconds; current allocated memory: 6.189 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.21 seconds; current allocated memory: 6.192 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 6.195 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0 seconds. Elapsed time: 0.18 seconds; current allocated memory: 6.198 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config48_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config48_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.11 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.13 seconds; current allocated memory: 6.198 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1359_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Ee0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1367_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Ffa' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1360_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Gfk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1368_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Hfu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1361_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_IfE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1369_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_JfO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1362_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_KfY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1370_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Lf8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1363_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Mgi' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1371_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Ngs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1364_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_OgC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1372_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_PgM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1365_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_QgW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1373_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Rg6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1366_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Shg' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1374_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_p_ZZN4nnet26conv_2d_Thq' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.5 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.53 seconds; current allocated memory: 6.200 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_w7_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_w7_ROMUhA' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_38s_38_1_1': 15 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_w7_ROMUhA' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.35 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.39 seconds; current allocated memory: 6.206 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_38' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_30' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_39' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_31' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_32' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_33' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_34' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_35' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_36' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_37' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_15' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 2.01 seconds. CPU system time: 0.17 seconds. Elapsed time: 2.18 seconds; current allocated memory: 6.216 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.17 seconds; current allocated memory: 6.219 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.14 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.16 seconds; current allocated memory: 6.220 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config49_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config49_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config49_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.18 seconds; current allocated memory: 6.222 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config49_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config49_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config49_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.18 seconds; current allocated memory: 6.224 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config49_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config49_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config49_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 6.228 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config49_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config49_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.13 seconds. CPU system time: 0 seconds. Elapsed time: 0.13 seconds; current allocated memory: 6.228 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_799_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dVhK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_815_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dWhU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_800_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dXh4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_816_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dYie' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_807_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dZio' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_823_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d0iy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_808_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d1iI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_824_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d2iS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_809_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d3i2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_825_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d4jc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_810_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d5jm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_826_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d6jw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_811_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d7jG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_827_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d8jQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_812_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d9j0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_828_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbak' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_813_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbbk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_829_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbck' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_814_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbdk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_830_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbek' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_801_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbfk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_817_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbgk' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_802_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbhl' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_818_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbil' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_803_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbjl' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_819_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbkl' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_804_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbll' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_820_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbml' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_805_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbnm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_821_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbom' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_806_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbpm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_822_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_p_ZZN4nnet26conv_2dbqm' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.89 seconds. CPU system time: 0.1 seconds. Elapsed time: 0.98 seconds; current allocated memory: 6.230 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbrm' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 15 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 16 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 2 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbrm' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.49 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.53 seconds; current allocated memory: 6.242 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4177' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4178' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4179' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4180' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4181' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4182' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4183' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4184' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4185' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4186' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4188' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4122' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4189' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4134' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4190' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4191' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4192' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4137' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4123' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4124' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4125' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4126' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4127' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4128' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4129' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4130' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4131' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4133' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4135' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4136' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_9' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 3.81 seconds. CPU system time: 0.46 seconds. Elapsed time: 4.27 seconds; current allocated memory: 6.261 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.2 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.21 seconds; current allocated memory: 6.265 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.15 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.17 seconds; current allocated memory: 6.267 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0 seconds. Elapsed time: 0.16 seconds; current allocated memory: 6.268 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bsm' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_btn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bun' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bvn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bwn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bxn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_byn' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bzo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bAo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bBo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_27_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbCo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_26_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbDo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_25_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbEo' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_24_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbFp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_23_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbGp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_22_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_p_ZZN4nnet12poolinbHp' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.54 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.58 seconds; current allocated memory: 6.272 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'sY_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_11' is power-on initialization. +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s' pipeline 'ReadInputHeight_ReadInputWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.82 seconds. CPU system time: 0.25 seconds. Elapsed time: 2.07 seconds; current allocated memory: 6.276 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config50_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config50_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config50_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.25 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.27 seconds; current allocated memory: 6.282 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config50_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config50_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config50_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 6.285 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config50_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config50_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config50_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 6.285 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config50_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config50_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.14 seconds; current allocated memory: 6.286 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_863_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bIp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_879_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bJp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_864_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_880_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bLp' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_871_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bMq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_887_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bNq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_872_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bOq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_888_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bPq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_873_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bQq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_889_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bRq' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_874_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bSr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_890_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bTr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_875_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bUr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_891_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bVr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_876_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bWr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_892_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bXr' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_877_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bYs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_893_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bZs' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_878_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b0s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_894_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b1s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_865_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b2s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_881_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b3s' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_866_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b4t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_882_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b5t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_867_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b6t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_883_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b7t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_868_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b8t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_884_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2b9t' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_869_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2cau' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_885_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2cbu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_870_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2ccu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_886_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2cdu' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.97 seconds. CPU system time: 0.07 seconds. Elapsed time: 1.04 seconds; current allocated memory: 6.289 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s_w12_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s_w12_Rceu' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 31 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 32 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 2 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s_w12_Rceu' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.56 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.6 seconds; current allocated memory: 6.305 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4416' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4428' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4441' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4453' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4465' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4432' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4433' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4434' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4435' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4436' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4417' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4437' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4419' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4438' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4420' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4439' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4421' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4442' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4422' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4443' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4423' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4444' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4424' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4445' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4425' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4446' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4426' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4447' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4427' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4448' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4430' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4449' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4431' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4450' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4452' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4454' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4455' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4456' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4457' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4458' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4459' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4460' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4461' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4463' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4464' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4466' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4467' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4468' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4469' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_8' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.15 seconds. CPU system time: 0.46 seconds. Elapsed time: 4.62 seconds; current allocated memory: 6.328 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.21 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.24 seconds; current allocated memory: 6.332 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.21 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.24 seconds; current allocated memory: 6.334 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config51_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config51_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config51_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.22 seconds; current allocated memory: 6.338 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config51_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config51_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config51_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 6.339 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config51_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config51_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config51_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.19 seconds; current allocated memory: 6.340 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config51_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config51_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.13 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.15 seconds; current allocated memory: 6.341 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_943_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cfu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_975_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cgu' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_944_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2chv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_976_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2civ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_955_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cjv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_987_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2ckv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_966_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2clv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_998_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cmv' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_969_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cnw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1001_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cow' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_970_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cpw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1002_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cqw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_971_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2crw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1003_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2csw' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_972_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2ctx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1004_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cux' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_973_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cvx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1005_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cwx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_974_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cxx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1006_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cyx' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_945_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2czy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_977_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cAy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_946_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cBy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_978_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cCy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_947_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cDy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_979_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cEy' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_948_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cFz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_980_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cGz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_949_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cHz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_981_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cIz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_950_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cJz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_982_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cKz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_951_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cLz' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_983_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cMA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_952_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cNA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_984_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cOA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_953_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cPA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_985_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cQA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_954_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cRA' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_986_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cSB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_956_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cTB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_988_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cUB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_957_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cVB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_989_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cWB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_958_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cXB' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_990_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cYC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_959_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2cZC' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_991_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c0C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_960_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c1C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_992_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c2C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_961_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c3C' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_993_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c4D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_962_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c5D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_994_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c6D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_963_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c7D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_995_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c8D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_964_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2c9D' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_996_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2daE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_965_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dbE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_997_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dcE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_967_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2ddE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_999_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2deE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_968_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dfE' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1000_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_p_ZZN4nnet26conv_2dgE' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.85 seconds. CPU system time: 0.19 seconds. Elapsed time: 2.05 seconds; current allocated memory: 6.347 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s_w14_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s_w14_RdhF' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s' is 9216 from HDL expression: (do_init_reg_1345 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 63 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 64 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 4 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s_w14_RdhF' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.83 seconds. CPU system time: 0.08 seconds. Elapsed time: 0.92 seconds; current allocated memory: 6.376 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5021' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_89' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5022' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_88' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5024' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_87' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5025' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_86' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5026' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_85' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5027' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_84' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5028' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_83' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5029' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_82' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5030' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_81' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5031' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_80' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5032' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5033' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5035' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5036' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5037' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4839' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5038' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4851' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5039' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4863' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5040' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4875' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5041' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4887' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5042' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4899' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5043' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4911' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5044' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4923' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5046' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4936' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5047' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4948' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5048' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4960' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5049' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4972' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5050' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4984' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5051' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4996' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5052' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5008' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5053' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5018' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5054' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5019' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5055' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5020' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5092' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5093' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5094' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5095' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4840' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4841' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4842' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4843' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4844' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4845' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4846' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4848' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4849' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4850' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4852' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4853' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4854' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4855' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4856' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4857' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4859' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4860' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4861' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4862' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4941' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4903' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4942' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4904' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4943' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4905' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4944' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4906' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4945' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4907' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4947' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4908' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4949' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4909' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4950' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4910' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4951' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4912' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4952' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4914' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4953' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4915' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4954' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4916' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4955' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4917' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4956' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4918' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4958' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4919' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4959' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4920' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4961' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4921' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4962' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4922' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4963' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4925' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4964' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4926' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4965' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4927' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4966' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4928' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4967' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4929' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4969' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4930' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4970' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4931' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4971' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4932' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4973' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4933' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4974' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4934' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4975' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4937' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4976' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4938' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4977' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4939' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4978' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4940' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5057' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5058' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5059' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5060' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5061' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5062' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5063' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5064' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5065' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5066' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5068' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5069' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5070' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5071' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5072' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5073' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5074' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5075' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5076' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5077' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5079' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5080' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5081' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5082' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5083' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5084' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5085' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5086' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5087' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5088' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5090' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5091' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4864' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4865' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4866' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4867' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4868' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4870' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4871' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4872' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4873' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4874' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4876' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4877' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4878' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4879' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4881' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4882' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4883' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4884' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4885' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4886' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4888' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4889' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4890' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4892' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4893' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4894' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4895' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4896' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4897' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4898' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4900' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4901' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4980' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4981' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4982' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4983' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4985' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4986' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4987' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4988' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4989' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4991' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4992' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4993' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4994' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4995' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4997' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4998' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5000' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5002' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5003' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5004' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5005' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5006' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5007' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5009' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5010' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5011' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5013' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5014' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5015' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5016' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5017' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_5' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 8.58 seconds. CPU system time: 0.95 seconds. Elapsed time: 9.53 seconds; current allocated memory: 6.419 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.29 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.3 seconds; current allocated memory: 6.424 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.27 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.27 seconds; current allocated memory: 6.427 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.2 seconds; current allocated memory: 6.431 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_diF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_djF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dkF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dlF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dmF' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dnG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_doG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dpG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_dqG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_void_pooling2d_cl_drG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_21_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindsG' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_20_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindtH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_19_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolinduH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_18_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindvH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_17_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindwH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_16_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindxH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_15_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindyH' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_14_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindzI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_13_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindAI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_12_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindBI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_11_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindCI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_10_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindDI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindEI' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindFJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindGJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindHJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindIJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindJJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindKJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindLJ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindMK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_p_ZZN4nnet12poolindNK' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.07 seconds. CPU system time: 0.1 seconds. Elapsed time: 1.16 seconds; current allocated memory: 6.434 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'sY_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_89' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_57' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_88' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_56' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_87' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_55' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_86' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_54' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_85' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_53' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_84' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_52' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_83' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_51' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_82' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_50' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_81' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_49' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_80' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_48' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_79' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_47' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_78' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_46' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_77' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_45' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_76' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_44' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_75' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_43' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_74' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_42' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_73' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_41' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_72' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_40' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_71' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_39' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_70' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_38' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_69' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_37' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_68' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_36' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_99' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_67' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_35' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_98' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_66' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_34' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_97' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_65' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_33' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_96' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_64' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_32' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_95' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_63' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_31' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_94' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_62' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_30' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_93' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_61' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_92' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_60' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_91' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_59' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_90' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_58' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_3' is power-on initialization. +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s' pipeline 'ReadInputHeight_ReadInputWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.08 seconds. CPU system time: 0.38 seconds. Elapsed time: 4.47 seconds; current allocated memory: 6.445 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config52_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config52_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config52_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.36 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.38 seconds; current allocated memory: 6.455 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.21 seconds; current allocated memory: 6.456 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config52_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config52_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config52_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.21 seconds; current allocated memory: 6.459 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.16 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.18 seconds; current allocated memory: 6.459 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1071_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dOK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1103_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dPK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1072_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dQK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1104_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dRK' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1083_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dSL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1115_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dTL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1094_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dUL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1126_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dVL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1097_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dWL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1129_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dXL' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1098_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dYM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1130_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dZM' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1099_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d0M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1131_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d1M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1100_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d2M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1132_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d3M' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1101_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d4N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1133_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d5N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1102_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d6N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1134_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d7N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1073_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d8N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1105_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d9N' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1074_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eaO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1106_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ebO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1075_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ecO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1107_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2edO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1076_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eeO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1108_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2efO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1077_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2egO' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1109_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ehP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1078_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eiP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1110_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ejP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1079_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ekP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1111_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2elP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1080_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2emP' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1112_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2enQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1081_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eoQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1113_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2epQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1082_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eqQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1114_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2erQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1084_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2esQ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1116_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2etR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1085_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2euR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1117_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2evR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1086_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ewR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1118_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2exR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1087_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eyR' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1119_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ezS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1088_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eAS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1120_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eBS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1089_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eCS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1121_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eDS' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1090_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eES' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1122_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eFT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1091_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eGT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1123_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eHT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1092_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eIT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1124_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eJT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1093_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eKT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1125_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eLT' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1095_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eMU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1127_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eNU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1096_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2eOU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1128_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2ePU' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 2.07 seconds. CPU system time: 0.2 seconds. Elapsed time: 2.27 seconds; current allocated memory: 6.465 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s_w17_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s_w17_ReQU' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s' is 9216 from HDL expression: (do_init_reg_1923 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 127 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 128 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 4 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s_w17_ReQU' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.16 seconds. CPU system time: 0.06 seconds. Elapsed time: 1.22 seconds; current allocated memory: 6.507 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_69' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_68' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_67' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_66' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_65' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_64' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_63' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_62' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_61' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_60' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5402' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5414' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5426' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5438' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5450' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5462' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5436' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5437' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5439' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5440' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5442' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5403' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5443' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5404' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5444' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5405' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5445' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5406' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5446' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5407' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5447' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5409' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5448' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5410' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5449' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5411' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5451' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5412' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5453' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5413' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5454' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5415' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5455' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5416' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5456' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5417' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5457' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5418' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5458' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5420' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5459' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5421' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5460' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5422' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5461' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5423' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5464' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5424' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5465' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5425' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5466' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5427' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5467' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5428' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5468' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5429' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5469' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5431' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5432' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5433' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5434' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5435' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_10' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 9.77 seconds. CPU system time: 1.03 seconds. Elapsed time: 10.82 seconds; current allocated memory: 6.567 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.35 seconds; current allocated memory: 6.572 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.33 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.35 seconds; current allocated memory: 6.577 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_64u_config53_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_64u_config53_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_64u_config53_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.3 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.32 seconds; current allocated memory: 6.583 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.21 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.23 seconds; current allocated memory: 6.585 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_64u_config53_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_64u_config53_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_64u_config53_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.22 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.22 seconds; current allocated memory: 6.586 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.19 seconds; current allocated memory: 6.587 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1231_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eRU' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1295_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eSV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1232_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eTV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1296_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eUV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1243_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eVV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1307_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eWV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1254_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eXV' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1318_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eYW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1265_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2eZW' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1329_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e0W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1276_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e1W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1340_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e2W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1287_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e3W' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1351_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e4X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1292_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e5X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1356_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e6X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1293_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e7X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1357_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e8X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1294_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2e9X' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1358_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2faY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1233_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fbY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1297_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fcY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1234_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fdY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1298_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2feY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1235_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ffY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1299_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fgY' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1236_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fhZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1300_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fiZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1237_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fjZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1301_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fkZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1238_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2flZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1302_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fmZ' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1239_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fn0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1303_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fo0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1240_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fp0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1304_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fq0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1241_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fr0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1305_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fs0' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1242_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ft1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1306_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fu1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1244_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fv1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1308_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fw1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1245_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fx1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1309_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fy1' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1246_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fz2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1310_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fA2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1247_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fB2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1311_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fC2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1248_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fD2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1312_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fE2' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1249_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fF3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1313_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fG3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1250_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fH3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1314_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fI3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1251_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fJ3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1315_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fK3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1252_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fL3' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1316_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fM4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1253_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fN4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1317_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fO4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1255_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fP4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1319_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fQ4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1256_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fR4' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1320_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fS5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1257_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fT5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1321_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fU5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1258_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fV5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1322_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fW5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1259_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fX5' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1323_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fY6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1260_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2fZ6' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1324_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f06' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1261_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f16' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1325_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f26' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1262_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f36' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1326_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f47' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1263_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f57' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1327_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f67' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1264_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f77' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1328_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f87' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1266_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2f97' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1330_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ga8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1267_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gb8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1331_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gc8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1268_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gd8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1332_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2ge8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1269_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gf8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1333_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gg8' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1270_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gh9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1334_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gi9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1271_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gj9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1335_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gk9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1272_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gl9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1336_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gm9' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1273_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1337_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1274_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1338_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1275_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2grb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1339_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1277_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gtb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1341_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1278_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1342_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1279_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1343_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1280_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1344_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gAb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1281_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gBb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1345_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gCb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1282_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gDb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1346_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gEb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1283_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gFb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1347_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gGb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1284_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gHb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1348_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gIb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1285_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gJb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1349_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gKb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1286_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gLb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1350_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gMb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1288_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1352_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1289_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1353_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1290_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1354_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1291_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1355_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_p_ZZN4nnet26conv_2gUb_x' due to conflict. +INFO: [RTGEN 206-104] Estimated max fanout for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s' is 9216 from HDL expression: (1'b1 == ap_CS_fsm_state1) +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.55 seconds. CPU system time: 0.47 seconds. Elapsed time: 5.02 seconds; current allocated memory: 6.598 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s_w19_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s_w19_RgVb' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s' is 18432 from HDL expression: (do_init_reg_3761 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 256 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_33s_33_1_1': 63 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 256 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_129_6_16_1_1': 9 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config19_mult_s_w19_RgVb' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 2.34 seconds. CPU system time: 0.14 seconds. Elapsed time: 2.49 seconds; current allocated memory: 6.677 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_49' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_48' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_47' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_46' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_45' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_44' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_43' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_42' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_41' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_40' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6184' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6293' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6305' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6317' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6329' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6341' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6353' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6366' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6378' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6390' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6402' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6414' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6426' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6438' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6450' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6462' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6487' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6499' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6511' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6523' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6177' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6535' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6179' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6547' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6180' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6181' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6182' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6183' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6185' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6186' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6187' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6188' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6190' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6191' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6192' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6361' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6362' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6363' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6364' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6287' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6367' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6289' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6368' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6290' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6369' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6291' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6370' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6292' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6371' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6294' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6372' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6295' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6373' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6296' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6374' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6297' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6375' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6298' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6377' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6300' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6379' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6301' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6380' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6302' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6381' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6303' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6382' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6304' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6383' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6306' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6384' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6307' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6385' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6308' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6386' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6309' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6388' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6311' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6389' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6312' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6391' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6313' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6392' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6314' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6393' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6315' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6394' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6316' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6395' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6318' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6396' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6319' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6397' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6320' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6399' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6322' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6400' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6323' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6401' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6324' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6403' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6325' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6404' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6326' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6405' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6327' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6406' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6328' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6407' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6330' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6408' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6331' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6410' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6333' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6411' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6334' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6412' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6335' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6413' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6336' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6415' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6337' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6416' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6338' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6417' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6339' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6418' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6340' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6419' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6342' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6421' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6344' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6422' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6345' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6423' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6346' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6424' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6347' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6425' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6348' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6427' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6349' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6428' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6350' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6429' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6351' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6430' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6352' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6432' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6355' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6433' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6356' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6434' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6357' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6435' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6358' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6436' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6359' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6437' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6360' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6516' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6520' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6521' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6522' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6524' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6525' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6526' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6527' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6531' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6532' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6533' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6534' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6536' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6537' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6538' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6542' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6543' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6544' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6545' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6546' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6548' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6549' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6439' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6440' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6441' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6443' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6444' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6445' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6446' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6447' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6448' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6449' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6451' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6452' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6454' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6455' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6456' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6457' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6458' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6459' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6460' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6461' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6463' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6465' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6466' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6467' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6468' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6469' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6470' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6471' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6472' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6476' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6477' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6478' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6479' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6480' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6481' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6482' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6483' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6488' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6489' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6490' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6491' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6492' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6493' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6494' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6498' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6500' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6501' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6502' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6503' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6504' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6505' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6509' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6510' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6512' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6513' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6514' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6515' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_16' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 21.73 seconds. CPU system time: 2.09 seconds. Elapsed time: 23.85 seconds; current allocated memory: 6.802 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.48 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.52 seconds; current allocated memory: 6.813 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.42 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.46 seconds; current allocated memory: 6.823 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.31 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.33 seconds; current allocated memory: 6.828 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' pipeline 'ConcatLoopHeight_ConcatLoopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.24 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.28 seconds; current allocated memory: 6.835 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.19 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.22 seconds; current allocated memory: 6.837 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_96u_config54_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_96u_config54_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_96u_config54_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.23 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.26 seconds; current allocated memory: 6.838 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.25 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.27 seconds; current allocated memory: 6.838 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_96u_config54_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_96u_config54_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_96u_config54_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.26 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.28 seconds; current allocated memory: 6.840 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.21 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.22 seconds; current allocated memory: 6.841 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1407_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2gWb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_95_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2gXb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1408_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2gYb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_94_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2gZb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1419_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_83_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1430_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_72_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1441_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_61_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1452_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_50_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1463_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_39_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2g9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1474_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_28_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1485_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_17_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1496_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2heb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_6_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1409_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_93_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1410_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_92_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1411_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_91_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hlb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1412_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_90_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1413_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_89_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1414_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_88_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1415_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_87_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2htb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1416_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_86_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1417_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_85_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1418_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_84_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1420_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_82_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1421_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_81_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1422_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_80_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1423_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_79_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1424_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_78_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1425_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_77_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1426_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_76_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1427_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_75_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1428_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_74_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1429_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_73_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1431_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_71_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1432_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_70_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1433_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_69_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2hZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1434_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_68_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1435_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_67_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1436_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_66_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1437_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_65_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1438_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_64_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2h9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1439_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_63_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ibb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1440_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2icb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_62_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2idb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1442_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ieb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_60_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ifb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1443_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2igb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_59_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ihb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1444_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_58_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ijb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1445_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ikb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_57_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ilb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1446_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2imb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_56_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2inb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1447_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_55_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ipb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1448_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_54_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2irb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1449_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2isb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_53_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2itb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1450_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_52_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ivb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1451_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_51_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2ixb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1453_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_49_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2izb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1454_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_48_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1455_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_47_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1456_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_46_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1457_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_45_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1458_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_44_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1459_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_43_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1460_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_42_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1461_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_41_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1462_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_40_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1464_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_38_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1465_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_37_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1466_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_36_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1467_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_35_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2iZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1468_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_34_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1469_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_33_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1470_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_32_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1471_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_31_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1472_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_30_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2i9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1473_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_29_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1475_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_27_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1476_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jeb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_26_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1477_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_25_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1478_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_24_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1479_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_23_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jlb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1480_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_22_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1481_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2job' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_21_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1482_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_20_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1483_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_19_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jtb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1484_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_18_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1486_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_16_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1487_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_15_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1488_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_14_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1489_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_13_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1490_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_12_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1491_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_11_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1492_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_10_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1493_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_9_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1494_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_8_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1495_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_7_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1497_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_5_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1498_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_4_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_99_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_3_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_98_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_2_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_97_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2jZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_96_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_p_ZZN4nnet26conv_2j1b' due to the length limit 80 +INFO: [RTGEN 206-104] Estimated max fanout for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s' is 13824 from HDL expression: (1'b1 == ap_CS_fsm_state1) +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 10.09 seconds. CPU system time: 1.01 seconds. Elapsed time: 11.12 seconds; current allocated memory: 6.850 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_w23_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_w23_Rj2b' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s' is 27648 from HDL expression: (do_init_reg_3523 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 128 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_33s_33_1_1': 127 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 128 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 12 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_w23_Rj2b' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 2.38 seconds. CPU system time: 0.13 seconds. Elapsed time: 2.51 seconds; current allocated memory: 6.929 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_3' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3846' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3857' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3868' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3879' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3890' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3901' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3912' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3923' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3934' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3945' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3956' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3967' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3978' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3989' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4000' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4011' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4022' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4033' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4044' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4055' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4066' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4077' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4088' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4099' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4110' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4121' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4363' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4484' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4847' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4968' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5089' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5210' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5331' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5452' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5936' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6057' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6178' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6299' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6420' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6541' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_94' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_83' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_72' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_61' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_50' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_39' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_17' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_10' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_9' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_8' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_7' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3928' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3929' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3930' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3931' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3932' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3933' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3935' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3936' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3937' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3938' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3939' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3940' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3941' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3942' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3943' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3944' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3839' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3946' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3840' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3947' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3841' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3948' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3842' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3949' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3843' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3950' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3844' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3951' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3845' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3952' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3847' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3953' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3848' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3954' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3849' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3955' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3850' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3957' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3851' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3958' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3852' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3959' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3853' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3960' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3854' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3961' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3855' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3962' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3856' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3963' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3858' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3964' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3859' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3965' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3860' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3966' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3861' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3968' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3862' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3969' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3863' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3970' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3864' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3971' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3865' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3972' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3866' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3973' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3867' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3974' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3869' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3975' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3870' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3976' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3871' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3977' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3872' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3979' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3873' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3980' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3874' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3981' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3875' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3982' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3876' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3983' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3877' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3984' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3878' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3985' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3880' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3986' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3881' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3987' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3882' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3988' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3883' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3990' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3884' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3991' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3885' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3992' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3886' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3993' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3887' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3994' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3888' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3995' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3889' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3996' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3891' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3997' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3892' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3998' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3893' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3894' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4001' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3895' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4002' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3896' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4003' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3897' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4004' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3898' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4005' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3899' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4006' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3900' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4007' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3902' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4008' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3903' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4009' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3904' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4010' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3905' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4012' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3906' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4013' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3907' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4014' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3908' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4015' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3909' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4016' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3910' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4017' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3911' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4018' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3913' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4019' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3914' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4020' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3915' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4021' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3916' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4023' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3917' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4024' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3918' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4025' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3919' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4026' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3920' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4027' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3921' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4028' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3922' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4029' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3924' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4030' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3925' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4031' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3926' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4032' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3927' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5485' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4319' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5496' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4330' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5507' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4341' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5518' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4352' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5529' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4374' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5540' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4385' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5551' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4396' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4407' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4418' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4429' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4440' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4451' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4462' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4473' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4495' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4506' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4517' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4528' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4539' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4550' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4616' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4627' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4638' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4649' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5826' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4660' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5837' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4671' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5848' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4682' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5859' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4693' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5870' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4704' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5881' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5892' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5903' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5914' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5925' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5947' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5958' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5969' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5980' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5991' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6002' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6013' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4858' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6024' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4869' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6035' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4880' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6046' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4891' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6068' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4902' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6079' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4913' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6090' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4924' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6101' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4935' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6112' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4946' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6123' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4957' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6134' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4979' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4990' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5001' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5012' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6189' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5023' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5034' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5045' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5056' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5067' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5078' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5100' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5111' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5122' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6288' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5133' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6310' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6321' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6332' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6343' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5177' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6354' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5188' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6365' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5199' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6376' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5221' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6387' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5232' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6398' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5243' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6409' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5254' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6431' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5265' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6442' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6453' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5287' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6464' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5298' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6475' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5309' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6486' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5320' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6497' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5342' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6508' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5353' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6519' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5364' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6530' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5375' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6552' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5386' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5397' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5408' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5419' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5430' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5441' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5463' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5474' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3793' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3804' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3815' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4034' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4035' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4036' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4037' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4038' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4039' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4040' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4041' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4042' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4043' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4045' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4046' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4047' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4048' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4049' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4050' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4051' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4052' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4053' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4054' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4056' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4057' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4058' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4059' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4060' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4061' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4062' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4063' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4064' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4065' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4067' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4068' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4069' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4070' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4071' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4072' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4073' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4074' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4075' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4076' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4078' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4079' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4080' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4081' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4082' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4083' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4084' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4085' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4086' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4087' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4089' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4090' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4091' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4092' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4093' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4094' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4095' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4096' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4097' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4098' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4100' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4101' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4102' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4103' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4104' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4105' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4106' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4107' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4108' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4109' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4111' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4112' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4113' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4114' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4115' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4116' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4117' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4118' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4119' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4120' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4132' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4187' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4297' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4308' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_99' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_98' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_97' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_96' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_95' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_93' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_92' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_91' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_90' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_89' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_88' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_87' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_86' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_85' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_84' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_82' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_81' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_80' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_79' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_78' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_77' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_76' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_75' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_74' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_73' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_71' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_70' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_69' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_68' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_67' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_66' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_65' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_64' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_63' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_62' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_60' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_59' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_58' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_57' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_56' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_55' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_54' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_53' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_52' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_51' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_49' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_48' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_47' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_46' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_45' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_44' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_43' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_42' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_41' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_40' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_38' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_37' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_36' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_35' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_34' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_33' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_32' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_31' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_30' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_19' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_18' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_16' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_12' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_12' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 36.13 seconds. CPU system time: 3.64 seconds. Elapsed time: 39.8 seconds; current allocated memory: 7.065 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.63 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.68 seconds; current allocated memory: 7.083 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.48 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.53 seconds; current allocated memory: 7.096 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config55_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config55_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config55_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.3 seconds. CPU system time: 0.06 seconds. Elapsed time: 0.37 seconds; current allocated memory: 7.102 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config55_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config55_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config55_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.32 seconds; current allocated memory: 7.105 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_32u_config55_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_32u_config55_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_32u_config55_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.31 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.33 seconds; current allocated memory: 7.107 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config55_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config55_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.25 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.28 seconds; current allocated memory: 7.108 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1007_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1039_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1008_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1040_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1019_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1051_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1030_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2j9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1062_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1033_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1065_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1034_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1066_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2keb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1035_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1067_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1036_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2khb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1068_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1037_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1069_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1038_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2klb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1070_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1009_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2knb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1041_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1010_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1042_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1011_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2krb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1043_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2ksb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1012_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2ktb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1044_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1013_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1045_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1014_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1046_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1015_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1047_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1016_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1048_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1017_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1049_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1018_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1050_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1020_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1052_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1021_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1053_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1022_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1054_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1023_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1055_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1024_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1056_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1025_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1057_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1026_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1058_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1027_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1059_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1028_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1060_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1029_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2kZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1061_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1031_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1063_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1032_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1064_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_p_ZZN4nnet26conv_2k4b' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.06 seconds. CPU system time: 0.35 seconds. Elapsed time: 4.42 seconds; current allocated memory: 7.109 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s_w25_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s_w25_Rk5b' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s' is 9216 from HDL expression: (do_init_reg_1343 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 63 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 64 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 4 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config25_mult_s_w25_Rk5b' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.09 seconds. CPU system time: 0.08 seconds. Elapsed time: 1.17 seconds; current allocated memory: 7.125 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5327' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_79' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5328' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_78' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5329' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_77' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5330' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_76' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5332' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_75' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5333' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_74' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5334' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_73' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5335' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_72' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5336' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_71' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5337' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_70' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5338' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5096' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5339' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5108' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5340' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5120' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5341' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5132' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5343' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5344' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5345' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5346' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5181' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5347' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5193' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5348' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5205' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5349' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5217' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5350' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5229' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5351' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5241' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5352' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5253' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5354' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5266' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5355' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5356' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5290' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5357' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5302' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5358' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5314' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5359' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5324' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5360' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5325' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5361' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5326' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5130' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5398' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5131' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5399' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5134' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5400' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5135' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5401' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5136' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5097' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5137' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5098' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5099' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5101' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5102' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5103' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5104' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5105' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5106' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5107' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5109' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5110' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5112' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5113' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5114' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5115' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5116' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5156' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5117' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5118' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5119' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5121' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5123' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5124' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5125' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5126' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5127' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5167' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5128' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5129' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5247' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5208' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5248' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5209' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5249' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5211' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5250' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5212' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5251' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5213' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5252' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5214' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5255' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5215' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5256' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5216' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5257' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5218' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5258' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5219' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5259' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5220' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5260' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5222' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5261' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5223' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5262' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5224' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5263' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5225' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5264' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5226' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5267' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5227' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5268' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5228' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5230' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5231' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5233' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5234' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5235' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5236' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5275' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5237' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5238' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5239' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5240' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5242' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5244' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5245' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5246' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5362' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5363' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5365' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5366' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5367' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5368' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5369' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5370' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5371' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5372' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5373' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5374' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5376' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5377' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5378' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5379' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5380' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5381' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5382' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5383' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5384' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5385' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5387' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5388' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5389' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5390' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5391' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5392' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5393' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5394' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5395' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5396' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5172' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5173' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5174' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5175' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5176' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5178' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5179' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5180' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5182' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5183' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5184' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5185' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5186' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5187' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5189' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5190' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5191' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5192' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5194' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5195' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5196' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5197' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5198' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5200' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5201' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5202' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5203' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5204' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5206' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5207' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5286' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5288' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5289' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5291' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5292' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5293' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5294' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5295' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5296' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5297' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5299' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5300' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5301' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5303' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5304' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5305' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5306' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5307' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5308' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5310' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5311' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5312' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5313' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5315' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5316' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5317' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5318' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5319' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5321' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5322' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5323' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_4' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_4' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 13.23 seconds. CPU system time: 1.36 seconds. Elapsed time: 14.6 seconds; current allocated memory: 7.164 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.4 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.45 seconds; current allocated memory: 7.174 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.4 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.43 seconds; current allocated memory: 7.194 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.33 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.36 seconds; current allocated memory: 7.198 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' pipeline 'ConcatLoopHeight_ConcatLoopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.34 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.37 seconds; current allocated memory: 7.203 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.27 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.29 seconds; current allocated memory: 7.205 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_48u_config56_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_48u_config56_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_48u_config56_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.3 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.33 seconds; current allocated memory: 7.205 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.36 seconds; current allocated memory: 7.206 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_48u_config56_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_48u_config56_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_48u_config56_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.33 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.36 seconds; current allocated memory: 7.208 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.26 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.29 seconds; current allocated memory: 7.210 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1135_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2k6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1183_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2k7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1136_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2k8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1184_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2k9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1147_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1195_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1158_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1206_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2ldb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1169_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2leb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1217_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1178_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1226_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1179_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1227_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2ljb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1180_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1228_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2llb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1181_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1229_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1182_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1230_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1137_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1185_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1138_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lsb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1186_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2ltb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1139_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1187_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1140_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1188_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1141_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lyb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1189_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lzb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1142_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lAb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lAb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lAb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1190_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lBb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lBb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lBb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1143_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lCb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lCb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lCb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1191_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lDb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lDb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lDb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1144_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lEb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lEb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lEb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1192_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lFb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lFb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lFb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1145_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lGb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lGb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lGb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1193_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lHb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lHb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lHb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1146_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lIb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lIb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lIb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1194_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lJb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lJb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lJb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1148_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lKb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lKb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lKb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1196_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lLb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lLb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lLb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1149_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lMb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lMb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lMb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1197_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lNb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lNb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lNb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1150_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lOb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lOb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lOb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1198_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lPb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lPb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lPb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1151_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lQb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lQb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lQb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1199_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lRb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lRb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lRb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1152_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lSb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lSb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lSb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1200_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lTb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lTb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lTb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1153_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lUb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lUb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lUb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1201_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lVb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lVb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lVb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1154_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lWb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lWb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lWb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1202_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lXb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lXb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lXb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1155_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lYb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lYb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lYb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1203_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lZb' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lZb' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2lZb_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1156_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l0b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1204_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l1b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1157_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l2b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1205_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l3b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1159_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l4b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1207_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l5b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1160_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l6b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1208_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l7b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1161_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l8b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1209_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2l9b' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1162_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mab' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1210_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mbb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1163_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mcb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1211_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mdb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1164_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2meb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1212_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mfb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1165_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mgb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1213_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mhb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1166_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mib' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1214_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mjb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1167_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mkb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1215_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mlb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1168_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mmb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1216_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mnb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1170_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mob' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1218_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mpb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1171_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mqb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1219_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mrb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1172_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2msb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1220_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mtb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1173_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mub' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1221_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mvb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1174_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mwb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1222_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mxb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1175_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2myb' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1223_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mzc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1176_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mAc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1224_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mBc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1177_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mCc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1225_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_p_ZZN4nnet26conv_2mDc' due to the length limit 80 +INFO: [RTGEN 206-104] Estimated max fanout for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s' is 6912 from HDL expression: (1'b1 == ap_CS_fsm_state1) +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 5.75 seconds. CPU system time: 0.58 seconds. Elapsed time: 6.33 seconds; current allocated memory: 7.211 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_w29_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_w29_RmEc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' is 13824 from HDL expression: (do_init_reg_1475 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 32 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_33s_33_1_1': 31 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_8s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 32 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 6 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_w29_RmEc' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.34 seconds. CPU system time: 0.08 seconds. Elapsed time: 1.43 seconds; current allocated memory: 7.234 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6115' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_59' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6116' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_58' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6117' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_57' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6118' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_56' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6119' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_55' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6120' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_54' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6121' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_53' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6122' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_52' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6124' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_51' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6125' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_50' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6126' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6127' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6128' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6129' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6130' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6131' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6132' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6133' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5792' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6135' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5805' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6136' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5817' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6137' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5829' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5841' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5853' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5865' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5877' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5889' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5901' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5913' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5926' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5938' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6148' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5950' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6149' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5962' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6150' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5974' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6151' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5986' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6152' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5998' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6153' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6010' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6154' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6022' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6155' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6034' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6157' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6047' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6158' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6059' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6159' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6071' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6160' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6083' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6161' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6095' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6162' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6107' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6163' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6110' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6164' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6111' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6165' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6113' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6166' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6114' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5820' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5821' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5822' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5823' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5824' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5825' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5827' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5828' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5770' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5830' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5831' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5832' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5833' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5834' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5835' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5836' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5838' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5839' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5781' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5840' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5842' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5843' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5844' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5845' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5846' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5847' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5849' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5790' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5850' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5791' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5851' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5794' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5852' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5795' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5854' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5796' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5855' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5797' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5856' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5798' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5857' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5799' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5858' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5800' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5860' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5801' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5861' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5802' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5862' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5803' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5863' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5806' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5864' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5807' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5866' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5808' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5867' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5809' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5868' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5810' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5869' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5811' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5871' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5812' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5872' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5813' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5873' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5814' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5874' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5816' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5875' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5818' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5876' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5819' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5994' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5935' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5995' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5937' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5996' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5939' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5997' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5940' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5999' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5941' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6000' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5942' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6001' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5943' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6003' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5944' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6004' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5945' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6005' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5946' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6006' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5948' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6007' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5949' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6008' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5951' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6009' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5952' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6011' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5953' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6012' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5954' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6014' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5955' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6015' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5956' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6016' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5957' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6017' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5959' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6018' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5960' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6019' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5961' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6020' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5963' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6021' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5964' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6023' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5965' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6025' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5966' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6026' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5967' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6027' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5968' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6028' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5970' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6029' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5971' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6030' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5972' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6031' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5973' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6032' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5975' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6033' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5976' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6036' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5977' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6037' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5978' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6038' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5979' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6039' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5981' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6040' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5982' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6041' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5983' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6042' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5984' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6043' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5985' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6044' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5987' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6045' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5988' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6048' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5989' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6049' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5990' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6050' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5992' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6051' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5993' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6168' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6169' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6170' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6171' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5715' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5726' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5737' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5748' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5759' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5878' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5879' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5880' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5882' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5883' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5884' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5885' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5886' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5887' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5888' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5890' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5891' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5893' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5894' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5895' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5896' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5897' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5898' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5899' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5900' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5902' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5904' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5905' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5906' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5907' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5908' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5909' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5910' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5911' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5912' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5915' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5916' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5917' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5918' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5919' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5920' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5921' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5922' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5923' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5924' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5927' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5928' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5929' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5930' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5931' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5932' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5933' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5934' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6052' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6053' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6054' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6055' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6056' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6058' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6060' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6061' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6062' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6063' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6064' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6065' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6066' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6067' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6069' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6070' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6072' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6073' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6074' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6075' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6076' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6077' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6078' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6080' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6081' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6082' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6084' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6085' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6086' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6087' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6088' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6089' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6091' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6092' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6093' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6094' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6096' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6097' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6098' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6099' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6100' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6102' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6103' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6104' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6105' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6106' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6108' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6109' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_1' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_1' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 21.1 seconds. CPU system time: 2 seconds. Elapsed time: 23.12 seconds; current allocated memory: 7.286 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.47 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.52 seconds; current allocated memory: 7.293 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.39 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.41 seconds; current allocated memory: 7.316 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config57_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config57_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config57_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.35 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.38 seconds; current allocated memory: 7.319 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config57_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config57_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config57_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.36 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.38 seconds; current allocated memory: 7.321 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16u_config57_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16u_config57_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16u_config57_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.36 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.38 seconds; current allocated memory: 7.323 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config57_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config57_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.3 seconds. CPU system time: 0 seconds. Elapsed time: 0.31 seconds; current allocated memory: 7.325 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_831_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mFc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_847_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mGc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_832_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mHc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_848_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mIc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_839_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mJc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_855_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mKc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_840_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mLc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_856_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mMc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_841_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mNc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_857_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mOc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_842_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mPc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_858_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mQc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_843_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mRc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_859_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mSc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_844_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mTc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_860_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mUc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_845_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mVc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_861_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mWc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_846_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mXc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_862_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mYc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_833_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2mZc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_849_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m0c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_834_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m1c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_850_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m2c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_835_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m3c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_851_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m4c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_836_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m5c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_852_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m6c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_837_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m7c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_853_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m8c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_838_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2m9c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_854_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_p_ZZN4nnet26conv_2nac' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.78 seconds. CPU system time: 0.2 seconds. Elapsed time: 1.98 seconds; current allocated memory: 7.326 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s_w31_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s_w31_Rnbc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 15 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 16 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 2 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s_w31_Rnbc' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.79 seconds. CPU system time: 0.08 seconds. Elapsed time: 0.87 seconds; current allocated memory: 7.330 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4324' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_138' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4325' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_139' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4326' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_140' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4327' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_141' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4328' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_142' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4329' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_143' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4331' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_144' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4332' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_145' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4333' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_146' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4334' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_147' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4335' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4269' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4336' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4281' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4337' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4293' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4338' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4305' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4339' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4317' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4340' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4323' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4377' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4359' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4378' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4360' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4379' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4361' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4380' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4362' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4381' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4364' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4382' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4365' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4383' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4366' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4384' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4367' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4386' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4368' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4387' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4369' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4388' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4370' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4389' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4371' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4390' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4372' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4391' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4373' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4392' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4375' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4393' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4376' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4284' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4412' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4285' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4413' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4287' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4414' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4288' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4415' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4289' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4270' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4290' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4271' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4291' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4272' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4292' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4273' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4294' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4274' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4295' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4276' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4296' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4277' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4298' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4278' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4299' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4279' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4300' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4280' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4301' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4282' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4302' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4283' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4342' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4343' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4344' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4345' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4346' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4347' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4348' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4349' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4350' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4351' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4353' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4354' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4355' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4356' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4357' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4358' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4394' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4395' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4397' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4398' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4399' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4400' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4401' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4402' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4403' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4404' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4405' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4406' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4408' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4409' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4410' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4411' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4303' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4304' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4306' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4307' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4309' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4310' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4311' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4312' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4313' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4314' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4315' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4316' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4318' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4320' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4321' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4322' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_2' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_2' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 7.58 seconds. CPU system time: 0.73 seconds. Elapsed time: 8.34 seconds; current allocated memory: 7.343 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.36 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.4 seconds; current allocated memory: 7.350 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.37 seconds; current allocated memory: 7.365 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.34 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.39 seconds; current allocated memory: 7.367 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' pipeline 'ConcatLoopHeight_ConcatLoopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.4 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.41 seconds; current allocated memory: 7.372 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.29 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.32 seconds; current allocated memory: 7.375 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_24u_config58_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_24u_config58_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_24u_config58_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.33 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.37 seconds; current allocated memory: 7.376 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config58_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config58_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config58_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.39 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.42 seconds; current allocated memory: 7.376 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_24u_config58_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_24u_config58_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_24u_config58_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.37 seconds. CPU system time: 0.06 seconds. Elapsed time: 0.41 seconds; current allocated memory: 7.380 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config58_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config58_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.29 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.31 seconds; current allocated memory: 7.383 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_895_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2ncc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_919_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2ndc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_896_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nec' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_920_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nfc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_907_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2ngc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_931_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nhc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_912_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nic' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_936_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2njc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_913_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nkc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_937_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nlc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_914_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nmc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_938_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nnc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_915_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2noc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_939_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2npc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_916_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nqc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_940_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nrc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_917_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nsc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_941_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2ntc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_918_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nuc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_942_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nvc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_897_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nwc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_921_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nxc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_898_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nyc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_922_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nzc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_899_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nAc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_923_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nBc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_900_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nCc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nCc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nCc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_924_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nDc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nDc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nDc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_901_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nEc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nEc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nEc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_925_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nFc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nFc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nFc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_902_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nGc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nGc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nGc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_926_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nHc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nHc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nHc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_903_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nIc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nIc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nIc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_927_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nJc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nJc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nJc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_904_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nKc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nKc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nKc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_928_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nLc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nLc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nLc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_905_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nMc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nMc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nMc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_929_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nNc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nNc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nNc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_906_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nOc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nOc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nOc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_930_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nPc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nPc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nPc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_908_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nQc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nQc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nQc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_932_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nRc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nRc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nRc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_909_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nSc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nSc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nSc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_933_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nTc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nTc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nTc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_910_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nUc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nUc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nUc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_934_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nVc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nVc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nVc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_911_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nWc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nWc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nWc_x' due to conflict. +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_935_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nXc' due to the length limit 80 +WARNING: [RTGEN 206-101] RTL name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nXc' is changed to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_p_ZZN4nnet26conv_2nXc_x' due to conflict. +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 3.75 seconds. CPU system time: 0.31 seconds. Elapsed time: 4.06 seconds; current allocated memory: 7.384 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_w35_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_w35_RnYc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-104] Estimated max fanout for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' is 6912 from HDL expression: (do_init_reg_739 == 1'd0) +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_10s_32s_32_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_32s_33_1_1': 8 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_33s_33_1_1': 7 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mul_16s_16s_32_1_1': 8 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 3 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_w35_RnYc' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.97 seconds. CPU system time: 0.11 seconds. Elapsed time: 1.08 seconds; current allocated memory: 7.390 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4707' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_99' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4708' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_98' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4709' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_97' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4710' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_96' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4711' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_95' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4712' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_94' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4713' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_93' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4714' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_92' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4716' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_91' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4717' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_90' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4718' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4719' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4720' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4721' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4722' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4723' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4624' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4724' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4636' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4725' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4648' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4727' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4661' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4728' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4673' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4729' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4685' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4730' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4697' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4731' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4705' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4732' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4706' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4786' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4760' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4787' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4761' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4788' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4762' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4789' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4763' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4764' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4765' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4766' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4767' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4768' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4769' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4771' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4772' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4773' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4774' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4775' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4776' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4777' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4778' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4779' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4780' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4782' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4783' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4784' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4785' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4646' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4618' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4647' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4619' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4650' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4620' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4651' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4621' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4652' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4622' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4653' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4623' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4654' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4625' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4655' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4626' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4656' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4628' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4657' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4629' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4658' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4630' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4659' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4631' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4662' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4632' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4663' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4633' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4664' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4634' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4665' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4635' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4666' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4637' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4667' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4639' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4668' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4640' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4669' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4641' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4670' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4642' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4672' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4643' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4674' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4644' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4675' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4645' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4733' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4734' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4735' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4736' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4738' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4739' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4740' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4741' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4742' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4743' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4744' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4745' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4746' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4747' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4749' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4750' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4751' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4752' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4753' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4754' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4755' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4756' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4757' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4758' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4615' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4617' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4676' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4677' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4678' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4679' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4680' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4681' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4683' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4684' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4686' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4687' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4688' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4689' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4690' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4691' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4692' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4694' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4695' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4696' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4698' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4699' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4700' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4701' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4702' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4703' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_6' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_6' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 11.4 seconds. CPU system time: 1.17 seconds. Elapsed time: 12.57 seconds; current allocated memory: 7.407 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.41 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.44 seconds; current allocated memory: 7.412 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.38 seconds. CPU system time: 0.06 seconds. Elapsed time: 0.44 seconds; current allocated memory: 7.435 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config59_Pipeline_PadTopWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config59_Pipeline_PadTopWidth' pipeline 'PadTopWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config59_Pipeline_PadTopWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.36 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.39 seconds; current allocated memory: 7.437 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config59_Pipeline_PadMain' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config59_Pipeline_PadMain' pipeline 'PadMain' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config59_Pipeline_PadMain'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.4 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.43 seconds; current allocated memory: 7.438 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_array_ap_fixed_8u_config59_Pipeline_PadBottomWidth' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'zeropad2d_cl_array_array_ap_fixed_8u_config59_Pipeline_PadBottomWidth' pipeline 'PadBottomWidth' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_array_ap_fixed_8u_config59_Pipeline_PadBottomWidth'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.4 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.43 seconds; current allocated memory: 7.442 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config59_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config59_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.29 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.32 seconds; current allocated memory: 7.445 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1391_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dnZc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1399_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn0c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1392_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn1c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1400_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn2c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1393_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn3c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1401_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn4c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1394_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn5c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1402_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn6c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1395_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn7c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1403_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn8c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1396_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dn9c' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1404_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2doac' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1397_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dobc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1405_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2docc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1398_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2dodc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1406_SHIFTREG_AUTO_0R0W' to 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_p_ZZN4nnet26conv_2doec' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 1.07 seconds. CPU system time: 0.14 seconds. Elapsed time: 1.21 seconds; current allocated memory: 7.445 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s_w37_ROM_NP_BRAM_1R' to 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s_w37_Rofc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s' pipeline 'ReuseLoop' pipeline type 'rewind pipeline' +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_16s_38s_38_1_1': 7 instance(s). +INFO: [RTGEN 206-100] Generating core module 'mac_muladd_16s_9s_31s_31_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Generating core module 'sparsemux_145_7_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config37_mult_s_w37_Rofc' using block ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.69 seconds. CPU system time: 0.05 seconds. Elapsed time: 0.74 seconds; current allocated memory: 7.448 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_21' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_29' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_20' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_28' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3553' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_27' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3554' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_26' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3555' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_25' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3556' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_24' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3557' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_23' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3558' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_22' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3575' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3567' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3576' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3568' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3577' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3569' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3578' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3570' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3579' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3571' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3580' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3572' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3581' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3573' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3582' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3574' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3599' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3591' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3600' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3592' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3601' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3593' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3602' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3594' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3603' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3595' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3604' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3596' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3605' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3597' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3606' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3598' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3559' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3560' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3561' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3562' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3563' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3564' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3565' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3566' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3583' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3584' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3585' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3586' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3587' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3588' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3589' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3590' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3607' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3608' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3609' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3610' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3611' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3612' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3613' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3614' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sX_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'sY_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pY_14' is power-on initialization. +WARNING: [RTGEN 206-101] Register 'pX_14' is power-on initialization. +INFO: [RTGEN 206-100] Finished creating RTL model for 'compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 4.27 seconds. CPU system time: 0.37 seconds. Elapsed time: 4.65 seconds; current allocated memory: 7.454 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.35 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.38 seconds; current allocated memory: 7.463 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s' pipeline 'ReLUActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.37 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.41 seconds; current allocated memory: 7.465 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config60_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config60_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.32 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.34 seconds; current allocated memory: 7.467 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [SYN 201-210] Renamed object name 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s_sigmoid_table_ROM_AUTO_1R' to 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s_sigmoid_table_Rogc' due to the length limit 80 +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s' pipeline 'SigmoidActLoop' pipeline type 'loop pipeline' +INFO: [RTGEN 206-100] Finished creating RTL model for 'sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s'. +INFO: [RTMG 210-279] Implementing memory 'myproject_sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s_sigmoid_table_Rogc' using auto ROMs. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.46 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.5 seconds; current allocated memory: 7.469 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'transpose_array_array_ap_fixed_1u_config42_Pipeline_VITIS_LOOP_45_1' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'transpose_array_array_ap_fixed_1u_config42_Pipeline_VITIS_LOOP_45_1' pipeline 'VITIS_LOOP_45_1' pipeline type 'loop pipeline' +INFO: [HLS 200-1553] Disabling free running pipeline (frp) architecture on pipeline 'VITIS_LOOP_45_1' in module 'transpose_array_array_ap_fixed_1u_config42_Pipeline_VITIS_LOOP_45_1', because the estimated Stream Port Number is 265, which is bigger than the frp_stream_port_number threshold of 20. +Resolution: For help on HLS 200-1553 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1553.html +INFO: [RTGEN 206-104] Estimated max fanout for 'transpose_array_array_ap_fixed_1u_config42_Pipeline_VITIS_LOOP_45_1' is 65536 from HDL expression: ((ap_loop_exit_ready == 1'b1) & (icmp_ln45_fu_61490_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_01001) & (1'b1 == ap_CS_fsm_pp0_stage0)) +INFO: [RTGEN 206-100] Finished creating RTL model for 'transpose_array_array_ap_fixed_1u_config42_Pipeline_VITIS_LOOP_45_1'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 21.74 seconds. CPU system time: 0.48 seconds. Elapsed time: 22.23 seconds; current allocated memory: 8.693 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'transpose_array_array_ap_fixed_1u_config42_Pipeline_VITIS_LOOP_54_3' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'transpose_array_array_ap_fixed_1u_config42_Pipeline_VITIS_LOOP_54_3' pipeline 'VITIS_LOOP_54_3' pipeline type 'loop pipeline' +INFO: [HLS 200-1553] Disabling free running pipeline (frp) architecture on pipeline 'VITIS_LOOP_54_3' in module 'transpose_array_array_ap_fixed_1u_config42_Pipeline_VITIS_LOOP_54_3', because the estimated Stream Port Number is 362, which is bigger than the frp_stream_port_number threshold of 20. +Resolution: For help on HLS 200-1553 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1553.html +INFO: [RTGEN 206-100] Generating core module 'sparsemux_8193_12_16_1_1': 1 instance(s). +INFO: [RTGEN 206-100] Finished creating RTL model for 'transpose_array_array_ap_fixed_1u_config42_Pipeline_VITIS_LOOP_54_3'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 43.83 seconds. CPU system time: 0.66 seconds. Elapsed time: 44.61 seconds; current allocated memory: 9.037 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'transpose_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config42_s' +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [RTGEN 206-100] Finished creating RTL model for 'transpose_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config42_s'. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 3.01 seconds. CPU system time: 0.35 seconds. Elapsed time: 3.38 seconds; current allocated memory: 9.217 GB. +INFO: [HLS 200-10] ---------------------------------------------------------------- +INFO: [HLS 200-10] -- Generating RTL for module 'myproject' +INFO: [HLS 200-10] ---------------------------------------------------------------- +WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low. +INFO: [RTGEN 206-500] Setting interface mode on port 'myproject/x' to 'axis' (register, both mode). +INFO: [RTGEN 206-500] Setting interface mode on port 'myproject/layer42_out' to 'axis' (register, both mode). +INFO: [RTGEN 206-500] Setting interface mode on function 'myproject' to 'ap_ctrl_hs'. +INFO: [SYN 201-210] Renamed object name 'start_for_zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config46_U0' to 'start_for_zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config4ohc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config47_U0' to 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4oic' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_U0' to 'start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6ojc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config48_U0' to 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4okc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_U0' to 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7olc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_U0' to 'start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configomc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_U0' to 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10onc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_U0' to 'start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384ooc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13opc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15oqc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_U0' to 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18orc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_U0' to 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20osc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24otc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_U0' to 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26ouc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_U0' to 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30ovc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_U0' to 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32owc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_U0' to 'start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3oxc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config59_U0' to 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config5oyc' due to the length limit 80 +INFO: [SYN 201-210] Renamed object name 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_U0' to 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37ozc' due to the length limit 80 +INFO: [RTGEN 206-100] Finished creating RTL model for 'myproject'. +INFO: [RTMG 210-285] Implementing FIFO 'layer41_out_U(myproject_fifo_w16_d64_S)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'layer46_out_U(myproject_fifo_w16_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer2_out_U(myproject_fifo_w296_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer3_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer47_out_U(myproject_fifo_w128_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer4_out_U(myproject_fifo_w320_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer5_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer43_cpy1_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer43_cpy2_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer6_out_U(myproject_fifo_w128_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer48_out_U(myproject_fifo_w128_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer7_out_U(myproject_fifo_w640_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer8_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer49_out_U(myproject_fifo_w256_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer9_out_U(myproject_fifo_w656_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer10_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer44_cpy1_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer44_cpy2_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer11_out_U(myproject_fifo_w256_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer50_out_U(myproject_fifo_w256_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer12_out_U(myproject_fifo_w1312_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer13_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer51_out_U(myproject_fifo_w512_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer14_out_U(myproject_fifo_w1344_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer15_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer45_cpy1_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer45_cpy2_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer16_out_U(myproject_fifo_w512_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer52_out_U(myproject_fifo_w512_d100_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer17_out_U(myproject_fifo_w2688_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer18_out_U(myproject_fifo_w1024_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer53_out_U(myproject_fifo_w1024_d100_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer19_out_U(myproject_fifo_w2752_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer20_out_U(myproject_fifo_w1024_d64_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer21_out_U(myproject_fifo_w1024_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer22_out_U(myproject_fifo_w1536_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer54_out_U(myproject_fifo_w1536_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer23_out_U(myproject_fifo_w1376_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer24_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer55_out_U(myproject_fifo_w512_d324_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer25_out_U(myproject_fifo_w1344_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer26_out_U(myproject_fifo_w512_d256_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer27_out_U(myproject_fifo_w512_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer28_out_U(myproject_fifo_w768_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer56_out_U(myproject_fifo_w768_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer29_out_U(myproject_fifo_w672_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer30_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer57_out_U(myproject_fifo_w256_d1156_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer31_out_U(myproject_fifo_w656_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer32_out_U(myproject_fifo_w256_d1024_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer33_out_U(myproject_fifo_w256_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer34_out_U(myproject_fifo_w384_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer58_out_U(myproject_fifo_w384_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer35_out_U(myproject_fifo_w328_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer36_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer59_out_U(myproject_fifo_w128_d4356_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer37_out_U(myproject_fifo_w320_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer38_out_U(myproject_fifo_w128_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer39_out_U(myproject_fifo_w36_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'layer40_out_U(myproject_fifo_w16_d4096_A)' using Vivado Default RAMs. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config4ohc_U(myproject_start_for_zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config4ohc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_U0_U(myproject_start_for_conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4oic_U(myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4oic)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_U0_U(myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0_U(myproject_start_for_clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6ojc_U(myproject_start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6ojc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0_U(myproject_start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4okc_U(myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4okc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7olc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7olc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_U0_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config49_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config49_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configomc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configomc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10onc_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10onc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384ooc_U(myproject_start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384ooc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0_U(myproject_start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0_U(myproject_start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config50_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config50_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13opc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13opc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config51_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config51_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15oqc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15oqc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0_U(myproject_start_for_clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_U0_U(myproject_start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0_U(myproject_start_for_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18orc_U(myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18orc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20osc_U(myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20osc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_U0_U(myproject_start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24otc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24otc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config55_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config55_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26ouc_U(myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26ouc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_U0_U(myproject_start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30ovc_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30ovc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config57_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config57_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_U0_U(myproject_start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32owc_U(myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32owc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_U0_U(myproject_start_for_resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config58_U0_U(myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config58_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3oxc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3oxc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config5oyc_U(myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config5oyc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37ozc_U(myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37ozc)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_U0_U(myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config60_U0_U(myproject_start_for_pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config60_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_U0_U(myproject_start_for_sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_U0)' using Shift Registers. +INFO: [RTMG 210-285] Implementing FIFO 'start_for_transpose_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config42_U0_U(myproject_start_for_transpose_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config42_U0)' using Shift Registers. +INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 8.54 seconds. CPU system time: 0.9 seconds. Elapsed time: 9.47 seconds; current allocated memory: 9.316 GB. +INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 2.88 seconds. CPU system time: 0.36 seconds. Elapsed time: 3.28 seconds; current allocated memory: 9.344 GB. +INFO: [HLS 200-111] Finished Updating report files: CPU user time: 25.67 seconds. CPU system time: 0.18 seconds. Elapsed time: 25.86 seconds; current allocated memory: 9.488 GB. +INFO: [VHDL 208-304] Generating VHDL RTL for myproject. +INFO: [VLOG 209-307] Generating Verilog RTL for myproject. +INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were NOT satisfied. +INFO: [HLS 200-789] **** Estimated Fmax: 226.71 MHz +INFO: [HLS 200-2161] Finished Command csynth_design Elapsed time: 11:59:15; Allocated memory: 9.239 GB. +***** C/RTL SYNTHESIS COMPLETED IN 11h59m15s ***** +INFO: [HLS 200-112] Total CPU user time: 43125.2 seconds. Total CPU system time: 45.38 seconds. Total elapsed time: 43158.9 seconds; peak allocated memory: 9.509 GB. +INFO: [vitis-run 60-791] Total elapsed time: 11h 59m 21s +INFO: [vitis-run 60-1662] Stopping dispatch session having empty uuid. diff --git a/myproject_prj/hls.app b/myproject_prj/hls.app new file mode 100644 index 0000000000000000000000000000000000000000..6203dc5637036b4751baf1ed4b367f1cd8939e7c --- /dev/null +++ b/myproject_prj/hls.app @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/myproject_prj/solution1/solution1.aps b/myproject_prj/solution1/solution1.aps new file mode 100644 index 0000000000000000000000000000000000000000..59098dcb7c2b8d6cb4d2675c7e78824d55cb66f0 --- /dev/null +++ b/myproject_prj/solution1/solution1.aps @@ -0,0 +1,24 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/myproject_prj/solution1/solution1.directive b/myproject_prj/solution1/solution1.directive new file mode 100644 index 0000000000000000000000000000000000000000..d9e2af0f84b8c204a276ddbc8029b4cf24ea1694 --- /dev/null +++ b/myproject_prj/solution1/solution1.directive @@ -0,0 +1,10 @@ + + + + + + + + + diff --git a/myproject_prj/solution1/solution1_data.json b/myproject_prj/solution1/solution1_data.json new file mode 100644 index 0000000000000000000000000000000000000000..874edb8815780da4b0ff8b551d110142604d6761 --- /dev/null +++ b/myproject_prj/solution1/solution1_data.json @@ -0,0 +1,8638 @@ +{ + "Top": "myproject", + "RtlTop": "myproject", + "RtlPrefix": "", + "RtlSubPrefix": "myproject_", + "SourceLanguage": "cpp", + "HostMachineBits": "64", + "FunctionProtocol": "ap_ctrl_hs", + "ResetStyle": "control", + "Target": { + "Family": "virtexuplushbm", + "Device": "xcvu47p", + "Package": "-fsvh2892", + "Speed": "-2L-e", + "Triple": "fpga64-xilinx-none" + }, + "Args": { + "x": { + "index": "0", + "direction": "in", + "srcType": "stream, 1>, 0>&", + "srcSize": "16", + "hwRefs": [{ + "type": "interface", + "interface": "x", + "name": "", + "usage": "data", + "direction": "in" + }] + }, + "layer40_out": { + "index": "1", + "direction": "out", + "srcType": "stream, 1>, 0>&", + "srcSize": "16", + "hwRefs": [{ + "type": "interface", + "interface": "layer40_out", + "name": "", + "usage": "data", + "direction": "out" + }] + } + }, + "HlsSolution": { + "FlowTarget": "vivado", + "ConfigTcl": [ + "config_compile -name_max_length=80", + "config_compile -complex-mul-dsp=0", + "config_compile -unsafe_math_optimizations=0", + "config_schedule -enable_dsp_full_reg=0", + "config_array_partition -complete_threshold=4096" + ], + "ProfileOption": "0", + "ProfileType": "none", + "KernelName": "myproject" + }, + "ClockInfo": { + "ClockName": "ap_clk", + "ClockPeriod": "4", + "Uncertainty": "1.35", + "IsCombinational": "0", + "II": "45058 ~ 1285022", + "Latency": "1285112" + }, + "Xdc": {"OocClocks": ["create_clock -name ap_clk -period 4.000 [get_ports ap_clk]"]}, + "Ipx": { + "Vendor": "xilinx.com", + "Library": "hls", + "Name": "myproject", + "Version": "1.0", + "DisplayName": "Myproject", + "Revision": "2114552870", + "Description": "An IP generated by Vitis HLS", + "Taxonomy": "\/VITIS_HLS_IP", + "AutoFamilySupport": "", + "ZipFile": "xilinx_com_hls_myproject_1_0.zip" + }, + "Files": { + "CSource": ["..\/..\/firmware\/myproject.cpp"], + "TestBench": [ + "..\/..\/myproject_test.cpp", + "..\/..\/firmware\/weights", + "..\/..\/tb_data" + ], + "Vhdl": [ + "impl\/vhdl\/myproject_clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s.vhd", + "impl\/vhdl\/myproject_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s.vhd", + "impl\/vhdl\/myproject_clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s.vhd", + "impl\/vhdl\/myproject_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s.vhd", + "impl\/vhdl\/myproject_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s.vhd", + "impl\/vhdl\/myproject_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s.vhd", + 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layer41_cpy1_U layer41_cpy2_U layer6_out_U layer46_out_U layer7_out_U layer8_out_U layer47_out_U layer9_out_U layer10_out_U layer42_cpy1_U layer42_cpy2_U layer11_out_U layer48_out_U layer12_out_U layer13_out_U layer49_out_U layer14_out_U layer15_out_U layer43_cpy1_U layer43_cpy2_U layer16_out_U layer50_out_U layer17_out_U layer18_out_U layer51_out_U layer19_out_U layer20_out_U layer21_out_U layer22_out_U layer52_out_U layer23_out_U layer24_out_U layer53_out_U layer25_out_U layer26_out_U layer27_out_U layer28_out_U layer54_out_U layer29_out_U layer30_out_U layer55_out_U layer31_out_U layer32_out_U layer33_out_U layer34_out_U layer56_out_U layer35_out_U layer36_out_U layer57_out_U layer37_out_U layer38_out_U layer39_out_U", + "Instances": [ + { + "ModuleName": "zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s", + "InstanceName": "zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_U0", + "Instances": [ + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth_fu_28", + "BindInstances": "icmp_ln53_fu_54_p2 j_8_fu_60_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain_fu_34", + "BindInstances": "icmp_ln59_fu_73_p2 i_22_fu_79_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth_fu_42", + "BindInstances": "icmp_ln77_fu_54_p2 j_33_fu_60_p2" + } + ] + }, + { + "ModuleName": "conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s", + "InstanceName": "conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_U0", + "BindInstances": "icmp_ln52_fu_128_p2 add_ln52_fu_134_p2", + "Instances": [{ + "ModuleName": "compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s", + "InstanceName": "grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78", + "BindInstances": "icmp_ln284_fu_151_p2 icmp_ln284_28_fu_169_p2 icmp_ln284_34_fu_185_p2 icmp_ln284_35_fu_201_p2 and_ln284_fu_207_p2 and_ln284_10_fu_213_p2 add_ln303_fu_272_p2 icmp_ln303_fu_277_p2 add_ln318_fu_289_p2 select_ln318_fu_294_p3 add_ln307_fu_319_p2 icmp_ln307_fu_324_p2 icmp_ln313_fu_336_p2 add_ln313_fu_341_p2 select_ln313_fu_346_p3", + "Instances": [ + { + "ModuleName": "shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s", + "InstanceName": "call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93", + "BindInstances": "void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_U void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_1_U" + }, + { + "ModuleName": "dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s", + "InstanceName": "grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121", + "BindInstances": "sparsemux_19_4_16_1_1_U19 mac_muladd_16s_16s_37s_38_1_1_U21 sparsemux_17_3_37_1_1_U20 mac_muladd_16s_16s_37s_38_1_1_U21 mac_muladd_16s_16s_37s_38_1_1_U21 icmp_ln144_fu_710_p2 icmp_ln144_11_fu_715_p2 icmp_ln144_12_fu_720_p2 icmp_ln144_13_fu_725_p2 icmp_ln144_14_fu_730_p2 icmp_ln144_15_fu_735_p2 icmp_ln144_16_fu_740_p2 icmp_ln144_17_fu_745_p2 or_ln144_fu_833_p2 or_ln144_1_fu_750_p2 or_ln144_2_fu_837_p2 or_ln144_3_fu_756_p2 or_ln144_4_fu_762_p2 or_ln144_5_fu_768_p2 or_ln144_6_fu_842_p2 acc_88_fu_847_p3 or_ln144_7_fu_855_p2 or_ln144_8_fu_859_p2 acc_87_fu_864_p3 acc_86_fu_777_p3 acc_85_fu_785_p3 acc_84_fu_793_p3 acc_83_fu_801_p3 acc_82_fu_809_p3 acc_81_fu_817_p3 acc_fu_825_p3 in_index_3_fu_641_p2 icmp_ln154_fu_647_p2 in_index_fu_653_p3 w_index_fu_581_p2 icmp_ln135_fu_587_p2 outidx_1_U w2_U" + } + ] + }] + }, + { + "ModuleName": "relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s", + "InstanceName": "relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0", + "BindInstances": "icmp_ln51_fu_205_p2 out_data_8_fu_221_p3 icmp_ln51_8_fu_229_p2 out_data_10_fu_245_p3 icmp_ln51_9_fu_253_p2 out_data_12_fu_269_p3 icmp_ln51_10_fu_277_p2 out_data_14_fu_293_p3 icmp_ln51_11_fu_301_p2 select_ln51_fu_317_p3 icmp_ln51_12_fu_325_p2 select_ln51_12_fu_341_p3 icmp_ln51_13_fu_349_p2 select_ln51_13_fu_365_p3 icmp_ln51_14_fu_373_p2 select_ln51_14_fu_389_p3 i_fu_397_p2 icmp_ln41_fu_403_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s", + "InstanceName": "zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_U0", + "Instances": [ + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth_fu_22", + "BindInstances": "icmp_ln53_fu_54_p2 j_6_fu_60_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain_fu_28", + "BindInstances": "icmp_ln59_fu_69_p2 i_8_fu_75_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth_fu_36", + "BindInstances": "icmp_ln77_fu_54_p2 j_14_fu_60_p2" + } + ] + }, + { + "ModuleName": "conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s", + "InstanceName": "conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_U0", + "BindInstances": "icmp_ln52_fu_472_p2 add_ln52_fu_478_p2", + "Instances": [{ + "ModuleName": "compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s", + "InstanceName": "grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262", + "BindInstances": "icmp_ln284_fu_655_p2 icmp_ln284_4_fu_673_p2 icmp_ln284_28_fu_689_p2 icmp_ln284_29_fu_705_p2 and_ln284_fu_711_p2 and_ln284_2_fu_717_p2 add_ln303_fu_768_p2 icmp_ln303_fu_773_p2 add_ln318_fu_785_p2 select_ln318_fu_790_p3 add_ln307_fu_815_p2 icmp_ln307_fu_820_p2 icmp_ln313_fu_832_p2 add_ln313_fu_837_p2 select_ln313_fu_842_p3", + "Instances": [ + { + "ModuleName": "shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s", + "InstanceName": "call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_fu_303", + "BindInstances": "p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1375_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1383_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1376_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1384_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1377_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1385_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1378_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1386_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1379_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1387_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1380_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1388_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1381_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1389_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1382_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1390_U" + }, + { + "ModuleName": "dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s", + "InstanceName": "grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_fu_499", + "BindInstances": "sparsemux_145_7_16_1_1_U128 mac_muladd_16s_16s_40s_41_1_1_U129 select_ln144_fu_3071_p3 mac_muladd_16s_16s_40s_41_1_1_U129 mac_muladd_16s_16s_40s_41_1_1_U129 icmp_ln144_fu_3173_p2 select_ln144_40_fu_3178_p3 select_ln144_41_fu_3185_p3 acc_63_fu_3192_p3 acc_62_fu_3200_p3 mac_muladd_16s_16s_40s_41_1_1_U130 select_ln144_42_fu_3100_p3 acc_74_fu_3208_p3 acc_73_fu_3214_p3 mac_muladd_16s_16s_40s_41_1_1_U130 mac_muladd_16s_16s_40s_41_1_1_U130 icmp_ln144_8_fu_3220_p2 select_ln144_45_fu_3225_p3 select_ln144_46_fu_3232_p3 acc_65_fu_3239_p3 acc_fu_3247_p3 mac_muladd_16s_16s_40s_41_1_1_U131 select_ln144_47_fu_3129_p3 acc_76_fu_3255_p3 acc_75_fu_3261_p3 mac_muladd_16s_16s_40s_41_1_1_U131 mac_muladd_16s_16s_40s_41_1_1_U131 icmp_ln144_9_fu_3267_p2 select_ln144_50_fu_3272_p3 select_ln144_51_fu_3279_p3 acc_68_fu_3286_p3 acc_67_fu_3294_p3 mac_muladd_16s_9s_40s_41_1_1_U132 select_ln144_52_fu_3158_p3 acc_78_fu_3302_p3 acc_77_fu_3308_p3 mac_muladd_16s_9s_40s_41_1_1_U132 mac_muladd_16s_9s_40s_41_1_1_U132 icmp_ln144_10_fu_3314_p2 select_ln144_55_fu_3319_p3 select_ln144_56_fu_3326_p3 acc_71_fu_3333_p3 acc_70_fu_3341_p3 acc_80_fu_3349_p3 acc_79_fu_3355_p3 in_index_2_fu_3025_p2 icmp_ln154_fu_3031_p2 in_index_fu_3037_p3 w_index_fu_3045_p2 icmp_ln135_fu_3051_p2 outidx_2_U w4_U" + } + ] + }] + }, + { + "ModuleName": "relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s", + "InstanceName": "relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_U0", + "BindInstances": "icmp_ln51_fu_205_p2 out_data_1_fu_221_p3 icmp_ln51_1_fu_229_p2 out_data_3_fu_245_p3 icmp_ln51_2_fu_253_p2 out_data_5_fu_269_p3 icmp_ln51_3_fu_277_p2 out_data_7_fu_293_p3 icmp_ln51_4_fu_301_p2 select_ln51_fu_317_p3 icmp_ln51_5_fu_325_p2 select_ln51_5_fu_341_p3 icmp_ln51_6_fu_349_p2 select_ln51_6_fu_365_p3 icmp_ln51_7_fu_373_p2 select_ln51_7_fu_389_p3 i_fu_397_p2 icmp_ln41_fu_403_p2" + }, + { + "ModuleName": "clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s", + "InstanceName": "clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0", + "BindInstances": "i_fu_72_p2 icmp_ln22_fu_78_p2" + }, + { + "ModuleName": "pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s", + "InstanceName": "pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_U0", + "BindInstances": "icmp_ln55_fu_292_p2 add_ln109_fu_302_p2 icmp_ln55_1_fu_312_p2 icmp_ln55_2_fu_322_p2 icmp_ln55_3_fu_328_p2 and_ln55_fu_334_p2 and_ln55_1_fu_340_p2 icmp_ln66_fu_563_p2 xor_ln66_fu_569_p2 select_ln0_fu_575_p3 icmp_ln66_1_fu_583_p2 xor_ln66_1_fu_589_p2 select_ln0_1_fu_595_p3 icmp_ln66_2_fu_603_p2 xor_ln66_2_fu_609_p2 res_pack_fu_615_p3 icmp_ln66_3_fu_639_p2 xor_ln66_3_fu_645_p2 select_ln0_2_fu_651_p3 icmp_ln66_4_fu_659_p2 xor_ln66_4_fu_665_p2 select_ln0_3_fu_671_p3 icmp_ln66_5_fu_679_p2 xor_ln66_5_fu_685_p2 res_pack_1_fu_691_p3 icmp_ln66_6_fu_715_p2 xor_ln66_6_fu_721_p2 select_ln0_4_fu_727_p3 icmp_ln66_7_fu_735_p2 xor_ln66_7_fu_741_p2 select_ln0_5_fu_747_p3 icmp_ln66_8_fu_755_p2 xor_ln66_8_fu_761_p2 res_pack_2_fu_767_p3 icmp_ln66_9_fu_791_p2 xor_ln66_9_fu_797_p2 select_ln0_6_fu_803_p3 icmp_ln66_10_fu_811_p2 xor_ln66_10_fu_817_p2 select_ln0_7_fu_823_p3 icmp_ln66_11_fu_831_p2 xor_ln66_11_fu_837_p2 res_pack_3_fu_843_p3 icmp_ln66_12_fu_867_p2 xor_ln66_12_fu_873_p2 select_ln0_8_fu_879_p3 icmp_ln66_13_fu_887_p2 xor_ln66_13_fu_893_p2 select_ln0_9_fu_899_p3 icmp_ln66_14_fu_907_p2 xor_ln66_14_fu_913_p2 res_pack_4_fu_919_p3 icmp_ln66_15_fu_943_p2 xor_ln66_15_fu_949_p2 select_ln0_10_fu_955_p3 icmp_ln66_16_fu_963_p2 xor_ln66_16_fu_969_p2 select_ln0_11_fu_975_p3 icmp_ln66_17_fu_983_p2 xor_ln66_17_fu_989_p2 res_pack_5_fu_995_p3 icmp_ln66_18_fu_1019_p2 xor_ln66_18_fu_1025_p2 select_ln0_12_fu_1031_p3 icmp_ln66_19_fu_1039_p2 xor_ln66_19_fu_1045_p2 select_ln0_13_fu_1051_p3 icmp_ln66_20_fu_1059_p2 xor_ln66_20_fu_1065_p2 res_pack_6_fu_1071_p3 icmp_ln66_21_fu_1095_p2 xor_ln66_21_fu_1101_p2 select_ln0_14_fu_1107_p3 icmp_ln66_22_fu_1115_p2 xor_ln66_22_fu_1121_p2 select_ln0_15_fu_1127_p3 icmp_ln66_23_fu_1135_p2 xor_ln66_23_fu_1141_p2 res_pack_7_fu_1147_p3 add_ln76_fu_346_p2 icmp_ln76_fu_352_p2 add_ln91_fu_364_p2 select_ln91_fu_370_p3 add_ln80_fu_400_p2 icmp_ln80_fu_406_p2 icmp_ln86_fu_422_p2 add_ln86_fu_428_p2 select_ln86_fu_434_p3 icmp_ln109_fu_448_p2", + "Instances": [{ + "ModuleName": "shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s", + "InstanceName": "call_ln52_shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_fu_188", + "BindInstances": "void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_U void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_1_U void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_2_U void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_3_U void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_4_U void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_5_U void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_6_U void_pooling2d_cl_stream_stream_array_ap_fixed_8u_0_line_buffer_7_U" + }] + }, + { + "ModuleName": "zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_s", + "InstanceName": "zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_U0", + "Instances": [ + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth_fu_22", + "BindInstances": "icmp_ln53_fu_54_p2 j_4_fu_60_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain_fu_28", + "BindInstances": "icmp_ln59_fu_69_p2 i_6_fu_75_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth_fu_36", + "BindInstances": "icmp_ln77_fu_54_p2 j_13_fu_60_p2" + } + ] + }, + { + "ModuleName": "conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s", + "InstanceName": "conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_U0", + "BindInstances": "icmp_ln52_fu_472_p2 add_ln52_fu_478_p2", + "Instances": [{ + "ModuleName": "compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s", + "InstanceName": "grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_262", + "BindInstances": "icmp_ln284_fu_655_p2 icmp_ln284_10_fu_673_p2 icmp_ln284_32_fu_689_p2 icmp_ln284_33_fu_705_p2 and_ln284_fu_711_p2 and_ln284_4_fu_717_p2 add_ln303_fu_808_p2 icmp_ln303_fu_813_p2 add_ln318_fu_825_p2 select_ln318_fu_830_p3 add_ln307_fu_855_p2 icmp_ln307_fu_860_p2 icmp_ln313_fu_872_p2 add_ln313_fu_877_p2 select_ln313_fu_882_p3", + "Instances": [ + { + "ModuleName": "shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s", + "InstanceName": "call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_fu_303", + "BindInstances": "p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1359_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1367_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1360_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1368_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1361_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1369_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1362_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1370_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1363_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1371_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1364_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1372_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1365_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1373_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1366_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1374_U" + }, + { + "ModuleName": "dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s", + "InstanceName": "grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_fu_499", + "BindInstances": "sparsemux_145_7_16_1_1_U356 mac_muladd_16s_16s_40s_41_1_1_U357 select_ln144_fu_3223_p3 mac_muladd_16s_16s_40s_41_1_1_U357 mac_muladd_16s_16s_40s_41_1_1_U357 icmp_ln144_fu_3441_p2 select_ln144_1_fu_3446_p3 select_ln144_2_fu_3453_p3 acc_17_fu_3460_p3 acc_16_fu_3468_p3 mac_muladd_16s_16s_40s_41_1_1_U358 select_ln144_3_fu_3252_p3 acc_40_fu_3476_p3 acc_39_fu_3482_p3 mac_muladd_16s_16s_40s_41_1_1_U358 mac_muladd_16s_16s_40s_41_1_1_U358 icmp_ln144_1_fu_3488_p2 select_ln144_6_fu_3493_p3 select_ln144_7_fu_3500_p3 acc_19_fu_3507_p3 acc_fu_3515_p3 mac_muladd_16s_16s_40s_41_1_1_U359 select_ln144_8_fu_3281_p3 acc_42_fu_3523_p3 acc_41_fu_3529_p3 mac_muladd_16s_16s_40s_41_1_1_U359 mac_muladd_16s_16s_40s_41_1_1_U359 icmp_ln144_2_fu_3535_p2 select_ln144_11_fu_3540_p3 select_ln144_12_fu_3547_p3 acc_22_fu_3554_p3 acc_21_fu_3562_p3 mac_muladd_16s_16s_40s_41_1_1_U360 select_ln144_13_fu_3310_p3 acc_44_fu_3570_p3 acc_43_fu_3576_p3 mac_muladd_16s_16s_40s_41_1_1_U360 mac_muladd_16s_16s_40s_41_1_1_U360 icmp_ln144_3_fu_3582_p2 select_ln144_16_fu_3587_p3 select_ln144_17_fu_3594_p3 acc_25_fu_3601_p3 acc_24_fu_3609_p3 mac_muladd_16s_16s_40s_41_1_1_U361 select_ln144_18_fu_3339_p3 acc_46_fu_3617_p3 acc_45_fu_3623_p3 mac_muladd_16s_16s_40s_41_1_1_U361 mac_muladd_16s_16s_40s_41_1_1_U361 icmp_ln144_4_fu_3629_p2 select_ln144_21_fu_3634_p3 select_ln144_22_fu_3641_p3 acc_28_fu_3648_p3 acc_27_fu_3656_p3 mac_muladd_16s_16s_40s_41_1_1_U362 select_ln144_23_fu_3368_p3 acc_48_fu_3664_p3 acc_47_fu_3670_p3 mac_muladd_16s_16s_40s_41_1_1_U362 mac_muladd_16s_16s_40s_41_1_1_U362 icmp_ln144_5_fu_3676_p2 select_ln144_26_fu_3681_p3 select_ln144_27_fu_3688_p3 acc_31_fu_3695_p3 acc_30_fu_3703_p3 mac_muladd_16s_16s_40s_41_1_1_U363 select_ln144_28_fu_3397_p3 acc_50_fu_3711_p3 acc_49_fu_3717_p3 mac_muladd_16s_16s_40s_41_1_1_U363 mac_muladd_16s_16s_40s_41_1_1_U363 icmp_ln144_6_fu_3723_p2 select_ln144_31_fu_3728_p3 select_ln144_32_fu_3735_p3 acc_34_fu_3742_p3 acc_33_fu_3750_p3 mac_muladd_16s_11s_40s_41_1_1_U364 select_ln144_33_fu_3426_p3 acc_52_fu_3758_p3 acc_51_fu_3764_p3 mac_muladd_16s_11s_40s_41_1_1_U364 mac_muladd_16s_11s_40s_41_1_1_U364 icmp_ln144_7_fu_3770_p2 select_ln144_36_fu_3775_p3 select_ln144_37_fu_3782_p3 acc_37_fu_3789_p3 acc_36_fu_3797_p3 acc_54_fu_3805_p3 acc_53_fu_3811_p3 in_index_1_fu_3177_p2 icmp_ln154_fu_3183_p2 in_index_fu_3189_p3 w_index_fu_3197_p2 icmp_ln135_fu_3203_p2 outidx_3_U w7_U" + } + ] + }] + }, + { + "ModuleName": "relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s", + "InstanceName": "relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_U0", + "BindInstances": "icmp_ln51_fu_349_p2 out_data_67_fu_365_p3 icmp_ln51_220_fu_373_p2 out_data_69_fu_389_p3 icmp_ln51_221_fu_397_p2 out_data_71_fu_413_p3 icmp_ln51_222_fu_421_p2 out_data_73_fu_437_p3 icmp_ln51_223_fu_445_p2 select_ln51_fu_461_p3 icmp_ln51_224_fu_469_p2 select_ln51_228_fu_485_p3 icmp_ln51_225_fu_493_p2 select_ln51_229_fu_509_p3 icmp_ln51_226_fu_517_p2 select_ln51_230_fu_533_p3 icmp_ln51_227_fu_541_p2 select_ln51_231_fu_557_p3 icmp_ln51_228_fu_565_p2 select_ln51_232_fu_581_p3 icmp_ln51_229_fu_589_p2 select_ln51_233_fu_605_p3 icmp_ln51_230_fu_613_p2 select_ln51_234_fu_629_p3 icmp_ln51_231_fu_637_p2 select_ln51_235_fu_653_p3 icmp_ln51_232_fu_661_p2 select_ln51_236_fu_677_p3 icmp_ln51_233_fu_685_p2 select_ln51_237_fu_701_p3 icmp_ln51_234_fu_709_p2 select_ln51_238_fu_725_p3 i_fu_733_p2 icmp_ln41_fu_739_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s", + "InstanceName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_U0", + "Instances": [ + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth_fu_22", + "BindInstances": "icmp_ln53_fu_54_p2 j_41_fu_60_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain_fu_28", + "BindInstances": "icmp_ln59_fu_69_p2 i_28_fu_75_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth_fu_36", + "BindInstances": "icmp_ln77_fu_54_p2 j_42_fu_60_p2" + } + ] + }, + { + "ModuleName": "conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s", + "InstanceName": "conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_U0", + "BindInstances": "icmp_ln52_fu_860_p2 add_ln52_fu_866_p2", + "Instances": [{ + "ModuleName": "compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s", + "InstanceName": "grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s_fu_468", + "BindInstances": "icmp_ln284_fu_1227_p2 icmp_ln284_22_fu_1245_p2 icmp_ln284_23_fu_1261_p2 icmp_ln284_24_fu_1277_p2 and_ln284_fu_1283_p2 and_ln284_8_fu_1289_p2 add_ln303_fu_1380_p2 icmp_ln303_fu_1385_p2 add_ln318_fu_1397_p2 select_ln318_fu_1402_p3 add_ln307_fu_1427_p2 icmp_ln307_fu_1432_p2 icmp_ln313_fu_1444_p2 add_ln313_fu_1449_p2 select_ln313_fu_1454_p3", + "Instances": [ + { + "ModuleName": "shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s", + "InstanceName": "call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_fu_541", + "BindInstances": "p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_799_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_815_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_800_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_816_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_807_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_823_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_808_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_824_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_809_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_825_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_810_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_826_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_811_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_827_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_812_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_828_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_813_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_829_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_814_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_830_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_801_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_817_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_802_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_818_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_803_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_819_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_804_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_820_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_805_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_821_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_806_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_822_U" + }, + { + "ModuleName": "dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s", + "InstanceName": "grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_fu_929", + "BindInstances": "sparsemux_289_8_16_1_1_U618 mac_muladd_16s_16s_39s_39_1_1_U619 mac_muladd_16s_16s_39s_39_1_1_U619 mac_muladd_16s_16s_39s_39_1_1_U619 mac_muladd_16s_16s_39s_39_1_1_U620 mac_muladd_16s_16s_39s_39_1_1_U620 mac_muladd_16s_16s_39s_39_1_1_U620 mac_muladd_16s_16s_39s_39_1_1_U621 mac_muladd_16s_16s_39s_39_1_1_U621 mac_muladd_16s_16s_39s_39_1_1_U621 mac_muladd_16s_16s_39s_39_1_1_U622 mac_muladd_16s_16s_39s_39_1_1_U622 mac_muladd_16s_16s_39s_39_1_1_U622 mac_muladd_16s_16s_39s_39_1_1_U623 mac_muladd_16s_16s_39s_39_1_1_U623 mac_muladd_16s_16s_39s_39_1_1_U623 mac_muladd_16s_16s_39s_39_1_1_U624 mac_muladd_16s_16s_39s_39_1_1_U624 mac_muladd_16s_16s_39s_39_1_1_U624 mac_muladd_16s_16s_39s_39_1_1_U625 mac_muladd_16s_16s_39s_39_1_1_U625 mac_muladd_16s_16s_39s_39_1_1_U625 mac_muladd_16s_16s_39s_39_1_1_U626 mac_muladd_16s_16s_39s_39_1_1_U626 mac_muladd_16s_16s_39s_39_1_1_U626 mac_muladd_16s_16s_39s_39_1_1_U627 mac_muladd_16s_16s_39s_39_1_1_U627 mac_muladd_16s_16s_39s_39_1_1_U627 mac_muladd_16s_16s_39s_39_1_1_U628 mac_muladd_16s_16s_39s_39_1_1_U628 mac_muladd_16s_16s_39s_39_1_1_U628 mac_muladd_16s_16s_39s_39_1_1_U629 mac_muladd_16s_16s_39s_39_1_1_U629 mac_muladd_16s_16s_39s_39_1_1_U629 mac_muladd_16s_16s_39s_39_1_1_U630 mac_muladd_16s_16s_39s_39_1_1_U630 mac_muladd_16s_16s_39s_39_1_1_U630 mac_muladd_16s_16s_39s_39_1_1_U631 mac_muladd_16s_16s_39s_39_1_1_U631 mac_muladd_16s_16s_39s_39_1_1_U631 mac_muladd_16s_16s_39s_39_1_1_U632 mac_muladd_16s_16s_39s_39_1_1_U632 mac_muladd_16s_16s_39s_39_1_1_U632 mac_muladd_16s_16s_39s_39_1_1_U633 mac_muladd_16s_16s_39s_39_1_1_U633 mac_muladd_16s_16s_39s_39_1_1_U633 mac_muladd_16s_11s_34s_34_1_1_U634 mac_muladd_16s_11s_34s_34_1_1_U634 mac_muladd_16s_11s_34s_34_1_1_U634 w_index_fu_5301_p2 icmp_ln46_fu_5307_p2 w9_U" + } + ] + }] + }, + { + "ModuleName": "relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s", + "InstanceName": "relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_U0", + "BindInstances": "icmp_ln51_fu_349_p2 out_data_88_fu_365_p3 icmp_ln51_250_fu_373_p2 out_data_90_fu_389_p3 icmp_ln51_251_fu_397_p2 out_data_92_fu_413_p3 icmp_ln51_252_fu_421_p2 out_data_94_fu_437_p3 icmp_ln51_253_fu_445_p2 select_ln51_fu_461_p3 icmp_ln51_254_fu_469_p2 select_ln51_252_fu_485_p3 icmp_ln51_255_fu_493_p2 select_ln51_253_fu_509_p3 icmp_ln51_256_fu_517_p2 select_ln51_254_fu_533_p3 icmp_ln51_257_fu_541_p2 select_ln51_255_fu_557_p3 icmp_ln51_258_fu_565_p2 select_ln51_256_fu_581_p3 icmp_ln51_259_fu_589_p2 select_ln51_257_fu_605_p3 icmp_ln51_260_fu_613_p2 select_ln51_258_fu_629_p3 icmp_ln51_261_fu_637_p2 select_ln51_259_fu_653_p3 icmp_ln51_262_fu_661_p2 select_ln51_260_fu_677_p3 icmp_ln51_263_fu_685_p2 select_ln51_261_fu_701_p3 icmp_ln51_264_fu_709_p2 select_ln51_262_fu_725_p3 i_fu_733_p2 icmp_ln41_fu_739_p2" + }, + { + "ModuleName": "clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s", + "InstanceName": "clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_U0", + "BindInstances": "i_fu_72_p2 icmp_ln22_fu_78_p2" + }, + { + "ModuleName": "pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s", + "InstanceName": "pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0", + "BindInstances": "icmp_ln55_fu_492_p2 add_ln109_fu_502_p2 icmp_ln55_7_fu_512_p2 icmp_ln55_8_fu_522_p2 icmp_ln55_9_fu_528_p2 and_ln55_fu_534_p2 and_ln55_3_fu_540_p2 icmp_ln66_fu_851_p2 xor_ln66_fu_857_p2 select_ln0_fu_863_p3 icmp_ln66_119_fu_871_p2 xor_ln66_119_fu_877_p2 select_ln0_79_fu_883_p3 icmp_ln66_120_fu_891_p2 xor_ln66_120_fu_897_p2 res_pack_fu_903_p3 icmp_ln66_121_fu_927_p2 xor_ln66_121_fu_933_p2 select_ln0_80_fu_939_p3 icmp_ln66_122_fu_947_p2 xor_ln66_122_fu_953_p2 select_ln0_81_fu_959_p3 icmp_ln66_123_fu_967_p2 xor_ln66_123_fu_973_p2 res_pack_39_fu_979_p3 icmp_ln66_124_fu_1003_p2 xor_ln66_124_fu_1009_p2 select_ln0_82_fu_1015_p3 icmp_ln66_125_fu_1023_p2 xor_ln66_125_fu_1029_p2 select_ln0_83_fu_1035_p3 icmp_ln66_126_fu_1043_p2 xor_ln66_126_fu_1049_p2 res_pack_40_fu_1055_p3 icmp_ln66_127_fu_1079_p2 xor_ln66_127_fu_1085_p2 select_ln0_84_fu_1091_p3 icmp_ln66_128_fu_1099_p2 xor_ln66_128_fu_1105_p2 select_ln0_85_fu_1111_p3 icmp_ln66_129_fu_1119_p2 xor_ln66_129_fu_1125_p2 res_pack_41_fu_1131_p3 icmp_ln66_130_fu_1155_p2 xor_ln66_130_fu_1161_p2 select_ln0_86_fu_1167_p3 icmp_ln66_131_fu_1175_p2 xor_ln66_131_fu_1181_p2 select_ln0_87_fu_1187_p3 icmp_ln66_132_fu_1195_p2 xor_ln66_132_fu_1201_p2 res_pack_42_fu_1207_p3 icmp_ln66_133_fu_1231_p2 xor_ln66_133_fu_1237_p2 select_ln0_88_fu_1243_p3 icmp_ln66_134_fu_1251_p2 xor_ln66_134_fu_1257_p2 select_ln0_89_fu_1263_p3 icmp_ln66_135_fu_1271_p2 xor_ln66_135_fu_1277_p2 res_pack_43_fu_1283_p3 icmp_ln66_136_fu_1307_p2 xor_ln66_136_fu_1313_p2 select_ln0_90_fu_1319_p3 icmp_ln66_137_fu_1327_p2 xor_ln66_137_fu_1333_p2 select_ln0_91_fu_1339_p3 icmp_ln66_138_fu_1347_p2 xor_ln66_138_fu_1353_p2 res_pack_44_fu_1359_p3 icmp_ln66_139_fu_1383_p2 xor_ln66_139_fu_1389_p2 select_ln0_92_fu_1395_p3 icmp_ln66_140_fu_1403_p2 xor_ln66_140_fu_1409_p2 select_ln0_93_fu_1415_p3 icmp_ln66_141_fu_1423_p2 xor_ln66_141_fu_1429_p2 res_pack_45_fu_1435_p3 icmp_ln66_142_fu_1459_p2 xor_ln66_142_fu_1465_p2 select_ln0_94_fu_1471_p3 icmp_ln66_143_fu_1479_p2 xor_ln66_143_fu_1485_p2 select_ln0_95_fu_1491_p3 icmp_ln66_144_fu_1499_p2 xor_ln66_144_fu_1505_p2 res_pack_46_fu_1511_p3 icmp_ln66_145_fu_1535_p2 xor_ln66_145_fu_1541_p2 select_ln0_96_fu_1547_p3 icmp_ln66_146_fu_1555_p2 xor_ln66_146_fu_1561_p2 select_ln0_97_fu_1567_p3 icmp_ln66_147_fu_1575_p2 xor_ln66_147_fu_1581_p2 res_pack_47_fu_1587_p3 icmp_ln66_148_fu_1611_p2 xor_ln66_148_fu_1617_p2 select_ln0_98_fu_1623_p3 icmp_ln66_149_fu_1631_p2 xor_ln66_149_fu_1637_p2 select_ln0_99_fu_1643_p3 icmp_ln66_150_fu_1651_p2 xor_ln66_150_fu_1657_p2 res_pack_48_fu_1663_p3 icmp_ln66_151_fu_1687_p2 xor_ln66_151_fu_1693_p2 select_ln0_100_fu_1699_p3 icmp_ln66_152_fu_1707_p2 xor_ln66_152_fu_1713_p2 select_ln0_101_fu_1719_p3 icmp_ln66_153_fu_1727_p2 xor_ln66_153_fu_1733_p2 res_pack_49_fu_1739_p3 icmp_ln66_154_fu_1763_p2 xor_ln66_154_fu_1769_p2 select_ln0_102_fu_1775_p3 icmp_ln66_155_fu_1783_p2 xor_ln66_155_fu_1789_p2 select_ln0_103_fu_1795_p3 icmp_ln66_156_fu_1803_p2 xor_ln66_156_fu_1809_p2 res_pack_50_fu_1815_p3 icmp_ln66_157_fu_1839_p2 xor_ln66_157_fu_1845_p2 select_ln0_104_fu_1851_p3 icmp_ln66_158_fu_1859_p2 xor_ln66_158_fu_1865_p2 select_ln0_105_fu_1871_p3 icmp_ln66_159_fu_1879_p2 xor_ln66_159_fu_1885_p2 res_pack_51_fu_1891_p3 icmp_ln66_160_fu_1915_p2 xor_ln66_160_fu_1921_p2 select_ln0_106_fu_1927_p3 icmp_ln66_161_fu_1935_p2 xor_ln66_161_fu_1941_p2 select_ln0_107_fu_1947_p3 icmp_ln66_162_fu_1955_p2 xor_ln66_162_fu_1961_p2 res_pack_52_fu_1967_p3 icmp_ln66_163_fu_1991_p2 xor_ln66_163_fu_1997_p2 select_ln0_108_fu_2003_p3 icmp_ln66_164_fu_2011_p2 xor_ln66_164_fu_2017_p2 select_ln0_109_fu_2023_p3 icmp_ln66_165_fu_2031_p2 xor_ln66_165_fu_2037_p2 res_pack_53_fu_2043_p3 add_ln76_fu_546_p2 icmp_ln76_fu_552_p2 add_ln91_fu_564_p2 select_ln91_fu_570_p3 add_ln80_fu_600_p2 icmp_ln80_fu_606_p2 icmp_ln86_fu_622_p2 add_ln86_fu_628_p2 select_ln86_fu_634_p3 icmp_ln109_fu_648_p2", + "Instances": [{ + "ModuleName": "shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s", + "InstanceName": "call_ln52_shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_fu_300", + "BindInstances": "void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_U void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_1_U void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_2_U void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_3_U void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_4_U void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_5_U void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_6_U void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_7_U void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_8_U void_pooling2d_cl_stream_stream_array_ap_fixed_16u_0_line_buffer_9_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_27_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_26_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_25_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_24_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_23_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_22_U" + }] + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_s", + "InstanceName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_U0", + "Instances": [ + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth_fu_22", + "BindInstances": "icmp_ln53_fu_54_p2 j_38_fu_60_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain_fu_28", + "BindInstances": "icmp_ln59_fu_69_p2 i_26_fu_75_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth_fu_36", + "BindInstances": "icmp_ln77_fu_54_p2 j_39_fu_60_p2" + } + ] + }, + { + "ModuleName": "conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s", + "InstanceName": "conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0", + "BindInstances": "icmp_ln52_fu_864_p2 add_ln52_fu_870_p2", + "Instances": [{ + "ModuleName": "compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s", + "InstanceName": "grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470", + "BindInstances": "icmp_ln284_fu_1231_p2 icmp_ln284_19_fu_1249_p2 icmp_ln284_20_fu_1265_p2 icmp_ln284_21_fu_1281_p2 and_ln284_fu_1287_p2 and_ln284_7_fu_1293_p2 add_ln303_fu_1496_p2 icmp_ln303_fu_1501_p2 add_ln318_fu_1513_p2 select_ln318_fu_1518_p3 add_ln307_fu_1543_p2 icmp_ln307_fu_1548_p2 icmp_ln313_fu_1560_p2 add_ln313_fu_1565_p2 select_ln313_fu_1570_p3", + "Instances": [ + { + "ModuleName": "shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s", + "InstanceName": "call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_fu_543", + "BindInstances": "p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_863_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_879_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_864_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_880_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_871_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_887_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_872_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_888_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_873_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_889_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_874_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_890_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_875_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_891_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_876_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_892_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_877_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_893_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_878_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_894_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_865_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_881_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_866_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_882_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_867_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_883_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_868_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_884_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_869_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_885_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_870_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_886_U" + }, + { + "ModuleName": "dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s", + "InstanceName": "grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s_fu_931", + "BindInstances": "sparsemux_289_8_16_1_1_U1057 mac_muladd_16s_16s_41s_42_1_1_U1066 sparsemux_9_2_41_1_1_U1058 mac_muladd_16s_16s_41s_42_1_1_U1066 mac_muladd_16s_16s_41s_42_1_1_U1066 icmp_ln144_fu_6311_p2 icmp_ln144_69_fu_6316_p2 icmp_ln144_70_fu_6321_p2 icmp_ln144_71_fu_6326_p2 or_ln144_fu_6331_p2 or_ln144_68_fu_6337_p2 or_ln144_69_fu_6343_p2 acc_588_fu_6349_p3 mac_muladd_16s_16s_41s_42_1_1_U1067 sparsemux_9_2_41_1_1_U1059 acc_559_fu_6386_p3 acc_558_fu_6394_p3 acc_557_fu_6402_p3 or_ln144_70_fu_6410_p2 acc_fu_6416_p3 mac_muladd_16s_16s_41s_42_1_1_U1067 mac_muladd_16s_16s_41s_42_1_1_U1067 icmp_ln144_72_fu_6428_p2 or_ln144_71_fu_6433_p2 or_ln144_72_fu_6439_p2 acc_590_fu_6445_p3 mac_muladd_16s_16s_41s_42_1_1_U1068 sparsemux_9_2_41_1_1_U1060 acc_563_fu_6482_p3 acc_562_fu_6490_p3 acc_561_fu_6498_p3 acc_560_fu_6506_p3 mac_muladd_16s_16s_41s_42_1_1_U1068 mac_muladd_16s_16s_41s_42_1_1_U1068 icmp_ln144_73_fu_6518_p2 or_ln144_73_fu_6523_p2 or_ln144_74_fu_6529_p2 acc_592_fu_6535_p3 mac_muladd_16s_16s_41s_42_1_1_U1069 sparsemux_9_2_41_1_1_U1061 acc_567_fu_6572_p3 acc_566_fu_6580_p3 acc_565_fu_6588_p3 acc_564_fu_6596_p3 mac_muladd_16s_16s_41s_42_1_1_U1069 mac_muladd_16s_16s_41s_42_1_1_U1069 icmp_ln144_74_fu_6608_p2 or_ln144_75_fu_6969_p2 or_ln144_76_fu_6973_p2 or_ln144_77_fu_6977_p2 acc_594_fu_6983_p3 mac_muladd_16s_16s_41s_42_1_1_U1070 sparsemux_9_2_41_1_1_U1062 acc_571_fu_6642_p3 acc_570_fu_6650_p3 acc_569_fu_6658_p3 or_ln144_78_fu_6991_p2 acc_568_fu_6996_p3 mac_muladd_16s_16s_41s_42_1_1_U1070 mac_muladd_16s_16s_41s_42_1_1_U1070 icmp_ln144_75_fu_6670_p2 or_ln144_79_fu_6675_p2 or_ln144_80_fu_6681_p2 acc_596_fu_6687_p3 mac_muladd_16s_16s_41s_42_1_1_U1071 sparsemux_9_2_41_1_1_U1063 acc_575_fu_6724_p3 acc_574_fu_6732_p3 acc_573_fu_6740_p3 acc_572_fu_6748_p3 mac_muladd_16s_16s_41s_42_1_1_U1071 mac_muladd_16s_16s_41s_42_1_1_U1071 icmp_ln144_76_fu_6760_p2 or_ln144_81_fu_6765_p2 or_ln144_82_fu_6771_p2 acc_598_fu_6777_p3 mac_muladd_16s_16s_41s_42_1_1_U1072 sparsemux_9_2_41_1_1_U1064 acc_579_fu_6814_p3 acc_578_fu_6822_p3 acc_577_fu_6830_p3 acc_576_fu_6838_p3 mac_muladd_16s_16s_41s_42_1_1_U1072 mac_muladd_16s_16s_41s_42_1_1_U1072 icmp_ln144_77_fu_6850_p2 or_ln144_83_fu_6855_p2 or_ln144_84_fu_6861_p2 acc_600_fu_6867_p3 mac_muladd_16s_10s_41s_42_1_1_U1073 sparsemux_9_2_41_1_1_U1065 acc_583_fu_6904_p3 acc_582_fu_6912_p3 acc_581_fu_6920_p3 acc_580_fu_6928_p3 mac_muladd_16s_10s_41s_42_1_1_U1073 mac_muladd_16s_10s_41s_42_1_1_U1073 icmp_ln144_78_fu_6940_p2 icmp_ln144_79_fu_6945_p2 xor_ln144_fu_7003_p2 or_ln144_85_fu_7008_p2 or_ln144_86_fu_7013_p2 or_ln144_87_fu_7017_p2 acc_603_fu_7023_p3 and_ln144_fu_7031_p2 acc_602_fu_7035_p3 acc_587_fu_7043_p3 or_ln144_88_fu_7049_p2 or_ln144_89_fu_7053_p2 acc_586_fu_7058_p3 acc_585_fu_6953_p3 acc_584_fu_6961_p3 in_index_10_fu_6255_p2 icmp_ln154_fu_6261_p2 in_index_fu_6267_p3 w_index_fu_5581_p2 icmp_ln135_fu_5587_p2 outidx_4_U w12_U" + } + ] + }] + }, + { + "ModuleName": "relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s", + "InstanceName": "relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_U0", + "BindInstances": "icmp_ln51_fu_637_p2 out_data_60_fu_653_p3 icmp_ln51_189_fu_661_p2 out_data_62_fu_677_p3 icmp_ln51_190_fu_685_p2 out_data_64_fu_701_p3 icmp_ln51_191_fu_709_p2 out_data_66_fu_725_p3 icmp_ln51_192_fu_733_p2 select_ln51_fu_749_p3 icmp_ln51_193_fu_757_p2 select_ln51_197_fu_773_p3 icmp_ln51_194_fu_781_p2 select_ln51_198_fu_797_p3 icmp_ln51_195_fu_805_p2 select_ln51_199_fu_821_p3 icmp_ln51_196_fu_829_p2 select_ln51_200_fu_845_p3 icmp_ln51_197_fu_853_p2 select_ln51_201_fu_869_p3 icmp_ln51_198_fu_877_p2 select_ln51_202_fu_893_p3 icmp_ln51_199_fu_901_p2 select_ln51_203_fu_917_p3 icmp_ln51_200_fu_925_p2 select_ln51_204_fu_941_p3 icmp_ln51_201_fu_949_p2 select_ln51_205_fu_965_p3 icmp_ln51_202_fu_973_p2 select_ln51_206_fu_989_p3 icmp_ln51_203_fu_997_p2 select_ln51_207_fu_1013_p3 icmp_ln51_204_fu_1021_p2 select_ln51_208_fu_1037_p3 icmp_ln51_205_fu_1045_p2 select_ln51_209_fu_1061_p3 icmp_ln51_206_fu_1069_p2 select_ln51_210_fu_1085_p3 icmp_ln51_207_fu_1093_p2 select_ln51_211_fu_1109_p3 icmp_ln51_208_fu_1117_p2 select_ln51_212_fu_1133_p3 icmp_ln51_209_fu_1141_p2 select_ln51_213_fu_1157_p3 icmp_ln51_210_fu_1165_p2 select_ln51_214_fu_1181_p3 icmp_ln51_211_fu_1189_p2 select_ln51_215_fu_1205_p3 icmp_ln51_212_fu_1213_p2 select_ln51_216_fu_1229_p3 icmp_ln51_213_fu_1237_p2 select_ln51_217_fu_1253_p3 icmp_ln51_214_fu_1261_p2 select_ln51_218_fu_1277_p3 icmp_ln51_215_fu_1285_p2 select_ln51_219_fu_1301_p3 icmp_ln51_216_fu_1309_p2 select_ln51_220_fu_1325_p3 icmp_ln51_217_fu_1333_p2 select_ln51_221_fu_1349_p3 icmp_ln51_218_fu_1357_p2 select_ln51_222_fu_1373_p3 icmp_ln51_219_fu_1381_p2 select_ln51_223_fu_1397_p3 i_fu_1405_p2 icmp_ln41_fu_1411_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s", + "InstanceName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0", + "Instances": [ + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth_fu_22", + "BindInstances": "icmp_ln53_fu_54_p2 j_28_fu_60_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain_fu_28", + "BindInstances": "icmp_ln59_fu_69_p2 i_18_fu_75_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth_fu_36", + "BindInstances": "icmp_ln77_fu_54_p2 j_29_fu_60_p2" + } + ] + }, + { + "ModuleName": "conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s", + "InstanceName": "conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_U0", + "BindInstances": "icmp_ln52_fu_1648_p2 add_ln52_fu_1654_p2", + "Instances": [{ + "ModuleName": "compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s", + "InstanceName": "grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886", + "BindInstances": "icmp_ln284_fu_2383_p2 icmp_ln284_10_fu_2401_p2 icmp_ln284_11_fu_2417_p2 icmp_ln284_12_fu_2433_p2 and_ln284_fu_2439_p2 and_ln284_4_fu_2445_p2 add_ln303_fu_2616_p2 icmp_ln303_fu_2621_p2 add_ln318_fu_2633_p2 select_ln318_fu_2638_p3 add_ln307_fu_2663_p2 icmp_ln307_fu_2668_p2 icmp_ln313_fu_2680_p2 add_ln313_fu_2685_p2 select_ln313_fu_2690_p3", + "Instances": [ + { + "ModuleName": "shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s", + "InstanceName": "call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_fu_1023", + "BindInstances": "p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_943_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_975_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_944_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_976_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_955_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_987_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_966_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_998_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_969_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1001_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_970_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1002_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_971_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1003_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_972_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1004_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_973_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1005_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_974_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1006_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_945_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_977_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_946_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_978_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_947_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_979_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_948_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_980_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_949_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_981_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_950_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_982_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_951_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_983_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_952_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_984_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_953_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_985_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_954_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_986_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_956_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_988_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_957_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_989_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_958_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_990_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_959_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_991_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_960_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_992_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_961_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_993_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_962_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_994_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_963_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_995_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_964_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_996_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_965_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_997_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_967_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_999_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_968_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1000_U" + }, + { + "ModuleName": "dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s", + "InstanceName": "grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_fu_1795", + "BindInstances": "sparsemux_577_9_16_1_1_U1570 mac_muladd_16s_16s_42s_43_1_1_U1571 select_ln144_fu_11733_p3 mac_muladd_16s_16s_42s_43_1_1_U1571 mac_muladd_16s_16s_42s_43_1_1_U1571 icmp_ln144_fu_12183_p2 select_ln144_160_fu_12188_p3 select_ln144_161_fu_12195_p3 acc_479_fu_12202_p3 acc_478_fu_12210_p3 mac_muladd_16s_16s_42s_43_1_1_U1572 select_ln144_162_fu_11762_p3 acc_526_fu_12218_p3 acc_525_fu_12224_p3 mac_muladd_16s_16s_42s_43_1_1_U1572 mac_muladd_16s_16s_42s_43_1_1_U1572 icmp_ln144_54_fu_12230_p2 select_ln144_165_fu_12235_p3 select_ln144_166_fu_12242_p3 acc_481_fu_12249_p3 acc_fu_12257_p3 mac_muladd_16s_16s_42s_43_1_1_U1573 select_ln144_167_fu_11791_p3 acc_528_fu_12265_p3 acc_527_fu_12271_p3 mac_muladd_16s_16s_42s_43_1_1_U1573 mac_muladd_16s_16s_42s_43_1_1_U1573 icmp_ln144_55_fu_12277_p2 select_ln144_170_fu_12282_p3 select_ln144_171_fu_12289_p3 acc_484_fu_12296_p3 acc_483_fu_12304_p3 mac_muladd_16s_16s_42s_43_1_1_U1574 select_ln144_172_fu_11820_p3 acc_530_fu_12312_p3 acc_529_fu_12318_p3 mac_muladd_16s_16s_42s_43_1_1_U1574 mac_muladd_16s_16s_42s_43_1_1_U1574 icmp_ln144_56_fu_12324_p2 select_ln144_175_fu_12329_p3 select_ln144_176_fu_12336_p3 acc_487_fu_12343_p3 acc_486_fu_12351_p3 mac_muladd_16s_16s_42s_43_1_1_U1575 select_ln144_177_fu_11849_p3 acc_532_fu_12359_p3 acc_531_fu_12365_p3 mac_muladd_16s_16s_42s_43_1_1_U1575 mac_muladd_16s_16s_42s_43_1_1_U1575 icmp_ln144_57_fu_12371_p2 select_ln144_180_fu_12376_p3 select_ln144_181_fu_12383_p3 acc_490_fu_12390_p3 acc_489_fu_12398_p3 mac_muladd_16s_16s_42s_43_1_1_U1576 select_ln144_182_fu_11878_p3 acc_534_fu_12406_p3 acc_533_fu_12412_p3 mac_muladd_16s_16s_42s_43_1_1_U1576 mac_muladd_16s_16s_42s_43_1_1_U1576 icmp_ln144_58_fu_12418_p2 select_ln144_185_fu_12423_p3 select_ln144_186_fu_12430_p3 acc_493_fu_12437_p3 acc_492_fu_12445_p3 mac_muladd_16s_16s_42s_43_1_1_U1577 select_ln144_187_fu_11907_p3 acc_536_fu_12453_p3 acc_535_fu_12459_p3 mac_muladd_16s_16s_42s_43_1_1_U1577 mac_muladd_16s_16s_42s_43_1_1_U1577 icmp_ln144_59_fu_12465_p2 select_ln144_190_fu_12470_p3 select_ln144_191_fu_12477_p3 acc_496_fu_12484_p3 acc_495_fu_12492_p3 mac_muladd_16s_16s_42s_43_1_1_U1578 select_ln144_192_fu_11936_p3 acc_538_fu_12500_p3 acc_537_fu_12506_p3 mac_muladd_16s_16s_42s_43_1_1_U1578 mac_muladd_16s_16s_42s_43_1_1_U1578 icmp_ln144_60_fu_12512_p2 select_ln144_195_fu_12517_p3 select_ln144_196_fu_12524_p3 acc_499_fu_12531_p3 acc_498_fu_12539_p3 mac_muladd_16s_16s_42s_43_1_1_U1579 select_ln144_197_fu_11965_p3 acc_540_fu_12547_p3 acc_539_fu_12553_p3 mac_muladd_16s_16s_42s_43_1_1_U1579 mac_muladd_16s_16s_42s_43_1_1_U1579 icmp_ln144_61_fu_12559_p2 select_ln144_200_fu_12564_p3 select_ln144_201_fu_12571_p3 acc_502_fu_12578_p3 acc_501_fu_12586_p3 mac_muladd_16s_16s_42s_43_1_1_U1580 select_ln144_202_fu_11994_p3 acc_542_fu_12594_p3 acc_541_fu_12600_p3 mac_muladd_16s_16s_42s_43_1_1_U1580 mac_muladd_16s_16s_42s_43_1_1_U1580 icmp_ln144_62_fu_12606_p2 select_ln144_205_fu_12611_p3 select_ln144_206_fu_12618_p3 acc_505_fu_12625_p3 acc_504_fu_12633_p3 mac_muladd_16s_16s_42s_43_1_1_U1581 select_ln144_207_fu_12023_p3 acc_544_fu_12641_p3 acc_543_fu_12647_p3 mac_muladd_16s_16s_42s_43_1_1_U1581 mac_muladd_16s_16s_42s_43_1_1_U1581 icmp_ln144_63_fu_12653_p2 select_ln144_210_fu_12658_p3 select_ln144_211_fu_12665_p3 acc_508_fu_12672_p3 acc_507_fu_12680_p3 mac_muladd_16s_16s_42s_43_1_1_U1582 select_ln144_212_fu_12052_p3 acc_546_fu_12688_p3 acc_545_fu_12694_p3 mac_muladd_16s_16s_42s_43_1_1_U1582 mac_muladd_16s_16s_42s_43_1_1_U1582 icmp_ln144_64_fu_12700_p2 select_ln144_215_fu_12705_p3 select_ln144_216_fu_12712_p3 acc_511_fu_12719_p3 acc_510_fu_12727_p3 mac_muladd_16s_16s_42s_43_1_1_U1583 select_ln144_217_fu_12081_p3 acc_548_fu_12735_p3 acc_547_fu_12741_p3 mac_muladd_16s_16s_42s_43_1_1_U1583 mac_muladd_16s_16s_42s_43_1_1_U1583 icmp_ln144_65_fu_12747_p2 select_ln144_220_fu_12752_p3 select_ln144_221_fu_12759_p3 acc_514_fu_12766_p3 acc_513_fu_12774_p3 mac_muladd_16s_16s_42s_43_1_1_U1584 select_ln144_222_fu_12110_p3 acc_550_fu_12782_p3 acc_549_fu_12788_p3 mac_muladd_16s_16s_42s_43_1_1_U1584 mac_muladd_16s_16s_42s_43_1_1_U1584 icmp_ln144_66_fu_12794_p2 select_ln144_225_fu_12799_p3 select_ln144_226_fu_12806_p3 acc_517_fu_12813_p3 acc_516_fu_12821_p3 mac_muladd_16s_16s_42s_43_1_1_U1585 select_ln144_227_fu_12139_p3 acc_552_fu_12829_p3 acc_551_fu_12835_p3 mac_muladd_16s_16s_42s_43_1_1_U1585 mac_muladd_16s_16s_42s_43_1_1_U1585 icmp_ln144_67_fu_12841_p2 select_ln144_230_fu_12846_p3 select_ln144_231_fu_12853_p3 acc_520_fu_12860_p3 acc_519_fu_12868_p3 mac_muladd_16s_10s_42s_43_1_1_U1586 select_ln144_232_fu_12168_p3 acc_554_fu_12876_p3 acc_553_fu_12882_p3 mac_muladd_16s_10s_42s_43_1_1_U1586 mac_muladd_16s_10s_42s_43_1_1_U1586 icmp_ln144_68_fu_12888_p2 select_ln144_235_fu_12893_p3 select_ln144_236_fu_12900_p3 acc_523_fu_12907_p3 acc_522_fu_12915_p3 acc_556_fu_12923_p3 acc_555_fu_12929_p3 in_index_9_fu_11687_p2 icmp_ln154_fu_11693_p2 in_index_fu_11699_p3 w_index_fu_11707_p2 icmp_ln135_fu_11713_p2 outidx_5_U w14_U" + } + ] + }] + }, + { + "ModuleName": "relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s", + "InstanceName": "relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_U0", + "BindInstances": "icmp_ln51_fu_637_p2 out_data_53_fu_653_p3 icmp_ln51_158_fu_661_p2 out_data_55_fu_677_p3 icmp_ln51_159_fu_685_p2 out_data_57_fu_701_p3 icmp_ln51_160_fu_709_p2 out_data_59_fu_725_p3 icmp_ln51_161_fu_733_p2 select_ln51_fu_749_p3 icmp_ln51_162_fu_757_p2 select_ln51_166_fu_773_p3 icmp_ln51_163_fu_781_p2 select_ln51_167_fu_797_p3 icmp_ln51_164_fu_805_p2 select_ln51_168_fu_821_p3 icmp_ln51_165_fu_829_p2 select_ln51_169_fu_845_p3 icmp_ln51_166_fu_853_p2 select_ln51_170_fu_869_p3 icmp_ln51_167_fu_877_p2 select_ln51_171_fu_893_p3 icmp_ln51_168_fu_901_p2 select_ln51_172_fu_917_p3 icmp_ln51_169_fu_925_p2 select_ln51_173_fu_941_p3 icmp_ln51_170_fu_949_p2 select_ln51_174_fu_965_p3 icmp_ln51_171_fu_973_p2 select_ln51_175_fu_989_p3 icmp_ln51_172_fu_997_p2 select_ln51_176_fu_1013_p3 icmp_ln51_173_fu_1021_p2 select_ln51_177_fu_1037_p3 icmp_ln51_174_fu_1045_p2 select_ln51_178_fu_1061_p3 icmp_ln51_175_fu_1069_p2 select_ln51_179_fu_1085_p3 icmp_ln51_176_fu_1093_p2 select_ln51_180_fu_1109_p3 icmp_ln51_177_fu_1117_p2 select_ln51_181_fu_1133_p3 icmp_ln51_178_fu_1141_p2 select_ln51_182_fu_1157_p3 icmp_ln51_179_fu_1165_p2 select_ln51_183_fu_1181_p3 icmp_ln51_180_fu_1189_p2 select_ln51_184_fu_1205_p3 icmp_ln51_181_fu_1213_p2 select_ln51_185_fu_1229_p3 icmp_ln51_182_fu_1237_p2 select_ln51_186_fu_1253_p3 icmp_ln51_183_fu_1261_p2 select_ln51_187_fu_1277_p3 icmp_ln51_184_fu_1285_p2 select_ln51_188_fu_1301_p3 icmp_ln51_185_fu_1309_p2 select_ln51_189_fu_1325_p3 icmp_ln51_186_fu_1333_p2 select_ln51_190_fu_1349_p3 icmp_ln51_187_fu_1357_p2 select_ln51_191_fu_1373_p3 icmp_ln51_188_fu_1381_p2 select_ln51_192_fu_1397_p3 i_fu_1405_p2 icmp_ln41_fu_1411_p2" + }, + { + "ModuleName": "clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s", + "InstanceName": "clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0", + "BindInstances": "i_fu_72_p2 icmp_ln22_fu_78_p2" + }, + { + "ModuleName": "pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s", + "InstanceName": "pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_U0", + "BindInstances": "icmp_ln55_fu_892_p2 add_ln109_fu_902_p2 icmp_ln55_4_fu_912_p2 icmp_ln55_5_fu_922_p2 icmp_ln55_6_fu_928_p2 and_ln55_fu_934_p2 and_ln55_2_fu_940_p2 icmp_ln66_fu_1427_p2 xor_ln66_fu_1433_p2 select_ln0_fu_1439_p3 icmp_ln66_24_fu_1447_p2 xor_ln66_24_fu_1453_p2 select_ln0_16_fu_1459_p3 icmp_ln66_25_fu_1467_p2 xor_ln66_25_fu_1473_p2 res_pack_fu_1479_p3 icmp_ln66_26_fu_1503_p2 xor_ln66_26_fu_1509_p2 select_ln0_17_fu_1515_p3 icmp_ln66_27_fu_1523_p2 xor_ln66_27_fu_1529_p2 select_ln0_18_fu_1535_p3 icmp_ln66_28_fu_1543_p2 xor_ln66_28_fu_1549_p2 res_pack_8_fu_1555_p3 icmp_ln66_29_fu_1579_p2 xor_ln66_29_fu_1585_p2 select_ln0_19_fu_1591_p3 icmp_ln66_30_fu_1599_p2 xor_ln66_30_fu_1605_p2 select_ln0_20_fu_1611_p3 icmp_ln66_31_fu_1619_p2 xor_ln66_31_fu_1625_p2 res_pack_9_fu_1631_p3 icmp_ln66_32_fu_1655_p2 xor_ln66_32_fu_1661_p2 select_ln0_21_fu_1667_p3 icmp_ln66_33_fu_1675_p2 xor_ln66_33_fu_1681_p2 select_ln0_22_fu_1687_p3 icmp_ln66_34_fu_1695_p2 xor_ln66_34_fu_1701_p2 res_pack_10_fu_1707_p3 icmp_ln66_35_fu_1731_p2 xor_ln66_35_fu_1737_p2 select_ln0_23_fu_1743_p3 icmp_ln66_36_fu_1751_p2 xor_ln66_36_fu_1757_p2 select_ln0_24_fu_1763_p3 icmp_ln66_37_fu_1771_p2 xor_ln66_37_fu_1777_p2 res_pack_11_fu_1783_p3 icmp_ln66_38_fu_1807_p2 xor_ln66_38_fu_1813_p2 select_ln0_25_fu_1819_p3 icmp_ln66_39_fu_1827_p2 xor_ln66_39_fu_1833_p2 select_ln0_26_fu_1839_p3 icmp_ln66_40_fu_1847_p2 xor_ln66_40_fu_1853_p2 res_pack_12_fu_1859_p3 icmp_ln66_41_fu_1883_p2 xor_ln66_41_fu_1889_p2 select_ln0_27_fu_1895_p3 icmp_ln66_42_fu_1903_p2 xor_ln66_42_fu_1909_p2 select_ln0_28_fu_1915_p3 icmp_ln66_43_fu_1923_p2 xor_ln66_43_fu_1929_p2 res_pack_13_fu_1935_p3 icmp_ln66_44_fu_1959_p2 xor_ln66_44_fu_1965_p2 select_ln0_29_fu_1971_p3 icmp_ln66_45_fu_1979_p2 xor_ln66_45_fu_1985_p2 select_ln0_30_fu_1991_p3 icmp_ln66_46_fu_1999_p2 xor_ln66_46_fu_2005_p2 res_pack_14_fu_2011_p3 icmp_ln66_47_fu_2035_p2 xor_ln66_47_fu_2041_p2 select_ln0_31_fu_2047_p3 icmp_ln66_48_fu_2055_p2 xor_ln66_48_fu_2061_p2 select_ln0_32_fu_2067_p3 icmp_ln66_49_fu_2075_p2 xor_ln66_49_fu_2081_p2 res_pack_15_fu_2087_p3 icmp_ln66_50_fu_2111_p2 xor_ln66_50_fu_2117_p2 select_ln0_33_fu_2123_p3 icmp_ln66_51_fu_2131_p2 xor_ln66_51_fu_2137_p2 select_ln0_34_fu_2143_p3 icmp_ln66_52_fu_2151_p2 xor_ln66_52_fu_2157_p2 res_pack_16_fu_2163_p3 icmp_ln66_53_fu_2187_p2 xor_ln66_53_fu_2193_p2 select_ln0_35_fu_2199_p3 icmp_ln66_54_fu_2207_p2 xor_ln66_54_fu_2213_p2 select_ln0_36_fu_2219_p3 icmp_ln66_55_fu_2227_p2 xor_ln66_55_fu_2233_p2 res_pack_17_fu_2239_p3 icmp_ln66_56_fu_2263_p2 xor_ln66_56_fu_2269_p2 select_ln0_37_fu_2275_p3 icmp_ln66_57_fu_2283_p2 xor_ln66_57_fu_2289_p2 select_ln0_38_fu_2295_p3 icmp_ln66_58_fu_2303_p2 xor_ln66_58_fu_2309_p2 res_pack_18_fu_2315_p3 icmp_ln66_59_fu_2339_p2 xor_ln66_59_fu_2345_p2 select_ln0_39_fu_2351_p3 icmp_ln66_60_fu_2359_p2 xor_ln66_60_fu_2365_p2 select_ln0_40_fu_2371_p3 icmp_ln66_61_fu_2379_p2 xor_ln66_61_fu_2385_p2 res_pack_19_fu_2391_p3 icmp_ln66_62_fu_2415_p2 xor_ln66_62_fu_2421_p2 select_ln0_41_fu_2427_p3 icmp_ln66_63_fu_2435_p2 xor_ln66_63_fu_2441_p2 select_ln0_42_fu_2447_p3 icmp_ln66_64_fu_2455_p2 xor_ln66_64_fu_2461_p2 res_pack_20_fu_2467_p3 icmp_ln66_65_fu_2491_p2 xor_ln66_65_fu_2497_p2 select_ln0_43_fu_2503_p3 icmp_ln66_66_fu_2511_p2 xor_ln66_66_fu_2517_p2 select_ln0_44_fu_2523_p3 icmp_ln66_67_fu_2531_p2 xor_ln66_67_fu_2537_p2 res_pack_21_fu_2543_p3 icmp_ln66_68_fu_2567_p2 xor_ln66_68_fu_2573_p2 select_ln0_45_fu_2579_p3 icmp_ln66_69_fu_2587_p2 xor_ln66_69_fu_2593_p2 select_ln0_46_fu_2599_p3 icmp_ln66_70_fu_2607_p2 xor_ln66_70_fu_2613_p2 res_pack_22_fu_2619_p3 icmp_ln66_71_fu_2643_p2 xor_ln66_71_fu_2649_p2 select_ln0_47_fu_2655_p3 icmp_ln66_72_fu_2663_p2 xor_ln66_72_fu_2669_p2 select_ln0_48_fu_2675_p3 icmp_ln66_73_fu_2683_p2 xor_ln66_73_fu_2689_p2 res_pack_23_fu_2695_p3 icmp_ln66_74_fu_2719_p2 xor_ln66_74_fu_2725_p2 select_ln0_49_fu_2731_p3 icmp_ln66_75_fu_2739_p2 xor_ln66_75_fu_2745_p2 select_ln0_50_fu_2751_p3 icmp_ln66_76_fu_2759_p2 xor_ln66_76_fu_2765_p2 res_pack_24_fu_2771_p3 icmp_ln66_77_fu_2795_p2 xor_ln66_77_fu_2801_p2 select_ln0_51_fu_2807_p3 icmp_ln66_78_fu_2815_p2 xor_ln66_78_fu_2821_p2 select_ln0_52_fu_2827_p3 icmp_ln66_79_fu_2835_p2 xor_ln66_79_fu_2841_p2 res_pack_25_fu_2847_p3 icmp_ln66_80_fu_2871_p2 xor_ln66_80_fu_2877_p2 select_ln0_53_fu_2883_p3 icmp_ln66_81_fu_2891_p2 xor_ln66_81_fu_2897_p2 select_ln0_54_fu_2903_p3 icmp_ln66_82_fu_2911_p2 xor_ln66_82_fu_2917_p2 res_pack_26_fu_2923_p3 icmp_ln66_83_fu_2947_p2 xor_ln66_83_fu_2953_p2 select_ln0_55_fu_2959_p3 icmp_ln66_84_fu_2967_p2 xor_ln66_84_fu_2973_p2 select_ln0_56_fu_2979_p3 icmp_ln66_85_fu_2987_p2 xor_ln66_85_fu_2993_p2 res_pack_27_fu_2999_p3 icmp_ln66_86_fu_3023_p2 xor_ln66_86_fu_3029_p2 select_ln0_57_fu_3035_p3 icmp_ln66_87_fu_3043_p2 xor_ln66_87_fu_3049_p2 select_ln0_58_fu_3055_p3 icmp_ln66_88_fu_3063_p2 xor_ln66_88_fu_3069_p2 res_pack_28_fu_3075_p3 icmp_ln66_89_fu_3099_p2 xor_ln66_89_fu_3105_p2 select_ln0_59_fu_3111_p3 icmp_ln66_90_fu_3119_p2 xor_ln66_90_fu_3125_p2 select_ln0_60_fu_3131_p3 icmp_ln66_91_fu_3139_p2 xor_ln66_91_fu_3145_p2 res_pack_29_fu_3151_p3 icmp_ln66_92_fu_3175_p2 xor_ln66_92_fu_3181_p2 select_ln0_61_fu_3187_p3 icmp_ln66_93_fu_3195_p2 xor_ln66_93_fu_3201_p2 select_ln0_62_fu_3207_p3 icmp_ln66_94_fu_3215_p2 xor_ln66_94_fu_3221_p2 res_pack_30_fu_3227_p3 icmp_ln66_95_fu_3251_p2 xor_ln66_95_fu_3257_p2 select_ln0_63_fu_3263_p3 icmp_ln66_96_fu_3271_p2 xor_ln66_96_fu_3277_p2 select_ln0_64_fu_3283_p3 icmp_ln66_97_fu_3291_p2 xor_ln66_97_fu_3297_p2 res_pack_31_fu_3303_p3 icmp_ln66_98_fu_3327_p2 xor_ln66_98_fu_3333_p2 select_ln0_65_fu_3339_p3 icmp_ln66_99_fu_3347_p2 xor_ln66_99_fu_3353_p2 select_ln0_66_fu_3359_p3 icmp_ln66_100_fu_3367_p2 xor_ln66_100_fu_3373_p2 res_pack_32_fu_3379_p3 icmp_ln66_101_fu_3403_p2 xor_ln66_101_fu_3409_p2 select_ln0_67_fu_3415_p3 icmp_ln66_102_fu_3423_p2 xor_ln66_102_fu_3429_p2 select_ln0_68_fu_3435_p3 icmp_ln66_103_fu_3443_p2 xor_ln66_103_fu_3449_p2 res_pack_33_fu_3455_p3 icmp_ln66_104_fu_3479_p2 xor_ln66_104_fu_3485_p2 select_ln0_69_fu_3491_p3 icmp_ln66_105_fu_3499_p2 xor_ln66_105_fu_3505_p2 select_ln0_70_fu_3511_p3 icmp_ln66_106_fu_3519_p2 xor_ln66_106_fu_3525_p2 res_pack_34_fu_3531_p3 icmp_ln66_107_fu_3555_p2 xor_ln66_107_fu_3561_p2 select_ln0_71_fu_3567_p3 icmp_ln66_108_fu_3575_p2 xor_ln66_108_fu_3581_p2 select_ln0_72_fu_3587_p3 icmp_ln66_109_fu_3595_p2 xor_ln66_109_fu_3601_p2 res_pack_35_fu_3607_p3 icmp_ln66_110_fu_3631_p2 xor_ln66_110_fu_3637_p2 select_ln0_73_fu_3643_p3 icmp_ln66_111_fu_3651_p2 xor_ln66_111_fu_3657_p2 select_ln0_74_fu_3663_p3 icmp_ln66_112_fu_3671_p2 xor_ln66_112_fu_3677_p2 res_pack_36_fu_3683_p3 icmp_ln66_113_fu_3707_p2 xor_ln66_113_fu_3713_p2 select_ln0_75_fu_3719_p3 icmp_ln66_114_fu_3727_p2 xor_ln66_114_fu_3733_p2 select_ln0_76_fu_3739_p3 icmp_ln66_115_fu_3747_p2 xor_ln66_115_fu_3753_p2 res_pack_37_fu_3759_p3 icmp_ln66_116_fu_3783_p2 xor_ln66_116_fu_3789_p2 select_ln0_77_fu_3795_p3 icmp_ln66_117_fu_3803_p2 xor_ln66_117_fu_3809_p2 select_ln0_78_fu_3815_p3 icmp_ln66_118_fu_3823_p2 xor_ln66_118_fu_3829_p2 res_pack_38_fu_3835_p3 add_ln76_fu_946_p2 icmp_ln76_fu_952_p2 add_ln91_fu_964_p2 select_ln91_fu_970_p3 add_ln80_fu_1000_p2 icmp_ln80_fu_1006_p2 icmp_ln86_fu_1022_p2 add_ln86_fu_1028_p2 select_ln86_fu_1034_p3 icmp_ln109_fu_1048_p2", + "Instances": [{ + "ModuleName": "shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s", + "InstanceName": "call_ln52_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_fu_524", + "BindInstances": "void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_9_U void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_8_U void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_7_U void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_6_U void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_5_U void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_4_U void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_3_U void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_2_U void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_1_U void_pooling2d_cl_stream_stream_array_ap_fixed_32u_0_line_buffer_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_21_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_20_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_19_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_18_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_17_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_16_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_15_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_14_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_13_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_12_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_11_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_10_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_9_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_8_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_7_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_6_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_5_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_4_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_3_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_2_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_1_U p_ZZN4nnet12pooling2d_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_o_mode3EL_U" + }] + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_s", + "InstanceName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_U0", + "Instances": [ + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth_fu_22", + "BindInstances": "icmp_ln53_fu_54_p2 j_25_fu_60_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain_fu_28", + "BindInstances": "icmp_ln59_fu_69_p2 i_16_fu_75_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth_fu_36", + "BindInstances": "icmp_ln77_fu_54_p2 j_26_fu_60_p2" + } + ] + }, + { + "ModuleName": "conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s", + "InstanceName": "conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_U0", + "BindInstances": "icmp_ln52_fu_1648_p2 add_ln52_fu_1654_p2", + "Instances": [{ + "ModuleName": "compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s", + "InstanceName": "grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886", + "BindInstances": "icmp_ln284_fu_2383_p2 icmp_ln284_4_fu_2401_p2 icmp_ln284_6_fu_2417_p2 icmp_ln284_7_fu_2433_p2 and_ln284_fu_2439_p2 and_ln284_2_fu_2445_p2 add_ln303_fu_2840_p2 icmp_ln303_fu_2845_p2 add_ln318_fu_2857_p2 select_ln318_fu_2862_p3 add_ln307_fu_2887_p2 icmp_ln307_fu_2892_p2 icmp_ln313_fu_2904_p2 add_ln313_fu_2909_p2 select_ln313_fu_2914_p3", + "Instances": [ + { + "ModuleName": "shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s", + "InstanceName": "call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_fu_1023", + "BindInstances": "p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1071_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1103_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1072_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1104_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1083_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1115_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1094_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1126_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1097_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1129_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1098_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1130_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1099_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1131_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1100_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1132_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1101_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1133_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1102_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1134_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1073_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1105_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1074_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1106_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1075_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1107_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1076_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1108_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1077_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1109_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1078_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1110_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1079_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1111_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1080_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1112_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1081_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1113_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1082_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1114_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1084_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1116_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1085_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1117_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1086_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1118_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1087_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1119_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1088_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1120_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1089_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1121_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1090_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1122_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1091_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1123_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1092_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1124_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1093_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1125_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1095_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1127_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1096_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1128_U" + }, + { + "ModuleName": "dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s", + "InstanceName": "grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s_fu_1795", + "BindInstances": "sparsemux_577_9_16_1_1_U2410 mac_muladd_16s_16s_42s_43_1_1_U2427 sparsemux_9_2_42_1_1_U2411 mac_muladd_16s_16s_42s_43_1_1_U2427 mac_muladd_16s_16s_42s_43_1_1_U2427 icmp_ln144_fu_12406_p2 icmp_ln144_41_fu_12411_p2 icmp_ln144_42_fu_12416_p2 icmp_ln144_43_fu_12421_p2 or_ln144_fu_12426_p2 or_ln144_30_fu_12432_p2 or_ln144_31_fu_12438_p2 acc_389_fu_12444_p3 mac_muladd_16s_16s_42s_43_1_1_U2428 sparsemux_9_2_42_1_1_U2412 acc_353_fu_12481_p3 acc_352_fu_12489_p3 acc_351_fu_12497_p3 or_ln144_32_fu_12505_p2 acc_fu_12511_p3 mac_muladd_16s_16s_42s_43_1_1_U2428 mac_muladd_16s_16s_42s_43_1_1_U2428 icmp_ln144_44_fu_12523_p2 or_ln144_33_fu_12528_p2 or_ln144_34_fu_12534_p2 acc_395_fu_12540_p3 mac_muladd_16s_16s_42s_43_1_1_U2429 sparsemux_9_2_42_1_1_U2413 acc_357_fu_12577_p3 acc_356_fu_12585_p3 acc_355_fu_12593_p3 acc_354_fu_12601_p3 mac_muladd_16s_16s_42s_43_1_1_U2429 mac_muladd_16s_16s_42s_43_1_1_U2429 icmp_ln144_45_fu_12613_p2 or_ln144_35_fu_12618_p2 or_ln144_36_fu_12624_p2 acc_401_fu_12630_p3 mac_muladd_16s_16s_42s_43_1_1_U2430 sparsemux_9_2_42_1_1_U2414 acc_361_fu_12667_p3 acc_360_fu_12675_p3 acc_359_fu_12683_p3 acc_358_fu_12691_p3 mac_muladd_16s_16s_42s_43_1_1_U2430 mac_muladd_16s_16s_42s_43_1_1_U2430 icmp_ln144_46_fu_12703_p2 or_ln144_37_fu_12708_p2 or_ln144_38_fu_12714_p2 acc_407_fu_12720_p3 mac_muladd_16s_16s_42s_43_1_1_U2431 sparsemux_9_2_42_1_1_U2415 acc_365_fu_12757_p3 acc_364_fu_12765_p3 acc_363_fu_12773_p3 acc_362_fu_12781_p3 mac_muladd_16s_16s_42s_43_1_1_U2431 mac_muladd_16s_16s_42s_43_1_1_U2431 icmp_ln144_47_fu_12793_p2 or_ln144_39_fu_12798_p2 or_ln144_40_fu_12804_p2 acc_413_fu_12810_p3 mac_muladd_16s_16s_42s_43_1_1_U2432 sparsemux_9_2_42_1_1_U2416 acc_369_fu_12847_p3 acc_368_fu_12855_p3 acc_367_fu_12863_p3 acc_366_fu_12871_p3 mac_muladd_16s_16s_42s_43_1_1_U2432 mac_muladd_16s_16s_42s_43_1_1_U2432 icmp_ln144_48_fu_12883_p2 or_ln144_41_fu_12888_p2 or_ln144_42_fu_12894_p2 acc_419_fu_12900_p3 mac_muladd_16s_16s_42s_43_1_1_U2433 sparsemux_9_2_42_1_1_U2417 acc_373_fu_12937_p3 acc_372_fu_12945_p3 acc_371_fu_12953_p3 acc_370_fu_12961_p3 mac_muladd_16s_16s_42s_43_1_1_U2433 mac_muladd_16s_16s_42s_43_1_1_U2433 icmp_ln144_49_fu_12973_p2 or_ln144_43_fu_12978_p2 or_ln144_44_fu_12984_p2 or_ln144_45_fu_12990_p2 acc_425_fu_12996_p3 mac_muladd_16s_16s_42s_43_1_1_U2434 sparsemux_9_2_42_1_1_U2418 acc_377_fu_13033_p3 acc_376_fu_13041_p3 acc_375_fu_13049_p3 or_ln144_46_fu_13057_p2 acc_374_fu_13063_p3 mac_muladd_16s_16s_42s_43_1_1_U2434 mac_muladd_16s_16s_42s_43_1_1_U2434 icmp_ln144_50_fu_13075_p2 or_ln144_47_fu_13080_p2 or_ln144_48_fu_13086_p2 acc_428_fu_13092_p3 mac_muladd_16s_16s_42s_43_1_1_U2435 sparsemux_9_2_42_1_1_U2419 acc_381_fu_13129_p3 acc_380_fu_13137_p3 acc_379_fu_13145_p3 acc_378_fu_13153_p3 mac_muladd_16s_16s_42s_43_1_1_U2435 mac_muladd_16s_16s_42s_43_1_1_U2435 icmp_ln144_51_fu_13165_p2 or_ln144_49_fu_13170_p2 or_ln144_50_fu_13176_p2 acc_430_fu_13182_p3 mac_muladd_16s_16s_42s_43_1_1_U2436 sparsemux_9_2_42_1_1_U2420 acc_385_fu_13219_p3 acc_384_fu_13227_p3 acc_383_fu_13235_p3 acc_382_fu_13243_p3 mac_muladd_16s_16s_42s_43_1_1_U2436 mac_muladd_16s_16s_42s_43_1_1_U2436 icmp_ln144_52_fu_13255_p2 or_ln144_51_fu_13260_p2 or_ln144_52_fu_13266_p2 acc_432_fu_13272_p3 mac_muladd_16s_16s_42s_43_1_1_U2437 sparsemux_9_2_42_1_1_U2421 acc_390_fu_13309_p3 acc_388_fu_13317_p3 acc_387_fu_13325_p3 acc_386_fu_13333_p3 mac_muladd_16s_16s_42s_43_1_1_U2437 mac_muladd_16s_16s_42s_43_1_1_U2437 icmp_ln144_54_fu_13345_p2 or_ln144_53_fu_13350_p2 or_ln144_54_fu_13356_p2 acc_434_fu_13362_p3 mac_muladd_16s_16s_42s_43_1_1_U2438 sparsemux_9_2_42_1_1_U2422 acc_394_fu_13399_p3 acc_393_fu_13407_p3 acc_392_fu_13415_p3 acc_391_fu_13423_p3 mac_muladd_16s_16s_42s_43_1_1_U2438 mac_muladd_16s_16s_42s_43_1_1_U2438 icmp_ln144_55_fu_13435_p2 or_ln144_55_fu_13440_p2 or_ln144_56_fu_13446_p2 acc_436_fu_13452_p3 mac_muladd_16s_16s_42s_43_1_1_U2439 sparsemux_9_2_42_1_1_U2423 acc_399_fu_13489_p3 acc_398_fu_13497_p3 acc_397_fu_13505_p3 acc_396_fu_13513_p3 mac_muladd_16s_16s_42s_43_1_1_U2439 mac_muladd_16s_16s_42s_43_1_1_U2439 icmp_ln144_56_fu_13525_p2 or_ln144_57_fu_13530_p2 or_ln144_58_fu_13536_p2 acc_438_fu_13542_p3 mac_muladd_16s_16s_42s_43_1_1_U2440 sparsemux_9_2_42_1_1_U2424 acc_404_fu_13579_p3 acc_403_fu_13587_p3 acc_402_fu_13595_p3 acc_400_fu_13603_p3 mac_muladd_16s_16s_42s_43_1_1_U2440 mac_muladd_16s_16s_42s_43_1_1_U2440 icmp_ln144_58_fu_13615_p2 or_ln144_59_fu_13620_p2 or_ln144_60_fu_13626_p2 acc_440_fu_13632_p3 mac_muladd_16s_16s_42s_43_1_1_U2441 sparsemux_9_2_42_1_1_U2425 acc_409_fu_13669_p3 acc_408_fu_13677_p3 acc_406_fu_13685_p3 acc_405_fu_13693_p3 mac_muladd_16s_16s_42s_43_1_1_U2441 mac_muladd_16s_16s_42s_43_1_1_U2441 icmp_ln144_59_fu_13705_p2 or_ln144_61_fu_13710_p2 or_ln144_62_fu_13716_p2 acc_442_fu_13722_p3 mac_muladd_16s_10s_42s_43_1_1_U2442 sparsemux_9_2_42_1_1_U2426 acc_414_fu_13759_p3 acc_412_fu_13767_p3 acc_411_fu_13775_p3 acc_410_fu_13783_p3 mac_muladd_16s_10s_42s_43_1_1_U2442 mac_muladd_16s_10s_42s_43_1_1_U2442 icmp_ln144_53_fu_13795_p2 icmp_ln144_57_fu_13800_p2 xor_ln144_fu_13824_p2 or_ln144_63_fu_13829_p2 or_ln144_64_fu_13834_p2 or_ln144_65_fu_13838_p2 acc_445_fu_13844_p3 and_ln144_fu_13852_p2 acc_444_fu_13856_p3 acc_418_fu_13864_p3 or_ln144_66_fu_13870_p2 or_ln144_67_fu_13874_p2 acc_417_fu_13879_p3 acc_416_fu_13808_p3 acc_415_fu_13816_p3 in_index_8_fu_12350_p2 icmp_ln154_fu_12356_p2 in_index_fu_12362_p3 w_index_fu_11020_p2 icmp_ln135_fu_11026_p2 outidx_6_U w17_U" + } + ] + }] + }, + { + "ModuleName": "relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s", + "InstanceName": "relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_U0", + "BindInstances": "icmp_ln51_fu_1213_p2 out_data_33_fu_1229_p3 icmp_ln51_64_fu_1237_p2 out_data_35_fu_1253_p3 icmp_ln51_65_fu_1261_p2 out_data_37_fu_1277_p3 icmp_ln51_66_fu_1285_p2 out_data_39_fu_1301_p3 icmp_ln51_67_fu_1309_p2 select_ln51_fu_1325_p3 icmp_ln51_68_fu_1333_p2 select_ln51_68_fu_1349_p3 icmp_ln51_69_fu_1357_p2 select_ln51_69_fu_1373_p3 icmp_ln51_70_fu_1381_p2 select_ln51_70_fu_1397_p3 icmp_ln51_71_fu_1405_p2 select_ln51_71_fu_1421_p3 icmp_ln51_72_fu_1429_p2 select_ln51_72_fu_1445_p3 icmp_ln51_73_fu_1453_p2 select_ln51_73_fu_1469_p3 icmp_ln51_74_fu_1477_p2 select_ln51_74_fu_1493_p3 icmp_ln51_75_fu_1501_p2 select_ln51_75_fu_1517_p3 icmp_ln51_76_fu_1525_p2 select_ln51_76_fu_1541_p3 icmp_ln51_77_fu_1549_p2 select_ln51_77_fu_1565_p3 icmp_ln51_78_fu_1573_p2 select_ln51_78_fu_1589_p3 icmp_ln51_79_fu_1597_p2 select_ln51_79_fu_1613_p3 icmp_ln51_80_fu_1621_p2 select_ln51_80_fu_1637_p3 icmp_ln51_81_fu_1645_p2 select_ln51_81_fu_1661_p3 icmp_ln51_82_fu_1669_p2 select_ln51_82_fu_1685_p3 icmp_ln51_83_fu_1693_p2 select_ln51_83_fu_1709_p3 icmp_ln51_84_fu_1717_p2 select_ln51_84_fu_1733_p3 icmp_ln51_85_fu_1741_p2 select_ln51_85_fu_1757_p3 icmp_ln51_86_fu_1765_p2 select_ln51_86_fu_1781_p3 icmp_ln51_87_fu_1789_p2 select_ln51_87_fu_1805_p3 icmp_ln51_88_fu_1813_p2 select_ln51_88_fu_1829_p3 icmp_ln51_89_fu_1837_p2 select_ln51_89_fu_1853_p3 icmp_ln51_90_fu_1861_p2 select_ln51_90_fu_1877_p3 icmp_ln51_91_fu_1885_p2 select_ln51_91_fu_1901_p3 icmp_ln51_92_fu_1909_p2 select_ln51_92_fu_1925_p3 icmp_ln51_93_fu_1933_p2 select_ln51_93_fu_1949_p3 icmp_ln51_94_fu_1957_p2 select_ln51_94_fu_1973_p3 icmp_ln51_95_fu_1981_p2 select_ln51_95_fu_1997_p3 icmp_ln51_96_fu_2005_p2 select_ln51_96_fu_2021_p3 icmp_ln51_97_fu_2029_p2 select_ln51_97_fu_2045_p3 icmp_ln51_98_fu_2053_p2 select_ln51_98_fu_2069_p3 icmp_ln51_99_fu_2077_p2 select_ln51_99_fu_2093_p3 icmp_ln51_100_fu_2101_p2 select_ln51_100_fu_2117_p3 icmp_ln51_101_fu_2125_p2 select_ln51_101_fu_2141_p3 icmp_ln51_102_fu_2149_p2 select_ln51_102_fu_2165_p3 icmp_ln51_103_fu_2173_p2 select_ln51_103_fu_2189_p3 icmp_ln51_104_fu_2197_p2 select_ln51_104_fu_2213_p3 icmp_ln51_105_fu_2221_p2 select_ln51_105_fu_2237_p3 icmp_ln51_106_fu_2245_p2 select_ln51_106_fu_2261_p3 icmp_ln51_107_fu_2269_p2 select_ln51_107_fu_2285_p3 icmp_ln51_108_fu_2293_p2 select_ln51_108_fu_2309_p3 icmp_ln51_109_fu_2317_p2 select_ln51_109_fu_2333_p3 icmp_ln51_110_fu_2341_p2 select_ln51_110_fu_2357_p3 icmp_ln51_111_fu_2365_p2 select_ln51_111_fu_2381_p3 icmp_ln51_112_fu_2389_p2 select_ln51_112_fu_2405_p3 icmp_ln51_113_fu_2413_p2 select_ln51_113_fu_2429_p3 icmp_ln51_114_fu_2437_p2 select_ln51_114_fu_2453_p3 icmp_ln51_115_fu_2461_p2 select_ln51_115_fu_2477_p3 icmp_ln51_116_fu_2485_p2 select_ln51_116_fu_2501_p3 icmp_ln51_117_fu_2509_p2 select_ln51_117_fu_2525_p3 icmp_ln51_118_fu_2533_p2 select_ln51_118_fu_2549_p3 icmp_ln51_119_fu_2557_p2 select_ln51_119_fu_2573_p3 icmp_ln51_120_fu_2581_p2 select_ln51_120_fu_2597_p3 icmp_ln51_121_fu_2605_p2 select_ln51_121_fu_2621_p3 icmp_ln51_122_fu_2629_p2 select_ln51_122_fu_2645_p3 icmp_ln51_123_fu_2653_p2 select_ln51_123_fu_2669_p3 icmp_ln51_124_fu_2677_p2 select_ln51_124_fu_2693_p3 icmp_ln51_125_fu_2701_p2 select_ln51_125_fu_2717_p3 icmp_ln51_126_fu_2725_p2 select_ln51_126_fu_2741_p3 i_fu_2749_p2 icmp_ln41_fu_2755_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_s", + "InstanceName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_U0", + "Instances": [ + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth_fu_22", + "BindInstances": "icmp_ln53_fu_54_p2 j_16_fu_60_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain_fu_28", + "BindInstances": "icmp_ln59_fu_69_p2 i_10_fu_75_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth_fu_36", + "BindInstances": "icmp_ln77_fu_54_p2 j_17_fu_60_p2" + } + ] + }, + { + "ModuleName": "conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s", + "InstanceName": "conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_U0", + "BindInstances": "icmp_ln52_fu_3216_p2 add_ln52_fu_3222_p2", + "Instances": [{ + "ModuleName": "compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s", + "InstanceName": "grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718", + "BindInstances": "icmp_ln284_fu_4687_p2 icmp_ln284_1_fu_4705_p2 icmp_ln284_2_fu_4721_p2 icmp_ln284_3_fu_4737_p2 and_ln284_fu_4743_p2 and_ln284_1_fu_4749_p2 add_ln303_fu_5080_p2 icmp_ln303_fu_5085_p2 add_ln318_fu_5097_p2 select_ln318_fu_5102_p3 add_ln307_fu_5127_p2 icmp_ln307_fu_5132_p2 icmp_ln313_fu_5144_p2 add_ln313_fu_5149_p2 select_ln313_fu_5154_p3", + "Instances": [ + { + "ModuleName": "shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s", + "InstanceName": "call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_fu_1983", + "BindInstances": "p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1231_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1295_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1232_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1296_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1243_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1307_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1254_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1318_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1265_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1329_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1276_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1340_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1287_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1351_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1292_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1356_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1293_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1357_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1294_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1358_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1233_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1297_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1234_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1298_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1235_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1299_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1236_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1300_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1237_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1301_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1238_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1302_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1239_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1303_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1240_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1304_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1241_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1305_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1242_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1306_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1244_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1308_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1245_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1309_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1246_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1310_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1247_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1311_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1248_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1312_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1249_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1313_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1250_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1314_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1251_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1315_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1252_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1316_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1253_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1317_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1255_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1319_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1256_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1320_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1257_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1321_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1258_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1322_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1259_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1323_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1260_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1324_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1261_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1325_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1262_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1326_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1263_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1327_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1264_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1328_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1266_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1330_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1267_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1331_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1268_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1332_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1269_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1333_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1270_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1334_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1271_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1335_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1272_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1336_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1273_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1337_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1274_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1338_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1275_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1339_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1277_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1341_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1278_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1342_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1279_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1343_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1280_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1344_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1281_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1345_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1282_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1346_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1283_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1347_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1284_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1348_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1285_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1349_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1286_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1350_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1288_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1352_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1289_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1353_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1290_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1354_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1291_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1355_U" + }, + { + "ModuleName": "dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s", + "InstanceName": "grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s_fu_3523", + "BindInstances": "sparsemux_1153_10_16_1_1_U3417 mac_muladd_16s_16s_43s_44_1_1_U3418 select_ln144_fu_23285_p3 mac_muladd_16s_16s_43s_44_1_1_U3418 mac_muladd_16s_16s_43s_44_1_1_U3418 icmp_ln144_fu_24199_p2 select_ln144_1_fu_24204_p3 select_ln144_2_fu_24211_p3 acc_65_fu_24218_p3 acc_64_fu_24226_p3 mac_muladd_16s_16s_43s_44_1_1_U3419 select_ln144_3_fu_23314_p3 acc_288_fu_24234_p3 acc_287_fu_24240_p3 mac_muladd_16s_16s_43s_44_1_1_U3419 mac_muladd_16s_16s_43s_44_1_1_U3419 icmp_ln144_1_fu_24246_p2 select_ln144_6_fu_24251_p3 select_ln144_7_fu_24258_p3 acc_70_fu_24265_p3 acc_69_fu_24273_p3 mac_muladd_16s_16s_43s_44_1_1_U3420 select_ln144_8_fu_23343_p3 acc_290_fu_24281_p3 acc_289_fu_24287_p3 mac_muladd_16s_16s_43s_44_1_1_U3420 mac_muladd_16s_16s_43s_44_1_1_U3420 icmp_ln144_2_fu_24293_p2 select_ln144_11_fu_24298_p3 select_ln144_12_fu_24305_p3 acc_75_fu_24312_p3 acc_74_fu_24320_p3 mac_muladd_16s_16s_43s_44_1_1_U3421 select_ln144_13_fu_23372_p3 acc_292_fu_24328_p3 acc_291_fu_24334_p3 mac_muladd_16s_16s_43s_44_1_1_U3421 mac_muladd_16s_16s_43s_44_1_1_U3421 icmp_ln144_3_fu_24340_p2 select_ln144_16_fu_24345_p3 select_ln144_17_fu_24352_p3 acc_80_fu_24359_p3 acc_79_fu_24367_p3 mac_muladd_16s_16s_43s_44_1_1_U3422 select_ln144_18_fu_23401_p3 acc_294_fu_24375_p3 acc_293_fu_24381_p3 mac_muladd_16s_16s_43s_44_1_1_U3422 mac_muladd_16s_16s_43s_44_1_1_U3422 icmp_ln144_4_fu_24387_p2 select_ln144_21_fu_24392_p3 select_ln144_22_fu_24399_p3 acc_85_fu_24406_p3 acc_84_fu_24414_p3 mac_muladd_16s_16s_43s_44_1_1_U3423 select_ln144_23_fu_23430_p3 acc_296_fu_24422_p3 acc_295_fu_24428_p3 mac_muladd_16s_16s_43s_44_1_1_U3423 mac_muladd_16s_16s_43s_44_1_1_U3423 icmp_ln144_5_fu_24434_p2 select_ln144_26_fu_24439_p3 select_ln144_27_fu_24446_p3 acc_90_fu_24453_p3 acc_89_fu_24461_p3 mac_muladd_16s_16s_43s_44_1_1_U3424 select_ln144_28_fu_23459_p3 acc_298_fu_24469_p3 acc_297_fu_24475_p3 mac_muladd_16s_16s_43s_44_1_1_U3424 mac_muladd_16s_16s_43s_44_1_1_U3424 icmp_ln144_6_fu_24481_p2 select_ln144_31_fu_24486_p3 select_ln144_32_fu_24493_p3 acc_95_fu_24500_p3 acc_94_fu_24508_p3 mac_muladd_16s_16s_43s_44_1_1_U3425 select_ln144_33_fu_23488_p3 acc_300_fu_24516_p3 acc_299_fu_24522_p3 mac_muladd_16s_16s_43s_44_1_1_U3425 mac_muladd_16s_16s_43s_44_1_1_U3425 icmp_ln144_7_fu_24528_p2 select_ln144_36_fu_24533_p3 select_ln144_37_fu_24540_p3 acc_100_fu_24547_p3 acc_99_fu_24555_p3 mac_muladd_16s_16s_43s_44_1_1_U3426 select_ln144_38_fu_23517_p3 acc_302_fu_24563_p3 acc_301_fu_24569_p3 mac_muladd_16s_16s_43s_44_1_1_U3426 mac_muladd_16s_16s_43s_44_1_1_U3426 icmp_ln144_8_fu_24575_p2 select_ln144_41_fu_24580_p3 select_ln144_42_fu_24587_p3 acc_105_fu_24594_p3 acc_104_fu_24602_p3 mac_muladd_16s_16s_43s_44_1_1_U3427 select_ln144_43_fu_23546_p3 acc_304_fu_24610_p3 acc_303_fu_24616_p3 mac_muladd_16s_16s_43s_44_1_1_U3427 mac_muladd_16s_16s_43s_44_1_1_U3427 icmp_ln144_9_fu_24622_p2 select_ln144_46_fu_24627_p3 select_ln144_47_fu_24634_p3 acc_110_fu_24641_p3 acc_109_fu_24649_p3 mac_muladd_16s_16s_43s_44_1_1_U3428 select_ln144_48_fu_23575_p3 acc_306_fu_24657_p3 acc_305_fu_24663_p3 mac_muladd_16s_16s_43s_44_1_1_U3428 mac_muladd_16s_16s_43s_44_1_1_U3428 icmp_ln144_10_fu_24669_p2 select_ln144_51_fu_24674_p3 select_ln144_52_fu_24681_p3 acc_115_fu_24688_p3 acc_114_fu_24696_p3 mac_muladd_16s_16s_43s_44_1_1_U3429 select_ln144_53_fu_23604_p3 acc_308_fu_24704_p3 acc_307_fu_24710_p3 mac_muladd_16s_16s_43s_44_1_1_U3429 mac_muladd_16s_16s_43s_44_1_1_U3429 icmp_ln144_11_fu_24716_p2 select_ln144_56_fu_24721_p3 select_ln144_57_fu_24728_p3 acc_120_fu_24735_p3 acc_119_fu_24743_p3 mac_muladd_16s_16s_43s_44_1_1_U3430 select_ln144_58_fu_23633_p3 acc_310_fu_24751_p3 acc_309_fu_24757_p3 mac_muladd_16s_16s_43s_44_1_1_U3430 mac_muladd_16s_16s_43s_44_1_1_U3430 icmp_ln144_12_fu_24763_p2 select_ln144_61_fu_24768_p3 select_ln144_62_fu_24775_p3 acc_125_fu_24782_p3 acc_124_fu_24790_p3 mac_muladd_16s_16s_43s_44_1_1_U3431 select_ln144_63_fu_23662_p3 acc_312_fu_24798_p3 acc_311_fu_24804_p3 mac_muladd_16s_16s_43s_44_1_1_U3431 mac_muladd_16s_16s_43s_44_1_1_U3431 icmp_ln144_13_fu_24810_p2 select_ln144_66_fu_24815_p3 select_ln144_67_fu_24822_p3 acc_130_fu_24829_p3 acc_129_fu_24837_p3 mac_muladd_16s_16s_43s_44_1_1_U3432 select_ln144_68_fu_23691_p3 acc_314_fu_24845_p3 acc_313_fu_24851_p3 mac_muladd_16s_16s_43s_44_1_1_U3432 mac_muladd_16s_16s_43s_44_1_1_U3432 icmp_ln144_14_fu_24857_p2 select_ln144_71_fu_24862_p3 select_ln144_72_fu_24869_p3 acc_135_fu_24876_p3 acc_134_fu_24884_p3 mac_muladd_16s_16s_43s_44_1_1_U3433 select_ln144_73_fu_23720_p3 acc_316_fu_24892_p3 acc_315_fu_24898_p3 mac_muladd_16s_16s_43s_44_1_1_U3433 mac_muladd_16s_16s_43s_44_1_1_U3433 icmp_ln144_15_fu_24904_p2 select_ln144_76_fu_24909_p3 select_ln144_77_fu_24916_p3 acc_140_fu_24923_p3 acc_139_fu_24931_p3 mac_muladd_16s_16s_43s_44_1_1_U3434 select_ln144_78_fu_23749_p3 acc_318_fu_24939_p3 acc_317_fu_24945_p3 mac_muladd_16s_16s_43s_44_1_1_U3434 mac_muladd_16s_16s_43s_44_1_1_U3434 icmp_ln144_16_fu_24951_p2 select_ln144_81_fu_24956_p3 select_ln144_82_fu_24963_p3 acc_145_fu_24970_p3 acc_144_fu_24978_p3 mac_muladd_16s_16s_43s_44_1_1_U3435 select_ln144_83_fu_23778_p3 acc_320_fu_24986_p3 acc_319_fu_24992_p3 mac_muladd_16s_16s_43s_44_1_1_U3435 mac_muladd_16s_16s_43s_44_1_1_U3435 icmp_ln144_17_fu_24998_p2 select_ln144_86_fu_25003_p3 select_ln144_87_fu_25010_p3 acc_150_fu_25017_p3 acc_149_fu_25025_p3 mac_muladd_16s_16s_43s_44_1_1_U3436 select_ln144_88_fu_23807_p3 acc_322_fu_25033_p3 acc_321_fu_25039_p3 mac_muladd_16s_16s_43s_44_1_1_U3436 mac_muladd_16s_16s_43s_44_1_1_U3436 icmp_ln144_18_fu_25045_p2 select_ln144_91_fu_25050_p3 select_ln144_92_fu_25057_p3 acc_155_fu_25064_p3 acc_154_fu_25072_p3 mac_muladd_16s_16s_43s_44_1_1_U3437 select_ln144_93_fu_23836_p3 acc_324_fu_25080_p3 acc_323_fu_25086_p3 mac_muladd_16s_16s_43s_44_1_1_U3437 mac_muladd_16s_16s_43s_44_1_1_U3437 icmp_ln144_19_fu_25092_p2 select_ln144_96_fu_25097_p3 select_ln144_97_fu_25104_p3 acc_160_fu_25111_p3 acc_159_fu_25119_p3 mac_muladd_16s_16s_43s_44_1_1_U3438 select_ln144_98_fu_23865_p3 acc_326_fu_25127_p3 acc_325_fu_25133_p3 mac_muladd_16s_16s_43s_44_1_1_U3438 mac_muladd_16s_16s_43s_44_1_1_U3438 icmp_ln144_20_fu_25139_p2 select_ln144_101_fu_25144_p3 select_ln144_102_fu_25151_p3 acc_165_fu_25158_p3 acc_164_fu_25166_p3 mac_muladd_16s_16s_43s_44_1_1_U3439 select_ln144_103_fu_23894_p3 acc_328_fu_25174_p3 acc_327_fu_25180_p3 mac_muladd_16s_16s_43s_44_1_1_U3439 mac_muladd_16s_16s_43s_44_1_1_U3439 icmp_ln144_21_fu_25186_p2 select_ln144_106_fu_25191_p3 select_ln144_107_fu_25198_p3 acc_170_fu_25205_p3 acc_169_fu_25213_p3 mac_muladd_16s_16s_43s_44_1_1_U3440 select_ln144_108_fu_23923_p3 acc_330_fu_25221_p3 acc_329_fu_25227_p3 mac_muladd_16s_16s_43s_44_1_1_U3440 mac_muladd_16s_16s_43s_44_1_1_U3440 icmp_ln144_22_fu_25233_p2 select_ln144_111_fu_25238_p3 select_ln144_112_fu_25245_p3 acc_175_fu_25252_p3 acc_174_fu_25260_p3 mac_muladd_16s_16s_43s_44_1_1_U3441 select_ln144_113_fu_23952_p3 acc_332_fu_25268_p3 acc_331_fu_25274_p3 mac_muladd_16s_16s_43s_44_1_1_U3441 mac_muladd_16s_16s_43s_44_1_1_U3441 icmp_ln144_23_fu_25280_p2 select_ln144_116_fu_25285_p3 select_ln144_117_fu_25292_p3 acc_180_fu_25299_p3 acc_179_fu_25307_p3 mac_muladd_16s_16s_43s_44_1_1_U3442 select_ln144_118_fu_23981_p3 acc_334_fu_25315_p3 acc_333_fu_25321_p3 mac_muladd_16s_16s_43s_44_1_1_U3442 mac_muladd_16s_16s_43s_44_1_1_U3442 icmp_ln144_24_fu_25327_p2 select_ln144_121_fu_25332_p3 select_ln144_122_fu_25339_p3 acc_185_fu_25346_p3 acc_184_fu_25354_p3 mac_muladd_16s_16s_43s_44_1_1_U3443 select_ln144_123_fu_24010_p3 acc_336_fu_25362_p3 acc_335_fu_25368_p3 mac_muladd_16s_16s_43s_44_1_1_U3443 mac_muladd_16s_16s_43s_44_1_1_U3443 icmp_ln144_25_fu_25374_p2 select_ln144_126_fu_25379_p3 select_ln144_127_fu_25386_p3 acc_190_fu_25393_p3 acc_189_fu_25401_p3 mac_muladd_16s_16s_43s_44_1_1_U3444 select_ln144_128_fu_24039_p3 acc_338_fu_25409_p3 acc_337_fu_25415_p3 mac_muladd_16s_16s_43s_44_1_1_U3444 mac_muladd_16s_16s_43s_44_1_1_U3444 icmp_ln144_26_fu_25421_p2 select_ln144_131_fu_25426_p3 select_ln144_132_fu_25433_p3 acc_195_fu_25440_p3 acc_194_fu_25448_p3 mac_muladd_16s_16s_43s_44_1_1_U3445 select_ln144_133_fu_24068_p3 acc_340_fu_25456_p3 acc_339_fu_25462_p3 mac_muladd_16s_16s_43s_44_1_1_U3445 mac_muladd_16s_16s_43s_44_1_1_U3445 icmp_ln144_27_fu_25468_p2 select_ln144_136_fu_25473_p3 select_ln144_137_fu_25480_p3 acc_200_fu_25487_p3 acc_199_fu_25495_p3 mac_muladd_16s_16s_43s_44_1_1_U3446 select_ln144_138_fu_24097_p3 acc_342_fu_25503_p3 acc_341_fu_25509_p3 mac_muladd_16s_16s_43s_44_1_1_U3446 mac_muladd_16s_16s_43s_44_1_1_U3446 icmp_ln144_28_fu_25515_p2 select_ln144_141_fu_25520_p3 select_ln144_142_fu_25527_p3 acc_205_fu_25534_p3 acc_204_fu_25542_p3 mac_muladd_16s_16s_43s_44_1_1_U3447 select_ln144_143_fu_24126_p3 acc_344_fu_25550_p3 acc_343_fu_25556_p3 mac_muladd_16s_16s_43s_44_1_1_U3447 mac_muladd_16s_16s_43s_44_1_1_U3447 icmp_ln144_29_fu_25562_p2 select_ln144_146_fu_25567_p3 select_ln144_147_fu_25574_p3 acc_210_fu_25581_p3 acc_209_fu_25589_p3 mac_muladd_16s_16s_43s_44_1_1_U3448 select_ln144_148_fu_24155_p3 acc_346_fu_25597_p3 acc_345_fu_25603_p3 mac_muladd_16s_16s_43s_44_1_1_U3448 mac_muladd_16s_16s_43s_44_1_1_U3448 icmp_ln144_30_fu_25609_p2 select_ln144_151_fu_25614_p3 select_ln144_152_fu_25621_p3 acc_215_fu_25628_p3 acc_214_fu_25636_p3 mac_muladd_16s_9s_43s_44_1_1_U3449 select_ln144_153_fu_24184_p3 acc_348_fu_25644_p3 acc_347_fu_25650_p3 mac_muladd_16s_9s_43s_44_1_1_U3449 mac_muladd_16s_9s_43s_44_1_1_U3449 icmp_ln144_31_fu_25656_p2 select_ln144_156_fu_25661_p3 select_ln144_157_fu_25668_p3 acc_220_fu_25675_p3 acc_219_fu_25683_p3 acc_350_fu_25691_p3 acc_349_fu_25697_p3 in_index_7_fu_23239_p2 icmp_ln154_fu_23245_p2 in_index_fu_23251_p3 w_index_fu_23259_p2 icmp_ln135_fu_23265_p2 outidx_7_U w19_U" + } + ] + }] + }, + { + "ModuleName": "relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s", + "InstanceName": "relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_U0", + "BindInstances": "icmp_ln51_fu_1213_p2 out_data_29_fu_1229_p3 icmp_ln51_1_fu_1237_p2 out_data_30_fu_1253_p3 icmp_ln51_2_fu_1261_p2 out_data_31_fu_1277_p3 icmp_ln51_3_fu_1285_p2 out_data_32_fu_1301_p3 icmp_ln51_4_fu_1309_p2 select_ln51_fu_1325_p3 icmp_ln51_5_fu_1333_p2 select_ln51_1_fu_1349_p3 icmp_ln51_6_fu_1357_p2 select_ln51_2_fu_1373_p3 icmp_ln51_7_fu_1381_p2 select_ln51_3_fu_1397_p3 icmp_ln51_8_fu_1405_p2 select_ln51_4_fu_1421_p3 icmp_ln51_9_fu_1429_p2 select_ln51_5_fu_1445_p3 icmp_ln51_10_fu_1453_p2 select_ln51_6_fu_1469_p3 icmp_ln51_11_fu_1477_p2 select_ln51_7_fu_1493_p3 icmp_ln51_12_fu_1501_p2 select_ln51_8_fu_1517_p3 icmp_ln51_13_fu_1525_p2 select_ln51_9_fu_1541_p3 icmp_ln51_14_fu_1549_p2 select_ln51_10_fu_1565_p3 icmp_ln51_15_fu_1573_p2 select_ln51_11_fu_1589_p3 icmp_ln51_16_fu_1597_p2 select_ln51_12_fu_1613_p3 icmp_ln51_17_fu_1621_p2 select_ln51_13_fu_1637_p3 icmp_ln51_18_fu_1645_p2 select_ln51_14_fu_1661_p3 icmp_ln51_19_fu_1669_p2 select_ln51_15_fu_1685_p3 icmp_ln51_20_fu_1693_p2 select_ln51_16_fu_1709_p3 icmp_ln51_21_fu_1717_p2 select_ln51_17_fu_1733_p3 icmp_ln51_22_fu_1741_p2 select_ln51_18_fu_1757_p3 icmp_ln51_23_fu_1765_p2 select_ln51_19_fu_1781_p3 icmp_ln51_24_fu_1789_p2 select_ln51_20_fu_1805_p3 icmp_ln51_25_fu_1813_p2 select_ln51_21_fu_1829_p3 icmp_ln51_26_fu_1837_p2 select_ln51_22_fu_1853_p3 icmp_ln51_27_fu_1861_p2 select_ln51_23_fu_1877_p3 icmp_ln51_28_fu_1885_p2 select_ln51_24_fu_1901_p3 icmp_ln51_29_fu_1909_p2 select_ln51_25_fu_1925_p3 icmp_ln51_30_fu_1933_p2 select_ln51_26_fu_1949_p3 icmp_ln51_31_fu_1957_p2 select_ln51_27_fu_1973_p3 icmp_ln51_32_fu_1981_p2 select_ln51_28_fu_1997_p3 icmp_ln51_33_fu_2005_p2 select_ln51_29_fu_2021_p3 icmp_ln51_34_fu_2029_p2 select_ln51_30_fu_2045_p3 icmp_ln51_35_fu_2053_p2 select_ln51_31_fu_2069_p3 icmp_ln51_36_fu_2077_p2 select_ln51_32_fu_2093_p3 icmp_ln51_37_fu_2101_p2 select_ln51_33_fu_2117_p3 icmp_ln51_38_fu_2125_p2 select_ln51_34_fu_2141_p3 icmp_ln51_39_fu_2149_p2 select_ln51_35_fu_2165_p3 icmp_ln51_40_fu_2173_p2 select_ln51_36_fu_2189_p3 icmp_ln51_41_fu_2197_p2 select_ln51_37_fu_2213_p3 icmp_ln51_42_fu_2221_p2 select_ln51_38_fu_2237_p3 icmp_ln51_43_fu_2245_p2 select_ln51_39_fu_2261_p3 icmp_ln51_44_fu_2269_p2 select_ln51_40_fu_2285_p3 icmp_ln51_45_fu_2293_p2 select_ln51_41_fu_2309_p3 icmp_ln51_46_fu_2317_p2 select_ln51_42_fu_2333_p3 icmp_ln51_47_fu_2341_p2 select_ln51_43_fu_2357_p3 icmp_ln51_48_fu_2365_p2 select_ln51_44_fu_2381_p3 icmp_ln51_49_fu_2389_p2 select_ln51_45_fu_2405_p3 icmp_ln51_50_fu_2413_p2 select_ln51_46_fu_2429_p3 icmp_ln51_51_fu_2437_p2 select_ln51_47_fu_2453_p3 icmp_ln51_52_fu_2461_p2 select_ln51_48_fu_2477_p3 icmp_ln51_53_fu_2485_p2 select_ln51_49_fu_2501_p3 icmp_ln51_54_fu_2509_p2 select_ln51_50_fu_2525_p3 icmp_ln51_55_fu_2533_p2 select_ln51_51_fu_2549_p3 icmp_ln51_56_fu_2557_p2 select_ln51_52_fu_2573_p3 icmp_ln51_57_fu_2581_p2 select_ln51_53_fu_2597_p3 icmp_ln51_58_fu_2605_p2 select_ln51_54_fu_2621_p3 icmp_ln51_59_fu_2629_p2 select_ln51_55_fu_2645_p3 icmp_ln51_60_fu_2653_p2 select_ln51_56_fu_2669_p3 icmp_ln51_61_fu_2677_p2 select_ln51_57_fu_2693_p3 icmp_ln51_62_fu_2701_p2 select_ln51_58_fu_2717_p3 icmp_ln51_63_fu_2725_p2 select_ln51_59_fu_2741_p3 i_fu_2749_p2 icmp_ln41_fu_2755_p2" + }, + { + "ModuleName": "resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s", + "InstanceName": "resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_U0", + "BindInstances": "h_fu_62_p2 icmp_ln16_fu_68_p2" + }, + { + "ModuleName": "concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s", + "InstanceName": "concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0", + "Instances": [{ + "ModuleName": "concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s", + "InstanceName": "grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18", + "BindInstances": "icmp_ln234_fu_73_p2 add_ln234_fu_79_p2" + }] + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_s", + "InstanceName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_U0", + "Instances": [ + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth_fu_22", + "BindInstances": "icmp_ln53_fu_54_p2 j_10_fu_60_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain_fu_28", + "BindInstances": "icmp_ln59_fu_69_p2 i_2_fu_75_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth_fu_36", + "BindInstances": "icmp_ln77_fu_54_p2 j_11_fu_60_p2" + } + ] + }, + { + "ModuleName": "conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s", + "InstanceName": "conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0", + "BindInstances": "icmp_ln52_fu_4780_p2 add_ln52_fu_4786_p2", + "Instances": [{ + "ModuleName": "compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s", + "InstanceName": "grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s_fu_2548", + "BindInstances": "icmp_ln284_fu_6987_p2 icmp_ln284_1_fu_7005_p2 icmp_ln284_4_fu_7021_p2 icmp_ln284_5_fu_7037_p2 and_ln284_fu_7043_p2 and_ln284_1_fu_7049_p2 add_ln303_fu_7220_p2 icmp_ln303_fu_7225_p2 add_ln318_fu_7237_p2 select_ln318_fu_7242_p3 add_ln307_fu_7267_p2 icmp_ln307_fu_7272_p2 icmp_ln313_fu_7284_p2 add_ln313_fu_7289_p2 select_ln313_fu_7294_p3", + "Instances": [ + { + "ModuleName": "shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s", + "InstanceName": "call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_fu_2941", + "BindInstances": "p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1407_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_95_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1408_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_94_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1419_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_83_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1430_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_72_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1441_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_61_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1452_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_50_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1463_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_39_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1474_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_28_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1485_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_17_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1496_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_6_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1409_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_93_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1410_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_92_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1411_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_91_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1412_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_90_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1413_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_89_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1414_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_88_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1415_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_87_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1416_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_86_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1417_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_85_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1418_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_84_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1420_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_82_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1421_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_81_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1422_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_80_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1423_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_79_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1424_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_78_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1425_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_77_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1426_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_76_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1427_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_75_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1428_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_74_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1429_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_73_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1431_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_71_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1432_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_70_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1433_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_69_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1434_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_68_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1435_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_67_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1436_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_66_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1437_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_65_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1438_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_64_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1439_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_63_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1440_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_62_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1442_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_60_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1443_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_59_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1444_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_58_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1445_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_57_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1446_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_56_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1447_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_55_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1448_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_54_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1449_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_53_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1450_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_52_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1451_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_51_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1453_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_49_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1454_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_48_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1455_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_47_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1456_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_46_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1457_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_45_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1458_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_44_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1459_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_43_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1460_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_42_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1461_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_41_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1462_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_40_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1464_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_38_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1465_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_37_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1466_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_36_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1467_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_35_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1468_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_34_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1469_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_33_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1470_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_32_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1471_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_31_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1472_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_30_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1473_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_29_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1475_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_27_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1476_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_26_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1477_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_25_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1478_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_24_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1479_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_23_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1480_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_22_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1481_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_21_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1482_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_20_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1483_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_19_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1484_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_18_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1486_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_16_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1487_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_15_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1488_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_14_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1489_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_13_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1490_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_12_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1491_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_11_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1492_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_10_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1493_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_9_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1494_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_8_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1495_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_7_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1497_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_5_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1498_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_4_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_99_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_3_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_98_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_2_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_97_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_96_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_U" + }, + { + "ModuleName": "dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s", + "InstanceName": "grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_fu_5249", + "BindInstances": "sparsemux_1729_10_16_1_1_U5074 mac_muladd_16s_16s_41s_41_1_1_U5075 mac_muladd_16s_16s_41s_41_1_1_U5075 mac_muladd_16s_16s_41s_41_1_1_U5075 mac_muladd_16s_16s_41s_41_1_1_U5076 mac_muladd_16s_16s_41s_41_1_1_U5076 mac_muladd_16s_16s_41s_41_1_1_U5076 mac_muladd_16s_16s_41s_41_1_1_U5077 mac_muladd_16s_16s_41s_41_1_1_U5077 mac_muladd_16s_16s_41s_41_1_1_U5077 mac_muladd_16s_16s_41s_41_1_1_U5078 mac_muladd_16s_16s_41s_41_1_1_U5078 mac_muladd_16s_16s_41s_41_1_1_U5078 mac_muladd_16s_16s_41s_41_1_1_U5079 mac_muladd_16s_16s_41s_41_1_1_U5079 mac_muladd_16s_16s_41s_41_1_1_U5079 mac_muladd_16s_16s_41s_41_1_1_U5080 mac_muladd_16s_16s_41s_41_1_1_U5080 mac_muladd_16s_16s_41s_41_1_1_U5080 mac_muladd_16s_16s_41s_41_1_1_U5081 mac_muladd_16s_16s_41s_41_1_1_U5081 mac_muladd_16s_16s_41s_41_1_1_U5081 mac_muladd_16s_16s_41s_41_1_1_U5082 mac_muladd_16s_16s_41s_41_1_1_U5082 mac_muladd_16s_16s_41s_41_1_1_U5082 mac_muladd_16s_16s_41s_41_1_1_U5083 mac_muladd_16s_16s_41s_41_1_1_U5083 mac_muladd_16s_16s_41s_41_1_1_U5083 mac_muladd_16s_16s_41s_41_1_1_U5084 mac_muladd_16s_16s_41s_41_1_1_U5084 mac_muladd_16s_16s_41s_41_1_1_U5084 mac_muladd_16s_16s_41s_41_1_1_U5085 mac_muladd_16s_16s_41s_41_1_1_U5085 mac_muladd_16s_16s_41s_41_1_1_U5085 mac_muladd_16s_16s_41s_41_1_1_U5086 mac_muladd_16s_16s_41s_41_1_1_U5086 mac_muladd_16s_16s_41s_41_1_1_U5086 mac_muladd_16s_16s_41s_41_1_1_U5087 mac_muladd_16s_16s_41s_41_1_1_U5087 mac_muladd_16s_16s_41s_41_1_1_U5087 mac_muladd_16s_16s_41s_41_1_1_U5088 mac_muladd_16s_16s_41s_41_1_1_U5088 mac_muladd_16s_16s_41s_41_1_1_U5088 mac_muladd_16s_16s_41s_41_1_1_U5089 mac_muladd_16s_16s_41s_41_1_1_U5089 mac_muladd_16s_16s_41s_41_1_1_U5089 mac_muladd_16s_16s_41s_41_1_1_U5090 mac_muladd_16s_16s_41s_41_1_1_U5090 mac_muladd_16s_16s_41s_41_1_1_U5090 mac_muladd_16s_16s_41s_41_1_1_U5091 mac_muladd_16s_16s_41s_41_1_1_U5091 mac_muladd_16s_16s_41s_41_1_1_U5091 mac_muladd_16s_16s_41s_41_1_1_U5092 mac_muladd_16s_16s_41s_41_1_1_U5092 mac_muladd_16s_16s_41s_41_1_1_U5092 mac_muladd_16s_16s_41s_41_1_1_U5093 mac_muladd_16s_16s_41s_41_1_1_U5093 mac_muladd_16s_16s_41s_41_1_1_U5093 mac_muladd_16s_16s_41s_41_1_1_U5094 mac_muladd_16s_16s_41s_41_1_1_U5094 mac_muladd_16s_16s_41s_41_1_1_U5094 mac_muladd_16s_16s_41s_41_1_1_U5095 mac_muladd_16s_16s_41s_41_1_1_U5095 mac_muladd_16s_16s_41s_41_1_1_U5095 mac_muladd_16s_16s_41s_41_1_1_U5096 mac_muladd_16s_16s_41s_41_1_1_U5096 mac_muladd_16s_16s_41s_41_1_1_U5096 mac_muladd_16s_16s_41s_41_1_1_U5097 mac_muladd_16s_16s_41s_41_1_1_U5097 mac_muladd_16s_16s_41s_41_1_1_U5097 mac_muladd_16s_16s_41s_41_1_1_U5098 mac_muladd_16s_16s_41s_41_1_1_U5098 mac_muladd_16s_16s_41s_41_1_1_U5098 mac_muladd_16s_16s_41s_41_1_1_U5099 mac_muladd_16s_16s_41s_41_1_1_U5099 mac_muladd_16s_16s_41s_41_1_1_U5099 mac_muladd_16s_16s_41s_41_1_1_U5100 mac_muladd_16s_16s_41s_41_1_1_U5100 mac_muladd_16s_16s_41s_41_1_1_U5100 mac_muladd_16s_16s_41s_41_1_1_U5101 mac_muladd_16s_16s_41s_41_1_1_U5101 mac_muladd_16s_16s_41s_41_1_1_U5101 mac_muladd_16s_16s_41s_41_1_1_U5102 mac_muladd_16s_16s_41s_41_1_1_U5102 mac_muladd_16s_16s_41s_41_1_1_U5102 mac_muladd_16s_16s_41s_41_1_1_U5103 mac_muladd_16s_16s_41s_41_1_1_U5103 mac_muladd_16s_16s_41s_41_1_1_U5103 mac_muladd_16s_16s_41s_41_1_1_U5104 mac_muladd_16s_16s_41s_41_1_1_U5104 mac_muladd_16s_16s_41s_41_1_1_U5104 mac_muladd_16s_16s_41s_41_1_1_U5105 mac_muladd_16s_16s_41s_41_1_1_U5105 mac_muladd_16s_16s_41s_41_1_1_U5105 mac_muladd_16s_9s_34s_34_1_1_U5106 mac_muladd_16s_9s_34s_34_1_1_U5106 mac_muladd_16s_9s_34s_34_1_1_U5106 w_index_fu_30101_p2 icmp_ln46_fu_30107_p2 w23_U" + } + ] + }] + }, + { + "ModuleName": "relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s", + "InstanceName": "relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_U0", + "BindInstances": "icmp_ln51_fu_637_p2 out_data_47_fu_653_p3 icmp_ln51_64_fu_661_p2 out_data_48_fu_677_p3 icmp_ln51_65_fu_685_p2 out_data_50_fu_701_p3 icmp_ln51_66_fu_709_p2 out_data_52_fu_725_p3 icmp_ln51_67_fu_733_p2 select_ln51_fu_749_p3 icmp_ln51_68_fu_757_p2 select_ln51_60_fu_773_p3 icmp_ln51_69_fu_781_p2 select_ln51_61_fu_797_p3 icmp_ln51_70_fu_805_p2 select_ln51_62_fu_821_p3 icmp_ln51_71_fu_829_p2 select_ln51_63_fu_845_p3 icmp_ln51_72_fu_853_p2 select_ln51_64_fu_869_p3 icmp_ln51_73_fu_877_p2 select_ln51_65_fu_893_p3 icmp_ln51_74_fu_901_p2 select_ln51_66_fu_917_p3 icmp_ln51_75_fu_925_p2 select_ln51_67_fu_941_p3 icmp_ln51_76_fu_949_p2 select_ln51_68_fu_965_p3 icmp_ln51_77_fu_973_p2 select_ln51_69_fu_989_p3 icmp_ln51_78_fu_997_p2 select_ln51_70_fu_1013_p3 icmp_ln51_79_fu_1021_p2 select_ln51_71_fu_1037_p3 icmp_ln51_80_fu_1045_p2 select_ln51_72_fu_1061_p3 icmp_ln51_81_fu_1069_p2 select_ln51_73_fu_1085_p3 icmp_ln51_82_fu_1093_p2 select_ln51_74_fu_1109_p3 icmp_ln51_83_fu_1117_p2 select_ln51_75_fu_1133_p3 icmp_ln51_84_fu_1141_p2 select_ln51_76_fu_1157_p3 icmp_ln51_85_fu_1165_p2 select_ln51_77_fu_1181_p3 icmp_ln51_86_fu_1189_p2 select_ln51_78_fu_1205_p3 icmp_ln51_87_fu_1213_p2 select_ln51_79_fu_1229_p3 icmp_ln51_88_fu_1237_p2 select_ln51_80_fu_1253_p3 icmp_ln51_89_fu_1261_p2 select_ln51_81_fu_1277_p3 icmp_ln51_90_fu_1285_p2 select_ln51_82_fu_1301_p3 icmp_ln51_91_fu_1309_p2 select_ln51_83_fu_1325_p3 icmp_ln51_92_fu_1333_p2 select_ln51_84_fu_1349_p3 icmp_ln51_93_fu_1357_p2 select_ln51_85_fu_1373_p3 icmp_ln51_94_fu_1381_p2 select_ln51_86_fu_1397_p3 i_fu_1405_p2 icmp_ln41_fu_1411_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_s", + "InstanceName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_U0", + "Instances": [ + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth_fu_22", + "BindInstances": "icmp_ln53_fu_54_p2 j_22_fu_60_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain_fu_28", + "BindInstances": "icmp_ln59_fu_69_p2 i_14_fu_75_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth_fu_36", + "BindInstances": "icmp_ln77_fu_54_p2 j_23_fu_60_p2" + } + ] + }, + { + "ModuleName": "conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s", + "InstanceName": "conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_U0", + "BindInstances": "icmp_ln52_fu_1648_p2 add_ln52_fu_1654_p2", + "Instances": [{ + "ModuleName": "compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s", + "InstanceName": "grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s_fu_886", + "BindInstances": "icmp_ln284_fu_2383_p2 icmp_ln284_7_fu_2401_p2 icmp_ln284_8_fu_2417_p2 icmp_ln284_9_fu_2433_p2 and_ln284_fu_2439_p2 and_ln284_3_fu_2445_p2 add_ln303_fu_2648_p2 icmp_ln303_fu_2653_p2 add_ln318_fu_2665_p2 select_ln318_fu_2670_p3 add_ln307_fu_2695_p2 icmp_ln307_fu_2700_p2 icmp_ln313_fu_2712_p2 add_ln313_fu_2717_p2 select_ln313_fu_2722_p3", + "Instances": [ + { + "ModuleName": "shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s", + "InstanceName": "call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_fu_1023", + "BindInstances": "p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1007_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1039_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1008_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1040_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1019_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1051_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1030_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1062_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1033_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1065_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1034_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1066_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1035_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1067_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1036_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1068_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1037_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1069_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1038_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1070_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1009_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1041_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1010_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1042_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1011_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1043_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1012_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1044_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1013_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1045_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1014_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1046_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1015_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1047_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1016_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1048_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1017_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1049_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1018_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1050_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1020_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1052_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1021_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1053_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1022_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1054_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1023_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1055_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1024_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1056_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1025_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1057_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1026_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1058_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1027_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1059_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1028_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1060_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1029_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1061_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1031_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1063_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1032_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1064_U" + }, + { + "ModuleName": "dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s", + "InstanceName": "grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s_fu_1795", + "BindInstances": "sparsemux_577_9_16_1_1_U6402 mac_muladd_16s_16s_42s_43_1_1_U6411 sparsemux_9_2_42_1_1_U6403 mac_muladd_16s_16s_42s_43_1_1_U6411 mac_muladd_16s_16s_42s_43_1_1_U6411 icmp_ln144_fu_11779_p2 icmp_ln144_30_fu_11784_p2 icmp_ln144_31_fu_11789_p2 icmp_ln144_32_fu_11794_p2 or_ln144_fu_11799_p2 or_ln144_1_fu_11805_p2 or_ln144_2_fu_11811_p2 acc_157_fu_11817_p3 mac_muladd_16s_16s_42s_43_1_1_U6412 sparsemux_9_2_42_1_1_U6404 acc_128_fu_11854_p3 acc_127_fu_11862_p3 acc_126_fu_11870_p3 or_ln144_4_fu_11878_p2 acc_fu_11884_p3 mac_muladd_16s_16s_42s_43_1_1_U6412 mac_muladd_16s_16s_42s_43_1_1_U6412 icmp_ln144_33_fu_11896_p2 or_ln144_5_fu_11901_p2 or_ln144_7_fu_11907_p2 acc_159_fu_11913_p3 mac_muladd_16s_16s_42s_43_1_1_U6413 sparsemux_9_2_42_1_1_U6405 acc_132_fu_11950_p3 acc_131_fu_11958_p3 acc_130_fu_11966_p3 acc_129_fu_11974_p3 mac_muladd_16s_16s_42s_43_1_1_U6413 mac_muladd_16s_16s_42s_43_1_1_U6413 icmp_ln144_34_fu_11986_p2 or_ln144_8_fu_11991_p2 or_ln144_10_fu_11997_p2 acc_161_fu_12003_p3 mac_muladd_16s_16s_42s_43_1_1_U6414 sparsemux_9_2_42_1_1_U6406 acc_136_fu_12040_p3 acc_135_fu_12048_p3 acc_134_fu_12056_p3 acc_133_fu_12064_p3 mac_muladd_16s_16s_42s_43_1_1_U6414 mac_muladd_16s_16s_42s_43_1_1_U6414 icmp_ln144_35_fu_12076_p2 or_ln144_11_fu_12437_p2 or_ln144_12_fu_12441_p2 or_ln144_13_fu_12445_p2 acc_163_fu_12451_p3 mac_muladd_16s_16s_42s_43_1_1_U6415 sparsemux_9_2_42_1_1_U6407 acc_140_fu_12110_p3 acc_139_fu_12118_p3 acc_138_fu_12126_p3 or_ln144_15_fu_12459_p2 acc_137_fu_12464_p3 mac_muladd_16s_16s_42s_43_1_1_U6415 mac_muladd_16s_16s_42s_43_1_1_U6415 icmp_ln144_36_fu_12138_p2 or_ln144_16_fu_12143_p2 or_ln144_18_fu_12149_p2 acc_165_fu_12155_p3 mac_muladd_16s_16s_42s_43_1_1_U6416 sparsemux_9_2_42_1_1_U6408 acc_144_fu_12192_p3 acc_143_fu_12200_p3 acc_142_fu_12208_p3 acc_141_fu_12216_p3 mac_muladd_16s_16s_42s_43_1_1_U6416 mac_muladd_16s_16s_42s_43_1_1_U6416 icmp_ln144_37_fu_12228_p2 or_ln144_19_fu_12233_p2 or_ln144_21_fu_12239_p2 acc_167_fu_12245_p3 mac_muladd_16s_16s_42s_43_1_1_U6417 sparsemux_9_2_42_1_1_U6409 acc_148_fu_12282_p3 acc_147_fu_12290_p3 acc_146_fu_12298_p3 acc_145_fu_12306_p3 mac_muladd_16s_16s_42s_43_1_1_U6417 mac_muladd_16s_16s_42s_43_1_1_U6417 icmp_ln144_39_fu_12318_p2 or_ln144_22_fu_12323_p2 or_ln144_24_fu_12329_p2 acc_169_fu_12335_p3 mac_muladd_16s_11s_42s_43_1_1_U6418 sparsemux_9_2_42_1_1_U6410 acc_152_fu_12372_p3 acc_151_fu_12380_p3 acc_150_fu_12388_p3 acc_149_fu_12396_p3 mac_muladd_16s_11s_42s_43_1_1_U6418 mac_muladd_16s_11s_42s_43_1_1_U6418 icmp_ln144_38_fu_12408_p2 icmp_ln144_40_fu_12413_p2 xor_ln144_fu_12471_p2 or_ln144_25_fu_12476_p2 or_ln144_26_fu_12481_p2 or_ln144_27_fu_12485_p2 acc_172_fu_12491_p3 and_ln144_fu_12499_p2 acc_171_fu_12503_p3 acc_156_fu_12511_p3 or_ln144_28_fu_12517_p2 or_ln144_29_fu_12521_p2 acc_155_fu_12526_p3 acc_154_fu_12421_p3 acc_153_fu_12429_p3 in_index_6_fu_11723_p2 icmp_ln154_fu_11729_p2 in_index_fu_11735_p3 w_index_fu_10473_p2 icmp_ln135_fu_10479_p2 outidx_8_U w25_U" + } + ] + }] + }, + { + "ModuleName": "relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s", + "InstanceName": "relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_U0", + "BindInstances": "icmp_ln51_fu_637_p2 out_data_40_fu_653_p3 icmp_ln51_127_fu_661_p2 out_data_42_fu_677_p3 icmp_ln51_128_fu_685_p2 out_data_44_fu_701_p3 icmp_ln51_129_fu_709_p2 out_data_46_fu_725_p3 icmp_ln51_130_fu_733_p2 select_ln51_fu_749_p3 icmp_ln51_131_fu_757_p2 select_ln51_131_fu_773_p3 icmp_ln51_132_fu_781_p2 select_ln51_132_fu_797_p3 icmp_ln51_133_fu_805_p2 select_ln51_133_fu_821_p3 icmp_ln51_134_fu_829_p2 select_ln51_134_fu_845_p3 icmp_ln51_135_fu_853_p2 select_ln51_135_fu_869_p3 icmp_ln51_136_fu_877_p2 select_ln51_136_fu_893_p3 icmp_ln51_137_fu_901_p2 select_ln51_137_fu_917_p3 icmp_ln51_138_fu_925_p2 select_ln51_138_fu_941_p3 icmp_ln51_139_fu_949_p2 select_ln51_139_fu_965_p3 icmp_ln51_140_fu_973_p2 select_ln51_140_fu_989_p3 icmp_ln51_141_fu_997_p2 select_ln51_141_fu_1013_p3 icmp_ln51_142_fu_1021_p2 select_ln51_142_fu_1037_p3 icmp_ln51_143_fu_1045_p2 select_ln51_143_fu_1061_p3 icmp_ln51_144_fu_1069_p2 select_ln51_144_fu_1085_p3 icmp_ln51_145_fu_1093_p2 select_ln51_145_fu_1109_p3 icmp_ln51_146_fu_1117_p2 select_ln51_146_fu_1133_p3 icmp_ln51_147_fu_1141_p2 select_ln51_147_fu_1157_p3 icmp_ln51_148_fu_1165_p2 select_ln51_148_fu_1181_p3 icmp_ln51_149_fu_1189_p2 select_ln51_149_fu_1205_p3 icmp_ln51_150_fu_1213_p2 select_ln51_150_fu_1229_p3 icmp_ln51_151_fu_1237_p2 select_ln51_151_fu_1253_p3 icmp_ln51_152_fu_1261_p2 select_ln51_152_fu_1277_p3 icmp_ln51_153_fu_1285_p2 select_ln51_153_fu_1301_p3 icmp_ln51_154_fu_1309_p2 select_ln51_154_fu_1325_p3 icmp_ln51_155_fu_1333_p2 select_ln51_155_fu_1349_p3 icmp_ln51_156_fu_1357_p2 select_ln51_156_fu_1373_p3 icmp_ln51_157_fu_1381_p2 select_ln51_157_fu_1397_p3 i_fu_1405_p2 icmp_ln41_fu_1411_p2" + }, + { + "ModuleName": "resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s", + "InstanceName": "resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_U0", + "BindInstances": "h_fu_62_p2 icmp_ln16_fu_68_p2" + }, + { + "ModuleName": "concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s", + "InstanceName": "concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0", + "Instances": [{ + "ModuleName": "concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s", + "InstanceName": "grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18", + "BindInstances": "icmp_ln234_fu_73_p2 add_ln234_fu_79_p2" + }] + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_s", + "InstanceName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_U0", + "Instances": [ + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth_fu_22", + "BindInstances": "icmp_ln53_fu_54_p2 j_19_fu_60_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain_fu_28", + "BindInstances": "icmp_ln59_fu_69_p2 i_12_fu_75_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth_fu_36", + "BindInstances": "icmp_ln77_fu_54_p2 j_20_fu_60_p2" + } + ] + }, + { + "ModuleName": "conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s", + "InstanceName": "conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_U0", + "BindInstances": "icmp_ln52_fu_2428_p2 add_ln52_fu_2434_p2", + "Instances": [{ + "ModuleName": "compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s", + "InstanceName": "grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300", + "BindInstances": "icmp_ln284_fu_3531_p2 icmp_ln284_13_fu_3549_p2 icmp_ln284_14_fu_3565_p2 icmp_ln284_15_fu_3581_p2 and_ln284_fu_3587_p2 and_ln284_5_fu_3593_p2 add_ln303_fu_3684_p2 icmp_ln303_fu_3689_p2 add_ln318_fu_3701_p2 select_ln318_fu_3706_p3 add_ln307_fu_3731_p2 icmp_ln307_fu_3736_p2 icmp_ln313_fu_3748_p2 add_ln313_fu_3753_p2 select_ln313_fu_3758_p3", + "Instances": [ + { + "ModuleName": "shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s", + "InstanceName": "call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_fu_1501", + "BindInstances": "p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1135_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1183_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1136_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1184_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1147_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1195_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1158_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1206_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1169_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1217_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1178_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1226_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1179_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1227_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1180_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1228_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1181_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1229_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1182_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1230_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1137_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1185_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1138_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1186_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1139_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1187_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1140_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1188_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1141_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1189_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1142_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1190_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1143_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1191_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1144_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1192_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1145_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1193_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1146_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1194_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1148_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1196_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1149_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1197_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1150_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1198_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1151_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1199_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1152_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1200_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1153_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1201_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1154_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1202_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1155_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1203_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1156_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1204_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1157_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1205_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1159_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1207_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1160_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1208_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1161_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1209_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1162_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1210_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1163_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1211_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1164_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1212_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1165_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1213_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1166_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1214_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1167_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1215_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1168_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1216_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1170_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1218_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1171_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1219_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1172_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1220_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1173_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1221_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1174_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1222_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1175_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1223_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1176_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1224_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1177_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1225_U" + }, + { + "ModuleName": "dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s", + "InstanceName": "grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_fu_2657", + "BindInstances": "sparsemux_865_9_16_1_1_U7240 mac_muladd_16s_16s_40s_40_1_1_U7241 mac_muladd_16s_16s_40s_40_1_1_U7241 mac_muladd_16s_16s_40s_40_1_1_U7241 mac_muladd_16s_16s_40s_40_1_1_U7242 mac_muladd_16s_16s_40s_40_1_1_U7242 mac_muladd_16s_16s_40s_40_1_1_U7242 mac_muladd_16s_16s_40s_40_1_1_U7243 mac_muladd_16s_16s_40s_40_1_1_U7243 mac_muladd_16s_16s_40s_40_1_1_U7243 mac_muladd_16s_16s_40s_40_1_1_U7244 mac_muladd_16s_16s_40s_40_1_1_U7244 mac_muladd_16s_16s_40s_40_1_1_U7244 mac_muladd_16s_16s_40s_40_1_1_U7245 mac_muladd_16s_16s_40s_40_1_1_U7245 mac_muladd_16s_16s_40s_40_1_1_U7245 mac_muladd_16s_16s_40s_40_1_1_U7246 mac_muladd_16s_16s_40s_40_1_1_U7246 mac_muladd_16s_16s_40s_40_1_1_U7246 mac_muladd_16s_16s_40s_40_1_1_U7247 mac_muladd_16s_16s_40s_40_1_1_U7247 mac_muladd_16s_16s_40s_40_1_1_U7247 mac_muladd_16s_16s_40s_40_1_1_U7248 mac_muladd_16s_16s_40s_40_1_1_U7248 mac_muladd_16s_16s_40s_40_1_1_U7248 mac_muladd_16s_16s_40s_40_1_1_U7249 mac_muladd_16s_16s_40s_40_1_1_U7249 mac_muladd_16s_16s_40s_40_1_1_U7249 mac_muladd_16s_16s_40s_40_1_1_U7250 mac_muladd_16s_16s_40s_40_1_1_U7250 mac_muladd_16s_16s_40s_40_1_1_U7250 mac_muladd_16s_16s_40s_40_1_1_U7251 mac_muladd_16s_16s_40s_40_1_1_U7251 mac_muladd_16s_16s_40s_40_1_1_U7251 mac_muladd_16s_16s_40s_40_1_1_U7252 mac_muladd_16s_16s_40s_40_1_1_U7252 mac_muladd_16s_16s_40s_40_1_1_U7252 mac_muladd_16s_16s_40s_40_1_1_U7253 mac_muladd_16s_16s_40s_40_1_1_U7253 mac_muladd_16s_16s_40s_40_1_1_U7253 mac_muladd_16s_16s_40s_40_1_1_U7254 mac_muladd_16s_16s_40s_40_1_1_U7254 mac_muladd_16s_16s_40s_40_1_1_U7254 mac_muladd_16s_16s_40s_40_1_1_U7255 mac_muladd_16s_16s_40s_40_1_1_U7255 mac_muladd_16s_16s_40s_40_1_1_U7255 mac_muladd_16s_9s_33s_33_1_1_U7256 mac_muladd_16s_9s_33s_33_1_1_U7256 mac_muladd_16s_9s_33s_33_1_1_U7256 w_index_fu_15093_p2 icmp_ln46_fu_15099_p2 w29_U" + } + ] + }] + }, + { + "ModuleName": "relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s", + "InstanceName": "relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_U0", + "BindInstances": "icmp_ln51_fu_349_p2 out_data_81_fu_365_p3 icmp_ln51_220_fu_373_p2 out_data_83_fu_389_p3 icmp_ln51_221_fu_397_p2 out_data_85_fu_413_p3 icmp_ln51_222_fu_421_p2 out_data_87_fu_437_p3 icmp_ln51_223_fu_445_p2 select_ln51_fu_461_p3 icmp_ln51_224_fu_469_p2 select_ln51_200_fu_485_p3 icmp_ln51_225_fu_493_p2 select_ln51_201_fu_509_p3 icmp_ln51_226_fu_517_p2 select_ln51_202_fu_533_p3 icmp_ln51_227_fu_541_p2 select_ln51_203_fu_557_p3 icmp_ln51_228_fu_565_p2 select_ln51_204_fu_581_p3 icmp_ln51_229_fu_589_p2 select_ln51_205_fu_605_p3 icmp_ln51_230_fu_613_p2 select_ln51_206_fu_629_p3 icmp_ln51_231_fu_637_p2 select_ln51_207_fu_653_p3 icmp_ln51_232_fu_661_p2 select_ln51_208_fu_677_p3 icmp_ln51_233_fu_685_p2 select_ln51_209_fu_701_p3 icmp_ln51_234_fu_709_p2 select_ln51_210_fu_725_p3 i_fu_733_p2 icmp_ln41_fu_739_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s", + "InstanceName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_U0", + "Instances": [ + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth_fu_22", + "BindInstances": "icmp_ln53_fu_54_p2 j_35_fu_60_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain_fu_28", + "BindInstances": "icmp_ln59_fu_69_p2 i_24_fu_75_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth_fu_36", + "BindInstances": "icmp_ln77_fu_54_p2 j_36_fu_60_p2" + } + ] + }, + { + "ModuleName": "conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s", + "InstanceName": "conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_U0", + "BindInstances": "icmp_ln52_fu_864_p2 add_ln52_fu_870_p2", + "Instances": [{ + "ModuleName": "compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s", + "InstanceName": "grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_470", + "BindInstances": "icmp_ln284_fu_1231_p2 icmp_ln284_25_fu_1249_p2 icmp_ln284_26_fu_1265_p2 icmp_ln284_27_fu_1281_p2 and_ln284_fu_1287_p2 and_ln284_9_fu_1293_p2 add_ln303_fu_1400_p2 icmp_ln303_fu_1405_p2 add_ln318_fu_1417_p2 select_ln318_fu_1422_p3 add_ln307_fu_1447_p2 icmp_ln307_fu_1452_p2 icmp_ln313_fu_1464_p2 add_ln313_fu_1469_p2 select_ln313_fu_1474_p3", + "Instances": [ + { + "ModuleName": "shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s", + "InstanceName": "call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_fu_543", + "BindInstances": "p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_831_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_847_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_832_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_848_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_839_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_855_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_840_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_856_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_841_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_857_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_842_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_858_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_843_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_859_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_844_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_860_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_845_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_861_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_846_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_862_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_833_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_849_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_834_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_850_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_835_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_851_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_836_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_852_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_837_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_853_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_838_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_854_U" + }, + { + "ModuleName": "dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s", + "InstanceName": "grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s_fu_931", + "BindInstances": "sparsemux_289_8_16_1_1_U7912 mac_muladd_16s_16s_41s_42_1_1_U7917 sparsemux_9_2_41_1_1_U7913 mac_muladd_16s_16s_41s_42_1_1_U7917 mac_muladd_16s_16s_41s_42_1_1_U7917 icmp_ln144_fu_5998_p2 icmp_ln144_23_fu_6003_p2 icmp_ln144_24_fu_6008_p2 icmp_ln144_25_fu_6013_p2 or_ln144_fu_6018_p2 or_ln144_17_fu_6024_p2 or_ln144_18_fu_6030_p2 acc_117_fu_6036_p3 mac_muladd_16s_16s_41s_42_1_1_U7918 sparsemux_9_2_41_1_1_U7914 acc_104_fu_6073_p3 acc_103_fu_6081_p3 acc_102_fu_6089_p3 or_ln144_19_fu_6097_p2 acc_fu_6103_p3 mac_muladd_16s_16s_41s_42_1_1_U7918 mac_muladd_16s_16s_41s_42_1_1_U7918 icmp_ln144_26_fu_6115_p2 or_ln144_20_fu_6120_p2 or_ln144_21_fu_6126_p2 acc_119_fu_6132_p3 mac_muladd_16s_16s_41s_42_1_1_U7919 sparsemux_9_2_41_1_1_U7915 acc_108_fu_6169_p3 acc_107_fu_6177_p3 acc_106_fu_6185_p3 acc_105_fu_6193_p3 mac_muladd_16s_16s_41s_42_1_1_U7919 mac_muladd_16s_16s_41s_42_1_1_U7919 icmp_ln144_27_fu_6205_p2 or_ln144_22_fu_6210_p2 or_ln144_23_fu_6216_p2 acc_121_fu_6222_p3 mac_muladd_16s_9s_41s_42_1_1_U7920 sparsemux_9_2_41_1_1_U7916 acc_112_fu_6259_p3 acc_111_fu_6267_p3 acc_110_fu_6275_p3 acc_109_fu_6283_p3 mac_muladd_16s_9s_41s_42_1_1_U7920 mac_muladd_16s_9s_41s_42_1_1_U7920 icmp_ln144_28_fu_6295_p2 icmp_ln144_29_fu_6300_p2 xor_ln144_fu_6324_p2 or_ln144_24_fu_6329_p2 or_ln144_25_fu_6334_p2 or_ln144_26_fu_6338_p2 acc_124_fu_6344_p3 and_ln144_fu_6352_p2 acc_123_fu_6356_p3 acc_116_fu_6364_p3 or_ln144_27_fu_6370_p2 or_ln144_28_fu_6374_p2 acc_115_fu_6379_p3 acc_114_fu_6308_p3 acc_113_fu_6316_p3 in_index_5_fu_5942_p2 icmp_ln154_fu_5948_p2 in_index_fu_5954_p3 w_index_fu_5308_p2 icmp_ln135_fu_5314_p2 outidx_9_U w31_U" + } + ] + }] + }, + { + "ModuleName": "relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s", + "InstanceName": "relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_U0", + "BindInstances": "icmp_ln51_fu_349_p2 out_data_74_fu_365_p3 icmp_ln51_235_fu_373_p2 out_data_76_fu_389_p3 icmp_ln51_236_fu_397_p2 out_data_78_fu_413_p3 icmp_ln51_237_fu_421_p2 out_data_80_fu_437_p3 icmp_ln51_238_fu_445_p2 select_ln51_fu_461_p3 icmp_ln51_239_fu_469_p2 select_ln51_241_fu_485_p3 icmp_ln51_240_fu_493_p2 select_ln51_242_fu_509_p3 icmp_ln51_241_fu_517_p2 select_ln51_243_fu_533_p3 icmp_ln51_242_fu_541_p2 select_ln51_244_fu_557_p3 icmp_ln51_243_fu_565_p2 select_ln51_245_fu_581_p3 icmp_ln51_244_fu_589_p2 select_ln51_246_fu_605_p3 icmp_ln51_245_fu_613_p2 select_ln51_247_fu_629_p3 icmp_ln51_246_fu_637_p2 select_ln51_248_fu_653_p3 icmp_ln51_247_fu_661_p2 select_ln51_249_fu_677_p3 icmp_ln51_248_fu_685_p2 select_ln51_250_fu_701_p3 icmp_ln51_249_fu_709_p2 select_ln51_251_fu_725_p3 i_fu_733_p2 icmp_ln41_fu_739_p2" + }, + { + "ModuleName": "resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s", + "InstanceName": "resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_U0", + "BindInstances": "h_fu_62_p2 icmp_ln16_fu_68_p2" + }, + { + "ModuleName": "concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s", + "InstanceName": "concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0", + "Instances": [{ + "ModuleName": "concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s", + "InstanceName": "grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18", + "BindInstances": "icmp_ln234_fu_73_p2 add_ln234_fu_79_p2" + }] + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s", + "InstanceName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_U0", + "Instances": [ + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth_fu_22", + "BindInstances": "icmp_ln53_fu_54_p2 j_31_fu_60_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain_fu_28", + "BindInstances": "icmp_ln59_fu_69_p2 i_20_fu_75_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth_fu_36", + "BindInstances": "icmp_ln77_fu_54_p2 j_32_fu_60_p2" + } + ] + }, + { + "ModuleName": "conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s", + "InstanceName": "conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_U0", + "BindInstances": "icmp_ln52_fu_1252_p2 add_ln52_fu_1258_p2", + "Instances": [{ + "ModuleName": "compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s", + "InstanceName": "grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676", + "BindInstances": "icmp_ln284_fu_1803_p2 icmp_ln284_16_fu_1821_p2 icmp_ln284_17_fu_1837_p2 icmp_ln284_18_fu_1853_p2 and_ln284_fu_1859_p2 and_ln284_6_fu_1865_p2 add_ln303_fu_1916_p2 icmp_ln303_fu_1921_p2 add_ln318_fu_1933_p2 select_ln318_fu_1938_p3 add_ln307_fu_1963_p2 icmp_ln307_fu_1968_p2 icmp_ln313_fu_1980_p2 add_ln313_fu_1985_p2 select_ln313_fu_1990_p3", + "Instances": [ + { + "ModuleName": "shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s", + "InstanceName": "call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_fu_781", + "BindInstances": "p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_895_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_919_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_896_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_920_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_907_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_931_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_912_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_936_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_913_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_937_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_914_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_938_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_915_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_939_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_916_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_940_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_917_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_941_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_918_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_942_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_897_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_921_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_898_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_922_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_899_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_923_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_900_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_924_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_901_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_925_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_902_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_926_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_903_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_927_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_904_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_928_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_905_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_929_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_906_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_930_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_908_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_932_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_909_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_933_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_910_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_934_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_911_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_935_U" + }, + { + "ModuleName": "dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s", + "InstanceName": "grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_fu_1361", + "BindInstances": "sparsemux_433_8_16_1_1_U8342 mac_muladd_16s_16s_39s_39_1_1_U8343 mac_muladd_16s_16s_39s_39_1_1_U8343 mac_muladd_16s_16s_39s_39_1_1_U8343 mac_muladd_16s_16s_39s_39_1_1_U8344 mac_muladd_16s_16s_39s_39_1_1_U8344 mac_muladd_16s_16s_39s_39_1_1_U8344 mac_muladd_16s_16s_39s_39_1_1_U8345 mac_muladd_16s_16s_39s_39_1_1_U8345 mac_muladd_16s_16s_39s_39_1_1_U8345 mac_muladd_16s_16s_39s_39_1_1_U8346 mac_muladd_16s_16s_39s_39_1_1_U8346 mac_muladd_16s_16s_39s_39_1_1_U8346 mac_muladd_16s_16s_39s_39_1_1_U8347 mac_muladd_16s_16s_39s_39_1_1_U8347 mac_muladd_16s_16s_39s_39_1_1_U8347 mac_muladd_16s_16s_39s_39_1_1_U8348 mac_muladd_16s_16s_39s_39_1_1_U8348 mac_muladd_16s_16s_39s_39_1_1_U8348 mac_muladd_16s_16s_39s_39_1_1_U8349 mac_muladd_16s_16s_39s_39_1_1_U8349 mac_muladd_16s_16s_39s_39_1_1_U8349 mac_muladd_16s_10s_33s_33_1_1_U8350 mac_muladd_16s_10s_33s_33_1_1_U8350 mac_muladd_16s_10s_33s_33_1_1_U8350 w_index_fu_7589_p2 icmp_ln46_fu_7595_p2 w35_U" + } + ] + }] + }, + { + "ModuleName": "relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s", + "InstanceName": "relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_U0", + "BindInstances": "icmp_ln51_fu_205_p2 out_data_22_fu_221_p3 icmp_ln51_22_fu_229_p2 out_data_24_fu_245_p3 icmp_ln51_23_fu_253_p2 out_data_26_fu_269_p3 icmp_ln51_24_fu_277_p2 out_data_28_fu_293_p3 icmp_ln51_25_fu_301_p2 select_ln51_fu_317_p3 icmp_ln51_26_fu_325_p2 select_ln51_26_fu_341_p3 icmp_ln51_27_fu_349_p2 select_ln51_27_fu_365_p3 icmp_ln51_28_fu_373_p2 select_ln51_28_fu_389_p3 i_fu_397_p2 icmp_ln41_fu_403_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_s", + "InstanceName": "zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_U0", + "Instances": [ + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth_fu_22", + "BindInstances": "icmp_ln53_fu_54_p2 j_2_fu_60_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain_fu_28", + "BindInstances": "icmp_ln59_fu_69_p2 i_4_fu_75_p2" + }, + { + "ModuleName": "zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth", + "InstanceName": "grp_zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth_fu_36", + "BindInstances": "icmp_ln77_fu_54_p2 j_12_fu_60_p2" + } + ] + }, + { + "ModuleName": "conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s", + "InstanceName": "conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_U0", + "BindInstances": "icmp_ln52_fu_472_p2 add_ln52_fu_478_p2", + "Instances": [{ + "ModuleName": "compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s", + "InstanceName": "grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262", + "BindInstances": "icmp_ln284_fu_655_p2 icmp_ln284_7_fu_673_p2 icmp_ln284_30_fu_689_p2 icmp_ln284_31_fu_705_p2 and_ln284_fu_711_p2 and_ln284_3_fu_717_p2 add_ln303_fu_776_p2 icmp_ln303_fu_781_p2 add_ln318_fu_793_p2 select_ln318_fu_798_p3 add_ln307_fu_823_p2 icmp_ln307_fu_828_p2 icmp_ln313_fu_840_p2 add_ln313_fu_845_p2 select_ln313_fu_850_p3", + "Instances": [ + { + "ModuleName": "shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s", + "InstanceName": "call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_fu_303", + "BindInstances": "p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1391_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1399_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1392_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1400_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1393_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1401_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1394_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1402_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1395_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1403_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1396_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1404_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1397_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1405_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1398_U p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1406_U" + }, + { + "ModuleName": "dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s", + "InstanceName": "grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s_fu_499", + "BindInstances": "sparsemux_145_7_16_1_1_U8685 mac_muladd_16s_16s_40s_41_1_1_U8688 sparsemux_9_2_40_1_1_U8686 mac_muladd_16s_16s_40s_41_1_1_U8688 mac_muladd_16s_16s_40s_41_1_1_U8688 icmp_ln144_fu_3105_p2 icmp_ln144_18_fu_3110_p2 icmp_ln144_19_fu_3115_p2 icmp_ln144_20_fu_3120_p2 or_ln144_fu_3211_p2 or_ln144_9_fu_3215_p2 or_ln144_10_fu_3219_p2 acc_97_fu_3225_p3 mac_muladd_16s_11s_40s_41_1_1_U8689 sparsemux_9_2_40_1_1_U8687 acc_92_fu_3154_p3 acc_91_fu_3162_p3 acc_90_fu_3170_p3 or_ln144_11_fu_3233_p2 acc_fu_3238_p3 mac_muladd_16s_11s_40s_41_1_1_U8689 mac_muladd_16s_11s_40s_41_1_1_U8689 icmp_ln144_21_fu_3182_p2 icmp_ln144_22_fu_3187_p2 xor_ln144_fu_3245_p2 or_ln144_12_fu_3250_p2 or_ln144_13_fu_3255_p2 or_ln144_14_fu_3259_p2 acc_100_fu_3265_p3 and_ln144_fu_3273_p2 acc_99_fu_3277_p3 acc_96_fu_3285_p3 or_ln144_15_fu_3291_p2 or_ln144_16_fu_3295_p2 acc_95_fu_3300_p3 acc_94_fu_3195_p3 acc_93_fu_3203_p3 in_index_4_fu_3049_p2 icmp_ln154_fu_3055_p2 in_index_fu_3061_p3 w_index_fu_2723_p2 icmp_ln135_fu_2729_p2 outidx_U w37_U" + } + ] + }] + }, + { + "ModuleName": "relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s", + "InstanceName": "relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_U0", + "BindInstances": "icmp_ln51_fu_205_p2 out_data_15_fu_221_p3 icmp_ln51_15_fu_229_p2 out_data_17_fu_245_p3 icmp_ln51_16_fu_253_p2 out_data_19_fu_269_p3 icmp_ln51_17_fu_277_p2 out_data_21_fu_293_p3 icmp_ln51_18_fu_301_p2 select_ln51_fu_317_p3 icmp_ln51_19_fu_325_p2 select_ln51_19_fu_341_p3 icmp_ln51_20_fu_349_p2 select_ln51_20_fu_365_p3 icmp_ln51_21_fu_373_p2 select_ln51_21_fu_389_p3 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"PipelineII": "", + "PipelineDepthMin": "4", + "PipelineDepthMax": "295", + "PipelineDepth": "4 ~ 295" + }], + "Area": { + "BRAM_18K": "1", + "AVAIL_BRAM": "4032", + "UTIL_BRAM": "~0", + "DSP": "2", + "AVAIL_DSP": "9024", + "UTIL_DSP": "~0", + "FF": "5573", + "AVAIL_FF": "2607360", + "UTIL_FF": "~0", + "LUT": "4991", + "AVAIL_LUT": "1303680", + "UTIL_LUT": "~0", + "URAM": "0", + "AVAIL_URAM": "960", + "UTIL_URAM": "0" + } + }, + "relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s": { + "Latency": { + "LatencyBest": "4098", + "LatencyAvg": "4098", + "LatencyWorst": "4098", + "PipelineII": "4096", + "PipelineDepth": "", + "PipelineType": "loop auto-rewind (delay=0 clock cycles(s))" + }, + "Timing": { + "Target": "4.00", + "Uncertainty": "1.35", + "Estimate": "2.443" + }, + "Loops": [{ + "Name": "ReLUActLoop", + "TripCount": "4096", + "Latency": "4096", + "PipelineII": "1", + "PipelineDepth": "2" + }], + "Area": { + "FF": "145", + "AVAIL_FF": "2607360", + "UTIL_FF": "~0", + "LUT": "613", + "AVAIL_LUT": "1303680", + "UTIL_LUT": "~0", + "BRAM_18K": "0", + "AVAIL_BRAM": "4032", + "UTIL_BRAM": "0", + "DSP": "0", + "AVAIL_DSP": "9024", + "UTIL_DSP": "0", + "URAM": "0", + "AVAIL_URAM": "960", + "UTIL_URAM": "0" + } + }, + "dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s": { + "Latency": { + "LatencyBest": "8", + "LatencyAvg": "8", + "LatencyWorst": "9", + "PipelineII": "8", + "PipelineDepth": "", + "PipelineType": "loop rewind (delay=0 clock cycles(s))" + }, + "Timing": { + "Target": "4.00", + "Uncertainty": "1.35", + "Estimate": "2.533" + }, + "Loops": [{ + "Name": "ReuseLoop", + "TripCount": "8", + "Latency": "8", + "PipelineII": "1", + "PipelineDepth": "2" + }], + "Area": { + "DSP": "1", + "AVAIL_DSP": "9024", + "UTIL_DSP": "~0", + "FF": "229", + "AVAIL_FF": "2607360", + "UTIL_FF": "~0", + "LUT": "418", + "AVAIL_LUT": "1303680", + "UTIL_LUT": "~0", + "BRAM_18K": "0", + "AVAIL_BRAM": "4032", + "UTIL_BRAM": "0", + "URAM": "0", + "AVAIL_URAM": "960", + "UTIL_URAM": "0" + } + }, + "pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_s": { + "Latency": { + "LatencyBest": "45057", + "LatencyAvg": "45057", + "LatencyWorst": "49153", + "PipelineIIMin": "45057", + "PipelineIIMax": "49153", + "PipelineII": "45057 ~ 49153", + "PipelineDepth": "", + "PipelineType": "no" + }, + "Timing": { + "Target": "4.00", + "Uncertainty": "1.35", + "Estimate": "2.563" + }, + "Loops": [{ + "Name": "ReadInputHeightSerial_ReadInputWidthSerial", + "TripCount": "4096", + "LatencyMin": "45056", + "LatencyMax": "49152", + "Latency": "45056 ~ 49152", + "PipelineII": "", + "PipelineDepthMin": "11", + "PipelineDepthMax": "12", + "PipelineDepth": "11 ~ 12" + }], + "Area": { + "DSP": "1", + "AVAIL_DSP": "9024", + "UTIL_DSP": "~0", + "FF": "420", + "AVAIL_FF": "2607360", + "UTIL_FF": "~0", + "LUT": "534", + "AVAIL_LUT": "1303680", + "UTIL_LUT": "~0", + "BRAM_18K": "0", + "AVAIL_BRAM": "4032", + "UTIL_BRAM": "0", + "URAM": "0", + "AVAIL_URAM": "960", + "UTIL_URAM": "0" + } + }, + "sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s": { + "Latency": { + "LatencyBest": "4101", + "LatencyAvg": "4101", + "LatencyWorst": "4101", + "PipelineII": "4096", + "PipelineDepth": "", + "PipelineType": "loop auto-rewind (delay=0 clock cycles(s))" + }, + "Timing": { + "Target": "4.00", + "Uncertainty": "1.35", + "Estimate": "2.034" + }, + "Loops": [{ + "Name": "SigmoidActLoop", + "TripCount": "4096", + "Latency": "4099", + "PipelineII": "1", + "PipelineDepth": "5" + }], + "Area": { + "BRAM_18K": "2", + "AVAIL_BRAM": "4032", + "UTIL_BRAM": "~0", + "FF": "118", + "AVAIL_FF": "2607360", + "UTIL_FF": "~0", + "LUT": "280", + "AVAIL_LUT": "1303680", + "UTIL_LUT": "~0", + "DSP": "0", + "AVAIL_DSP": "9024", + "UTIL_DSP": "0", + "URAM": "0", + "AVAIL_URAM": "960", + "UTIL_URAM": "0" + } + }, + "myproject": { + "Latency": { + "LatencyBest": "1285112", + "LatencyAvg": "1285112", + "LatencyWorst": "1285393", + "PipelineIIMin": "45058", + "PipelineIIMax": "1285022", + "PipelineII": "45058 ~ 1285022", + "PipelineDepth": "", + "PipelineType": "dataflow" + }, + "Timing": { + "Target": "4.00", + "Uncertainty": "1.35", + "Estimate": "4.449" + }, + "Area": { + "BRAM_18K": "1069", + "AVAIL_BRAM": "4032", + "UTIL_BRAM": "26", + "DSP": "172", + "AVAIL_DSP": "9024", + "UTIL_DSP": "1", + "FF": "369440", + "AVAIL_FF": "2607360", + "UTIL_FF": "14", + "LUT": "297261", + "AVAIL_LUT": "1303680", + "UTIL_LUT": "22", + "URAM": "0", + "AVAIL_URAM": "960", + "UTIL_URAM": "0" + } + } + } + }, + "GenerateBdFiles": "0", + "GenData": { + "DataVersion": "0.2", + "Time": "2026-04-05 21:51:09 UTC", + "ToolName": "vitis_hls", + "ToolVersion": "2024.1" + } +} diff --git a/myproject_prj/solution1/syn/report/clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s_csynth.xml b/myproject_prj/solution1/syn/report/clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..cbc98e2d73bac98c80d62b79954e397cb7008934 --- /dev/null +++ b/myproject_prj/solution1/syn/report/clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s_csynth.xml @@ -0,0 +1,356 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s +4.00 +1.35 +vivado + + + +loop auto-rewind stp(delay=0 clock cycles(s)) + +ns +2.590 + + +clock cycles +257 +257 +257 +1.028 us +1.028 us +1.028 us +256 +256 + + + +2.65 +256 +255 +1020 +1 +1 + + + + + +- +- +firmware/nnet_utils/nnet_stream.h:22 + + +CloneLoop +- +- +firmware/nnet_utils/nnet_stream.h:22 + + + + + + + +11 +95 +0 +0 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +clone_stream<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,8192> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +clone_stream<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,8192> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +clone_stream<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,8192> +return value + +ap_ctrl_hs + +in +1 +control + + +start_full_n +clone_stream<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,8192> +return value + +ap_ctrl_hs + +in +1 +unknown + + +ap_done +clone_stream<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,8192> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_continue +clone_stream<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,8192> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_idle +clone_stream<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,8192> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +clone_stream<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,8192> +return value + +ap_ctrl_hs + +out +1 +control + + +start_out +clone_stream<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,8192> +return value + +ap_ctrl_hs + +out +1 +unknown + + +start_write +clone_stream<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,8192> +return value + +ap_ctrl_hs + +out +1 +unknown + + +layer15_out_dout +layer15_out +pointer + +ap_fifo + +in +512 +control + + +layer15_out_num_data_valid +layer15_out +pointer + +ap_fifo + +in +9 +control + + +layer15_out_fifo_cap +layer15_out +pointer + +ap_fifo + +in +9 +unknown + + +layer15_out_empty_n +layer15_out +pointer + +ap_fifo + +in +1 +control + + +layer15_out_read +layer15_out +pointer + +ap_fifo + +out +1 +control + + +layer43_cpy1_din +layer43_cpy1 +pointer + +ap_fifo + +out +512 +control + + +layer43_cpy1_num_data_valid +layer43_cpy1 +pointer + +ap_fifo + +in +9 +control + + +layer43_cpy1_fifo_cap +layer43_cpy1 +pointer + +ap_fifo + +in +9 +unknown + + +layer43_cpy1_full_n +layer43_cpy1 +pointer + +ap_fifo + +in +1 +control + + +layer43_cpy1_write +layer43_cpy1 +pointer + +ap_fifo + +out +1 +control + + +layer43_cpy2_din +layer43_cpy2 +pointer + +ap_fifo + +out +512 +control + + +layer43_cpy2_num_data_valid +layer43_cpy2 +pointer + +ap_fifo + +in +9 +control + + +layer43_cpy2_fifo_cap +layer43_cpy2 +pointer + +ap_fifo + +in +9 +unknown + + +layer43_cpy2_full_n +layer43_cpy2 +pointer + +ap_fifo + +in +1 +control + + +layer43_cpy2_write +layer43_cpy2 +pointer + +ap_fifo + +out +1 +control + + + + diff --git a/myproject_prj/solution1/syn/report/clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s_csynth.xml b/myproject_prj/solution1/syn/report/clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..a43b5711147e2532e1d473da8a0aad678c63938f --- /dev/null +++ b/myproject_prj/solution1/syn/report/clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s_csynth.xml @@ -0,0 +1,356 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s +4.00 +1.35 +vivado + + + +loop auto-rewind stp(delay=0 clock cycles(s)) + +ns +2.448 + + +clock cycles +4097 +4097 +4097 +16.388 us +16.388 us +16.388 us +4096 +4096 + + + +2.65 +4096 +4095 +16380 +1 +1 + + + + + +- +- +firmware/nnet_utils/nnet_stream.h:22 + + +CloneLoop +- +- +firmware/nnet_utils/nnet_stream.h:22 + + + + + + + +15 +103 +0 +0 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +clone_stream<array<ap_fixed,8u>,array<ap_fixed<16,6,5,3,0>,8u>,32768> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +clone_stream<array<ap_fixed,8u>,array<ap_fixed<16,6,5,3,0>,8u>,32768> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +clone_stream<array<ap_fixed,8u>,array<ap_fixed<16,6,5,3,0>,8u>,32768> +return value + +ap_ctrl_hs + +in +1 +control + + +start_full_n +clone_stream<array<ap_fixed,8u>,array<ap_fixed<16,6,5,3,0>,8u>,32768> +return value + +ap_ctrl_hs + +in +1 +unknown + + +ap_done +clone_stream<array<ap_fixed,8u>,array<ap_fixed<16,6,5,3,0>,8u>,32768> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_continue +clone_stream<array<ap_fixed,8u>,array<ap_fixed<16,6,5,3,0>,8u>,32768> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_idle +clone_stream<array<ap_fixed,8u>,array<ap_fixed<16,6,5,3,0>,8u>,32768> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +clone_stream<array<ap_fixed,8u>,array<ap_fixed<16,6,5,3,0>,8u>,32768> +return value + +ap_ctrl_hs + +out +1 +control + + +start_out +clone_stream<array<ap_fixed,8u>,array<ap_fixed<16,6,5,3,0>,8u>,32768> +return value + +ap_ctrl_hs + +out +1 +unknown + + +start_write +clone_stream<array<ap_fixed,8u>,array<ap_fixed<16,6,5,3,0>,8u>,32768> +return value + +ap_ctrl_hs + +out +1 +unknown + + +layer5_out_dout +layer5_out +pointer + +ap_fifo + +in +128 +control + + +layer5_out_num_data_valid +layer5_out +pointer + +ap_fifo + +in +13 +control + + +layer5_out_fifo_cap +layer5_out +pointer + +ap_fifo + +in +13 +unknown + + +layer5_out_empty_n +layer5_out +pointer + +ap_fifo + +in +1 +control + + +layer5_out_read +layer5_out +pointer + +ap_fifo + +out +1 +control + + +layer41_cpy1_din +layer41_cpy1 +pointer + +ap_fifo + +out +128 +control + + +layer41_cpy1_num_data_valid +layer41_cpy1 +pointer + +ap_fifo + +in +13 +control + + +layer41_cpy1_fifo_cap +layer41_cpy1 +pointer + +ap_fifo + +in +13 +unknown + + +layer41_cpy1_full_n +layer41_cpy1 +pointer + +ap_fifo + +in +1 +control + + +layer41_cpy1_write +layer41_cpy1 +pointer + +ap_fifo + +out +1 +control + + +layer41_cpy2_din +layer41_cpy2 +pointer + +ap_fifo + +out +128 +control + + +layer41_cpy2_num_data_valid +layer41_cpy2 +pointer + +ap_fifo + +in +13 +control + + +layer41_cpy2_fifo_cap +layer41_cpy2 +pointer + +ap_fifo + +in +13 +unknown + + +layer41_cpy2_full_n +layer41_cpy2 +pointer + +ap_fifo + +in +1 +control + + +layer41_cpy2_write +layer41_cpy2 +pointer + +ap_fifo + +out +1 +control + + + + diff --git a/myproject_prj/solution1/syn/report/compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_csynth.rpt b/myproject_prj/solution1/syn/report/compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..c7d7ff21b05c2c7d2685f4024f3a98e6206ade1d --- /dev/null +++ b/myproject_prj/solution1/syn/report/compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_csynth.rpt @@ -0,0 +1,335 @@ + + +================================================================ +== Vitis HLS Report for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s' +================================================================ +* Date: Sun Apr 5 21:47:00 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 4.437 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+----------+----------+-----+-----+---------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline| + | min | max | min | max | min | max | Type | + +---------+---------+----------+----------+-----+-----+---------+ + | 2| 581| 8.873 ns| 2.578 us| 2| 581| no| + +---------+---------+----------+----------+-----+-----+---------+ + + + Detail: + * Instance: + +------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+---------+----------+----------+-----+-----+------------------------------------------+ + | | | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | Instance | Module | min | max | min | max | min | max | Type | + +------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+---------+----------+----------+-----+-----+------------------------------------------+ + |call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_fu_543 |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s | 0| 0| 0 ns| 0 ns| 1| 1| yes| + |grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s_fu_931 |dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s | 578| 579| 2.564 us| 2.569 us| 576| 576| loop rewind stp(delay=0 clock cycles(s))| + +------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+---------+----------+----------+-----+-----+------------------------------------------+ + + * Loop: + N/A + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 505| -| +|FIFO | -| -| -| -| -| +|Instance | 8| 8| 9548| 9887| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| 0| 70| -| +|Register | -| -| 2438| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 8| 8| 11986| 10462| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | ~0| ~0| 1| 2| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | ~0| ~0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + +------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+------+------+-----+ + | Instance | Module | BRAM_18K| DSP| FF | LUT | URAM| + +------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+------+------+-----+ + |grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s_fu_931 |dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s | 8| 8| 7499| 7999| 0| + |call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_fu_543 |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s | 0| 0| 2049| 1888| 0| + +------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+------+------+-----+ + |Total | | 8| 8| 9548| 9887| 0| + +------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+------+------+-----+ + + * DSP: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +---------------------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +---------------------------------+----------+----+---+----+------------+------------+ + |add_ln303_fu_1496_p2 | +| 0| 0| 39| 32| 1| + |add_ln307_fu_1543_p2 | +| 0| 0| 39| 32| 1| + |add_ln313_fu_1565_p2 | +| 0| 0| 39| 32| 1| + |add_ln318_fu_1513_p2 | +| 0| 0| 39| 32| 1| + |and_ln284_7_fu_1293_p2 | and| 0| 0| 2| 1| 1| + |and_ln284_fu_1287_p2 | and| 0| 0| 2| 1| 1| + |ap_block_state3 | and| 0| 0| 2| 1| 1| + |ap_block_state3_on_subcall_done | and| 0| 0| 2| 1| 1| + |ap_condition_1153 | and| 0| 0| 2| 1| 1| + |ap_condition_822 | and| 0| 0| 2| 1| 1| + |ap_predicate_op37_call_state3 | and| 0| 0| 2| 1| 1| + |icmp_ln284_19_fu_1249_p2 | icmp| 0| 0| 39| 32| 2| + |icmp_ln284_20_fu_1265_p2 | icmp| 0| 0| 38| 31| 1| + |icmp_ln284_21_fu_1281_p2 | icmp| 0| 0| 38| 31| 1| + |icmp_ln284_fu_1231_p2 | icmp| 0| 0| 39| 32| 2| + |icmp_ln303_fu_1501_p2 | icmp| 0| 0| 39| 32| 5| + |icmp_ln307_fu_1548_p2 | icmp| 0| 0| 39| 32| 5| + |icmp_ln313_fu_1560_p2 | icmp| 0| 0| 39| 32| 2| + |select_ln313_fu_1570_p3 | select| 0| 0| 32| 1| 2| + |select_ln318_fu_1518_p3 | select| 0| 0| 32| 1| 2| + +---------------------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0| 505| 359| 33| + +---------------------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +-------------------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +-------------------------------------+----+-----------+-----+-----------+ + |ap_NS_fsm | 20| 4| 1| 4| + |ap_phi_mux_storemerge_phi_fu_536_p4 | 14| 3| 32| 96| + |layer12_out_blk_n | 9| 2| 1| 2| + |pX_8 | 9| 2| 32| 64| + |pY_8 | 9| 2| 32| 64| + |sX_8 | 9| 2| 32| 64| + +-------------------------------------+----+-----------+-----+-----------+ + |Total | 70| 15| 130| 294| + +-------------------------------------+----+-----------+-----+-----------+ + + * Register: + +-----------------------------------------------------------------------------------------+----+----+-----+-----------+ + | Name | FF | LUT| Bits| Const Bits| + +-----------------------------------------------------------------------------------------+----+----+-----+-----------+ + |and_ln284_7_reg_1608 | 1| 0| 1| 0| + |ap_CS_fsm | 3| 0| 3| 0| + |grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s_fu_931_ap_start_reg | 1| 0| 1| 0| + |icmp_ln284_reg_1594 | 1| 0| 1| 0| + |pX_8 | 32| 0| 32| 0| + |pY_8 | 32| 0| 32| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4416 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4417 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4419 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4420 | 16| 0| 16| 0| + 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|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4520 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4521 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4522 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4523 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4524 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4525 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4526 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4527 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4529 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4530 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4531 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4532 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4533 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4534 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4535 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4536 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4537 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4538 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4540 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4541 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4542 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4543 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4544 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4545 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4546 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4547 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4548 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4549 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4551 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4552 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4553 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4554 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4555 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4556 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4557 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4558 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4559 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4560 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4562 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4563 | 16| 0| 16| 0| + |sX_8 | 32| 0| 32| 0| + |sY_8 | 32| 0| 32| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_158 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_159 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_160 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_161 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_162 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_163 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_164 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_165 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_166 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_167 | 16| 0| 16| 0| + +-----------------------------------------------------------------------------------------+----+----+-----+-----------+ + |Total |2438| 0| 2438| 0| + +-----------------------------------------------------------------------------------------+----+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------+-----+------+------------+---------------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits | Protocol | Source Object | C Type | ++----------------------------+-----+------+------------+---------------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config12>| return value| +|ap_rst | in| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config12>| return value| +|ap_start | in| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config12>| return value| +|ap_done | out| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config12>| return value| +|ap_idle | out| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config12>| return value| +|ap_ready | out| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config12>| return value| +|p_read | in| 16| ap_none| p_read| scalar| +|p_read1 | in| 16| ap_none| p_read1| scalar| +|p_read2 | in| 16| ap_none| p_read2| scalar| +|p_read3 | in| 16| ap_none| p_read3| scalar| +|p_read4 | in| 16| ap_none| p_read4| scalar| +|p_read5 | in| 16| ap_none| p_read5| scalar| +|p_read6 | in| 16| ap_none| p_read6| scalar| +|p_read7 | in| 16| ap_none| p_read7| scalar| +|p_read8 | in| 16| ap_none| p_read8| scalar| +|p_read9 | in| 16| ap_none| p_read9| scalar| +|p_read10 | in| 16| ap_none| p_read10| scalar| +|p_read11 | in| 16| ap_none| p_read11| scalar| +|p_read12 | in| 16| ap_none| p_read12| scalar| +|p_read13 | in| 16| ap_none| p_read13| scalar| +|p_read14 | in| 16| ap_none| p_read14| scalar| +|p_read15 | in| 16| ap_none| p_read15| scalar| +|layer12_out_din | out| 1312| ap_fifo| layer12_out| pointer| +|layer12_out_num_data_valid | in| 9| ap_fifo| layer12_out| pointer| +|layer12_out_fifo_cap | in| 9| ap_fifo| layer12_out| pointer| +|layer12_out_full_n | in| 1| ap_fifo| layer12_out| pointer| +|layer12_out_write | out| 1| ap_fifo| layer12_out| pointer| ++----------------------------+-----+------+------------+---------------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_csynth.rpt b/myproject_prj/solution1/syn/report/compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..9efef2e38bf5816109af061f1870d24082a90713 --- /dev/null +++ b/myproject_prj/solution1/syn/report/compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_csynth.rpt @@ -0,0 +1,421 @@ + + +================================================================ +== Vitis HLS Report for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s' +================================================================ +* Date: Sun Apr 5 21:50:35 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 2.533 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+----------+----------+-----+-----+---------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline| + | min | max | min | max | min | max | Type | + +---------+---------+----------+----------+-----+-----+---------+ + | 2| 221| 8.000 ns| 0.884 us| 2| 221| no| + +---------+---------+----------+----------+-----+-----+---------+ + + + Detail: + * Instance: + +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+---------+----------+----------+-----+-----+------------------------------------------+ + | | | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | Instance | Module | min | max | min | max | min | max | Type | + +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+---------+----------+----------+-----+-----+------------------------------------------+ + |call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_fu_781 |shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s | 0| 0| 0 ns| 0 ns| 1| 1| yes| + |grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_fu_1361 |dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s | 217| 218| 0.868 us| 0.872 us| 216| 216| loop rewind stp(delay=0 clock cycles(s))| + +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+---------+----------+----------+-----+-----+------------------------------------------+ + + * Loop: + N/A + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 501| -| +|FIFO | -| -| -| -| -| +|Instance | 4| 8| 10784| 10117| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| 0| 76| -| +|Register | -| -| 3919| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 4| 8| 14703| 10694| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | ~0| ~0| 1| 2| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | ~0| ~0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+----+------+------+-----+ + | Instance | Module | BRAM_18K| DSP| FF | LUT | URAM| + +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+----+------+------+-----+ + |grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_fu_1361 |dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s | 4| 8| 7711| 7285| 0| + |call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_fu_781 |shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s | 0| 0| 3073| 2832| 0| + +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+----+------+------+-----+ + |Total | | 4| 8| 10784| 10117| 0| + +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+----+------+------+-----+ + + * DSP: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +--------------------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +--------------------------------+----------+----+---+----+------------+------------+ + |add_ln303_fu_1916_p2 | +| 0| 0| 39| 32| 1| + |add_ln307_fu_1963_p2 | +| 0| 0| 39| 32| 1| + |add_ln313_fu_1985_p2 | +| 0| 0| 39| 32| 1| + |add_ln318_fu_1933_p2 | +| 0| 0| 39| 32| 1| + |and_ln284_6_fu_1865_p2 | and| 0| 0| 2| 1| 1| + |and_ln284_fu_1859_p2 | and| 0| 0| 2| 1| 1| + |ap_block_state4 | and| 0| 0| 2| 1| 1| + |ap_condition_1647 | and| 0| 0| 2| 1| 1| + |ap_predicate_op56_write_state4 | and| 0| 0| 2| 1| 1| + |icmp_ln284_16_fu_1821_p2 | icmp| 0| 0| 39| 32| 2| + |icmp_ln284_17_fu_1837_p2 | icmp| 0| 0| 38| 31| 1| + |icmp_ln284_18_fu_1853_p2 | icmp| 0| 0| 38| 31| 1| + |icmp_ln284_fu_1803_p2 | icmp| 0| 0| 39| 32| 2| + |icmp_ln303_fu_1921_p2 | icmp| 0| 0| 39| 32| 7| + |icmp_ln307_fu_1968_p2 | icmp| 0| 0| 39| 32| 7| + |icmp_ln313_fu_1980_p2 | icmp| 0| 0| 39| 32| 2| + |select_ln313_fu_1990_p3 | select| 0| 0| 32| 1| 2| + |select_ln318_fu_1938_p3 | select| 0| 0| 32| 1| 2| + +--------------------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0| 501| 357| 35| + +--------------------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +-------------------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +-------------------------------------+----+-----------+-----+-----------+ + |ap_NS_fsm | 26| 5| 1| 5| + |ap_phi_mux_storemerge_phi_fu_774_p4 | 14| 3| 32| 96| + |layer35_out_blk_n | 9| 2| 1| 2| + |pX_6 | 9| 2| 32| 64| + |pY_6 | 9| 2| 32| 64| + |sX_6 | 9| 2| 32| 64| + +-------------------------------------+----+-----------+-----+-----------+ + |Total | 76| 16| 130| 295| + +-------------------------------------+----+-----------+-----+-----------+ + + * Register: + +--------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + | Name | FF | LUT| Bits| Const Bits| + +--------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + |and_ln284_6_reg_2028 | 1| 0| 1| 0| + |ap_CS_fsm | 4| 0| 4| 0| + |grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_fu_1361_ap_start_reg | 1| 0| 1| 0| + |icmp_ln284_reg_2014 | 1| 0| 1| 0| + |pX_6 | 32| 0| 32| 0| + |pY_6 | 32| 0| 32| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4564 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4565 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4566 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4567 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4568 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4569 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4570 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4571 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4573 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4574 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4575 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4576 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4577 | 16| 0| 16| 0| + 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|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4736 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4738 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4739 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4740 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4741 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4742 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4743 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4744 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4745 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4746 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4747 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4749 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4750 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4751 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4752 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4753 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4754 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4755 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4756 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4757 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4758 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4760 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4761 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4762 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4763 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4764 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4765 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4766 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4767 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4768 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4769 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4771 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4772 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4773 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4774 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4775 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4776 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4777 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4778 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4779 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4780 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4782 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4783 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4784 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4785 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4786 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4787 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4788 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4789 | 16| 0| 16| 0| + |res_out_1_reg_2037 | 41| 0| 41| 0| + |res_out_2_reg_2042 | 41| 0| 41| 0| + |res_out_3_reg_2047 | 41| 0| 41| 0| + |res_out_4_reg_2052 | 41| 0| 41| 0| + |res_out_5_reg_2057 | 41| 0| 41| 0| + |res_out_6_reg_2062 | 41| 0| 41| 0| + |res_out_7_reg_2067 | 41| 0| 41| 0| + |res_out_reg_2032 | 41| 0| 41| 0| + |sX_6 | 32| 0| 32| 0| + |sY_6 | 32| 0| 32| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_90 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_91 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_92 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_93 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_94 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_95 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_96 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_97 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_98 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_99 | 16| 0| 16| 0| + +--------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + |Total |3919| 0| 3919| 0| + +--------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------+-----+-----+------------+--------------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++----------------------------+-----+-----+------------+--------------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| compute_output_buffer_2d,8u>,config35>| return value| +|ap_rst | in| 1| ap_ctrl_hs| compute_output_buffer_2d,8u>,config35>| return value| +|ap_start | in| 1| ap_ctrl_hs| compute_output_buffer_2d,8u>,config35>| return value| +|ap_done | out| 1| ap_ctrl_hs| compute_output_buffer_2d,8u>,config35>| return value| +|ap_idle | out| 1| ap_ctrl_hs| compute_output_buffer_2d,8u>,config35>| return value| +|ap_ready | out| 1| ap_ctrl_hs| compute_output_buffer_2d,8u>,config35>| return value| +|p_read | in| 16| ap_none| p_read| scalar| +|p_read1 | in| 16| ap_none| p_read1| scalar| +|p_read2 | in| 16| ap_none| p_read2| scalar| +|p_read3 | in| 16| ap_none| p_read3| scalar| +|p_read4 | in| 16| ap_none| p_read4| scalar| +|p_read5 | in| 16| ap_none| p_read5| scalar| +|p_read6 | in| 16| ap_none| p_read6| scalar| +|p_read7 | in| 16| ap_none| p_read7| scalar| +|p_read8 | in| 16| ap_none| p_read8| scalar| +|p_read9 | in| 16| ap_none| p_read9| scalar| +|p_read10 | in| 16| ap_none| p_read10| scalar| +|p_read11 | in| 16| ap_none| p_read11| scalar| +|p_read12 | in| 16| ap_none| p_read12| scalar| +|p_read13 | in| 16| ap_none| p_read13| scalar| +|p_read14 | in| 16| ap_none| p_read14| scalar| +|p_read15 | in| 16| ap_none| p_read15| scalar| +|p_read16 | in| 16| ap_none| p_read16| scalar| +|p_read17 | in| 16| ap_none| p_read17| scalar| +|p_read18 | in| 16| ap_none| p_read18| scalar| +|p_read19 | in| 16| ap_none| p_read19| scalar| +|p_read20 | in| 16| ap_none| p_read20| scalar| +|p_read21 | in| 16| ap_none| p_read21| scalar| +|p_read22 | in| 16| ap_none| p_read22| scalar| +|p_read23 | in| 16| ap_none| p_read23| scalar| +|layer35_out_din | out| 328| ap_fifo| layer35_out| pointer| +|layer35_out_num_data_valid | in| 13| ap_fifo| layer35_out| pointer| +|layer35_out_fifo_cap | in| 13| ap_fifo| layer35_out| pointer| +|layer35_out_full_n | in| 1| ap_fifo| layer35_out| pointer| +|layer35_out_write | out| 1| ap_fifo| layer35_out| pointer| ++----------------------------+-----+-----+------------+--------------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_csynth.xml b/myproject_prj/solution1/syn/report/compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..2947d04852e1981c289fe67ce1195f3760816ff0 --- /dev/null +++ b/myproject_prj/solution1/syn/report/compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_csynth.xml @@ -0,0 +1,710 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s +4.00 +1.35 +vivado + + + +no + +ns +2.533 + + +clock cycles +2 +147 +437 +8.000 ns +0.588 us +1.748 us +2 +437 + + +- +- +firmware/nnet_utils/nnet_conv_stream.h:281 + + + + + +8 +16 +29287 +20707 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +compute_output_buffer_2d<array,array<ap_fixed<42,22,5,3,0>,16u>,config29> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +compute_output_buffer_2d<array,array<ap_fixed<42,22,5,3,0>,16u>,config29> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +compute_output_buffer_2d<array,array<ap_fixed<42,22,5,3,0>,16u>,config29> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_done +compute_output_buffer_2d<array,array<ap_fixed<42,22,5,3,0>,16u>,config29> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_idle +compute_output_buffer_2d<array,array<ap_fixed<42,22,5,3,0>,16u>,config29> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +compute_output_buffer_2d<array,array<ap_fixed<42,22,5,3,0>,16u>,config29> +return value + +ap_ctrl_hs + +out +1 +control + + +p_read +p_read +scalar + +ap_none + +in +16 +data + + +p_read1 +p_read1 +scalar + +ap_none + +in +16 +data + + +p_read2 +p_read2 +scalar + +ap_none + +in +16 +data + + +p_read3 +p_read3 +scalar + +ap_none + +in +16 +data + + +p_read4 +p_read4 +scalar + +ap_none + +in +16 +data + + +p_read5 +p_read5 +scalar + +ap_none + +in +16 +data + + +p_read6 +p_read6 +scalar + +ap_none + +in +16 +data + + +p_read7 +p_read7 +scalar + +ap_none + +in +16 +data + + +p_read8 +p_read8 +scalar + +ap_none + +in +16 +data + + +p_read9 +p_read9 +scalar + +ap_none + +in +16 +data + + +p_read10 +p_read10 +scalar + +ap_none + +in +16 +data + + +p_read11 +p_read11 +scalar + +ap_none + +in +16 +data + + +p_read12 +p_read12 +scalar + +ap_none + +in +16 +data + + +p_read13 +p_read13 +scalar + +ap_none + +in +16 +data + + +p_read14 +p_read14 +scalar + +ap_none + +in +16 +data + + +p_read15 +p_read15 +scalar + +ap_none + +in +16 +data + + +p_read16 +p_read16 +scalar + +ap_none + +in +16 +data + + +p_read17 +p_read17 +scalar + +ap_none + +in +16 +data + + +p_read18 +p_read18 +scalar + +ap_none + +in +16 +data + + +p_read19 +p_read19 +scalar + +ap_none + +in +16 +data + + +p_read20 +p_read20 +scalar + +ap_none + +in +16 +data + + +p_read21 +p_read21 +scalar + +ap_none + +in +16 +data + + +p_read22 +p_read22 +scalar + +ap_none + +in +16 +data + + +p_read23 +p_read23 +scalar + +ap_none + +in +16 +data + + +p_read24 +p_read24 +scalar + +ap_none + +in +16 +data + + +p_read25 +p_read25 +scalar + +ap_none + +in +16 +data + + +p_read26 +p_read26 +scalar + +ap_none + +in +16 +data + + +p_read27 +p_read27 +scalar + +ap_none + +in +16 +data + + +p_read28 +p_read28 +scalar + +ap_none + +in +16 +data + + +p_read29 +p_read29 +scalar + +ap_none + +in +16 +data + + +p_read30 +p_read30 +scalar + +ap_none + +in +16 +data + + +p_read31 +p_read31 +scalar + +ap_none + +in +16 +data + + +p_read32 +p_read32 +scalar + +ap_none + +in +16 +data + + +p_read33 +p_read33 +scalar + +ap_none + +in +16 +data + + +p_read34 +p_read34 +scalar + +ap_none + +in +16 +data + + +p_read35 +p_read35 +scalar + +ap_none + +in +16 +data + + +p_read36 +p_read36 +scalar + +ap_none + +in +16 +data + + +p_read37 +p_read37 +scalar + +ap_none + +in +16 +data + + +p_read38 +p_read38 +scalar + +ap_none + +in +16 +data + + +p_read39 +p_read39 +scalar + +ap_none + +in +16 +data + + +p_read40 +p_read40 +scalar + +ap_none + +in +16 +data + + +p_read41 +p_read41 +scalar + +ap_none + +in +16 +data + + +p_read42 +p_read42 +scalar + +ap_none + +in +16 +data + + +p_read43 +p_read43 +scalar + +ap_none + +in +16 +data + + +p_read44 +p_read44 +scalar + +ap_none + +in +16 +data + + +p_read45 +p_read45 +scalar + +ap_none + +in +16 +data + + +p_read46 +p_read46 +scalar + +ap_none + +in +16 +data + + +p_read47 +p_read47 +scalar + +ap_none + +in +16 +data + + +layer29_out_din +layer29_out +pointer + +ap_fifo + +out +672 +control + + +layer29_out_num_data_valid +layer29_out +pointer + +ap_fifo + +in +11 +control + + +layer29_out_fifo_cap +layer29_out +pointer + +ap_fifo + +in +11 +unknown + + +layer29_out_full_n +layer29_out +pointer + +ap_fifo + +in +1 +control + + +layer29_out_write +layer29_out +pointer + +ap_fifo + +out +1 +control + + + + diff --git a/myproject_prj/solution1/syn/report/compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_csynth.rpt b/myproject_prj/solution1/syn/report/compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..7a0fec68b385b2e703c6d161b3ba957e64a86642 --- /dev/null +++ b/myproject_prj/solution1/syn/report/compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_csynth.rpt @@ -0,0 +1,525 @@ + + +================================================================ +== Vitis HLS Report for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s' +================================================================ +* Date: Sun Apr 5 21:47:13 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 4.118 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+----------+----------+-----+-----+---------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline| + | min | max | min | max | min | max | Type | + +---------+---------+----------+----------+-----+-----+---------+ + | 2| 581| 8.236 ns| 2.393 us| 2| 581| no| + +---------+---------+----------+----------+-----+-----+---------+ + + + Detail: + * Instance: + +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+---------+----------+----------+-----+-----+------------------------------------------+ + | | | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | Instance | Module | min | max | min | max | min | max | Type | + +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+---------+----------+----------+-----+-----+------------------------------------------+ + |call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_fu_1023 |shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s | 0| 0| 0 ns| 0 ns| 1| 1| yes| + |grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_fu_1795 |dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s | 577| 578| 2.376 us| 2.380 us| 576| 576| loop rewind stp(delay=0 clock cycles(s))| + +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+---------+----------+----------+-----+-----+------------------------------------------+ + + * Loop: + N/A + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 501| -| +|FIFO | -| -| -| -| -| +|Instance | 15| 16| 11522| 19870| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| 0| 76| -| +|Register | -| -| 6087| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 15| 16| 17609| 20447| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 1| ~0| 2| 4| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | ~0| ~0| ~0| 1| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+------+-------+-----+ + | Instance | Module | BRAM_18K| DSP| FF | LUT | URAM| + +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+------+-------+-----+ + |grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_fu_1795 |dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s | 15| 16| 7425| 16094| 0| + |call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_fu_1023 |shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s | 0| 0| 4097| 3776| 0| + +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+------+-------+-----+ + |Total | | 15| 16| 11522| 19870| 0| + +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+------+-------+-----+ + + * DSP: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +--------------------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +--------------------------------+----------+----+---+----+------------+------------+ + |add_ln303_fu_2616_p2 | +| 0| 0| 39| 32| 1| + |add_ln307_fu_2663_p2 | +| 0| 0| 39| 32| 1| + |add_ln313_fu_2685_p2 | +| 0| 0| 39| 32| 1| + |add_ln318_fu_2633_p2 | +| 0| 0| 39| 32| 1| + |and_ln284_4_fu_2445_p2 | and| 0| 0| 2| 1| 1| + |and_ln284_fu_2439_p2 | and| 0| 0| 2| 1| 1| + |ap_block_state4 | and| 0| 0| 2| 1| 1| + |ap_condition_2223 | and| 0| 0| 2| 1| 1| + |ap_predicate_op88_write_state4 | and| 0| 0| 2| 1| 1| + |icmp_ln284_10_fu_2401_p2 | icmp| 0| 0| 39| 32| 2| + |icmp_ln284_11_fu_2417_p2 | icmp| 0| 0| 38| 31| 1| + |icmp_ln284_12_fu_2433_p2 | icmp| 0| 0| 38| 31| 1| + |icmp_ln284_fu_2383_p2 | icmp| 0| 0| 39| 32| 2| + |icmp_ln303_fu_2621_p2 | icmp| 0| 0| 39| 32| 5| + |icmp_ln307_fu_2668_p2 | icmp| 0| 0| 39| 32| 5| + |icmp_ln313_fu_2680_p2 | icmp| 0| 0| 39| 32| 2| + |select_ln313_fu_2690_p3 | select| 0| 0| 32| 1| 2| + |select_ln318_fu_2638_p3 | select| 0| 0| 32| 1| 2| + +--------------------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0| 501| 357| 31| + +--------------------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +--------------------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +--------------------------------------+----+-----------+-----+-----------+ + |ap_NS_fsm | 26| 5| 1| 5| + |ap_phi_mux_storemerge_phi_fu_1016_p4 | 14| 3| 32| 96| + |layer14_out_blk_n | 9| 2| 1| 2| + |pX_5 | 9| 2| 32| 64| + |pY_5 | 9| 2| 32| 64| + |sX_5 | 9| 2| 32| 64| + +--------------------------------------+----+-----------+-----+-----------+ + |Total | 76| 16| 130| 295| + +--------------------------------------+----+-----------+-----+-----------+ + + * Register: + +------------------------------------------------------------------------------------------+----+----+-----+-----------+ + | Name | FF | LUT| Bits| Const Bits| + +------------------------------------------------------------------------------------------+----+----+-----+-----------+ + |and_ln284_4_reg_2728 | 1| 0| 1| 0| + |ap_CS_fsm | 4| 0| 4| 0| + |grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_fu_1795_ap_start_reg | 1| 0| 1| 0| + |icmp_ln284_reg_2714 | 1| 0| 1| 0| + |pX_5 | 32| 0| 32| 0| + |pY_5 | 32| 0| 32| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4790 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4791 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4793 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4794 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4795 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4796 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4797 | 16| 0| 16| 0| + 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|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5065 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5066 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5068 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5069 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5070 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5071 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5072 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5073 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5074 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5075 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5076 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5077 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5079 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5080 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5081 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5082 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5083 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5084 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5085 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5086 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5087 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5088 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5090 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5091 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5092 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5093 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5094 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5095 | 16| 0| 16| 0| + |res_out_162_reg_2782 | 42| 0| 42| 0| + |res_out_163_reg_2787 | 42| 0| 42| 0| + |res_out_164_reg_2792 | 42| 0| 42| 0| + |res_out_165_reg_2797 | 42| 0| 42| 0| + |res_out_166_reg_2802 | 42| 0| 42| 0| + |res_out_167_reg_2807 | 42| 0| 42| 0| + |res_out_168_reg_2812 | 42| 0| 42| 0| + |res_out_169_reg_2817 | 42| 0| 42| 0| + |res_out_170_reg_2822 | 42| 0| 42| 0| + |res_out_171_reg_2827 | 42| 0| 42| 0| + |res_out_172_reg_2832 | 42| 0| 42| 0| + |res_out_173_reg_2837 | 42| 0| 42| 0| + |res_out_174_reg_2842 | 42| 0| 42| 0| + |res_out_175_reg_2847 | 42| 0| 42| 0| + |res_out_176_reg_2852 | 42| 0| 42| 0| + |res_out_177_reg_2857 | 42| 0| 42| 0| + |res_out_178_reg_2862 | 42| 0| 42| 0| + |res_out_179_reg_2867 | 42| 0| 42| 0| + |res_out_180_reg_2872 | 42| 0| 42| 0| + |res_out_181_reg_2877 | 42| 0| 42| 0| + |res_out_182_reg_2882 | 42| 0| 42| 0| + |res_out_183_reg_2887 | 42| 0| 42| 0| + |res_out_1_reg_2737 | 42| 0| 42| 0| + |res_out_2_reg_2742 | 42| 0| 42| 0| + |res_out_3_reg_2747 | 42| 0| 42| 0| + |res_out_4_reg_2752 | 42| 0| 42| 0| + |res_out_5_reg_2757 | 42| 0| 42| 0| + |res_out_6_reg_2762 | 42| 0| 42| 0| + |res_out_7_reg_2767 | 42| 0| 42| 0| + |res_out_8_reg_2772 | 42| 0| 42| 0| + |res_out_9_reg_2777 | 42| 0| 42| 0| + |res_out_reg_2732 | 42| 0| 42| 0| + |sX_5 | 32| 0| 32| 0| + |sY_5 | 32| 0| 32| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_80 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_81 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_82 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_83 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_84 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_85 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_86 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_87 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_88 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_89 | 16| 0| 16| 0| + +------------------------------------------------------------------------------------------+----+----+-----+-----------+ + |Total |6087| 0| 6087| 0| + +------------------------------------------------------------------------------------------+----+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------+-----+------+------------+---------------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits | Protocol | Source Object | C Type | ++----------------------------+-----+------+------------+---------------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config14>| return value| +|ap_rst | in| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config14>| return value| +|ap_start | in| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config14>| return value| +|ap_done | out| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config14>| return value| +|ap_idle | out| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config14>| return value| +|ap_ready | out| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config14>| return value| +|p_read | in| 16| ap_none| p_read| scalar| +|p_read1 | in| 16| ap_none| p_read1| scalar| +|p_read2 | in| 16| ap_none| p_read2| scalar| +|p_read3 | in| 16| ap_none| p_read3| scalar| +|p_read4 | in| 16| ap_none| p_read4| scalar| +|p_read5 | in| 16| ap_none| p_read5| scalar| +|p_read6 | in| 16| ap_none| p_read6| scalar| +|p_read7 | in| 16| ap_none| p_read7| scalar| +|p_read8 | in| 16| ap_none| p_read8| scalar| +|p_read9 | in| 16| ap_none| p_read9| scalar| +|p_read10 | in| 16| ap_none| p_read10| scalar| +|p_read11 | in| 16| ap_none| p_read11| scalar| +|p_read12 | in| 16| ap_none| p_read12| scalar| +|p_read13 | in| 16| ap_none| p_read13| scalar| +|p_read14 | in| 16| ap_none| p_read14| scalar| +|p_read15 | in| 16| ap_none| p_read15| scalar| +|p_read16 | in| 16| ap_none| p_read16| scalar| +|p_read17 | in| 16| ap_none| p_read17| scalar| +|p_read18 | in| 16| ap_none| p_read18| scalar| +|p_read19 | in| 16| ap_none| p_read19| scalar| +|p_read20 | in| 16| ap_none| p_read20| scalar| +|p_read21 | in| 16| ap_none| p_read21| scalar| +|p_read22 | in| 16| ap_none| p_read22| scalar| +|p_read23 | in| 16| ap_none| p_read23| scalar| +|p_read24 | in| 16| ap_none| p_read24| scalar| +|p_read25 | in| 16| ap_none| p_read25| scalar| +|p_read26 | in| 16| ap_none| p_read26| scalar| +|p_read27 | in| 16| ap_none| p_read27| scalar| +|p_read28 | in| 16| ap_none| p_read28| scalar| +|p_read29 | in| 16| ap_none| p_read29| scalar| +|p_read30 | in| 16| ap_none| p_read30| scalar| +|p_read31 | in| 16| ap_none| p_read31| scalar| +|layer14_out_din | out| 1344| ap_fifo| layer14_out| pointer| +|layer14_out_num_data_valid | in| 9| ap_fifo| layer14_out| pointer| +|layer14_out_fifo_cap | in| 9| ap_fifo| layer14_out| pointer| +|layer14_out_full_n | in| 1| ap_fifo| layer14_out| pointer| +|layer14_out_write | out| 1| ap_fifo| layer14_out| pointer| ++----------------------------+-----+------+------------+---------------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s_csynth.rpt b/myproject_prj/solution1/syn/report/compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..3714f47d41d34660ceebebf316861d0d60865e70 --- /dev/null +++ b/myproject_prj/solution1/syn/report/compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s_csynth.rpt @@ -0,0 +1,495 @@ + + +================================================================ +== Vitis HLS Report for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +================================================================ +* Date: Sun Apr 5 21:49:26 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 4.449 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+----------+----------+-----+------+---------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline| + | min | max | min | max | min | max | Type | + +---------+---------+----------+----------+-----+------+---------+ + | 2| 1157| 8.899 ns| 5.148 us| 2| 1157| no| + +---------+---------+----------+----------+-----+------+---------+ + + + Detail: + * Instance: + +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+---------+----------+----------+------+------+------------------------------------------+ + | | | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | Instance | Module | min | max | min | max | min | max | Type | + +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+---------+----------+----------+------+------+------------------------------------------+ + |call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_fu_1023 |shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s | 0| 0| 0 ns| 0 ns| 1| 1| yes| + |grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s_fu_1795 |dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s | 1154| 1155| 5.135 us| 5.139 us| 1152| 1152| loop rewind stp(delay=0 clock cycles(s))| + +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+---------+----------+----------+------+------+------------------------------------------+ + + * Loop: + N/A + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 505| -| +|FIFO | -| -| -| -| -| +|Instance | 16| 8| 16268| 16447| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| 0| 70| -| +|Register | -| -| 4742| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 16| 8| 21010| 17022| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 1| ~0| 2| 3| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | ~0| ~0| ~0| 1| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+-------+-------+-----+ + | Instance | Module | BRAM_18K| DSP| FF | LUT | URAM| + +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+-------+-------+-----+ + |grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s_fu_1795 |dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s | 16| 8| 12171| 12671| 0| + |call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_fu_1023 |shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s | 0| 0| 4097| 3776| 0| + +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+-------+-------+-----+ + |Total | | 16| 8| 16268| 16447| 0| + +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+-------+-------+-----+ + + * DSP: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +---------------------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +---------------------------------+----------+----+---+----+------------+------------+ + |add_ln303_fu_2648_p2 | +| 0| 0| 39| 32| 1| + |add_ln307_fu_2695_p2 | +| 0| 0| 39| 32| 1| + |add_ln313_fu_2717_p2 | +| 0| 0| 39| 32| 1| + |add_ln318_fu_2665_p2 | +| 0| 0| 39| 32| 1| + |and_ln284_3_fu_2445_p2 | and| 0| 0| 2| 1| 1| + |and_ln284_fu_2439_p2 | and| 0| 0| 2| 1| 1| + |ap_block_state3 | and| 0| 0| 2| 1| 1| + |ap_block_state3_on_subcall_done | and| 0| 0| 2| 1| 1| + |ap_condition_1526 | and| 0| 0| 2| 1| 1| + |ap_condition_2161 | and| 0| 0| 2| 1| 1| + |ap_predicate_op53_call_state3 | and| 0| 0| 2| 1| 1| + |icmp_ln284_7_fu_2401_p2 | icmp| 0| 0| 39| 32| 2| + |icmp_ln284_8_fu_2417_p2 | icmp| 0| 0| 38| 31| 1| + |icmp_ln284_9_fu_2433_p2 | icmp| 0| 0| 38| 31| 1| + |icmp_ln284_fu_2383_p2 | icmp| 0| 0| 39| 32| 2| + |icmp_ln303_fu_2653_p2 | icmp| 0| 0| 39| 32| 5| + |icmp_ln307_fu_2700_p2 | icmp| 0| 0| 39| 32| 5| + |icmp_ln313_fu_2712_p2 | icmp| 0| 0| 39| 32| 2| + |select_ln313_fu_2722_p3 | select| 0| 0| 32| 1| 2| + |select_ln318_fu_2670_p3 | select| 0| 0| 32| 1| 2| + +---------------------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0| 505| 359| 33| + +---------------------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +--------------------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +--------------------------------------+----+-----------+-----+-----------+ + |ap_NS_fsm | 20| 4| 1| 4| + |ap_phi_mux_storemerge_phi_fu_1016_p4 | 14| 3| 32| 96| + |layer25_out_blk_n | 9| 2| 1| 2| + |pX_4 | 9| 2| 32| 64| + |pY_4 | 9| 2| 32| 64| + |sX_4 | 9| 2| 32| 64| + +--------------------------------------+----+-----------+-----+-----------+ + |Total | 70| 15| 130| 294| + +--------------------------------------+----+-----------+-----+-----------+ + + * Register: + +------------------------------------------------------------------------------------------+----+----+-----+-----------+ + | Name | FF | LUT| Bits| Const Bits| + +------------------------------------------------------------------------------------------+----+----+-----+-----------+ + |and_ln284_3_reg_2760 | 1| 0| 1| 0| + |ap_CS_fsm | 3| 0| 3| 0| + |grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s_fu_1795_ap_start_reg | 1| 0| 1| 0| + |icmp_ln284_reg_2746 | 1| 0| 1| 0| + |pX_4 | 32| 0| 32| 0| + |pY_4 | 32| 0| 32| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5096 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5097 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5098 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5099 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5101 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5102 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5103 | 16| 0| 16| 0| + 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|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5361 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5362 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5363 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5365 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5366 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5367 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5368 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5369 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5370 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5371 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5372 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5373 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5374 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5376 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5377 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5378 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5379 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5380 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5381 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5382 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5383 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5384 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5385 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5387 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5388 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5389 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5390 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5391 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5392 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5393 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5394 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5395 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5396 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5398 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5399 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5400 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5401 | 16| 0| 16| 0| + |sX_4 | 32| 0| 32| 0| + |sY_4 | 32| 0| 32| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_70 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_71 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_72 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_73 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_74 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_75 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_76 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_77 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_78 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_79 | 16| 0| 16| 0| + +------------------------------------------------------------------------------------------+----+----+-----+-----------+ + |Total |4742| 0| 4742| 0| + +------------------------------------------------------------------------------------------+----+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------+-----+------+------------+---------------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits | Protocol | Source Object | C Type | ++----------------------------+-----+------+------------+---------------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config25>| return value| +|ap_rst | in| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config25>| return value| +|ap_start | in| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config25>| return value| +|ap_done | out| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config25>| return value| +|ap_idle | out| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config25>| return value| +|ap_ready | out| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config25>| return value| +|p_read | in| 16| ap_none| p_read| scalar| +|p_read1 | in| 16| ap_none| p_read1| scalar| +|p_read2 | in| 16| ap_none| p_read2| scalar| +|p_read3 | in| 16| ap_none| p_read3| scalar| +|p_read4 | in| 16| ap_none| p_read4| scalar| +|p_read5 | in| 16| ap_none| p_read5| scalar| +|p_read6 | in| 16| ap_none| p_read6| scalar| +|p_read7 | in| 16| ap_none| p_read7| scalar| +|p_read8 | in| 16| ap_none| p_read8| scalar| +|p_read9 | in| 16| ap_none| p_read9| scalar| +|p_read10 | in| 16| ap_none| p_read10| scalar| +|p_read11 | in| 16| ap_none| p_read11| scalar| +|p_read12 | in| 16| ap_none| p_read12| scalar| +|p_read13 | in| 16| ap_none| p_read13| scalar| +|p_read14 | in| 16| ap_none| p_read14| scalar| +|p_read15 | in| 16| ap_none| p_read15| scalar| +|p_read16 | in| 16| ap_none| p_read16| scalar| +|p_read17 | in| 16| ap_none| p_read17| scalar| +|p_read18 | in| 16| ap_none| p_read18| scalar| +|p_read19 | in| 16| ap_none| p_read19| scalar| +|p_read20 | in| 16| ap_none| p_read20| scalar| +|p_read21 | in| 16| ap_none| p_read21| scalar| +|p_read22 | in| 16| ap_none| p_read22| scalar| +|p_read23 | in| 16| ap_none| p_read23| scalar| +|p_read24 | in| 16| ap_none| p_read24| scalar| +|p_read25 | in| 16| ap_none| p_read25| scalar| +|p_read26 | in| 16| ap_none| p_read26| scalar| +|p_read27 | in| 16| ap_none| p_read27| scalar| +|p_read28 | in| 16| ap_none| p_read28| scalar| +|p_read29 | in| 16| ap_none| p_read29| scalar| +|p_read30 | in| 16| ap_none| p_read30| scalar| +|p_read31 | in| 16| ap_none| p_read31| scalar| +|layer25_out_din | out| 1344| ap_fifo| layer25_out| pointer| +|layer25_out_num_data_valid | in| 9| ap_fifo| layer25_out| pointer| +|layer25_out_fifo_cap | in| 9| ap_fifo| layer25_out| pointer| +|layer25_out_full_n | in| 1| ap_fifo| layer25_out| pointer| +|layer25_out_write | out| 1| ap_fifo| layer25_out| pointer| ++----------------------------+-----+------+------------+---------------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s_csynth.rpt b/myproject_prj/solution1/syn/report/compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..eef03646d3acc0b2b1bdde6c8315f6186c781c80 --- /dev/null +++ b/myproject_prj/solution1/syn/report/compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s_csynth.rpt @@ -0,0 +1,1165 @@ + + +================================================================ +== Vitis HLS Report for 'compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +================================================================ +* Date: Sun Apr 5 21:49:03 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 2.533 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+----------+----------+-----+-----+---------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline| + | min | max | min | max | min | max | Type | + +---------+---------+----------+----------+-----+-----+---------+ + | 2| 869| 8.000 ns| 3.476 us| 2| 869| no| + +---------+---------+----------+----------+-----+-----+---------+ + + + Detail: + * Instance: + +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+---------+----------+----------+-----+-----+------------------------------------------+ + | | | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | Instance | Module | min | max | min | max | min | max | Type | + +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+---------+----------+----------+-----+-----+------------------------------------------+ + |call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_fu_2941 |shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s | 0| 0| 0 ns| 0 ns| 1| 1| yes| + |grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_fu_5249 |dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s | 865| 866| 3.460 us| 3.464 us| 864| 864| loop rewind stp(delay=0 clock cycles(s))| + +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+---------+----------+----------+-----+-----+------------------------------------------+ + + * Loop: + N/A + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 501| -| +|FIFO | -| -| -| -| -| +|Instance | 25| 32| 43170| 38308| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| 0| 76| -| +|Register | -| -| 15335| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 25| 32| 58505| 38885| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 1| 1| 6| 8| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | ~0| ~0| 2| 2| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+----+-------+-------+-----+ + | Instance | Module | BRAM_18K| DSP| FF | LUT | URAM| + +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+----+-------+-------+-----+ + |grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_fu_5249 |dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s | 25| 32| 30881| 26980| 0| + |call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_fu_2941 |shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s | 0| 0| 12289| 11328| 0| + +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+----+-------+-------+-----+ + |Total | | 25| 32| 43170| 38308| 0| + +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+----+-------+-------+-----+ + + * DSP: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +---------------------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +---------------------------------+----------+----+---+----+------------+------------+ + |add_ln303_fu_7220_p2 | +| 0| 0| 39| 32| 1| + |add_ln307_fu_7267_p2 | +| 0| 0| 39| 32| 1| + |add_ln313_fu_7289_p2 | +| 0| 0| 39| 32| 1| + |add_ln318_fu_7237_p2 | +| 0| 0| 39| 32| 1| + |and_ln284_1_fu_7049_p2 | and| 0| 0| 2| 1| 1| + |and_ln284_fu_7043_p2 | and| 0| 0| 2| 1| 1| + |ap_block_state4 | and| 0| 0| 2| 1| 1| + |ap_condition_6255 | and| 0| 0| 2| 1| 1| + |ap_predicate_op152_write_state4 | and| 0| 0| 2| 1| 1| + |icmp_ln284_1_fu_7005_p2 | icmp| 0| 0| 39| 32| 2| + |icmp_ln284_4_fu_7021_p2 | icmp| 0| 0| 38| 31| 1| + |icmp_ln284_5_fu_7037_p2 | icmp| 0| 0| 38| 31| 1| + |icmp_ln284_fu_6987_p2 | icmp| 0| 0| 39| 32| 2| + |icmp_ln303_fu_7225_p2 | icmp| 0| 0| 39| 32| 5| + |icmp_ln307_fu_7272_p2 | icmp| 0| 0| 39| 32| 5| + |icmp_ln313_fu_7284_p2 | icmp| 0| 0| 39| 32| 2| + |select_ln313_fu_7294_p3 | select| 0| 0| 32| 1| 2| + |select_ln318_fu_7242_p3 | select| 0| 0| 32| 1| 2| + +---------------------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0| 501| 357| 31| + +---------------------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +--------------------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +--------------------------------------+----+-----------+-----+-----------+ + |ap_NS_fsm | 26| 5| 1| 5| + |ap_phi_mux_storemerge_phi_fu_2934_p4 | 14| 3| 32| 96| + |layer23_out_blk_n | 9| 2| 1| 2| + |pX_12 | 9| 2| 32| 64| + |pY_12 | 9| 2| 32| 64| + |sX_12 | 9| 2| 32| 64| + +--------------------------------------+----+-----------+-----+-----------+ + |Total | 76| 16| 130| 295| + +--------------------------------------+----+-----------+-----+-----------+ + + * Register: + +--------------------------------------------------------------------------------------------------+-----+----+-----+-----------+ + | Name | FF | LUT| Bits| Const Bits| + +--------------------------------------------------------------------------------------------------+-----+----+-----+-----------+ + |and_ln284_1_reg_7332 | 1| 0| 1| 0| + |ap_CS_fsm | 4| 0| 4| 0| + |grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_fu_5249_ap_start_reg | 1| 0| 1| 0| + |icmp_ln284_reg_7318 | 1| 0| 1| 0| + |pX_12 | 32| 0| 32| 0| + |pY_12 | 32| 0| 32| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_1 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_10 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_16 | 16| 0| 16| 0| + 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|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_84 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_85 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_86 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_87 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_88 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_89 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_9 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_90 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_91 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_92 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_93 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_94 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_95 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_96 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_97 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_98 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_99 | 16| 0| 16| 0| + |res_out_1_reg_7341 | 43| 0| 43| 0| + |res_out_2_reg_7346 | 43| 0| 43| 0| + |res_out_3_reg_7351 | 43| 0| 43| 0| + |res_out_4_reg_7356 | 43| 0| 43| 0| + |res_out_5_reg_7361 | 43| 0| 43| 0| + |res_out_64_reg_7386 | 43| 0| 43| 0| + |res_out_65_reg_7391 | 43| 0| 43| 0| + |res_out_66_reg_7396 | 43| 0| 43| 0| + |res_out_67_reg_7401 | 43| 0| 43| 0| + |res_out_68_reg_7406 | 43| 0| 43| 0| + |res_out_69_reg_7411 | 43| 0| 43| 0| + |res_out_6_reg_7366 | 43| 0| 43| 0| + |res_out_70_reg_7416 | 43| 0| 43| 0| + |res_out_71_reg_7421 | 43| 0| 43| 0| + |res_out_72_reg_7426 | 43| 0| 43| 0| + |res_out_73_reg_7431 | 43| 0| 43| 0| + |res_out_74_reg_7436 | 43| 0| 43| 0| + |res_out_75_reg_7441 | 43| 0| 43| 0| + |res_out_76_reg_7446 | 43| 0| 43| 0| + |res_out_77_reg_7451 | 43| 0| 43| 0| + |res_out_78_reg_7456 | 43| 0| 43| 0| + |res_out_79_reg_7461 | 43| 0| 43| 0| + |res_out_7_reg_7371 | 43| 0| 43| 0| + |res_out_80_reg_7466 | 43| 0| 43| 0| + |res_out_81_reg_7471 | 43| 0| 43| 0| + |res_out_82_reg_7476 | 43| 0| 43| 0| + |res_out_83_reg_7481 | 43| 0| 43| 0| + |res_out_84_reg_7486 | 43| 0| 43| 0| + |res_out_85_reg_7491 | 43| 0| 43| 0| + |res_out_8_reg_7376 | 43| 0| 43| 0| + |res_out_9_reg_7381 | 43| 0| 43| 0| + |res_out_reg_7336 | 43| 0| 43| 0| + |sX_12 | 32| 0| 32| 0| + |sY_12 | 32| 0| 32| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_1 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_2 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_3 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_4 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_5 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_6 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_7 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_8 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_9 | 16| 0| 16| 0| + +--------------------------------------------------------------------------------------------------+-----+----+-----+-----------+ + |Total |15335| 0|15335| 0| + +--------------------------------------------------------------------------------------------------+-----+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------+-----+------+------------+---------------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits | Protocol | Source Object | C Type | ++----------------------------+-----+------+------------+---------------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config23>| return value| +|ap_rst | in| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config23>| return value| +|ap_start | in| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config23>| return value| +|ap_done | out| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config23>| return value| +|ap_idle | out| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config23>| return value| +|ap_ready | out| 1| ap_ctrl_hs| compute_output_buffer_2d,32u>,config23>| return value| +|p_read | in| 16| ap_none| p_read| scalar| +|p_read1 | in| 16| ap_none| p_read1| scalar| +|p_read2 | in| 16| ap_none| p_read2| scalar| +|p_read3 | in| 16| ap_none| p_read3| scalar| +|p_read4 | in| 16| ap_none| p_read4| scalar| +|p_read5 | in| 16| ap_none| p_read5| scalar| +|p_read6 | in| 16| ap_none| p_read6| scalar| +|p_read7 | in| 16| ap_none| p_read7| scalar| +|p_read8 | in| 16| ap_none| p_read8| scalar| +|p_read9 | in| 16| ap_none| p_read9| scalar| +|p_read10 | in| 16| ap_none| p_read10| scalar| +|p_read11 | in| 16| ap_none| p_read11| scalar| +|p_read12 | in| 16| ap_none| p_read12| scalar| +|p_read13 | in| 16| ap_none| p_read13| scalar| +|p_read14 | in| 16| ap_none| p_read14| scalar| +|p_read15 | in| 16| ap_none| p_read15| scalar| +|p_read16 | in| 16| ap_none| p_read16| scalar| +|p_read17 | in| 16| ap_none| p_read17| scalar| +|p_read18 | in| 16| ap_none| p_read18| scalar| +|p_read19 | in| 16| ap_none| p_read19| scalar| +|p_read20 | in| 16| ap_none| p_read20| scalar| +|p_read21 | in| 16| ap_none| p_read21| scalar| +|p_read22 | in| 16| ap_none| p_read22| scalar| +|p_read23 | in| 16| ap_none| p_read23| scalar| +|p_read24 | in| 16| ap_none| p_read24| scalar| +|p_read25 | in| 16| ap_none| p_read25| scalar| +|p_read26 | in| 16| ap_none| p_read26| scalar| +|p_read27 | in| 16| ap_none| p_read27| scalar| +|p_read28 | in| 16| ap_none| p_read28| scalar| +|p_read29 | in| 16| ap_none| p_read29| scalar| +|p_read30 | in| 16| ap_none| p_read30| scalar| +|p_read31 | in| 16| ap_none| p_read31| scalar| +|p_read32 | in| 16| ap_none| p_read32| scalar| +|p_read33 | in| 16| ap_none| p_read33| scalar| +|p_read34 | in| 16| ap_none| p_read34| scalar| +|p_read35 | in| 16| ap_none| p_read35| scalar| +|p_read36 | in| 16| ap_none| p_read36| scalar| +|p_read37 | in| 16| ap_none| p_read37| scalar| +|p_read38 | in| 16| ap_none| p_read38| scalar| +|p_read39 | in| 16| ap_none| p_read39| scalar| +|p_read40 | in| 16| ap_none| p_read40| scalar| +|p_read41 | in| 16| ap_none| p_read41| scalar| +|p_read42 | in| 16| ap_none| p_read42| scalar| +|p_read43 | in| 16| ap_none| p_read43| scalar| +|p_read44 | in| 16| ap_none| p_read44| scalar| +|p_read45 | in| 16| ap_none| p_read45| scalar| +|p_read46 | in| 16| ap_none| p_read46| scalar| +|p_read47 | in| 16| ap_none| p_read47| scalar| +|p_read48 | in| 16| ap_none| p_read48| scalar| +|p_read49 | in| 16| ap_none| p_read49| scalar| +|p_read50 | in| 16| ap_none| p_read50| scalar| +|p_read51 | in| 16| ap_none| p_read51| scalar| +|p_read52 | in| 16| ap_none| p_read52| scalar| +|p_read53 | in| 16| ap_none| p_read53| scalar| +|p_read54 | in| 16| ap_none| p_read54| scalar| +|p_read55 | in| 16| ap_none| p_read55| scalar| +|p_read56 | in| 16| ap_none| p_read56| scalar| +|p_read57 | in| 16| ap_none| p_read57| scalar| +|p_read58 | in| 16| ap_none| p_read58| scalar| +|p_read59 | in| 16| ap_none| p_read59| scalar| +|p_read60 | in| 16| ap_none| p_read60| scalar| +|p_read61 | in| 16| ap_none| p_read61| scalar| +|p_read62 | in| 16| ap_none| p_read62| scalar| +|p_read63 | in| 16| ap_none| p_read63| scalar| +|p_read64 | in| 16| ap_none| p_read64| scalar| +|p_read65 | in| 16| ap_none| p_read65| scalar| +|p_read66 | in| 16| ap_none| p_read66| scalar| +|p_read67 | in| 16| ap_none| p_read67| scalar| +|p_read68 | in| 16| ap_none| p_read68| scalar| +|p_read69 | in| 16| ap_none| p_read69| scalar| +|p_read70 | in| 16| ap_none| p_read70| scalar| +|p_read71 | in| 16| ap_none| p_read71| scalar| +|p_read72 | in| 16| ap_none| p_read72| scalar| +|p_read73 | in| 16| ap_none| p_read73| scalar| +|p_read74 | in| 16| ap_none| p_read74| scalar| +|p_read75 | in| 16| ap_none| p_read75| scalar| +|p_read76 | in| 16| ap_none| p_read76| scalar| +|p_read77 | in| 16| ap_none| p_read77| scalar| +|p_read78 | in| 16| ap_none| p_read78| scalar| +|p_read79 | in| 16| ap_none| p_read79| scalar| +|p_read80 | in| 16| ap_none| p_read80| scalar| +|p_read81 | in| 16| ap_none| p_read81| scalar| +|p_read82 | in| 16| ap_none| p_read82| scalar| +|p_read83 | in| 16| ap_none| p_read83| scalar| +|p_read84 | in| 16| ap_none| p_read84| scalar| +|p_read85 | in| 16| ap_none| p_read85| scalar| +|p_read86 | in| 16| ap_none| p_read86| scalar| +|p_read87 | in| 16| ap_none| p_read87| scalar| +|p_read88 | in| 16| ap_none| p_read88| scalar| +|p_read89 | in| 16| ap_none| p_read89| scalar| +|p_read90 | in| 16| ap_none| p_read90| scalar| +|p_read91 | in| 16| ap_none| p_read91| scalar| +|p_read92 | in| 16| ap_none| p_read92| scalar| +|p_read93 | in| 16| ap_none| p_read93| scalar| +|p_read94 | in| 16| ap_none| p_read94| scalar| +|p_read95 | in| 16| ap_none| p_read95| scalar| +|layer23_out_din | out| 1376| ap_fifo| layer23_out| pointer| +|layer23_out_num_data_valid | in| 9| ap_fifo| layer23_out| pointer| +|layer23_out_fifo_cap | in| 9| ap_fifo| layer23_out| pointer| +|layer23_out_full_n | in| 1| ap_fifo| layer23_out| pointer| +|layer23_out_write | out| 1| ap_fifo| layer23_out| pointer| ++----------------------------+-----+------+------------+---------------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_csynth.xml b/myproject_prj/solution1/syn/report/concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..f2b7ca45f5a7684f9d0098bb8cbe61297dad695b --- /dev/null +++ b/myproject_prj/solution1/syn/report/concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_csynth.xml @@ -0,0 +1,312 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s +4.00 +1.35 +vivado + + + +loop auto-rewind stp(delay=0 clock cycles(s)) + +ns +2.460 + + +clock cycles +4098 +4098 +4098 +16.392 us +16.392 us +16.392 us +4097 +4097 + + + +2.65 +4096 +4096 +16384 +1 +2 + + + + + +- +- +firmware/nnet_utils/nnet_merge_stream.h:234 + + +ConcatLoopHeight_ConcatLoopWidth +- +- +firmware/nnet_utils/nnet_merge_stream.h:234 + + + + + + + +16 +110 +0 +0 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +concatenate3d_2<array,array,array<ap_fixed<16,6,5,3,0>,24u>,config34> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +concatenate3d_2<array,array,array<ap_fixed<16,6,5,3,0>,24u>,config34> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +concatenate3d_2<array,array,array<ap_fixed<16,6,5,3,0>,24u>,config34> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_done +concatenate3d_2<array,array,array<ap_fixed<16,6,5,3,0>,24u>,config34> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_idle +concatenate3d_2<array,array,array<ap_fixed<16,6,5,3,0>,24u>,config34> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +concatenate3d_2<array,array,array<ap_fixed<16,6,5,3,0>,24u>,config34> +return value + +ap_ctrl_hs + +out +1 +control + + +layer33_out_dout +layer33_out +pointer + +ap_fifo + +in +256 +control + + +layer33_out_num_data_valid +layer33_out +pointer + +ap_fifo + +in +13 +control + + +layer33_out_fifo_cap +layer33_out +pointer + +ap_fifo + +in +13 +unknown + + +layer33_out_empty_n +layer33_out +pointer + +ap_fifo + +in +1 +control + + +layer33_out_read +layer33_out +pointer + +ap_fifo + +out +1 +control + + +layer41_cpy2_dout +layer41_cpy2 +pointer + +ap_fifo + +in +128 +control + + +layer41_cpy2_num_data_valid +layer41_cpy2 +pointer + +ap_fifo + +in +13 +control + + +layer41_cpy2_fifo_cap +layer41_cpy2 +pointer + +ap_fifo + +in +13 +unknown + + +layer41_cpy2_empty_n +layer41_cpy2 +pointer + +ap_fifo + +in +1 +control + + +layer41_cpy2_read +layer41_cpy2 +pointer + +ap_fifo + +out +1 +control + + +layer34_out_din +layer34_out +pointer + +ap_fifo + +out +384 +control + + +layer34_out_num_data_valid +layer34_out +pointer + +ap_fifo + +in +13 +control + + +layer34_out_fifo_cap +layer34_out +pointer + +ap_fifo + +in +13 +unknown + + +layer34_out_full_n +layer34_out +pointer + +ap_fifo + +in +1 +control + + +layer34_out_write +layer34_out +pointer + +ap_fifo + +out +1 +control + + + + diff --git a/myproject_prj/solution1/syn/report/concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_csynth.rpt b/myproject_prj/solution1/syn/report/concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..7d9508ceacf12239d939bb3fa33854d6bfd43584 --- /dev/null +++ b/myproject_prj/solution1/syn/report/concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_csynth.rpt @@ -0,0 +1,164 @@ + + +================================================================ +== Vitis HLS Report for 'concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s' +================================================================ +* Date: Sun Apr 5 21:50:16 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 2.460 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+-----------+-----------+------+------+---------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline| + | min | max | min | max | min | max | Type | + +---------+---------+-----------+-----------+------+------+---------+ + | 4099| 4099| 16.396 us| 16.396 us| 4099| 4099| no| + +---------+---------+-----------+-----------+------+------+---------+ + + + Detail: + * Instance: + +--------------------------------------------------------------------------------+----------------------------------------------------------------------+---------+---------+-----------+-----------+------+------+-----------------------------------------------+ + | | | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | Instance | Module | min | max | min | max | min | max | Type | + +--------------------------------------------------------------------------------+----------------------------------------------------------------------+---------+---------+-----------+-----------+------+------+-----------------------------------------------+ + |grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18 |concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s | 4098| 4098| 16.392 us| 16.392 us| 4097| 4097| loop auto-rewind stp(delay=0 clock cycles(s))| + +--------------------------------------------------------------------------------+----------------------------------------------------------------------+---------+---------+-----------+-----------+------+------+-----------------------------------------------+ + + * Loop: + N/A + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 2| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| 16| 110| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| 0| 59| -| +|Register | -| -| 5| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 0| 0| 21| 171| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + +--------------------------------------------------------------------------------+----------------------------------------------------------------------+---------+----+----+-----+-----+ + | Instance | Module | BRAM_18K| DSP| FF | LUT | URAM| + +--------------------------------------------------------------------------------+----------------------------------------------------------------------+---------+----+----+-----+-----+ + |grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18 |concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s | 0| 0| 16| 110| 0| + +--------------------------------------------------------------------------------+----------------------------------------------------------------------+---------+----+----+-----+-----+ + |Total | | 0| 0| 16| 110| 0| + +--------------------------------------------------------------------------------+----------------------------------------------------------------------+---------+----+----+-----+-----+ + + * DSP: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +-----------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +-----------------+----------+----+---+----+------------+------------+ + |ap_block_state1 | or| 0| 0| 2| 1| 1| + +-----------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0| 2| 1| 1| + +-----------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +-------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +-------------------+----+-----------+-----+-----------+ + |ap_NS_fsm | 14| 3| 1| 3| + |ap_done | 9| 2| 1| 2| + |layer33_out_read | 9| 2| 1| 2| + |layer34_out_write | 9| 2| 1| 2| + |layer41_cpy2_read | 9| 2| 1| 2| + |real_start | 9| 2| 1| 2| + +-------------------+----+-----------+-----+-----------+ + |Total | 59| 13| 6| 13| + +-------------------+----+-----------+-----+-----------+ + + * Register: + +---------------------------------------------------------------------------------------------+---+----+-----+-----------+ + | Name | FF| LUT| Bits| Const Bits| + +---------------------------------------------------------------------------------------------+---+----+-----+-----------+ + |ap_CS_fsm | 2| 0| 2| 0| + |ap_done_reg | 1| 0| 1| 0| + |grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_start_reg | 1| 0| 1| 0| + |start_once_reg | 1| 0| 1| 0| + +---------------------------------------------------------------------------------------------+---+----+-----+-----------+ + |Total | 5| 0| 5| 0| + +---------------------------------------------------------------------------------------------+---+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++-----------------------------+-----+-----+------------+---------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++-----------------------------+-----+-----+------------+---------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| concatenate3d,24u>,config34>| return value| +|ap_rst | in| 1| ap_ctrl_hs| concatenate3d,24u>,config34>| return value| +|ap_start | in| 1| ap_ctrl_hs| concatenate3d,24u>,config34>| return value| +|start_full_n | in| 1| ap_ctrl_hs| concatenate3d,24u>,config34>| return value| +|ap_done | out| 1| ap_ctrl_hs| concatenate3d,24u>,config34>| return value| +|ap_continue | in| 1| ap_ctrl_hs| concatenate3d,24u>,config34>| return value| +|ap_idle | out| 1| ap_ctrl_hs| concatenate3d,24u>,config34>| return value| +|ap_ready | out| 1| ap_ctrl_hs| concatenate3d,24u>,config34>| return value| +|start_out | out| 1| ap_ctrl_hs| concatenate3d,24u>,config34>| return value| +|start_write | out| 1| ap_ctrl_hs| concatenate3d,24u>,config34>| return value| +|layer33_out_dout | in| 256| ap_fifo| layer33_out| pointer| +|layer33_out_num_data_valid | in| 13| ap_fifo| layer33_out| pointer| +|layer33_out_fifo_cap | in| 13| ap_fifo| layer33_out| pointer| +|layer33_out_empty_n | in| 1| ap_fifo| layer33_out| pointer| +|layer33_out_read | out| 1| ap_fifo| layer33_out| pointer| +|layer41_cpy2_dout | in| 128| ap_fifo| layer41_cpy2| pointer| +|layer41_cpy2_num_data_valid | in| 13| ap_fifo| layer41_cpy2| pointer| +|layer41_cpy2_fifo_cap | in| 13| ap_fifo| layer41_cpy2| pointer| +|layer41_cpy2_empty_n | in| 1| ap_fifo| layer41_cpy2| pointer| +|layer41_cpy2_read | out| 1| ap_fifo| layer41_cpy2| pointer| +|layer34_out_din | out| 384| ap_fifo| layer34_out| pointer| +|layer34_out_num_data_valid | in| 13| ap_fifo| layer34_out| pointer| +|layer34_out_fifo_cap | in| 13| ap_fifo| layer34_out| pointer| +|layer34_out_full_n | in| 1| ap_fifo| layer34_out| pointer| +|layer34_out_write | out| 1| ap_fifo| layer34_out| pointer| ++-----------------------------+-----+-----+------------+---------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_csynth.xml b/myproject_prj/solution1/syn/report/concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..48aa9f8f89b48ae9889f9801811178cb8311c499 --- /dev/null +++ b/myproject_prj/solution1/syn/report/concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_csynth.xml @@ -0,0 +1,336 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s +4.00 +1.35 +vivado + + + +no + +ns +2.561 + + +clock cycles +1027 +1027 +1027 +4.108 us +4.108 us +4.108 us +1027 +1027 + + +- +- +firmware/nnet_utils/nnet_merge_stream.h:264 + + + + + +19 +167 +0 +0 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +concatenate3d<array,array,array<ap_fixed<16,6,5,3,0>,48u>,config28> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +concatenate3d<array,array,array<ap_fixed<16,6,5,3,0>,48u>,config28> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +concatenate3d<array,array,array<ap_fixed<16,6,5,3,0>,48u>,config28> +return value + +ap_ctrl_hs + +in +1 +control + + +start_full_n +concatenate3d<array,array,array<ap_fixed<16,6,5,3,0>,48u>,config28> +return value + +ap_ctrl_hs + +in +1 +unknown + + +ap_done +concatenate3d<array,array,array<ap_fixed<16,6,5,3,0>,48u>,config28> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_continue +concatenate3d<array,array,array<ap_fixed<16,6,5,3,0>,48u>,config28> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_idle +concatenate3d<array,array,array<ap_fixed<16,6,5,3,0>,48u>,config28> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +concatenate3d<array,array,array<ap_fixed<16,6,5,3,0>,48u>,config28> +return value + +ap_ctrl_hs + +out +1 +control + + +start_out +concatenate3d<array,array,array<ap_fixed<16,6,5,3,0>,48u>,config28> +return value + +ap_ctrl_hs + +out +1 +unknown + + +start_write +concatenate3d<array,array,array<ap_fixed<16,6,5,3,0>,48u>,config28> +return value + +ap_ctrl_hs + +out +1 +unknown + + +layer27_out_dout +layer27_out +pointer + +ap_fifo + +in +512 +control + + +layer27_out_num_data_valid +layer27_out +pointer + +ap_fifo + +in +11 +control + + +layer27_out_fifo_cap +layer27_out +pointer + +ap_fifo + +in +11 +unknown + + +layer27_out_empty_n +layer27_out +pointer + +ap_fifo + +in +1 +control + + +layer27_out_read +layer27_out +pointer + +ap_fifo + +out +1 +control + + +layer42_cpy2_dout +layer42_cpy2 +pointer + +ap_fifo + +in +256 +control + + +layer42_cpy2_num_data_valid +layer42_cpy2 +pointer + +ap_fifo + +in +11 +control + + +layer42_cpy2_fifo_cap +layer42_cpy2 +pointer + +ap_fifo + +in +11 +unknown + + +layer42_cpy2_empty_n +layer42_cpy2 +pointer + +ap_fifo + +in +1 +control + + +layer42_cpy2_read +layer42_cpy2 +pointer + +ap_fifo + +out +1 +control + + +layer28_out_din +layer28_out +pointer + +ap_fifo + +out +768 +control + + +layer28_out_num_data_valid +layer28_out +pointer + +ap_fifo + +in +11 +control + + +layer28_out_fifo_cap +layer28_out +pointer + +ap_fifo + +in +11 +unknown + + +layer28_out_full_n +layer28_out +pointer + +ap_fifo + +in +1 +control + + +layer28_out_write +layer28_out +pointer + +ap_fifo + +out +1 +control + + + + diff --git a/myproject_prj/solution1/syn/report/conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s_csynth.rpt b/myproject_prj/solution1/syn/report/conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..8ffe0112eace92964d541fc9271bae4ccba621e7 --- /dev/null +++ b/myproject_prj/solution1/syn/report/conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s_csynth.rpt @@ -0,0 +1,184 @@ + + +================================================================ +== Vitis HLS Report for 'conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s' +================================================================ +* Date: Sun Apr 5 21:46:49 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 2.533 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+-----------+----------+------+--------+---------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline| + | min | max | min | max | min | max | Type | + +---------+---------+-----------+----------+------+--------+---------+ + | 4625| 174557| 18.500 us| 0.698 ms| 4625| 174557| no| + +---------+---------+-----------+----------+------+--------+---------+ + + + Detail: + * Instance: + +------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+---------+----------+----------+-----+-----+---------+ + | | | Latency (cycles) | Latency (absolute) | Interval | Pipeline| + | Instance | Module | min | max | min | max | min | max | Type | + +------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+---------+----------+----------+-----+-----+---------+ + |grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s_fu_468 |compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s | 2| 149| 8.000 ns| 0.596 us| 2| 149| no| + +------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+---------+----------+----------+-----+-----+---------+ + + * Loop: + +----------------------------------+---------+---------+----------+-----------+-----------+------+----------+ + | | Latency (cycles) | Iteration| Initiation Interval | Trip | | + | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| + +----------------------------------+---------+---------+----------+-----------+-----------+------+----------+ + |- ReadInputHeight_ReadInputWidth | 4624| 174556| 4 ~ 151| -| -| 1156| no| + +----------------------------------+---------+---------+----------+-----------+-----------+------+----------+ + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 40| -| +|FIFO | -| -| -| -| -| +|Instance | 8| 16| 11321| 7635| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| 0| 65| -| +|Register | -| -| 273| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 8| 16| 11594| 7740| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | ~0| ~0| 1| 1| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | ~0| ~0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + +------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+----+-------+------+-----+ + | Instance | Module | BRAM_18K| DSP| FF | LUT | URAM| + +------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+----+-------+------+-----+ + |grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s_fu_468 |compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s | 8| 16| 11321| 7635| 0| + +------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+----+-------+------+-----+ + |Total | | 8| 16| 11321| 7635| 0| + +------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+----+-------+------+-----+ + + * DSP: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +---------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +---------------------+----------+----+---+----+------------+------------+ + |add_ln52_fu_866_p2 | +| 0| 0| 18| 11| 1| + |ap_block_state2 | and| 0| 0| 2| 1| 1| + |icmp_ln52_fu_860_p2 | icmp| 0| 0| 18| 11| 11| + |ap_block_state1 | or| 0| 0| 2| 1| 1| + +---------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0| 40| 24| 14| + +---------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +-----------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +-----------------------+----+-----------+-----+-----------+ + |ap_NS_fsm | 20| 4| 1| 4| + |ap_done | 9| 2| 1| 2| + |indvar_flatten_fu_458 | 9| 2| 11| 22| + |layer47_out_blk_n | 9| 2| 1| 2| + |layer9_out_write | 9| 2| 1| 2| + |real_start | 9| 2| 1| 2| + +-----------------------+----+-----------+-----+-----------+ + |Total | 65| 14| 16| 34| + +-----------------------+----+-----------+-----+-----------+ + + * Register: + +-------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + | Name | FF | LUT| Bits| Const Bits| + +-------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + |ap_CS_fsm | 3| 0| 3| 0| + |ap_done_reg | 1| 0| 1| 0| + |grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s_fu_468_ap_start_reg | 1| 0| 1| 0| + |indvar_flatten_fu_458 | 11| 0| 11| 0| + |start_once_reg | 1| 0| 1| 0| + |trunc_ln58_32_reg_1067 | 16| 0| 16| 0| + |trunc_ln58_33_reg_1072 | 16| 0| 16| 0| + |trunc_ln58_34_reg_1077 | 16| 0| 16| 0| + |trunc_ln58_35_reg_1082 | 16| 0| 16| 0| + |trunc_ln58_36_reg_1087 | 16| 0| 16| 0| + |trunc_ln58_37_reg_1092 | 16| 0| 16| 0| + |trunc_ln58_38_reg_1097 | 16| 0| 16| 0| + |trunc_ln58_39_reg_1102 | 16| 0| 16| 0| + |trunc_ln58_40_reg_1107 | 16| 0| 16| 0| + |trunc_ln58_41_reg_1112 | 16| 0| 16| 0| + |trunc_ln58_42_reg_1117 | 16| 0| 16| 0| + |trunc_ln58_43_reg_1122 | 16| 0| 16| 0| + |trunc_ln58_44_reg_1127 | 16| 0| 16| 0| + |trunc_ln58_45_reg_1132 | 16| 0| 16| 0| + |trunc_ln58_reg_1057 | 16| 0| 16| 0| + |trunc_ln58_s_reg_1062 | 16| 0| 16| 0| + +-------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + |Total | 273| 0| 273| 0| + +-------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------+-----+-----+------------+--------------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++----------------------------+-----+-----+------------+--------------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| conv_2d_cl,array,16u>,config9>| return value| +|ap_rst | in| 1| ap_ctrl_hs| conv_2d_cl,array,16u>,config9>| return value| +|ap_start | in| 1| ap_ctrl_hs| conv_2d_cl,array,16u>,config9>| return value| +|start_full_n | in| 1| ap_ctrl_hs| conv_2d_cl,array,16u>,config9>| return value| +|ap_done | out| 1| ap_ctrl_hs| conv_2d_cl,array,16u>,config9>| return value| +|ap_continue | in| 1| ap_ctrl_hs| conv_2d_cl,array,16u>,config9>| return value| +|ap_idle | out| 1| ap_ctrl_hs| conv_2d_cl,array,16u>,config9>| return value| +|ap_ready | out| 1| ap_ctrl_hs| conv_2d_cl,array,16u>,config9>| return value| +|start_out | out| 1| ap_ctrl_hs| conv_2d_cl,array,16u>,config9>| return value| +|start_write | out| 1| ap_ctrl_hs| conv_2d_cl,array,16u>,config9>| return value| +|layer47_out_dout | in| 256| ap_fifo| layer47_out| pointer| +|layer47_out_num_data_valid | in| 12| ap_fifo| layer47_out| pointer| +|layer47_out_fifo_cap | in| 12| ap_fifo| layer47_out| pointer| +|layer47_out_empty_n | in| 1| ap_fifo| layer47_out| pointer| +|layer47_out_read | out| 1| ap_fifo| layer47_out| pointer| +|layer9_out_din | out| 656| ap_fifo| layer9_out| pointer| +|layer9_out_num_data_valid | in| 11| ap_fifo| layer9_out| pointer| +|layer9_out_fifo_cap | in| 11| ap_fifo| layer9_out| pointer| +|layer9_out_full_n | in| 1| ap_fifo| layer9_out| pointer| +|layer9_out_write | out| 1| ap_fifo| layer9_out| pointer| ++----------------------------+-----+-----+------------+--------------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s_csynth.xml b/myproject_prj/solution1/syn/report/conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..7704c4e1b383b4901c2b1a2d9d34b71b4a750dd0 --- /dev/null +++ b/myproject_prj/solution1/syn/report/conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s_csynth.xml @@ -0,0 +1,315 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s +4.00 +1.35 +vivado + + + +no + +ns +4.411 + + +clock cycles +17425 +126325 +344125 +76.860 us +0.557 ms +1.518 ms +17425 +344125 + + + +2.65 +4356 + + +17424 +344124 + + + + +76855 +1517894 + + + + +4 +79 + + + + + + + +- +- +firmware/nnet_utils/nnet_conv2d_stream.h:52~firmware/nnet_utils/nnet_conv2d_stream.h:78 + + +ReadInputHeight_ReadInputWidth +- +- +firmware/nnet_utils/nnet_conv2d_stream.h:52~firmware/nnet_utils/nnet_conv2d_stream.h:78 + + + + + + + +1 +1 +1519 +2052 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +conv_2d_cl<array<ap_fixed,1u>,array<ap_fixed<37,17,5,3,0>,8u>,config2> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +conv_2d_cl<array<ap_fixed,1u>,array<ap_fixed<37,17,5,3,0>,8u>,config2> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +conv_2d_cl<array<ap_fixed,1u>,array<ap_fixed<37,17,5,3,0>,8u>,config2> +return value + +ap_ctrl_hs + +in +1 +control + + +start_full_n +conv_2d_cl<array<ap_fixed,1u>,array<ap_fixed<37,17,5,3,0>,8u>,config2> +return value + +ap_ctrl_hs + +in +1 +unknown + + +ap_done +conv_2d_cl<array<ap_fixed,1u>,array<ap_fixed<37,17,5,3,0>,8u>,config2> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_continue +conv_2d_cl<array<ap_fixed,1u>,array<ap_fixed<37,17,5,3,0>,8u>,config2> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_idle +conv_2d_cl<array<ap_fixed,1u>,array<ap_fixed<37,17,5,3,0>,8u>,config2> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +conv_2d_cl<array<ap_fixed,1u>,array<ap_fixed<37,17,5,3,0>,8u>,config2> +return value + +ap_ctrl_hs + +out +1 +control + + +start_out +conv_2d_cl<array<ap_fixed,1u>,array<ap_fixed<37,17,5,3,0>,8u>,config2> +return value + +ap_ctrl_hs + +out +1 +unknown + + +start_write +conv_2d_cl<array<ap_fixed,1u>,array<ap_fixed<37,17,5,3,0>,8u>,config2> +return value + +ap_ctrl_hs + +out +1 +unknown + + +layer44_out_dout +layer44_out +pointer + +ap_fifo + +in +16 +control + + +layer44_out_num_data_valid +layer44_out +pointer + +ap_fifo + +in +14 +control + + +layer44_out_fifo_cap +layer44_out +pointer + +ap_fifo + +in +14 +unknown + + +layer44_out_empty_n +layer44_out +pointer + +ap_fifo + +in +1 +control + + +layer44_out_read +layer44_out +pointer + +ap_fifo + +out +1 +control + + +layer2_out_din +layer2_out +pointer + +ap_fifo + +out +296 +control + + +layer2_out_num_data_valid +layer2_out +pointer + +ap_fifo + +in +13 +control + + +layer2_out_fifo_cap +layer2_out +pointer + +ap_fifo + +in +13 +unknown + + +layer2_out_full_n +layer2_out +pointer + +ap_fifo + +in +1 +control + + +layer2_out_write +layer2_out +pointer + +ap_fifo + +out +1 +control + + + + diff --git a/myproject_prj/solution1/syn/report/conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_csynth.xml b/myproject_prj/solution1/syn/report/conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..ef49e1a1952a3395db1932c468d4fe8bd7beea83 --- /dev/null +++ b/myproject_prj/solution1/syn/report/conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_csynth.xml @@ -0,0 +1,315 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s +4.00 +1.35 +vivado + + + +no + +ns +4.315 + + +clock cycles +4625 +227733 +673949 +19.955 us +0.983 ms +2.908 ms +4625 +673949 + + + +2.65 +1156 + + +4624 +673948 + + + + +19950 +2907825 + + + + +4 +583 + + + + + + + +- +- +firmware/nnet_utils/nnet_conv2d_stream.h:52~firmware/nnet_utils/nnet_conv2d_stream.h:78 + + +ReadInputHeight_ReadInputWidth +- +- +firmware/nnet_utils/nnet_conv2d_stream.h:52~firmware/nnet_utils/nnet_conv2d_stream.h:78 + + + + + + + +4 +4 +10881 +9083 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +conv_2d_cl<array,array<ap_fixed<41,21,5,3,0>,16u>,config31> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +conv_2d_cl<array,array<ap_fixed<41,21,5,3,0>,16u>,config31> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +conv_2d_cl<array,array<ap_fixed<41,21,5,3,0>,16u>,config31> +return value + +ap_ctrl_hs + +in +1 +control + + +start_full_n +conv_2d_cl<array,array<ap_fixed<41,21,5,3,0>,16u>,config31> +return value + +ap_ctrl_hs + +in +1 +unknown + + +ap_done +conv_2d_cl<array,array<ap_fixed<41,21,5,3,0>,16u>,config31> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_continue +conv_2d_cl<array,array<ap_fixed<41,21,5,3,0>,16u>,config31> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_idle +conv_2d_cl<array,array<ap_fixed<41,21,5,3,0>,16u>,config31> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +conv_2d_cl<array,array<ap_fixed<41,21,5,3,0>,16u>,config31> +return value + +ap_ctrl_hs + +out +1 +control + + +start_out +conv_2d_cl<array,array<ap_fixed<41,21,5,3,0>,16u>,config31> +return value + +ap_ctrl_hs + +out +1 +unknown + + +start_write +conv_2d_cl<array,array<ap_fixed<41,21,5,3,0>,16u>,config31> +return value + +ap_ctrl_hs + +out +1 +unknown + + +layer55_out_dout +layer55_out +pointer + +ap_fifo + +in +256 +control + + +layer55_out_num_data_valid +layer55_out +pointer + +ap_fifo + +in +12 +control + + +layer55_out_fifo_cap +layer55_out +pointer + +ap_fifo + +in +12 +unknown + + +layer55_out_empty_n +layer55_out +pointer + +ap_fifo + +in +1 +control + + +layer55_out_read +layer55_out +pointer + +ap_fifo + +out +1 +control + + +layer31_out_din +layer31_out +pointer + +ap_fifo + +out +656 +control + + +layer31_out_num_data_valid +layer31_out +pointer + +ap_fifo + +in +11 +control + + +layer31_out_fifo_cap +layer31_out +pointer + +ap_fifo + +in +11 +unknown + + +layer31_out_full_n +layer31_out +pointer + +ap_fifo + +in +1 +control + + +layer31_out_write +layer31_out +pointer + +ap_fifo + +out +1 +control + + + + diff --git a/myproject_prj/solution1/syn/report/conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s_csynth.rpt b/myproject_prj/solution1/syn/report/conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..9b55179e399cbc60a076cdf31ae32654bf7172ae --- /dev/null +++ b/myproject_prj/solution1/syn/report/conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s_csynth.rpt @@ -0,0 +1,200 @@ + + +================================================================ +== Vitis HLS Report for 'conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s' +================================================================ +* Date: Sun Apr 5 21:49:26 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 4.449 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+----------+----------+------+--------+---------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline| + | min | max | min | max | min | max | Type | + +---------+---------+----------+----------+------+--------+---------+ + | 1297| 375517| 5.771 us| 1.671 ms| 1297| 375517| no| + +---------+---------+----------+----------+------+--------+---------+ + + + Detail: + * Instance: + +-------------------------------------------------------------------------------------+--------------------------------------------------------------------------+---------+---------+----------+----------+-----+------+---------+ + | | | Latency (cycles) | Latency (absolute) | Interval | Pipeline| + | Instance | Module | min | max | min | max | min | max | Type | + +-------------------------------------------------------------------------------------+--------------------------------------------------------------------------+---------+---------+----------+----------+-----+------+---------+ + |grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s_fu_886 |compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s | 2| 1157| 8.899 ns| 5.148 us| 2| 1157| no| + +-------------------------------------------------------------------------------------+--------------------------------------------------------------------------+---------+---------+----------+----------+-----+------+---------+ + + * Loop: + +----------------------------------+---------+---------+----------+-----------+-----------+------+----------+ + | | Latency (cycles) | Iteration| Initiation Interval | Trip | | + | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| + +----------------------------------+---------+---------+----------+-----------+-----------+------+----------+ + |- ReadInputHeight_ReadInputWidth | 1296| 375516| 4 ~ 1159| -| -| 324| no| + +----------------------------------+---------+---------+----------+-----------+-----------+------+----------+ + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 36| -| +|FIFO | -| -| -| -| -| +|Instance | 16| 8| 21010| 17022| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| 0| 65| -| +|Register | -| -| 527| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 16| 8| 21537| 17123| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 1| ~0| 2| 3| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | ~0| ~0| ~0| 1| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + +-------------------------------------------------------------------------------------+--------------------------------------------------------------------------+---------+----+-------+-------+-----+ + | Instance | Module | BRAM_18K| DSP| FF | LUT | URAM| + +-------------------------------------------------------------------------------------+--------------------------------------------------------------------------+---------+----+-------+-------+-----+ + |grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s_fu_886 |compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s | 16| 8| 21010| 17022| 0| + +-------------------------------------------------------------------------------------+--------------------------------------------------------------------------+---------+----+-------+-------+-----+ + |Total | | 16| 8| 21010| 17022| 0| + +-------------------------------------------------------------------------------------+--------------------------------------------------------------------------+---------+----+-------+-------+-----+ + + * DSP: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +----------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +----------------------+----------+----+---+----+------------+------------+ + |add_ln52_fu_1654_p2 | +| 0| 0| 16| 9| 1| + |ap_block_state2 | and| 0| 0| 2| 1| 1| + |icmp_ln52_fu_1648_p2 | icmp| 0| 0| 16| 9| 9| + |ap_block_state1 | or| 0| 0| 2| 1| 1| + +----------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0| 36| 20| 12| + +----------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +-----------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +-----------------------+----+-----------+-----+-----------+ + |ap_NS_fsm | 20| 4| 1| 4| + |ap_done | 9| 2| 1| 2| + |indvar_flatten_fu_876 | 9| 2| 9| 18| + |layer25_out_write | 9| 2| 1| 2| + |layer53_out_blk_n | 9| 2| 1| 2| + |real_start | 9| 2| 1| 2| + +-----------------------+----+-----------+-----+-----------+ + |Total | 65| 14| 14| 30| + +-----------------------+----+-----------+-----+-----------+ + + * Register: + +--------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + | Name | FF | LUT| Bits| Const Bits| + +--------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + |ap_CS_fsm | 3| 0| 3| 0| + |ap_done_reg | 1| 0| 1| 0| + |grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s_fu_886_ap_start_reg | 1| 0| 1| 0| + |indvar_flatten_fu_876 | 9| 0| 9| 0| + |start_once_reg | 1| 0| 1| 0| + |trunc_ln58_138_reg_2031 | 16| 0| 16| 0| + |trunc_ln58_139_reg_2036 | 16| 0| 16| 0| + |trunc_ln58_140_reg_2041 | 16| 0| 16| 0| + |trunc_ln58_141_reg_2046 | 16| 0| 16| 0| + |trunc_ln58_142_reg_2051 | 16| 0| 16| 0| + |trunc_ln58_143_reg_2056 | 16| 0| 16| 0| + |trunc_ln58_144_reg_2061 | 16| 0| 16| 0| + |trunc_ln58_145_reg_2066 | 16| 0| 16| 0| + |trunc_ln58_146_reg_2071 | 16| 0| 16| 0| + |trunc_ln58_147_reg_2076 | 16| 0| 16| 0| + |trunc_ln58_148_reg_2081 | 16| 0| 16| 0| + |trunc_ln58_149_reg_2086 | 16| 0| 16| 0| + |trunc_ln58_150_reg_2091 | 16| 0| 16| 0| + |trunc_ln58_151_reg_2096 | 16| 0| 16| 0| + |trunc_ln58_152_reg_2101 | 16| 0| 16| 0| + |trunc_ln58_153_reg_2106 | 16| 0| 16| 0| + |trunc_ln58_154_reg_2111 | 16| 0| 16| 0| + |trunc_ln58_155_reg_2116 | 16| 0| 16| 0| + |trunc_ln58_156_reg_2121 | 16| 0| 16| 0| + |trunc_ln58_157_reg_2126 | 16| 0| 16| 0| + |trunc_ln58_158_reg_2131 | 16| 0| 16| 0| + |trunc_ln58_159_reg_2136 | 16| 0| 16| 0| + |trunc_ln58_160_reg_2141 | 16| 0| 16| 0| + |trunc_ln58_161_reg_2146 | 16| 0| 16| 0| + |trunc_ln58_162_reg_2151 | 16| 0| 16| 0| + |trunc_ln58_163_reg_2156 | 16| 0| 16| 0| + |trunc_ln58_164_reg_2161 | 16| 0| 16| 0| + |trunc_ln58_165_reg_2166 | 16| 0| 16| 0| + |trunc_ln58_166_reg_2171 | 16| 0| 16| 0| + |trunc_ln58_167_reg_2176 | 16| 0| 16| 0| + |trunc_ln58_reg_2021 | 16| 0| 16| 0| + |trunc_ln58_s_reg_2026 | 16| 0| 16| 0| + +--------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + |Total | 527| 0| 527| 0| + +--------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------+-----+------+------------+-------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits | Protocol | Source Object | C Type | ++----------------------------+-----+------+------------+-------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| conv_2d_cl,32u>,config25>| return value| +|ap_rst | in| 1| ap_ctrl_hs| conv_2d_cl,32u>,config25>| return value| +|ap_start | in| 1| ap_ctrl_hs| conv_2d_cl,32u>,config25>| return value| +|start_full_n | in| 1| ap_ctrl_hs| conv_2d_cl,32u>,config25>| return value| +|ap_done | out| 1| ap_ctrl_hs| conv_2d_cl,32u>,config25>| return value| +|ap_continue | in| 1| ap_ctrl_hs| conv_2d_cl,32u>,config25>| return value| +|ap_idle | out| 1| ap_ctrl_hs| conv_2d_cl,32u>,config25>| return value| +|ap_ready | out| 1| ap_ctrl_hs| conv_2d_cl,32u>,config25>| return value| +|start_out | out| 1| ap_ctrl_hs| conv_2d_cl,32u>,config25>| return value| +|start_write | out| 1| ap_ctrl_hs| conv_2d_cl,32u>,config25>| return value| +|layer53_out_dout | in| 512| ap_fifo| layer53_out| pointer| +|layer53_out_num_data_valid | in| 10| ap_fifo| layer53_out| pointer| +|layer53_out_fifo_cap | in| 10| ap_fifo| layer53_out| pointer| +|layer53_out_empty_n | in| 1| ap_fifo| layer53_out| pointer| +|layer53_out_read | out| 1| ap_fifo| layer53_out| pointer| +|layer25_out_din | out| 1344| ap_fifo| layer25_out| pointer| +|layer25_out_num_data_valid | in| 9| ap_fifo| layer25_out| pointer| +|layer25_out_fifo_cap | in| 9| ap_fifo| layer25_out| pointer| +|layer25_out_full_n | in| 1| ap_fifo| layer25_out| pointer| +|layer25_out_write | out| 1| ap_fifo| layer25_out| pointer| ++----------------------------+-----+------+------------+-------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s_csynth.rpt b/myproject_prj/solution1/syn/report/conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..4a7f30a0d98d64c19fbcbc850010ca07671cf597 --- /dev/null +++ b/myproject_prj/solution1/syn/report/conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s_csynth.rpt @@ -0,0 +1,264 @@ + + +================================================================ +== Vitis HLS Report for 'conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s' +================================================================ +* Date: Sun Apr 5 21:49:04 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 2.533 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+----------+----------+------+--------+---------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline| + | min | max | min | max | min | max | Type | + +---------+---------+----------+----------+------+--------+---------+ + | 1297| 282205| 5.188 us| 1.129 ms| 1297| 282205| no| + +---------+---------+----------+----------+------+--------+---------+ + + + Detail: + * Instance: + +--------------------------------------------------------------------------------------+--------------------------------------------------------------------------+---------+---------+----------+----------+-----+-----+---------+ + | | | Latency (cycles) | Latency (absolute) | Interval | Pipeline| + | Instance | Module | min | max | min | max | min | max | Type | + +--------------------------------------------------------------------------------------+--------------------------------------------------------------------------+---------+---------+----------+----------+-----+-----+---------+ + |grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s_fu_2548 |compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s | 2| 869| 8.000 ns| 3.476 us| 2| 869| no| + +--------------------------------------------------------------------------------------+--------------------------------------------------------------------------+---------+---------+----------+----------+-----+-----+---------+ + + * Loop: + +----------------------------------+---------+---------+----------+-----------+-----------+------+----------+ + | | Latency (cycles) | Iteration| Initiation Interval | Trip | | + | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| + +----------------------------------+---------+---------+----------+-----------+-----------+------+----------+ + |- ReadInputHeight_ReadInputWidth | 1296| 282204| 4 ~ 871| -| -| 324| no| + +----------------------------------+---------+---------+----------+-----------+-----------+------+----------+ + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 36| -| +|FIFO | -| -| -| -| -| +|Instance | 25| 32| 58505| 38885| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| 0| 65| -| +|Register | -| -| 1551| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 25| 32| 60056| 38986| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 1| 1| 6| 8| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | ~0| ~0| 2| 2| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + +--------------------------------------------------------------------------------------+--------------------------------------------------------------------------+---------+----+-------+-------+-----+ + | Instance | Module | BRAM_18K| DSP| FF | LUT | URAM| + +--------------------------------------------------------------------------------------+--------------------------------------------------------------------------+---------+----+-------+-------+-----+ + |grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s_fu_2548 |compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s | 25| 32| 58505| 38885| 0| + +--------------------------------------------------------------------------------------+--------------------------------------------------------------------------+---------+----+-------+-------+-----+ + |Total | | 25| 32| 58505| 38885| 0| + +--------------------------------------------------------------------------------------+--------------------------------------------------------------------------+---------+----+-------+-------+-----+ + + * DSP: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +----------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +----------------------+----------+----+---+----+------------+------------+ + |add_ln52_fu_4786_p2 | +| 0| 0| 16| 9| 1| + |ap_block_state2 | and| 0| 0| 2| 1| 1| + |icmp_ln52_fu_4780_p2 | icmp| 0| 0| 16| 9| 9| + |ap_block_state1 | or| 0| 0| 2| 1| 1| + +----------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0| 36| 20| 12| + +----------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +------------------------+----+-----------+-----+-----------+ + |ap_NS_fsm | 20| 4| 1| 4| + |ap_done | 9| 2| 1| 2| + |indvar_flatten_fu_2538 | 9| 2| 9| 18| + |layer23_out_write | 9| 2| 1| 2| + |layer52_out_blk_n | 9| 2| 1| 2| + |real_start | 9| 2| 1| 2| + +------------------------+----+-----------+-----+-----------+ + |Total | 65| 14| 14| 30| + +------------------------+----+-----------+-----+-----------+ + + * Register: + +---------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + | Name | FF | LUT| Bits| Const Bits| + +---------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + |ap_CS_fsm | 3| 0| 3| 0| + |ap_done_reg | 1| 0| 1| 0| + |grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s_fu_2548_ap_start_reg | 1| 0| 1| 0| + |indvar_flatten_fu_2538 | 9| 0| 9| 0| + |start_once_reg | 1| 0| 1| 0| + |trunc_ln58_10_reg_5907 | 16| 0| 16| 0| + |trunc_ln58_11_reg_5912 | 16| 0| 16| 0| + |trunc_ln58_12_reg_5917 | 16| 0| 16| 0| + |trunc_ln58_13_reg_5922 | 16| 0| 16| 0| + |trunc_ln58_14_reg_5927 | 16| 0| 16| 0| + |trunc_ln58_15_reg_5932 | 16| 0| 16| 0| + |trunc_ln58_16_reg_5937 | 16| 0| 16| 0| + |trunc_ln58_17_reg_5942 | 16| 0| 16| 0| + |trunc_ln58_18_reg_5947 | 16| 0| 16| 0| + |trunc_ln58_19_reg_5952 | 16| 0| 16| 0| + |trunc_ln58_1_reg_5862 | 16| 0| 16| 0| + |trunc_ln58_20_reg_5957 | 16| 0| 16| 0| + |trunc_ln58_21_reg_5962 | 16| 0| 16| 0| + |trunc_ln58_22_reg_5967 | 16| 0| 16| 0| + |trunc_ln58_23_reg_5972 | 16| 0| 16| 0| + |trunc_ln58_24_reg_5977 | 16| 0| 16| 0| + |trunc_ln58_25_reg_5982 | 16| 0| 16| 0| + |trunc_ln58_26_reg_5987 | 16| 0| 16| 0| + |trunc_ln58_27_reg_5992 | 16| 0| 16| 0| + |trunc_ln58_28_reg_5997 | 16| 0| 16| 0| + |trunc_ln58_29_reg_6002 | 16| 0| 16| 0| + |trunc_ln58_2_reg_5867 | 16| 0| 16| 0| + |trunc_ln58_30_reg_6007 | 16| 0| 16| 0| + |trunc_ln58_31_reg_6012 | 16| 0| 16| 0| + |trunc_ln58_32_reg_6017 | 16| 0| 16| 0| + |trunc_ln58_33_reg_6022 | 16| 0| 16| 0| + |trunc_ln58_34_reg_6027 | 16| 0| 16| 0| + |trunc_ln58_35_reg_6032 | 16| 0| 16| 0| + |trunc_ln58_36_reg_6037 | 16| 0| 16| 0| + |trunc_ln58_37_reg_6042 | 16| 0| 16| 0| + |trunc_ln58_38_reg_6047 | 16| 0| 16| 0| + |trunc_ln58_39_reg_6052 | 16| 0| 16| 0| + |trunc_ln58_3_reg_5872 | 16| 0| 16| 0| + |trunc_ln58_40_reg_6057 | 16| 0| 16| 0| + |trunc_ln58_41_reg_6062 | 16| 0| 16| 0| + |trunc_ln58_42_reg_6067 | 16| 0| 16| 0| + |trunc_ln58_43_reg_6072 | 16| 0| 16| 0| + |trunc_ln58_44_reg_6077 | 16| 0| 16| 0| + |trunc_ln58_45_reg_6082 | 16| 0| 16| 0| + |trunc_ln58_46_reg_6087 | 16| 0| 16| 0| + |trunc_ln58_47_reg_6092 | 16| 0| 16| 0| + |trunc_ln58_48_reg_6097 | 16| 0| 16| 0| + |trunc_ln58_49_reg_6102 | 16| 0| 16| 0| + |trunc_ln58_4_reg_5877 | 16| 0| 16| 0| + |trunc_ln58_50_reg_6107 | 16| 0| 16| 0| + |trunc_ln58_51_reg_6112 | 16| 0| 16| 0| + |trunc_ln58_52_reg_6117 | 16| 0| 16| 0| + |trunc_ln58_53_reg_6122 | 16| 0| 16| 0| + |trunc_ln58_54_reg_6127 | 16| 0| 16| 0| + |trunc_ln58_55_reg_6132 | 16| 0| 16| 0| + |trunc_ln58_56_reg_6137 | 16| 0| 16| 0| + |trunc_ln58_57_reg_6142 | 16| 0| 16| 0| + |trunc_ln58_58_reg_6147 | 16| 0| 16| 0| + |trunc_ln58_59_reg_6152 | 16| 0| 16| 0| + |trunc_ln58_5_reg_5882 | 16| 0| 16| 0| + |trunc_ln58_60_reg_6157 | 16| 0| 16| 0| + |trunc_ln58_61_reg_6162 | 16| 0| 16| 0| + |trunc_ln58_62_reg_6167 | 16| 0| 16| 0| + |trunc_ln58_63_reg_6172 | 16| 0| 16| 0| + |trunc_ln58_64_reg_6177 | 16| 0| 16| 0| + |trunc_ln58_65_reg_6182 | 16| 0| 16| 0| + |trunc_ln58_66_reg_6187 | 16| 0| 16| 0| + |trunc_ln58_67_reg_6192 | 16| 0| 16| 0| + |trunc_ln58_68_reg_6197 | 16| 0| 16| 0| + |trunc_ln58_69_reg_6202 | 16| 0| 16| 0| + |trunc_ln58_6_reg_5887 | 16| 0| 16| 0| + |trunc_ln58_70_reg_6207 | 16| 0| 16| 0| + |trunc_ln58_71_reg_6212 | 16| 0| 16| 0| + |trunc_ln58_72_reg_6217 | 16| 0| 16| 0| + |trunc_ln58_73_reg_6222 | 16| 0| 16| 0| + |trunc_ln58_74_reg_6227 | 16| 0| 16| 0| + |trunc_ln58_75_reg_6232 | 16| 0| 16| 0| + |trunc_ln58_76_reg_6237 | 16| 0| 16| 0| + |trunc_ln58_77_reg_6242 | 16| 0| 16| 0| + |trunc_ln58_78_reg_6247 | 16| 0| 16| 0| + |trunc_ln58_79_reg_6252 | 16| 0| 16| 0| + |trunc_ln58_7_reg_5892 | 16| 0| 16| 0| + |trunc_ln58_80_reg_6257 | 16| 0| 16| 0| + |trunc_ln58_81_reg_6262 | 16| 0| 16| 0| + |trunc_ln58_82_reg_6267 | 16| 0| 16| 0| + |trunc_ln58_83_reg_6272 | 16| 0| 16| 0| + |trunc_ln58_84_reg_6277 | 16| 0| 16| 0| + |trunc_ln58_85_reg_6282 | 16| 0| 16| 0| + |trunc_ln58_86_reg_6287 | 16| 0| 16| 0| + |trunc_ln58_87_reg_6292 | 16| 0| 16| 0| + |trunc_ln58_88_reg_6297 | 16| 0| 16| 0| + |trunc_ln58_89_reg_6302 | 16| 0| 16| 0| + |trunc_ln58_8_reg_5897 | 16| 0| 16| 0| + |trunc_ln58_90_reg_6307 | 16| 0| 16| 0| + |trunc_ln58_91_reg_6312 | 16| 0| 16| 0| + |trunc_ln58_92_reg_6317 | 16| 0| 16| 0| + |trunc_ln58_93_reg_6322 | 16| 0| 16| 0| + |trunc_ln58_94_reg_6327 | 16| 0| 16| 0| + |trunc_ln58_95_reg_6332 | 16| 0| 16| 0| + |trunc_ln58_9_reg_5902 | 16| 0| 16| 0| + |trunc_ln58_reg_5857 | 16| 0| 16| 0| + +---------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + |Total |1551| 0| 1551| 0| + +---------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------+-----+------+------------+-------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits | Protocol | Source Object | C Type | ++----------------------------+-----+------+------------+-------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| conv_2d_cl,32u>,config23>| return value| +|ap_rst | in| 1| ap_ctrl_hs| conv_2d_cl,32u>,config23>| return value| +|ap_start | in| 1| ap_ctrl_hs| conv_2d_cl,32u>,config23>| return value| +|start_full_n | in| 1| ap_ctrl_hs| conv_2d_cl,32u>,config23>| return value| +|ap_done | out| 1| ap_ctrl_hs| conv_2d_cl,32u>,config23>| return value| +|ap_continue | in| 1| ap_ctrl_hs| conv_2d_cl,32u>,config23>| return value| +|ap_idle | out| 1| ap_ctrl_hs| conv_2d_cl,32u>,config23>| return value| +|ap_ready | out| 1| ap_ctrl_hs| conv_2d_cl,32u>,config23>| return value| +|start_out | out| 1| ap_ctrl_hs| conv_2d_cl,32u>,config23>| return value| +|start_write | out| 1| ap_ctrl_hs| conv_2d_cl,32u>,config23>| return value| +|layer52_out_dout | in| 1536| ap_fifo| layer52_out| pointer| +|layer52_out_num_data_valid | in| 10| ap_fifo| layer52_out| pointer| +|layer52_out_fifo_cap | in| 10| ap_fifo| layer52_out| pointer| +|layer52_out_empty_n | in| 1| ap_fifo| layer52_out| pointer| +|layer52_out_read | out| 1| ap_fifo| layer52_out| pointer| +|layer23_out_din | out| 1376| ap_fifo| layer23_out| pointer| +|layer23_out_num_data_valid | in| 9| ap_fifo| layer23_out| pointer| +|layer23_out_fifo_cap | in| 9| ap_fifo| layer23_out| pointer| +|layer23_out_full_n | in| 1| ap_fifo| layer23_out| pointer| +|layer23_out_write | out| 1| ap_fifo| layer23_out| pointer| ++----------------------------+-----+------+------------+-------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_csynth.xml b/myproject_prj/solution1/syn/report/conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..a3b5ee86d383a03f6cf3f791c28090ebad14d6e1 --- /dev/null +++ b/myproject_prj/solution1/syn/report/conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_csynth.xml @@ -0,0 +1,315 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s +4.00 +1.35 +vivado + + + +no + +ns +4.138 + + +clock cycles +401 +38901 +115901 +1.659 us +0.161 ms +0.480 ms +401 +115901 + + + +2.65 +100 + + +400 +115900 + + + + +1655 +479542 + + + + +4 +1159 + + + + + + + +- +- +firmware/nnet_utils/nnet_conv2d_stream.h:52~firmware/nnet_utils/nnet_conv2d_stream.h:78 + + +ReadInputHeight_ReadInputWidth +- +- +firmware/nnet_utils/nnet_conv2d_stream.h:52~firmware/nnet_utils/nnet_conv2d_stream.h:78 + + + + + + + +33 +32 +36198 +40011 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +conv_2d_cl<array,array<ap_fixed<43,23,5,3,0>,64u>,config19> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +conv_2d_cl<array,array<ap_fixed<43,23,5,3,0>,64u>,config19> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +conv_2d_cl<array,array<ap_fixed<43,23,5,3,0>,64u>,config19> +return value + +ap_ctrl_hs + +in +1 +control + + +start_full_n +conv_2d_cl<array,array<ap_fixed<43,23,5,3,0>,64u>,config19> +return value + +ap_ctrl_hs + +in +1 +unknown + + +ap_done +conv_2d_cl<array,array<ap_fixed<43,23,5,3,0>,64u>,config19> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_continue +conv_2d_cl<array,array<ap_fixed<43,23,5,3,0>,64u>,config19> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_idle +conv_2d_cl<array,array<ap_fixed<43,23,5,3,0>,64u>,config19> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +conv_2d_cl<array,array<ap_fixed<43,23,5,3,0>,64u>,config19> +return value + +ap_ctrl_hs + +out +1 +control + + +start_out +conv_2d_cl<array,array<ap_fixed<43,23,5,3,0>,64u>,config19> +return value + +ap_ctrl_hs + +out +1 +unknown + + +start_write +conv_2d_cl<array,array<ap_fixed<43,23,5,3,0>,64u>,config19> +return value + +ap_ctrl_hs + +out +1 +unknown + + +layer51_out_dout +layer51_out +pointer + +ap_fifo + +in +1024 +control + + +layer51_out_num_data_valid +layer51_out +pointer + +ap_fifo + +in +8 +control + + +layer51_out_fifo_cap +layer51_out +pointer + +ap_fifo + +in +8 +unknown + + +layer51_out_empty_n +layer51_out +pointer + +ap_fifo + +in +1 +control + + +layer51_out_read +layer51_out +pointer + +ap_fifo + +out +1 +control + + +layer19_out_din +layer19_out +pointer + +ap_fifo + +out +2752 +control + + +layer19_out_num_data_valid +layer19_out +pointer + +ap_fifo + +in +7 +control + + +layer19_out_fifo_cap +layer19_out +pointer + +ap_fifo + +in +7 +unknown + + +layer19_out_full_n +layer19_out +pointer + +ap_fifo + +in +1 +control + + +layer19_out_write +layer19_out +pointer + +ap_fifo + +out +1 +control + + + + diff --git a/myproject_prj/solution1/syn/report/csynth_design_size.xml b/myproject_prj/solution1/syn/report/csynth_design_size.xml new file mode 100644 index 0000000000000000000000000000000000000000..5ccd30b79d3dd2fe7a4c63af42aa944c0a8d6571 --- /dev/null +++ b/myproject_prj/solution1/syn/report/csynth_design_size.xml @@ -0,0 +1,608 @@ + + + + Phase, Step, Instructions, Description + , 28299, After all functions are compiled and linked into a single design + , , + , , After user unroll and inline pragmas are applied + (1) unroll, 169202 *, user unroll pragmas are applied + (2) simplification, 90029, simplification of applied user unroll pragmas + (3) inline, 78923, user inline pragmas are applied + (4) simplification, 35354, simplification of applied user inline pragmas + , , + , , After user array partition and struct aggregate/disaggregate pragmas are applied + (1) array partition, 53132, user array partition pragmas are applied + (2) simplification, 39560, simplification of applied user array partition & struct aggregate/disaggregate pragmas + (3) aggregate/disaggregate , 40455, user struct aggregate/disaggregate pragmas are applied + (4) array reshape, 85724, apply array reshape pragmas + (5) access patterns, 83664, array access pattern optmizations + , , + , , After transformations are applied to meet performance pragma targets + (1) loop simplification, 85310, loop and instruction simplification + (2) parallelization, 196081 *, loops are unrolled or pipelined to meet performance targets + (3) array partition, 193395 *, arrays are partitioned to meet performance targets + (4) simplification, 193395 *, simplification of design after performance transformations + , , + , , After hardware transfomations + (1) lowering, 154571 *, initial conversion to HW specific instructions + (2) optimizations, 146893 *, high level synthesis optimizations +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Message Setting, Value, Description + 100000, Show a warning when total design instructions exceeds this value +
+ + + diff --git a/myproject_prj/solution1/syn/report/dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_csynth.xml b/myproject_prj/solution1/syn/report/dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..d3cb4ce28f1969b2b6eda98f6e1111d8e44d7b78 --- /dev/null +++ b/myproject_prj/solution1/syn/report/dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_csynth.xml @@ -0,0 +1,334 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s +4.00 +1.35 +vivado + + + +loop rewind stp(delay=0 clock cycles(s)) + +ns +4.411 + + +clock cycles +74 +74 +75 +0.326 us +0.326 us +0.331 us +72 +72 + + + +2.65 +72 +74 +326 +1 +4 + + + + + +Timing Violation +- +firmware/nnet_utils/nnet_dense_resource.h:135 + + +ReuseLoop +- +- +firmware/nnet_utils/nnet_dense_resource.h:135 + + + + + + + +1 +1 +1077 +1250 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<37,17,5,3,0>,config2_mult> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<37,17,5,3,0>,config2_mult> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<37,17,5,3,0>,config2_mult> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_done +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<37,17,5,3,0>,config2_mult> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_idle +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<37,17,5,3,0>,config2_mult> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<37,17,5,3,0>,config2_mult> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_return_0 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<37,17,5,3,0>,config2_mult> +return value + +ap_ctrl_hs + +out +37 +data + + +ap_return_1 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<37,17,5,3,0>,config2_mult> +return value + +ap_ctrl_hs + +out +37 +data + + +ap_return_2 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<37,17,5,3,0>,config2_mult> +return value + +ap_ctrl_hs + +out +37 +data + + +ap_return_3 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<37,17,5,3,0>,config2_mult> +return value + +ap_ctrl_hs + +out +37 +data + + +ap_return_4 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<37,17,5,3,0>,config2_mult> +return value + +ap_ctrl_hs + +out +37 +data + + +ap_return_5 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<37,17,5,3,0>,config2_mult> +return value + +ap_ctrl_hs + +out +37 +data + + +ap_return_6 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<37,17,5,3,0>,config2_mult> +return value + +ap_ctrl_hs + +out +37 +data + + +ap_return_7 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<37,17,5,3,0>,config2_mult> +return value + +ap_ctrl_hs + +out +37 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168 +pointer +global +ap_none + +in +16 +data + + + + diff --git a/myproject_prj/solution1/syn/report/dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_csynth.rpt b/myproject_prj/solution1/syn/report/dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..30e8e737fbdf55ffc9f507421da1b786c0e7e87b --- /dev/null +++ b/myproject_prj/solution1/syn/report/dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_csynth.rpt @@ -0,0 +1,538 @@ + + +================================================================ +== Vitis HLS Report for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s' +================================================================ +* Date: Sun Apr 5 21:46:33 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 4.079 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+----------+----------+-----+-----+------------------------------------------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | min | max | min | max | min | max | Type | + +---------+---------+----------+----------+-----+-----+------------------------------------------+ + | 145| 146| 0.591 us| 0.596 us| 144| 144| loop rewind stp(delay=0 clock cycles(s))| + +---------+---------+----------+----------+-----+-----+------------------------------------------+ + + + Detail: + * Instance: + N/A + + * Loop: + +-------------+---------+---------+----------+-----------+-----------+------+----------+ + | | Latency (cycles) | Iteration| Initiation Interval | Trip | | + | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| + +-------------+---------+---------+----------+-----------+-----------+------+----------+ + |- ReuseLoop | 145| 145| 3| 1| 1| 144| yes| + +-------------+---------+---------+----------+-----------+-----------+------+----------+ + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| 4| -| -| -| +|Expression | -| -| 0| 1456| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| 0| 325| -| +|Memory | 2| -| 2| 9| -| +|Multiplexer | -| -| 0| 2278| -| +|Register | -| -| 1903| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 2| 4| 1905| 4068| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | ~0| ~0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | ~0| ~0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + +-----------------------------+------------------------+---------+----+---+-----+-----+ + | Instance | Module | BRAM_18K| DSP| FF| LUT | URAM| + +-----------------------------+------------------------+---------+----+---+-----+-----+ + |sparsemux_145_7_16_1_1_U128 |sparsemux_145_7_16_1_1 | 0| 0| 0| 325| 0| + +-----------------------------+------------------------+---------+----+---+-----+-----+ + |Total | | 0| 0| 0| 325| 0| + +-----------------------------+------------------------+---------+----+---+-----+-----+ + + * DSP: + +------------------------------------+-------------------------------+--------------+ + | Instance | Module | Expression | + +------------------------------------+-------------------------------+--------------+ + |mac_muladd_16s_16s_40s_41_1_1_U129 |mac_muladd_16s_16s_40s_41_1_1 | i0 + i1 * i2| + |mac_muladd_16s_16s_40s_41_1_1_U130 |mac_muladd_16s_16s_40s_41_1_1 | i0 + i1 * i2| + |mac_muladd_16s_16s_40s_41_1_1_U131 |mac_muladd_16s_16s_40s_41_1_1 | i0 + i1 * i2| + |mac_muladd_16s_9s_40s_41_1_1_U132 |mac_muladd_16s_9s_40s_41_1_1 | i0 + i1 * i2| + +------------------------------------+-------------------------------+--------------+ + + * Memory: + +------------+----------------------------------------------------------------------------------+---------+---+----+-----+------+-----+------+-------------+ + | Memory | Module | BRAM_18K| FF| LUT| URAM| Words| Bits| Banks| W*Bits*Banks| + +------------+----------------------------------------------------------------------------------+---------+---+----+-----+------+-----+------+-------------+ + |outidx_2_U |dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_ouvdy | 0| 2| 9| 0| 144| 1| 1| 144| + |w4_U |dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_w4wdI | 2| 0| 0| 0| 144| 57| 1| 8208| + +------------+----------------------------------------------------------------------------------+---------+---+----+-----+------+-----+------+-------------+ + |Total | | 2| 2| 9| 0| 288| 58| 2| 8352| + +------------+----------------------------------------------------------------------------------+---------+---+----+-----+------+-----+------+-------------+ + + * FIFO: + N/A + + * Expression: + +----------------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +----------------------------+----------+----+---+----+------------+------------+ + |in_index_2_fu_3025_p2 | +| 0| 0| 39| 32| 1| + |w_index_fu_3045_p2 | +| 0| 0| 15| 8| 1| + |ap_condition_465 | and| 0| 0| 2| 1| 1| + |icmp_ln135_fu_3051_p2 | icmp| 0| 0| 15| 8| 8| + |icmp_ln144_10_fu_3314_p2 | icmp| 0| 0| 48| 41| 1| + |icmp_ln144_8_fu_3220_p2 | icmp| 0| 0| 48| 41| 1| + |icmp_ln144_9_fu_3267_p2 | icmp| 0| 0| 48| 41| 1| + |icmp_ln144_fu_3173_p2 | icmp| 0| 0| 48| 41| 1| + |icmp_ln154_fu_3031_p2 | icmp| 0| 0| 39| 32| 7| + |acc_62_fu_3200_p3 | select| 0| 0| 40| 1| 40| + |acc_63_fu_3192_p3 | select| 0| 0| 40| 1| 40| + |acc_65_fu_3239_p3 | select| 0| 0| 40| 1| 40| + |acc_67_fu_3294_p3 | select| 0| 0| 40| 1| 40| + |acc_68_fu_3286_p3 | select| 0| 0| 40| 1| 40| + |acc_70_fu_3341_p3 | select| 0| 0| 40| 1| 40| + |acc_71_fu_3333_p3 | select| 0| 0| 40| 1| 40| + |acc_73_fu_3214_p3 | select| 0| 0| 40| 1| 40| + |acc_74_fu_3208_p3 | select| 0| 0| 40| 1| 40| + |acc_75_fu_3261_p3 | select| 0| 0| 40| 1| 40| + |acc_76_fu_3255_p3 | select| 0| 0| 40| 1| 40| + |acc_77_fu_3308_p3 | select| 0| 0| 40| 1| 40| + |acc_78_fu_3302_p3 | select| 0| 0| 40| 1| 40| + |acc_79_fu_3355_p3 | select| 0| 0| 40| 1| 40| + |acc_80_fu_3349_p3 | select| 0| 0| 40| 1| 40| + |acc_fu_3247_p3 | select| 0| 0| 40| 1| 40| + |in_index_fu_3037_p3 | select| 0| 0| 32| 1| 1| + |select_ln144_40_fu_3178_p3 | select| 0| 0| 40| 1| 1| + |select_ln144_41_fu_3185_p3 | select| 0| 0| 40| 1| 40| + |select_ln144_42_fu_3100_p3 | select| 0| 0| 40| 1| 40| + |select_ln144_45_fu_3225_p3 | select| 0| 0| 40| 1| 1| + |select_ln144_46_fu_3232_p3 | select| 0| 0| 40| 1| 40| + |select_ln144_47_fu_3129_p3 | select| 0| 0| 40| 1| 40| + |select_ln144_50_fu_3272_p3 | select| 0| 0| 40| 1| 1| + |select_ln144_51_fu_3279_p3 | select| 0| 0| 40| 1| 40| + |select_ln144_52_fu_3158_p3 | select| 0| 0| 40| 1| 40| + |select_ln144_55_fu_3319_p3 | select| 0| 0| 40| 1| 1| + |select_ln144_56_fu_3326_p3 | select| 0| 0| 40| 1| 40| + |select_ln144_fu_3071_p3 | select| 0| 0| 40| 1| 40| + |ap_enable_pp0 | xor| 0| 0| 2| 1| 2| + +----------------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0|1456| 275| 989| + +----------------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +-------------------------------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +-------------------------------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + |acc24_reg_2239 | 9| 2| 40| 80| + |acc_5622_reg_2254 | 9| 2| 40| 80| + |acc_5720_reg_2269 | 9| 2| 40| 80| + |acc_5818_reg_2284 | 9| 2| 40| 80| + |acc_5916_reg_2299 | 9| 2| 40| 80| + |acc_6014_reg_2314 | 9| 2| 40| 80| + |acc_6112_reg_2329 | 9| 2| 40| 80| + |acc_6210_reg_2344 | 9| 2| 40| 80| + |ap_done_int | 9| 2| 1| 2| + |ap_loop_exit_ready_pp0_iter2_reg | 9| 2| 1| 2| + |ap_phi_mux_acc24_phi_fu_2243_p6 | 14| 3| 40| 120| + |ap_phi_mux_acc_5622_phi_fu_2258_p6 | 14| 3| 40| 120| + |ap_phi_mux_acc_5720_phi_fu_2273_p6 | 14| 3| 40| 120| + |ap_phi_mux_acc_5818_phi_fu_2288_p6 | 14| 3| 40| 120| + |ap_phi_mux_acc_5916_phi_fu_2303_p6 | 14| 3| 40| 120| + |ap_phi_mux_acc_6014_phi_fu_2318_p6 | 14| 3| 40| 120| + |ap_phi_mux_acc_6112_phi_fu_2333_p6 | 14| 3| 40| 120| + |ap_phi_mux_acc_6210_phi_fu_2348_p6 | 14| 3| 40| 120| + |ap_phi_mux_do_init_phi_fu_401_p6 | 14| 3| 1| 3| + |ap_phi_mux_in_index26_phi_fu_1352_p6 | 14| 3| 32| 96| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14267_phi_fu_1379_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14268_phi_fu_1391_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14269_phi_fu_1403_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14270_phi_fu_1415_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14271_phi_fu_1427_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14272_phi_fu_1439_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14273_phi_fu_1451_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14274_phi_fu_1463_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14275_phi_fu_1475_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14276_phi_fu_1487_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14277_phi_fu_1499_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14278_phi_fu_1511_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14279_phi_fu_1523_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14280_phi_fu_1535_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14281_phi_fu_1547_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14282_phi_fu_1559_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14283_phi_fu_1571_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14284_phi_fu_1583_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14285_phi_fu_1595_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14286_phi_fu_1607_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14287_phi_fu_1619_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14288_phi_fu_1631_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14289_phi_fu_1643_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14290_phi_fu_1655_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14291_phi_fu_1667_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14292_phi_fu_1679_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14293_phi_fu_1691_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14294_phi_fu_1703_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14295_phi_fu_1715_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14296_phi_fu_1727_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14297_phi_fu_1739_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14298_phi_fu_1751_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14299_phi_fu_1763_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14300_phi_fu_1775_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14301_phi_fu_1787_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14302_phi_fu_1799_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14303_phi_fu_1811_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14304_phi_fu_1823_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14305_phi_fu_1835_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14306_phi_fu_1847_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14307_phi_fu_1859_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14308_phi_fu_1871_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14309_phi_fu_1883_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14310_phi_fu_1895_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14311_phi_fu_1907_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14312_phi_fu_1919_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14313_phi_fu_1931_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14314_phi_fu_1943_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14315_phi_fu_1955_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14316_phi_fu_1967_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14317_phi_fu_1979_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14318_phi_fu_1991_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14319_phi_fu_2003_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14320_phi_fu_2015_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14321_phi_fu_2027_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14322_phi_fu_2039_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14323_phi_fu_2051_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14324_phi_fu_2063_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14325_phi_fu_2075_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14326_phi_fu_2087_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14327_phi_fu_2099_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14328_phi_fu_2111_p4 | 14| 3| 16| 48| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_339_phi_fu_2123_p4 | 14| 3| 16| 48| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_340_phi_fu_2135_p4 | 14| 3| 16| 48| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_341_phi_fu_2147_p4 | 14| 3| 16| 48| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_342_phi_fu_2159_p4 | 14| 3| 16| 48| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_343_phi_fu_2171_p4 | 14| 3| 16| 48| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_344_phi_fu_2183_p4 | 14| 3| 16| 48| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_345_phi_fu_2195_p4 | 14| 3| 16| 48| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_346_phi_fu_2207_p4 | 14| 3| 16| 48| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_347_phi_fu_2219_p4 | 14| 3| 16| 48| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_348_phi_fu_2231_p4 | 14| 3| 16| 48| + |ap_phi_mux_w_index25_phi_fu_1365_p6 | 14| 3| 8| 24| + |in_index26_reg_1349 | 9| 2| 32| 64| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14267_reg_1375 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14268_reg_1387 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14269_reg_1399 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14270_reg_1411 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14271_reg_1423 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14272_reg_1435 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14273_reg_1447 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14274_reg_1459 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14275_reg_1471 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14276_reg_1483 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14277_reg_1495 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14278_reg_1507 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14279_reg_1519 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14280_reg_1531 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14281_reg_1543 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14282_reg_1555 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14283_reg_1567 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14284_reg_1579 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14285_reg_1591 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14286_reg_1603 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14287_reg_1615 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14288_reg_1627 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14289_reg_1639 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14290_reg_1651 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14291_reg_1663 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14292_reg_1675 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14293_reg_1687 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14294_reg_1699 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14295_reg_1711 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14296_reg_1723 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14297_reg_1735 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14298_reg_1747 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14299_reg_1759 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14300_reg_1771 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14301_reg_1783 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14302_reg_1795 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14303_reg_1807 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14304_reg_1819 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14305_reg_1831 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14306_reg_1843 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14307_reg_1855 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14308_reg_1867 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14309_reg_1879 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14310_reg_1891 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14311_reg_1903 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14312_reg_1915 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14313_reg_1927 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14314_reg_1939 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14315_reg_1951 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14316_reg_1963 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14317_reg_1975 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14318_reg_1987 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14319_reg_1999 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14320_reg_2011 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14321_reg_2023 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14322_reg_2035 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14323_reg_2047 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14324_reg_2059 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14325_reg_2071 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14326_reg_2083 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14327_reg_2095 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14328_reg_2107 | 14| 3| 16| 48| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_339_reg_2119 | 14| 3| 16| 48| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_340_reg_2131 | 14| 3| 16| 48| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_341_reg_2143 | 14| 3| 16| 48| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_342_reg_2155 | 14| 3| 16| 48| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_343_reg_2167 | 14| 3| 16| 48| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_344_reg_2179 | 14| 3| 16| 48| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_345_reg_2191 | 14| 3| 16| 48| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_346_reg_2203 | 14| 3| 16| 48| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_347_reg_2215 | 14| 3| 16| 48| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_348_reg_2227 | 14| 3| 16| 48| + |w_index25_reg_1362 | 9| 2| 8| 16| + +-------------------------------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + |Total |2278| 489| 3027| 8719| + +-------------------------------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + + * Register: + +--------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + | Name | FF | LUT| Bits| Const Bits| + +--------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + |a_reg_3454 | 16| 0| 16| 0| + |acc24_reg_2239 | 40| 0| 40| 0| + |acc_5622_reg_2254 | 40| 0| 40| 0| + |acc_5720_reg_2269 | 40| 0| 40| 0| + |acc_5818_reg_2284 | 40| 0| 40| 0| + |acc_5916_reg_2299 | 40| 0| 40| 0| + |acc_6014_reg_2314 | 40| 0| 40| 0| + |acc_6112_reg_2329 | 40| 0| 40| 0| + |acc_6210_reg_2344 | 40| 0| 40| 0| + |acc_64_reg_3504 | 40| 0| 40| 0| + |acc_66_reg_3515 | 40| 0| 40| 0| + |acc_69_reg_3526 | 40| 0| 40| 0| + |acc_72_reg_3537 | 40| 0| 40| 0| + |add_ln144_10_reg_3532 | 41| 0| 41| 0| + |add_ln144_8_reg_3510 | 41| 0| 41| 0| + |add_ln144_9_reg_3521 | 41| 0| 41| 0| + |add_ln144_reg_3499 | 41| 0| 41| 0| + |ap_CS_fsm | 1| 0| 1| 0| + |ap_done_reg | 1| 0| 1| 0| + |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| + |ap_enable_reg_pp0_iter2 | 1| 0| 1| 0| + |ap_loop_exit_ready_pp0_iter1_reg | 1| 0| 1| 0| + |ap_loop_exit_ready_pp0_iter2_reg | 1| 0| 1| 0| + |ap_loop_init_pp0_iter1_reg | 1| 0| 1| 0| + |do_init_reg_398 | 1| 0| 1| 0| + |icmp_ln135_reg_3475 | 1| 0| 1| 0| + |icmp_ln135_reg_3475_pp0_iter1_reg | 1| 0| 1| 0| + |in_index26_reg_1349 | 32| 0| 32| 0| + |in_index_reg_3465 | 32| 0| 32| 0| + |out_index_reg_3479 | 1| 0| 1| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14267_reg_1375 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14268_reg_1387 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14269_reg_1399 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14270_reg_1411 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14271_reg_1423 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14272_reg_1435 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14273_reg_1447 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14274_reg_1459 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14275_reg_1471 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14276_reg_1483 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14277_reg_1495 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14278_reg_1507 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14279_reg_1519 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14280_reg_1531 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14281_reg_1543 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14282_reg_1555 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14283_reg_1567 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14284_reg_1579 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14285_reg_1591 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14286_reg_1603 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14287_reg_1615 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14288_reg_1627 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14289_reg_1639 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14290_reg_1651 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14291_reg_1663 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14292_reg_1675 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14293_reg_1687 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14294_reg_1699 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14295_reg_1711 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14296_reg_1723 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14297_reg_1735 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14298_reg_1747 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14299_reg_1759 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14300_reg_1771 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14301_reg_1783 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14302_reg_1795 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14303_reg_1807 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14304_reg_1819 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14305_reg_1831 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14306_reg_1843 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14307_reg_1855 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14308_reg_1867 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14309_reg_1879 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14310_reg_1891 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14311_reg_1903 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14312_reg_1915 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14313_reg_1927 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14314_reg_1939 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14315_reg_1951 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14316_reg_1963 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14317_reg_1975 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14318_reg_1987 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14319_reg_1999 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14320_reg_2011 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14321_reg_2023 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14322_reg_2035 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14323_reg_2047 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14324_reg_2059 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14325_reg_2071 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14326_reg_2083 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14327_reg_2095 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14328_reg_2107 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_339_reg_2119 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_340_reg_2131 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_341_reg_2143 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_342_reg_2155 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_343_reg_2167 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_344_reg_2179 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_345_reg_2191 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_346_reg_2203 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_347_reg_2215 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_348_reg_2227 | 16| 0| 16| 0| + |w_index25_reg_1362 | 8| 0| 8| 0| + |w_index_reg_3470 | 8| 0| 8| 0| + +--------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + |Total |1903| 0| 1903| 0| + +--------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++----------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config4_mult>| return value| +|ap_rst | in| 1| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config4_mult>| return value| +|ap_start | in| 1| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config4_mult>| return value| +|ap_done | out| 1| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config4_mult>| return value| +|ap_idle | out| 1| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config4_mult>| return value| +|ap_ready | out| 1| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config4_mult>| return value| +|ap_return_0 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config4_mult>| return value| +|ap_return_1 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config4_mult>| return value| +|ap_return_2 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config4_mult>| return value| +|ap_return_3 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config4_mult>| return value| +|ap_return_4 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config4_mult>| return value| +|ap_return_5 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config4_mult>| return value| +|ap_return_6 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config4_mult>| return value| +|ap_return_7 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config4_mult>| return value| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_10 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_10| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_11 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_11| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_12 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_12| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_13 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_13| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_14 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_14| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_15 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_15| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_16 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_16| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_17 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_17| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_18 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_18| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_19 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_19| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3491 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3491| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3492 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3492| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3493 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3493| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3494 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3494| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3495 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3495| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3496 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3496| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3497 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3497| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3498 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3498| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3499 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3499| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3500 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3500| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3501 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3501| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3502 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3502| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3503 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3503| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3504 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3504| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3505 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3505| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3506 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3506| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3507 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3507| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3508 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3508| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3509 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3509| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3510 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3510| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3511 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3511| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3512 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3512| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3513 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3513| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3514 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3514| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3515 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3515| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3516 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3516| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3517 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3517| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3518 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3518| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3519 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3519| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3520 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3520| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3521 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3521| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3522 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3522| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3523 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3523| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3524 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3524| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3525 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3525| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3526 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3526| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3527 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3527| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3528 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3528| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3529 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3529| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3530 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3530| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3531 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3531| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3532 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3532| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3533 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3533| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3534 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3534| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3535 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3535| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3536 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3536| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3537 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3537| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3538 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3538| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3539 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3539| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3540 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3540| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3541 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3541| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3542 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3542| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3543 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3543| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3544 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3544| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3545 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3545| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3546 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3546| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3547 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3547| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3548 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3548| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3549 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3549| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3550 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3550| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3551 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3551| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3552 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3552| pointer| ++----------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_csynth.xml b/myproject_prj/solution1/syn/report/dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..9027f60008db849880aefcebcc89413a2cdda7d9 --- /dev/null +++ b/myproject_prj/solution1/syn/report/dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_csynth.xml @@ -0,0 +1,1027 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s +4.00 +1.35 +vivado + + + +loop rewind stp(delay=0 clock cycles(s)) + +ns +4.079 + + +clock cycles +145 +145 +146 +0.591 us +0.591 us +0.596 us +144 +144 + + + +2.65 +144 +145 +591 +1 +3 + + + + + +Timing Violation +- +firmware/nnet_utils/nnet_dense_resource.h:135 + + +ReuseLoop +- +- +firmware/nnet_utils/nnet_dense_resource.h:135 + + + + + + + +2 +4 +1905 +4068 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<40,20,5,3,0>,config4_mult> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<40,20,5,3,0>,config4_mult> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<40,20,5,3,0>,config4_mult> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_done +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<40,20,5,3,0>,config4_mult> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_idle +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<40,20,5,3,0>,config4_mult> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<40,20,5,3,0>,config4_mult> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_return_0 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<40,20,5,3,0>,config4_mult> +return value + +ap_ctrl_hs + +out +40 +data + + +ap_return_1 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<40,20,5,3,0>,config4_mult> +return value + +ap_ctrl_hs + +out +40 +data + + +ap_return_2 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<40,20,5,3,0>,config4_mult> +return value + +ap_ctrl_hs + +out +40 +data + + +ap_return_3 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<40,20,5,3,0>,config4_mult> +return value + +ap_ctrl_hs + +out +40 +data + + +ap_return_4 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<40,20,5,3,0>,config4_mult> +return value + +ap_ctrl_hs + +out +40 +data + + +ap_return_5 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<40,20,5,3,0>,config4_mult> +return value + +ap_ctrl_hs + +out +40 +data + + +ap_return_6 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<40,20,5,3,0>,config4_mult> +return value + +ap_ctrl_hs + +out +40 +data + + +ap_return_7 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed<40,20,5,3,0>,config4_mult> +return value + +ap_ctrl_hs + +out +40 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_10 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_10 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_11 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_11 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_12 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_12 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_13 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_13 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_14 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_14 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_15 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_15 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_16 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_16 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_17 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_17 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_18 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_18 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_19 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_19 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3491 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3491 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3492 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3492 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3493 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3493 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3494 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3494 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3495 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3495 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3496 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3496 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3497 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3497 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3498 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3498 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3499 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3499 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3500 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3500 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3501 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3501 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3502 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3502 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3503 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3503 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3504 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3504 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3505 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3505 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3506 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3506 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3507 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3507 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3508 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+================================================================ +* Date: Sun Apr 5 21:46:39 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 4.079 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+----------+----------+-----+-----+------------------------------------------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | min | max | min | max | min | max | Type | + +---------+---------+----------+----------+-----+-----+------------------------------------------+ + | 145| 146| 0.591 us| 0.596 us| 144| 144| loop rewind stp(delay=0 clock cycles(s))| + +---------+---------+----------+----------+-----+-----+------------------------------------------+ + + + Detail: + * Instance: + N/A + + * Loop: + +-------------+---------+---------+----------+-----------+-----------+------+----------+ + | | Latency (cycles) | Iteration| Initiation Interval | Trip | | + | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| + +-------------+---------+---------+----------+-----------+-----------+------+----------+ + |- ReuseLoop | 145| 145| 3| 1| 1| 144| yes| + +-------------+---------+---------+----------+-----------+-----------+------+----------+ + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| 8| -| -| -| +|Expression | -| -| 0| 2768| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| 0| 325| -| +|Memory | 4| -| 2| 9| -| +|Multiplexer | -| -| 0| 2462| -| +|Register | -| -| 2547| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 4| 8| 2549| 5564| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | ~0| ~0| ~0| 1| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | ~0| ~0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + +-----------------------------+------------------------+---------+----+---+-----+-----+ + | Instance | Module | BRAM_18K| DSP| FF| LUT | URAM| + +-----------------------------+------------------------+---------+----+---+-----+-----+ + |sparsemux_145_7_16_1_1_U356 |sparsemux_145_7_16_1_1 | 0| 0| 0| 325| 0| + +-----------------------------+------------------------+---------+----+---+-----+-----+ + |Total | | 0| 0| 0| 325| 0| + +-----------------------------+------------------------+---------+----+---+-----+-----+ + + * DSP: + +------------------------------------+-------------------------------+--------------+ + | Instance | Module | Expression | + +------------------------------------+-------------------------------+--------------+ + |mac_muladd_16s_11s_40s_41_1_1_U364 |mac_muladd_16s_11s_40s_41_1_1 | i0 + i1 * i2| + |mac_muladd_16s_16s_40s_41_1_1_U357 |mac_muladd_16s_16s_40s_41_1_1 | i0 + i1 * i2| + |mac_muladd_16s_16s_40s_41_1_1_U358 |mac_muladd_16s_16s_40s_41_1_1 | i0 + i1 * i2| + |mac_muladd_16s_16s_40s_41_1_1_U359 |mac_muladd_16s_16s_40s_41_1_1 | i0 + i1 * i2| + |mac_muladd_16s_16s_40s_41_1_1_U360 |mac_muladd_16s_16s_40s_41_1_1 | i0 + i1 * i2| + |mac_muladd_16s_16s_40s_41_1_1_U361 |mac_muladd_16s_16s_40s_41_1_1 | i0 + i1 * i2| + |mac_muladd_16s_16s_40s_41_1_1_U362 |mac_muladd_16s_16s_40s_41_1_1 | i0 + i1 * i2| + |mac_muladd_16s_16s_40s_41_1_1_U363 |mac_muladd_16s_16s_40s_41_1_1 | i0 + i1 * i2| + +------------------------------------+-------------------------------+--------------+ + + * Memory: + +------------+----------------------------------------------------------------------------------+---------+---+----+-----+------+-----+------+-------------+ + | Memory | Module | BRAM_18K| FF| LUT| URAM| Words| Bits| Banks| W*Bits*Banks| + +------------+----------------------------------------------------------------------------------+---------+---+----+-----+------+-----+------+-------------+ + |outidx_3_U |dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_ouvdy | 0| 2| 9| 0| 144| 1| 1| 144| + |w7_U |dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_w7WhU | 4| 0| 0| 0| 144| 123| 1| 17712| + +------------+----------------------------------------------------------------------------------+---------+---+----+-----+------+-----+------+-------------+ + |Total | | 4| 2| 9| 0| 288| 124| 2| 17856| + +------------+----------------------------------------------------------------------------------+---------+---+----+-----+------+-----+------+-------------+ + + * FIFO: + N/A + + * Expression: + +----------------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +----------------------------+----------+----+---+----+------------+------------+ + |in_index_1_fu_3177_p2 | +| 0| 0| 39| 32| 1| + |w_index_fu_3197_p2 | +| 0| 0| 15| 8| 1| + |ap_condition_489 | and| 0| 0| 2| 1| 1| + |icmp_ln135_fu_3203_p2 | icmp| 0| 0| 15| 8| 8| + |icmp_ln144_1_fu_3488_p2 | icmp| 0| 0| 48| 41| 1| + |icmp_ln144_2_fu_3535_p2 | icmp| 0| 0| 48| 41| 1| + |icmp_ln144_3_fu_3582_p2 | icmp| 0| 0| 48| 41| 1| + |icmp_ln144_4_fu_3629_p2 | icmp| 0| 0| 48| 41| 1| + |icmp_ln144_5_fu_3676_p2 | icmp| 0| 0| 48| 41| 1| + |icmp_ln144_6_fu_3723_p2 | icmp| 0| 0| 48| 41| 1| + |icmp_ln144_7_fu_3770_p2 | icmp| 0| 0| 48| 41| 1| + |icmp_ln144_fu_3441_p2 | icmp| 0| 0| 48| 41| 1| + |icmp_ln154_fu_3183_p2 | icmp| 0| 0| 39| 32| 7| + |acc_16_fu_3468_p3 | select| 0| 0| 40| 1| 40| + |acc_17_fu_3460_p3 | select| 0| 0| 40| 1| 40| + |acc_19_fu_3507_p3 | select| 0| 0| 40| 1| 40| + |acc_21_fu_3562_p3 | select| 0| 0| 40| 1| 40| + |acc_22_fu_3554_p3 | select| 0| 0| 40| 1| 40| + |acc_24_fu_3609_p3 | select| 0| 0| 40| 1| 40| + |acc_25_fu_3601_p3 | select| 0| 0| 40| 1| 40| + |acc_27_fu_3656_p3 | select| 0| 0| 40| 1| 40| + |acc_28_fu_3648_p3 | select| 0| 0| 40| 1| 40| + |acc_30_fu_3703_p3 | select| 0| 0| 40| 1| 40| + |acc_31_fu_3695_p3 | select| 0| 0| 40| 1| 40| + |acc_33_fu_3750_p3 | select| 0| 0| 40| 1| 40| + |acc_34_fu_3742_p3 | select| 0| 0| 40| 1| 40| + |acc_36_fu_3797_p3 | select| 0| 0| 40| 1| 40| + |acc_37_fu_3789_p3 | select| 0| 0| 40| 1| 40| + |acc_39_fu_3482_p3 | select| 0| 0| 40| 1| 40| + |acc_40_fu_3476_p3 | select| 0| 0| 40| 1| 40| + |acc_41_fu_3529_p3 | select| 0| 0| 40| 1| 40| + |acc_42_fu_3523_p3 | select| 0| 0| 40| 1| 40| + |acc_43_fu_3576_p3 | select| 0| 0| 40| 1| 40| + |acc_44_fu_3570_p3 | select| 0| 0| 40| 1| 40| + |acc_45_fu_3623_p3 | select| 0| 0| 40| 1| 40| + |acc_46_fu_3617_p3 | select| 0| 0| 40| 1| 40| + |acc_47_fu_3670_p3 | select| 0| 0| 40| 1| 40| + |acc_48_fu_3664_p3 | select| 0| 0| 40| 1| 40| + |acc_49_fu_3717_p3 | select| 0| 0| 40| 1| 40| + |acc_50_fu_3711_p3 | select| 0| 0| 40| 1| 40| + |acc_51_fu_3764_p3 | select| 0| 0| 40| 1| 40| + |acc_52_fu_3758_p3 | select| 0| 0| 40| 1| 40| + |acc_53_fu_3811_p3 | select| 0| 0| 40| 1| 40| + |acc_54_fu_3805_p3 | select| 0| 0| 40| 1| 40| + |acc_fu_3515_p3 | select| 0| 0| 40| 1| 40| + |in_index_fu_3189_p3 | select| 0| 0| 32| 1| 1| + |select_ln144_11_fu_3540_p3 | select| 0| 0| 40| 1| 1| + |select_ln144_12_fu_3547_p3 | select| 0| 0| 40| 1| 40| + |select_ln144_13_fu_3310_p3 | select| 0| 0| 40| 1| 40| + |select_ln144_16_fu_3587_p3 | select| 0| 0| 40| 1| 1| + |select_ln144_17_fu_3594_p3 | select| 0| 0| 40| 1| 40| + |select_ln144_18_fu_3339_p3 | select| 0| 0| 40| 1| 40| + |select_ln144_1_fu_3446_p3 | select| 0| 0| 40| 1| 1| + |select_ln144_21_fu_3634_p3 | select| 0| 0| 40| 1| 1| + |select_ln144_22_fu_3641_p3 | select| 0| 0| 40| 1| 40| + |select_ln144_23_fu_3368_p3 | select| 0| 0| 40| 1| 40| + |select_ln144_26_fu_3681_p3 | select| 0| 0| 40| 1| 1| + |select_ln144_27_fu_3688_p3 | select| 0| 0| 40| 1| 40| + |select_ln144_28_fu_3397_p3 | select| 0| 0| 40| 1| 40| + |select_ln144_2_fu_3453_p3 | select| 0| 0| 40| 1| 40| + |select_ln144_31_fu_3728_p3 | select| 0| 0| 40| 1| 1| + |select_ln144_32_fu_3735_p3 | select| 0| 0| 40| 1| 40| + |select_ln144_33_fu_3426_p3 | select| 0| 0| 40| 1| 40| + |select_ln144_36_fu_3775_p3 | select| 0| 0| 40| 1| 1| + |select_ln144_37_fu_3782_p3 | select| 0| 0| 40| 1| 40| + |select_ln144_3_fu_3252_p3 | select| 0| 0| 40| 1| 40| + |select_ln144_6_fu_3493_p3 | select| 0| 0| 40| 1| 1| + |select_ln144_7_fu_3500_p3 | select| 0| 0| 40| 1| 40| + |select_ln144_8_fu_3281_p3 | select| 0| 0| 40| 1| 40| + |select_ln144_fu_3223_p3 | select| 0| 0| 40| 1| 40| + |ap_enable_pp0 | xor| 0| 0| 2| 1| 2| + +----------------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0|2768| 467| 1957| + +----------------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +-------------------------------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +-------------------------------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + |acc40_reg_2271 | 9| 2| 40| 80| + |acc_1020_reg_2421 | 9| 2| 40| 80| + |acc_1118_reg_2436 | 9| 2| 40| 80| + |acc_1216_reg_2451 | 9| 2| 40| 80| + |acc_1314_reg_2466 | 9| 2| 40| 80| + |acc_138_reg_2286 | 9| 2| 40| 80| + |acc_1412_reg_2481 | 9| 2| 40| 80| + |acc_1510_reg_2496 | 9| 2| 40| 80| + |acc_236_reg_2301 | 9| 2| 40| 80| + |acc_334_reg_2316 | 9| 2| 40| 80| + |acc_432_reg_2331 | 9| 2| 40| 80| + |acc_530_reg_2346 | 9| 2| 40| 80| + |acc_628_reg_2361 | 9| 2| 40| 80| + |acc_726_reg_2376 | 9| 2| 40| 80| + |acc_824_reg_2391 | 9| 2| 40| 80| + |acc_922_reg_2406 | 9| 2| 40| 80| + |ap_done_int | 9| 2| 1| 2| + |ap_loop_exit_ready_pp0_iter2_reg | 9| 2| 1| 2| + |ap_phi_mux_acc40_phi_fu_2275_p6 | 14| 3| 40| 120| + |ap_phi_mux_acc_1020_phi_fu_2425_p6 | 14| 3| 40| 120| + |ap_phi_mux_acc_1118_phi_fu_2440_p6 | 14| 3| 40| 120| + |ap_phi_mux_acc_1216_phi_fu_2455_p6 | 14| 3| 40| 120| + |ap_phi_mux_acc_1314_phi_fu_2470_p6 | 14| 3| 40| 120| + |ap_phi_mux_acc_138_phi_fu_2290_p6 | 14| 3| 40| 120| + |ap_phi_mux_acc_1412_phi_fu_2485_p6 | 14| 3| 40| 120| + |ap_phi_mux_acc_1510_phi_fu_2500_p6 | 14| 3| 40| 120| + |ap_phi_mux_acc_236_phi_fu_2305_p6 | 14| 3| 40| 120| + |ap_phi_mux_acc_334_phi_fu_2320_p6 | 14| 3| 40| 120| + |ap_phi_mux_acc_432_phi_fu_2335_p6 | 14| 3| 40| 120| + |ap_phi_mux_acc_530_phi_fu_2350_p6 | 14| 3| 40| 120| + |ap_phi_mux_acc_628_phi_fu_2365_p6 | 14| 3| 40| 120| + |ap_phi_mux_acc_726_phi_fu_2380_p6 | 14| 3| 40| 120| + |ap_phi_mux_acc_824_phi_fu_2395_p6 | 14| 3| 40| 120| + |ap_phi_mux_acc_922_phi_fu_2410_p6 | 14| 3| 40| 120| + |ap_phi_mux_do_init_phi_fu_433_p6 | 14| 3| 1| 3| + |ap_phi_mux_in_index42_phi_fu_1384_p6 | 14| 3| 32| 96| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14081_phi_fu_1411_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14082_phi_fu_1423_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14083_phi_fu_1435_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14084_phi_fu_1447_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14085_phi_fu_1459_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14086_phi_fu_1471_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14087_phi_fu_1483_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14088_phi_fu_1495_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14089_phi_fu_1507_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14090_phi_fu_1519_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14091_phi_fu_1531_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14092_phi_fu_1543_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14093_phi_fu_1555_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14094_phi_fu_1567_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14095_phi_fu_1579_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14096_phi_fu_1591_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14097_phi_fu_1603_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14098_phi_fu_1615_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14099_phi_fu_1627_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14100_phi_fu_1639_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14101_phi_fu_1651_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14102_phi_fu_1663_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14103_phi_fu_1675_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14104_phi_fu_1687_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14105_phi_fu_1699_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14106_phi_fu_1711_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14107_phi_fu_1723_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14108_phi_fu_1735_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14109_phi_fu_1747_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14110_phi_fu_1759_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14111_phi_fu_1771_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14112_phi_fu_1783_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14113_phi_fu_1795_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14114_phi_fu_1807_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14115_phi_fu_1819_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14116_phi_fu_1831_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14117_phi_fu_1843_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14118_phi_fu_1855_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14119_phi_fu_1867_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14120_phi_fu_1879_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14121_phi_fu_1891_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14122_phi_fu_1903_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14123_phi_fu_1915_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14124_phi_fu_1927_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14125_phi_fu_1939_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14126_phi_fu_1951_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14127_phi_fu_1963_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14128_phi_fu_1975_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14129_phi_fu_1987_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14130_phi_fu_1999_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14131_phi_fu_2011_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14132_phi_fu_2023_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14133_phi_fu_2035_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14134_phi_fu_2047_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14135_phi_fu_2059_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14136_phi_fu_2071_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14137_phi_fu_2083_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14138_phi_fu_2095_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14139_phi_fu_2107_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14140_phi_fu_2119_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14141_phi_fu_2131_p4 | 14| 3| 16| 48| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14142_phi_fu_2143_p4 | 14| 3| 16| 48| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_309_phi_fu_2155_p4 | 14| 3| 16| 48| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_310_phi_fu_2167_p4 | 14| 3| 16| 48| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_311_phi_fu_2179_p4 | 14| 3| 16| 48| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_312_phi_fu_2191_p4 | 14| 3| 16| 48| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_313_phi_fu_2203_p4 | 14| 3| 16| 48| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_314_phi_fu_2215_p4 | 14| 3| 16| 48| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_315_phi_fu_2227_p4 | 14| 3| 16| 48| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_316_phi_fu_2239_p4 | 14| 3| 16| 48| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_317_phi_fu_2251_p4 | 14| 3| 16| 48| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_318_phi_fu_2263_p4 | 14| 3| 16| 48| + |ap_phi_mux_w_index41_phi_fu_1397_p6 | 14| 3| 8| 24| + |in_index42_reg_1381 | 9| 2| 32| 64| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14081_reg_1407 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14082_reg_1419 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14083_reg_1431 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14084_reg_1443 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14085_reg_1455 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14086_reg_1467 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14087_reg_1479 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14088_reg_1491 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14089_reg_1503 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14090_reg_1515 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14091_reg_1527 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14092_reg_1539 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14093_reg_1551 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14094_reg_1563 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14095_reg_1575 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14096_reg_1587 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14097_reg_1599 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14098_reg_1611 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14099_reg_1623 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14100_reg_1635 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14101_reg_1647 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14102_reg_1659 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14103_reg_1671 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14104_reg_1683 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14105_reg_1695 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14106_reg_1707 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14107_reg_1719 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14108_reg_1731 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14109_reg_1743 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14110_reg_1755 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14111_reg_1767 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14112_reg_1779 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14113_reg_1791 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14114_reg_1803 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14115_reg_1815 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14116_reg_1827 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14117_reg_1839 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14118_reg_1851 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14119_reg_1863 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14120_reg_1875 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14121_reg_1887 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14122_reg_1899 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14123_reg_1911 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14124_reg_1923 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14125_reg_1935 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14126_reg_1947 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14127_reg_1959 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14128_reg_1971 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14129_reg_1983 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14130_reg_1995 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14131_reg_2007 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14132_reg_2019 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14133_reg_2031 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14134_reg_2043 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14135_reg_2055 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14136_reg_2067 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14137_reg_2079 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14138_reg_2091 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14139_reg_2103 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14140_reg_2115 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14141_reg_2127 | 14| 3| 16| 48| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14142_reg_2139 | 14| 3| 16| 48| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_309_reg_2151 | 14| 3| 16| 48| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_310_reg_2163 | 14| 3| 16| 48| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_311_reg_2175 | 14| 3| 16| 48| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_312_reg_2187 | 14| 3| 16| 48| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_313_reg_2199 | 14| 3| 16| 48| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_314_reg_2211 | 14| 3| 16| 48| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_315_reg_2223 | 14| 3| 16| 48| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_316_reg_2235 | 14| 3| 16| 48| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_317_reg_2247 | 14| 3| 16| 48| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_318_reg_2259 | 14| 3| 16| 48| + |w_index41_reg_1394 | 9| 2| 8| 16| + +-------------------------------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + |Total |2462| 529| 3667| 10319| + +-------------------------------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + + * Register: + +--------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + | Name | FF | LUT| Bits| Const Bits| + +--------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + |a_reg_3994 | 16| 0| 16| 0| + |acc40_reg_2271 | 40| 0| 40| 0| + |acc_1020_reg_2421 | 40| 0| 40| 0| + |acc_1118_reg_2436 | 40| 0| 40| 0| + |acc_1216_reg_2451 | 40| 0| 40| 0| + |acc_1314_reg_2466 | 40| 0| 40| 0| + |acc_138_reg_2286 | 40| 0| 40| 0| + |acc_1412_reg_2481 | 40| 0| 40| 0| + |acc_1510_reg_2496 | 40| 0| 40| 0| + |acc_18_reg_4060 | 40| 0| 40| 0| + |acc_20_reg_4071 | 40| 0| 40| 0| + |acc_236_reg_2301 | 40| 0| 40| 0| + |acc_23_reg_4082 | 40| 0| 40| 0| + |acc_26_reg_4093 | 40| 0| 40| 0| + |acc_29_reg_4104 | 40| 0| 40| 0| + |acc_32_reg_4115 | 40| 0| 40| 0| + |acc_334_reg_2316 | 40| 0| 40| 0| + |acc_35_reg_4126 | 40| 0| 40| 0| + |acc_38_reg_4137 | 40| 0| 40| 0| + |acc_432_reg_2331 | 40| 0| 40| 0| + |acc_530_reg_2346 | 40| 0| 40| 0| + |acc_628_reg_2361 | 40| 0| 40| 0| + |acc_726_reg_2376 | 40| 0| 40| 0| + |acc_824_reg_2391 | 40| 0| 40| 0| + |acc_922_reg_2406 | 40| 0| 40| 0| + |add_ln144_1_reg_4066 | 41| 0| 41| 0| + |add_ln144_2_reg_4077 | 41| 0| 41| 0| + |add_ln144_3_reg_4088 | 41| 0| 41| 0| + |add_ln144_4_reg_4099 | 41| 0| 41| 0| + |add_ln144_5_reg_4110 | 41| 0| 41| 0| + |add_ln144_6_reg_4121 | 41| 0| 41| 0| + |add_ln144_7_reg_4132 | 41| 0| 41| 0| + |add_ln144_reg_4055 | 41| 0| 41| 0| + |ap_CS_fsm | 1| 0| 1| 0| + |ap_done_reg | 1| 0| 1| 0| + |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| + |ap_enable_reg_pp0_iter2 | 1| 0| 1| 0| + |ap_loop_exit_ready_pp0_iter1_reg | 1| 0| 1| 0| + |ap_loop_exit_ready_pp0_iter2_reg | 1| 0| 1| 0| + |ap_loop_init_pp0_iter1_reg | 1| 0| 1| 0| + |do_init_reg_430 | 1| 0| 1| 0| + |icmp_ln135_reg_4015 | 1| 0| 1| 0| + |icmp_ln135_reg_4015_pp0_iter1_reg | 1| 0| 1| 0| + |in_index42_reg_1381 | 32| 0| 32| 0| + |in_index_reg_4005 | 32| 0| 32| 0| + |out_index_reg_4019 | 1| 0| 1| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14081_reg_1407 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14082_reg_1419 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14083_reg_1431 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14084_reg_1443 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14085_reg_1455 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14086_reg_1467 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14087_reg_1479 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14088_reg_1491 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14089_reg_1503 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14090_reg_1515 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14091_reg_1527 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14092_reg_1539 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14093_reg_1551 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14094_reg_1563 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14095_reg_1575 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14096_reg_1587 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14097_reg_1599 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14098_reg_1611 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14099_reg_1623 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14100_reg_1635 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14101_reg_1647 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14102_reg_1659 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14103_reg_1671 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14104_reg_1683 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14105_reg_1695 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14106_reg_1707 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14107_reg_1719 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14108_reg_1731 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14109_reg_1743 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14110_reg_1755 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14111_reg_1767 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14112_reg_1779 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14113_reg_1791 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14114_reg_1803 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14115_reg_1815 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14116_reg_1827 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14117_reg_1839 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14118_reg_1851 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14119_reg_1863 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14120_reg_1875 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14121_reg_1887 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14122_reg_1899 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14123_reg_1911 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14124_reg_1923 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14125_reg_1935 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14126_reg_1947 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14127_reg_1959 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14128_reg_1971 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14129_reg_1983 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14130_reg_1995 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14131_reg_2007 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14132_reg_2019 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14133_reg_2031 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14134_reg_2043 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14135_reg_2055 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14136_reg_2067 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14137_reg_2079 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14138_reg_2091 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14139_reg_2103 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14140_reg_2115 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14141_reg_2127 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_14142_reg_2139 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_309_reg_2151 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_310_reg_2163 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_311_reg_2175 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_312_reg_2187 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_313_reg_2199 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_314_reg_2211 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_315_reg_2223 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_316_reg_2235 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_317_reg_2247 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_318_reg_2259 | 16| 0| 16| 0| + |w_index41_reg_1394 | 8| 0| 8| 0| + |w_index_reg_4010 | 8| 0| 8| 0| + +--------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + |Total |2547| 0| 2547| 0| + +--------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++----------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config7_mult>| return value| +|ap_rst | in| 1| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config7_mult>| return value| +|ap_start | in| 1| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config7_mult>| return value| +|ap_done | out| 1| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config7_mult>| return value| +|ap_idle | out| 1| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config7_mult>| return value| +|ap_ready | out| 1| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config7_mult>| return value| +|ap_return_0 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config7_mult>| return value| +|ap_return_1 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config7_mult>| return value| +|ap_return_2 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config7_mult>| return value| +|ap_return_3 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config7_mult>| return value| +|ap_return_4 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config7_mult>| return value| +|ap_return_5 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config7_mult>| return value| +|ap_return_6 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config7_mult>| return value| +|ap_return_7 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config7_mult>| return value| +|ap_return_8 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config7_mult>| return value| +|ap_return_9 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config7_mult>| return value| +|ap_return_10 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config7_mult>| return value| +|ap_return_11 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config7_mult>| return value| +|ap_return_12 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config7_mult>| return value| +|ap_return_13 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config7_mult>| return value| +|ap_return_14 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config7_mult>| return value| +|ap_return_15 | out| 40| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0,config7_mult>| return value| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_30 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_30| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_31 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_31| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_32 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_32| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_33 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_33| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_34 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_34| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_35 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_35| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_36 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_36| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_37 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_37| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_38 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_38| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_39 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_39| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6795 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6795| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6796 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6796| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6797 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6797| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6798 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6798| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6799 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6799| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6800 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6800| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6801 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6801| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6802 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6802| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6803 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6803| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6804 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6804| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6806 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6806| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6807 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6807| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6808 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6808| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6809 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6809| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6810 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6810| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6811 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6811| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6812 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6812| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6813 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6813| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6814 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6814| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6815 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6815| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6817 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6817| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6818 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6818| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6819 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6819| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6820 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6820| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6821 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6821| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6822 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6822| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6823 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6823| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6824 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6824| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6825 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6825| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6826 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6826| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6828 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6828| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6829 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6829| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6830 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6830| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6831 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6831| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6832 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6832| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6833 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6833| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6834 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6834| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6835 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6835| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6836 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6836| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6837 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6837| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_999 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_999| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3470 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3470| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3471 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3471| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3472 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3472| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3473 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3473| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3474 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3474| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3475 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3475| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3476 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3476| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3477 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3477| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3478 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3478| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3479 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3479| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3480 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3480| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3481 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3481| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3482 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3482| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3483 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3483| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3484 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3484| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3485 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3485| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3486 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3486| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3487 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3487| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3488 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3488| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3489 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3489| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3490 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3490| pointer| ++----------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s_csynth.xml b/myproject_prj/solution1/syn/report/dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..7c9160c25f874ea3bad14e32582953c3253f5112 --- /dev/null +++ b/myproject_prj/solution1/syn/report/dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s_csynth.xml @@ -0,0 +1,7187 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s +4.00 +1.35 +vivado + + + +loop rewind stp(delay=0 clock cycles(s)) + +ns +4.138 + + +clock cycles +1153 +1153 +1154 +4.771 us +4.771 us +4.775 us +1152 +1152 + + + +2.65 +1152 +1153 +4770 +1 +3 + + + + + +Timing Violation +- +firmware/nnet_utils/nnet_dense_resource.h:135 + + +ReuseLoop +- +- +firmware/nnet_utils/nnet_dense_resource.h:135 + + + + + + + +33 +32 +14865 +31785 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_done +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_idle +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_return_0 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_1 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_2 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_3 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_4 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_5 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_6 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_7 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_8 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_9 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_10 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_11 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_12 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_13 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_14 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_15 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_16 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_17 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_18 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_19 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_20 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_21 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_22 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_23 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_24 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_25 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_26 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_27 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_28 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_29 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_30 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_31 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_32 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_33 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_34 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_35 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_36 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_37 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_38 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_39 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_40 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_41 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_42 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_43 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_44 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_45 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_46 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_47 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_48 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_49 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_50 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_51 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_52 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_53 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_54 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_55 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_56 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_57 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_58 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_59 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_60 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_61 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_62 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +ap_return_63 +dense_resource_rf_gt_nin_rem0<ap_fixed,ap_fixed,config19_mult> +return value + +ap_ctrl_hs + +out +43 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_49 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_49 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_48 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_48 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_47 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_47 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_46 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_46 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_45 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_45 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_44 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_44 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_43 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_43 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_42 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_42 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_41 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_41 +pointer +global +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_40 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_40 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6172 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6172 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6184 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6184 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6196 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6196 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6208 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6208 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6220 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6220 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6232 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6232 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6245 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6245 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6257 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6257 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6269 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6269 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6281 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6281 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6293 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6293 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6305 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6305 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6317 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6317 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6329 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6329 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6341 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6341 +pointer +global +ap_none + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6353 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+ap_none + +in +16 +data + + + + diff --git a/myproject_prj/solution1/syn/report/dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s_csynth.rpt b/myproject_prj/solution1/syn/report/dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..ea68a0fc7161c3f5dde51a0512215d780c92e888 --- /dev/null +++ b/myproject_prj/solution1/syn/report/dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s_csynth.rpt @@ -0,0 +1,2173 @@ + + +================================================================ +== Vitis HLS Report for 'dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s' +================================================================ +* Date: Sun Apr 5 21:49:11 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 4.449 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+----------+----------+------+------+------------------------------------------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | min | max | min | max | min | max | Type | + +---------+---------+----------+----------+------+------+------------------------------------------+ + | 1154| 1155| 5.135 us| 5.139 us| 1152| 1152| loop rewind stp(delay=0 clock cycles(s))| + +---------+---------+----------+----------+------+------+------------------------------------------+ + + + Detail: + * Instance: + N/A + + * Loop: + +-------------+---------+---------+----------+-----------+-----------+------+----------+ + | | Latency (cycles) | Iteration| Initiation Interval | Trip | | + | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| + +-------------+---------+---------+----------+-----------+-----------+------+----------+ + |- ReuseLoop | 1154| 1154| 4| 1| 1| 1152| yes| + +-------------+---------+---------+----------+-----------+-----------+------+----------+ + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| 8| -| -| -| +|Expression | -| -| 0| 2361| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| 0| 1688| -| +|Memory | 16| -| 0| 0| -| +|Multiplexer | -| -| 0| 8590| -| +|Register | -| -| 12171| 32| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 16| 8| 12171| 12671| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 1| ~0| 1| 2| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | ~0| ~0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + +------------------------------+------------------------+---------+----+---+------+-----+ + | Instance | Module | BRAM_18K| DSP| FF| LUT | URAM| + +------------------------------+------------------------+---------+----+---+------+-----+ + |sparsemux_577_9_16_1_1_U6402 |sparsemux_577_9_16_1_1 | 0| 0| 0| 1528| 0| + |sparsemux_9_2_42_1_1_U6403 |sparsemux_9_2_42_1_1 | 0| 0| 0| 20| 0| + |sparsemux_9_2_42_1_1_U6404 |sparsemux_9_2_42_1_1 | 0| 0| 0| 20| 0| + |sparsemux_9_2_42_1_1_U6405 |sparsemux_9_2_42_1_1 | 0| 0| 0| 20| 0| + |sparsemux_9_2_42_1_1_U6406 |sparsemux_9_2_42_1_1 | 0| 0| 0| 20| 0| + |sparsemux_9_2_42_1_1_U6407 |sparsemux_9_2_42_1_1 | 0| 0| 0| 20| 0| + |sparsemux_9_2_42_1_1_U6408 |sparsemux_9_2_42_1_1 | 0| 0| 0| 20| 0| + |sparsemux_9_2_42_1_1_U6409 |sparsemux_9_2_42_1_1 | 0| 0| 0| 20| 0| + |sparsemux_9_2_42_1_1_U6410 |sparsemux_9_2_42_1_1 | 0| 0| 0| 20| 0| + +------------------------------+------------------------+---------+----+---+------+-----+ + |Total | | 0| 0| 0| 1688| 0| + +------------------------------+------------------------+---------+----+---+------+-----+ + + * DSP: + +-------------------------------------+-------------------------------+--------------+ + | Instance | Module | Expression | + +-------------------------------------+-------------------------------+--------------+ + |mac_muladd_16s_11s_42s_43_1_1_U6418 |mac_muladd_16s_11s_42s_43_1_1 | i0 + i1 * i2| + |mac_muladd_16s_16s_42s_43_1_1_U6411 |mac_muladd_16s_16s_42s_43_1_1 | i0 + i1 * i2| + |mac_muladd_16s_16s_42s_43_1_1_U6412 |mac_muladd_16s_16s_42s_43_1_1 | i0 + i1 * i2| + |mac_muladd_16s_16s_42s_43_1_1_U6413 |mac_muladd_16s_16s_42s_43_1_1 | i0 + i1 * i2| + |mac_muladd_16s_16s_42s_43_1_1_U6414 |mac_muladd_16s_16s_42s_43_1_1 | i0 + i1 * i2| + |mac_muladd_16s_16s_42s_43_1_1_U6415 |mac_muladd_16s_16s_42s_43_1_1 | i0 + i1 * i2| + |mac_muladd_16s_16s_42s_43_1_1_U6416 |mac_muladd_16s_16s_42s_43_1_1 | i0 + i1 * i2| + |mac_muladd_16s_16s_42s_43_1_1_U6417 |mac_muladd_16s_16s_42s_43_1_1 | i0 + i1 * i2| + +-------------------------------------+-------------------------------+--------------+ + + * Memory: + +------------+----------------------------------------------------------------------------------+---------+---+----+-----+------+-----+------+-------------+ + | Memory | Module | BRAM_18K| FF| LUT| URAM| Words| Bits| Banks| W*Bits*Banks| + +------------+----------------------------------------------------------------------------------+---------+---+----+-----+------+-----+------+-------------+ + |outidx_8_U |dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s_outidx_6_ROM_eUV | 1| 0| 0| 0| 1152| 2| 1| 2304| + |w25_U |dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s_w25_ROM_NP_BRlcb | 15| 0| 0| 0| 1152| 123| 1| 141696| + +------------+----------------------------------------------------------------------------------+---------+---+----+-----+------+-----+------+-------------+ + |Total | | 16| 0| 0| 0| 2304| 125| 2| 144000| + +------------+----------------------------------------------------------------------------------+---------+---+----+-----+------+-----+------+-------------+ + + * FIFO: + N/A + + * Expression: + +---------------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +---------------------------+----------+----+---+----+------------+------------+ + |in_index_6_fu_11723_p2 | +| 0| 0| 39| 32| 1| + |w_index_fu_10473_p2 | +| 0| 0| 18| 11| 1| + |and_ln144_fu_12499_p2 | and| 0| 0| 2| 1| 1| + |ap_condition_2195 | and| 0| 0| 2| 1| 1| + |ap_condition_2224 | and| 0| 0| 2| 1| 1| + |icmp_ln135_fu_10479_p2 | icmp| 0| 0| 18| 11| 11| + |icmp_ln144_30_fu_11784_p2 | icmp| 0| 0| 10| 2| 3| + |icmp_ln144_31_fu_11789_p2 | icmp| 0| 0| 9| 2| 1| + |icmp_ln144_32_fu_11794_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln144_33_fu_11896_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln144_34_fu_11986_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln144_35_fu_12076_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln144_36_fu_12138_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln144_37_fu_12228_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln144_38_fu_12408_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln144_39_fu_12318_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln144_40_fu_12413_p2 | icmp| 0| 0| 9| 2| 1| + |icmp_ln144_fu_11779_p2 | icmp| 0| 0| 9| 2| 2| + |icmp_ln154_fu_11729_p2 | icmp| 0| 0| 39| 32| 9| + |or_ln144_10_fu_11997_p2 | or| 0| 0| 2| 1| 1| + |or_ln144_11_fu_12437_p2 | or| 0| 0| 2| 1| 1| + |or_ln144_12_fu_12441_p2 | or| 0| 0| 2| 1| 1| + |or_ln144_13_fu_12445_p2 | or| 0| 0| 2| 1| 1| + |or_ln144_15_fu_12459_p2 | or| 0| 0| 2| 1| 1| + |or_ln144_16_fu_12143_p2 | or| 0| 0| 2| 1| 1| + |or_ln144_18_fu_12149_p2 | or| 0| 0| 2| 1| 1| + |or_ln144_19_fu_12233_p2 | or| 0| 0| 2| 1| 1| + |or_ln144_1_fu_11805_p2 | or| 0| 0| 2| 1| 1| + |or_ln144_21_fu_12239_p2 | or| 0| 0| 2| 1| 1| + |or_ln144_22_fu_12323_p2 | or| 0| 0| 2| 1| 1| + |or_ln144_24_fu_12329_p2 | or| 0| 0| 2| 1| 1| + |or_ln144_25_fu_12476_p2 | or| 0| 0| 2| 1| 1| + |or_ln144_26_fu_12481_p2 | or| 0| 0| 2| 1| 1| + |or_ln144_27_fu_12485_p2 | or| 0| 0| 2| 1| 1| + |or_ln144_28_fu_12517_p2 | or| 0| 0| 2| 1| 1| + |or_ln144_29_fu_12521_p2 | or| 0| 0| 2| 1| 1| + |or_ln144_2_fu_11811_p2 | or| 0| 0| 2| 1| 1| + |or_ln144_4_fu_11878_p2 | or| 0| 0| 2| 1| 1| + |or_ln144_5_fu_11901_p2 | or| 0| 0| 2| 1| 1| + |or_ln144_7_fu_11907_p2 | or| 0| 0| 2| 1| 1| + |or_ln144_8_fu_11991_p2 | or| 0| 0| 2| 1| 1| + |or_ln144_fu_11799_p2 | or| 0| 0| 2| 1| 1| + |acc_126_fu_11870_p3 | select| 0| 0| 42| 1| 42| + |acc_127_fu_11862_p3 | select| 0| 0| 42| 1| 42| + |acc_128_fu_11854_p3 | select| 0| 0| 42| 1| 42| + |acc_129_fu_11974_p3 | select| 0| 0| 42| 1| 42| + |acc_130_fu_11966_p3 | select| 0| 0| 42| 1| 42| + |acc_131_fu_11958_p3 | select| 0| 0| 42| 1| 42| + |acc_132_fu_11950_p3 | select| 0| 0| 42| 1| 42| + |acc_133_fu_12064_p3 | select| 0| 0| 42| 1| 42| + |acc_134_fu_12056_p3 | select| 0| 0| 42| 1| 42| + |acc_135_fu_12048_p3 | select| 0| 0| 42| 1| 42| + |acc_136_fu_12040_p3 | select| 0| 0| 42| 1| 42| + |acc_137_fu_12464_p3 | select| 0| 0| 42| 1| 42| + |acc_138_fu_12126_p3 | select| 0| 0| 42| 1| 42| + |acc_139_fu_12118_p3 | select| 0| 0| 42| 1| 42| + |acc_140_fu_12110_p3 | select| 0| 0| 42| 1| 42| + |acc_141_fu_12216_p3 | select| 0| 0| 42| 1| 42| + |acc_142_fu_12208_p3 | select| 0| 0| 42| 1| 42| + |acc_143_fu_12200_p3 | select| 0| 0| 42| 1| 42| + |acc_144_fu_12192_p3 | select| 0| 0| 42| 1| 42| + |acc_145_fu_12306_p3 | select| 0| 0| 42| 1| 42| + |acc_146_fu_12298_p3 | select| 0| 0| 42| 1| 42| + |acc_147_fu_12290_p3 | select| 0| 0| 42| 1| 42| + |acc_148_fu_12282_p3 | select| 0| 0| 42| 1| 42| + |acc_149_fu_12396_p3 | select| 0| 0| 42| 1| 42| + |acc_150_fu_12388_p3 | select| 0| 0| 42| 1| 42| + |acc_151_fu_12380_p3 | select| 0| 0| 42| 1| 42| + |acc_152_fu_12372_p3 | select| 0| 0| 42| 1| 42| + |acc_153_fu_12429_p3 | select| 0| 0| 42| 1| 42| + |acc_154_fu_12421_p3 | select| 0| 0| 42| 1| 42| + |acc_155_fu_12526_p3 | select| 0| 0| 42| 1| 42| + |acc_156_fu_12511_p3 | select| 0| 0| 42| 1| 42| + |acc_157_fu_11817_p3 | select| 0| 0| 42| 1| 42| + |acc_159_fu_11913_p3 | select| 0| 0| 42| 1| 42| + |acc_161_fu_12003_p3 | select| 0| 0| 42| 1| 42| + |acc_163_fu_12451_p3 | select| 0| 0| 42| 1| 42| + |acc_165_fu_12155_p3 | select| 0| 0| 42| 1| 42| + |acc_167_fu_12245_p3 | select| 0| 0| 42| 1| 42| + |acc_169_fu_12335_p3 | select| 0| 0| 42| 1| 42| + |acc_171_fu_12503_p3 | select| 0| 0| 42| 1| 1| + |acc_172_fu_12491_p3 | select| 0| 0| 42| 1| 42| + |acc_fu_11884_p3 | select| 0| 0| 42| 1| 42| + |in_index_fu_11735_p3 | select| 0| 0| 32| 1| 1| + |ap_enable_pp0 | xor| 0| 0| 2| 1| 2| + |xor_ln144_fu_12471_p2 | xor| 0| 0| 2| 1| 2| + +---------------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0|2361| 508| 1749| + +---------------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +-----------------------------------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +-----------------------------------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + |acc72_reg_8864 | 9| 2| 42| 84| + |acc_16069_reg_8878 | 9| 2| 42| 84| + |acc_16167_reg_8892 | 9| 2| 42| 84| + |acc_16265_reg_8906 | 9| 2| 42| 84| + |acc_16364_reg_8920 | 9| 2| 42| 84| + |acc_16461_reg_8934 | 9| 2| 42| 84| + |acc_16559_reg_8948 | 9| 2| 42| 84| + |acc_16657_reg_8962 | 9| 2| 42| 84| + |acc_16756_reg_8976 | 9| 2| 42| 84| + |acc_16853_reg_8990 | 9| 2| 42| 84| + |acc_16951_reg_9004 | 9| 2| 42| 84| + |acc_17049_reg_9018 | 9| 2| 42| 84| + |acc_17148_reg_9032 | 9| 2| 42| 84| + |acc_17245_reg_9047 | 9| 2| 42| 84| + |acc_17343_reg_9061 | 9| 2| 42| 84| + |acc_17441_reg_9075 | 9| 2| 42| 84| + |acc_17540_reg_9089 | 9| 2| 42| 84| + |acc_17637_reg_9103 | 9| 2| 42| 84| + |acc_17735_reg_9117 | 9| 2| 42| 84| + |acc_17833_reg_9131 | 9| 2| 42| 84| + |acc_17932_reg_9145 | 9| 2| 42| 84| + |acc_18029_reg_9159 | 9| 2| 42| 84| + |acc_18127_reg_9173 | 9| 2| 42| 84| + |acc_18225_reg_9187 | 9| 2| 42| 84| + |acc_18324_reg_9201 | 9| 2| 42| 84| + |acc_18421_reg_9215 | 9| 2| 42| 84| + |acc_18519_reg_9229 | 9| 2| 42| 84| + |acc_18617_reg_9243 | 9| 2| 42| 84| + |acc_18715_reg_9257 | 9| 2| 42| 84| + |acc_18813_reg_9271 | 9| 2| 42| 84| + |acc_18912_reg_9285 | 9| 2| 42| 84| + |acc_19010_reg_9300 | 9| 2| 42| 84| + |ap_done_int | 9| 2| 1| 2| + |ap_loop_exit_ready_pp0_iter3_reg | 9| 2| 1| 2| + |ap_phi_mux_acc72_phi_fu_8868_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_16069_phi_fu_8882_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_16167_phi_fu_8896_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_16265_phi_fu_8910_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_16364_phi_fu_8924_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_16461_phi_fu_8938_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_16559_phi_fu_8952_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_16657_phi_fu_8966_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_16756_phi_fu_8980_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_16853_phi_fu_8994_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_16951_phi_fu_9008_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_17049_phi_fu_9022_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_17148_phi_fu_9036_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_17245_phi_fu_9051_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_17343_phi_fu_9065_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_17441_phi_fu_9079_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_17540_phi_fu_9093_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_17637_phi_fu_9107_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_17735_phi_fu_9121_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_17833_phi_fu_9135_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_17932_phi_fu_9149_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_18029_phi_fu_9163_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_18127_phi_fu_9177_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_18225_phi_fu_9191_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_18324_phi_fu_9205_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_18421_phi_fu_9219_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_18519_phi_fu_9233_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_18617_phi_fu_9247_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_18715_phi_fu_9261_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_18813_phi_fu_9275_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_18912_phi_fu_9289_p6 | 14| 3| 42| 126| + |ap_phi_mux_acc_19010_phi_fu_9304_p6 | 14| 3| 42| 126| + |ap_phi_mux_do_init_phi_fu_1337_p6 | 14| 3| 1| 3| + |ap_phi_mux_in_index74_phi_fu_5398_p6 | 14| 3| 32| 96| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15041_phi_fu_5412_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15042_phi_fu_5424_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15043_phi_fu_5436_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15044_phi_fu_5448_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15045_phi_fu_5460_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15046_phi_fu_5472_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15047_phi_fu_5484_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15048_phi_fu_5496_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15049_phi_fu_5508_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15050_phi_fu_5520_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15051_phi_fu_5532_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15052_phi_fu_5544_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15053_phi_fu_5556_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15054_phi_fu_5568_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15055_phi_fu_5580_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15056_phi_fu_5592_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15057_phi_fu_5604_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15058_phi_fu_5616_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15059_phi_fu_5628_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15060_phi_fu_5640_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15061_phi_fu_5652_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15062_phi_fu_5664_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15063_phi_fu_5676_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15064_phi_fu_5688_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15065_phi_fu_5700_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15066_phi_fu_5712_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15067_phi_fu_5724_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15068_phi_fu_5736_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15069_phi_fu_5748_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15070_phi_fu_5760_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15071_phi_fu_5772_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15072_phi_fu_5784_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15073_phi_fu_5796_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15074_phi_fu_5808_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15075_phi_fu_5820_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15076_phi_fu_5832_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15077_phi_fu_5844_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15078_phi_fu_5856_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15079_phi_fu_5868_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15080_phi_fu_5880_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15081_phi_fu_5892_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15082_phi_fu_5904_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15083_phi_fu_5916_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15084_phi_fu_5928_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15085_phi_fu_5940_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15086_phi_fu_5952_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15087_phi_fu_5964_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15088_phi_fu_5976_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15089_phi_fu_5988_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15090_phi_fu_6000_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15091_phi_fu_6012_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15092_phi_fu_6024_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15093_phi_fu_6036_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15094_phi_fu_6048_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15095_phi_fu_6060_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15096_phi_fu_6072_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15097_phi_fu_6084_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15098_phi_fu_6096_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15099_phi_fu_6108_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15100_phi_fu_6120_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15101_phi_fu_6132_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15102_phi_fu_6144_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15103_phi_fu_6156_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15104_phi_fu_6168_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15105_phi_fu_6180_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15106_phi_fu_6192_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15107_phi_fu_6204_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15108_phi_fu_6216_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15109_phi_fu_6228_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15110_phi_fu_6240_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15111_phi_fu_6252_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15112_phi_fu_6264_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15113_phi_fu_6276_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15114_phi_fu_6288_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15115_phi_fu_6300_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15116_phi_fu_6312_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15117_phi_fu_6324_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15118_phi_fu_6336_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15119_phi_fu_6348_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15120_phi_fu_6360_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15121_phi_fu_6372_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15122_phi_fu_6384_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15123_phi_fu_6396_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15124_phi_fu_6408_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15125_phi_fu_6420_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15126_phi_fu_6432_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15127_phi_fu_6444_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15128_phi_fu_6456_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15129_phi_fu_6468_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15130_phi_fu_6480_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15131_phi_fu_6492_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15132_phi_fu_6504_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15133_phi_fu_6516_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15134_phi_fu_6528_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15135_phi_fu_6540_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15136_phi_fu_6552_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15137_phi_fu_6564_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15138_phi_fu_6576_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15139_phi_fu_6588_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15140_phi_fu_6600_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15141_phi_fu_6612_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15142_phi_fu_6624_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15143_phi_fu_6636_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15144_phi_fu_6648_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15145_phi_fu_6660_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15146_phi_fu_6672_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15147_phi_fu_6684_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15148_phi_fu_6696_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15149_phi_fu_6708_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15150_phi_fu_6720_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15151_phi_fu_6732_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15152_phi_fu_6744_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15153_phi_fu_6756_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15154_phi_fu_6768_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15155_phi_fu_6780_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15156_phi_fu_6792_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15157_phi_fu_6804_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15158_phi_fu_6816_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15159_phi_fu_6828_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15160_phi_fu_6840_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15161_phi_fu_6852_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15162_phi_fu_6864_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15163_phi_fu_6876_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15164_phi_fu_6888_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15165_phi_fu_6900_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15166_phi_fu_6912_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15167_phi_fu_6924_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15168_phi_fu_6936_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15169_phi_fu_6948_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15170_phi_fu_6960_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15171_phi_fu_6972_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15172_phi_fu_6984_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15173_phi_fu_6996_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15174_phi_fu_7008_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15175_phi_fu_7020_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15176_phi_fu_7032_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15177_phi_fu_7044_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15178_phi_fu_7056_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15179_phi_fu_7068_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15180_phi_fu_7080_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15181_phi_fu_7092_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15182_phi_fu_7104_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15183_phi_fu_7116_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15184_phi_fu_7128_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15185_phi_fu_7140_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15186_phi_fu_7152_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15187_phi_fu_7164_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15188_phi_fu_7176_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15189_phi_fu_7188_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15190_phi_fu_7200_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15191_phi_fu_7212_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15192_phi_fu_7224_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15193_phi_fu_7236_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15194_phi_fu_7248_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15195_phi_fu_7260_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15196_phi_fu_7272_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15197_phi_fu_7284_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15198_phi_fu_7296_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15199_phi_fu_7308_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15200_phi_fu_7320_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15201_phi_fu_7332_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15202_phi_fu_7344_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15203_phi_fu_7356_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15204_phi_fu_7368_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15205_phi_fu_7380_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15206_phi_fu_7392_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15207_phi_fu_7404_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15208_phi_fu_7416_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15209_phi_fu_7428_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15210_phi_fu_7440_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15211_phi_fu_7452_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15212_phi_fu_7464_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15213_phi_fu_7476_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15214_phi_fu_7488_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15215_phi_fu_7500_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15216_phi_fu_7512_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15217_phi_fu_7524_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15218_phi_fu_7536_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15219_phi_fu_7548_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15220_phi_fu_7560_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15221_phi_fu_7572_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15222_phi_fu_7584_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15223_phi_fu_7596_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15224_phi_fu_7608_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15225_phi_fu_7620_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15226_phi_fu_7632_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15227_phi_fu_7644_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15228_phi_fu_7656_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15229_phi_fu_7668_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15230_phi_fu_7680_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15231_phi_fu_7692_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15232_phi_fu_7704_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15233_phi_fu_7716_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15234_phi_fu_7728_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15235_phi_fu_7740_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15236_phi_fu_7752_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15237_phi_fu_7764_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15238_phi_fu_7776_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15239_phi_fu_7788_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15240_phi_fu_7800_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15241_phi_fu_7812_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15242_phi_fu_7824_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15243_phi_fu_7836_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15244_phi_fu_7848_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15245_phi_fu_7860_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15246_phi_fu_7872_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15247_phi_fu_7884_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15248_phi_fu_7896_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15249_phi_fu_7908_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15250_phi_fu_7920_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15251_phi_fu_7932_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15252_phi_fu_7944_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15253_phi_fu_7956_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15254_phi_fu_7968_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15255_phi_fu_7980_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15256_phi_fu_7992_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15257_phi_fu_8004_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15258_phi_fu_8016_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15259_phi_fu_8028_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15260_phi_fu_8040_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15261_phi_fu_8052_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15262_phi_fu_8064_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15263_phi_fu_8076_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15264_phi_fu_8088_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15265_phi_fu_8100_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15266_phi_fu_8112_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15267_phi_fu_8124_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15268_phi_fu_8136_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15269_phi_fu_8148_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15270_phi_fu_8160_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15271_phi_fu_8172_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15272_phi_fu_8184_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15273_phi_fu_8196_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15274_phi_fu_8208_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15275_phi_fu_8220_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15276_phi_fu_8232_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15277_phi_fu_8244_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15278_phi_fu_8256_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15279_phi_fu_8268_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15280_phi_fu_8280_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15281_phi_fu_8292_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15282_phi_fu_8304_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15283_phi_fu_8316_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15284_phi_fu_8328_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15285_phi_fu_8340_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15286_phi_fu_8352_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15287_phi_fu_8364_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15288_phi_fu_8376_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15289_phi_fu_8388_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15290_phi_fu_8400_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15291_phi_fu_8412_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15292_phi_fu_8424_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15293_phi_fu_8436_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15294_phi_fu_8448_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15295_phi_fu_8460_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15296_phi_fu_8472_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15297_phi_fu_8484_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15298_phi_fu_8496_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15299_phi_fu_8508_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15300_phi_fu_8520_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15301_phi_fu_8532_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15302_phi_fu_8544_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15303_phi_fu_8556_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15304_phi_fu_8568_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15305_phi_fu_8580_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15306_phi_fu_8592_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15307_phi_fu_8604_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15308_phi_fu_8616_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15309_phi_fu_8628_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15310_phi_fu_8640_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15311_phi_fu_8652_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15312_phi_fu_8664_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15313_phi_fu_8676_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15314_phi_fu_8688_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15315_phi_fu_8700_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15316_phi_fu_8712_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15317_phi_fu_8724_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15318_phi_fu_8736_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_456_phi_fu_8748_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_457_phi_fu_8760_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_458_phi_fu_8772_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_459_phi_fu_8784_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_460_phi_fu_8796_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_461_phi_fu_8808_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_462_phi_fu_8820_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_463_phi_fu_8832_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_464_phi_fu_8844_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_465_phi_fu_8856_p4 | 9| 2| 16| 32| + |ap_phi_mux_w_index73_phi_fu_1352_p6 | 14| 3| 11| 33| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15041_reg_5408 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15042_reg_5420 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15043_reg_5432 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15044_reg_5444 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15045_reg_5456 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15046_reg_5468 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15047_reg_5480 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15048_reg_5492 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15049_reg_5504 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15050_reg_5516 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15051_reg_5528 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15052_reg_5540 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15053_reg_5552 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15054_reg_5564 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15055_reg_5576 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15056_reg_5588 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15057_reg_5600 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15058_reg_5612 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15059_reg_5624 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15060_reg_5636 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15061_reg_5648 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15062_reg_5660 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15063_reg_5672 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15064_reg_5684 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15065_reg_5696 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15066_reg_5708 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15067_reg_5720 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15068_reg_5732 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15069_reg_5744 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15070_reg_5756 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15071_reg_5768 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15072_reg_5780 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15073_reg_5792 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15074_reg_5804 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15075_reg_5816 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15076_reg_5828 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15077_reg_5840 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15078_reg_5852 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15079_reg_5864 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15080_reg_5876 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15081_reg_5888 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15082_reg_5900 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15083_reg_5912 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15084_reg_5924 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15085_reg_5936 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15086_reg_5948 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15087_reg_5960 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15088_reg_5972 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15089_reg_5984 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15090_reg_5996 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15091_reg_6008 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15092_reg_6020 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15093_reg_6032 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15094_reg_6044 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15095_reg_6056 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15096_reg_6068 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15097_reg_6080 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15098_reg_6092 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15099_reg_6104 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15100_reg_6116 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15101_reg_6128 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15102_reg_6140 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15103_reg_6152 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15104_reg_6164 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15105_reg_6176 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15106_reg_6188 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15107_reg_6200 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15108_reg_6212 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15109_reg_6224 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15110_reg_6236 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15111_reg_6248 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15112_reg_6260 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15113_reg_6272 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15114_reg_6284 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15115_reg_6296 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15116_reg_6308 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15117_reg_6320 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15118_reg_6332 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15119_reg_6344 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15120_reg_6356 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15121_reg_6368 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15122_reg_6380 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15123_reg_6392 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15124_reg_6404 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15125_reg_6416 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15126_reg_6428 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15127_reg_6440 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15128_reg_6452 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15129_reg_6464 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15130_reg_6476 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15131_reg_6488 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15132_reg_6500 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15133_reg_6512 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15134_reg_6524 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15135_reg_6536 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15136_reg_6548 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15137_reg_6560 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15138_reg_6572 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15139_reg_6584 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15140_reg_6596 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15141_reg_6608 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15142_reg_6620 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15143_reg_6632 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15144_reg_6644 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15145_reg_6656 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15146_reg_6668 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15147_reg_6680 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15148_reg_6692 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15149_reg_6704 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15150_reg_6716 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15151_reg_6728 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15152_reg_6740 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15153_reg_6752 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15154_reg_6764 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15155_reg_6776 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15156_reg_6788 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15157_reg_6800 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15158_reg_6812 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15159_reg_6824 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15160_reg_6836 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15161_reg_6848 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15162_reg_6860 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15163_reg_6872 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15164_reg_6884 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15165_reg_6896 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15166_reg_6908 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15167_reg_6920 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15168_reg_6932 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15169_reg_6944 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15170_reg_6956 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15171_reg_6968 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15172_reg_6980 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15173_reg_6992 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15174_reg_7004 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15175_reg_7016 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15176_reg_7028 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15177_reg_7040 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15178_reg_7052 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15179_reg_7064 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15180_reg_7076 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15181_reg_7088 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15182_reg_7100 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15183_reg_7112 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15184_reg_7124 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15185_reg_7136 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15186_reg_7148 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15187_reg_7160 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15188_reg_7172 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15189_reg_7184 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15190_reg_7196 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15191_reg_7208 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15192_reg_7220 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15193_reg_7232 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15194_reg_7244 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15195_reg_7256 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15196_reg_7268 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15197_reg_7280 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15198_reg_7292 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15199_reg_7304 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15200_reg_7316 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15201_reg_7328 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15202_reg_7340 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15203_reg_7352 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15204_reg_7364 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15205_reg_7376 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15206_reg_7388 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15207_reg_7400 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15208_reg_7412 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15209_reg_7424 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15210_reg_7436 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15211_reg_7448 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15212_reg_7460 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15213_reg_7472 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15214_reg_7484 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15215_reg_7496 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15216_reg_7508 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15217_reg_7520 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15218_reg_7532 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15219_reg_7544 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15220_reg_7556 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15221_reg_7568 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15222_reg_7580 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15223_reg_7592 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15224_reg_7604 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15225_reg_7616 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15226_reg_7628 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15227_reg_7640 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15228_reg_7652 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15229_reg_7664 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15230_reg_7676 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15231_reg_7688 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15232_reg_7700 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15233_reg_7712 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15234_reg_7724 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15235_reg_7736 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15236_reg_7748 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15237_reg_7760 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15238_reg_7772 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15239_reg_7784 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15240_reg_7796 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15241_reg_7808 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15242_reg_7820 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15243_reg_7832 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15244_reg_7844 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15245_reg_7856 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15246_reg_7868 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15247_reg_7880 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15248_reg_7892 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15249_reg_7904 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15250_reg_7916 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15251_reg_7928 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15252_reg_7940 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15253_reg_7952 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15254_reg_7964 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15255_reg_7976 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15256_reg_7988 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15257_reg_8000 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15258_reg_8012 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15259_reg_8024 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15260_reg_8036 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15261_reg_8048 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15262_reg_8060 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15263_reg_8072 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15264_reg_8084 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15265_reg_8096 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15266_reg_8108 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15267_reg_8120 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15268_reg_8132 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15269_reg_8144 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15270_reg_8156 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15271_reg_8168 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15272_reg_8180 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15273_reg_8192 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15274_reg_8204 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15275_reg_8216 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15276_reg_8228 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15277_reg_8240 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15278_reg_8252 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15279_reg_8264 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15280_reg_8276 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15281_reg_8288 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15282_reg_8300 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15283_reg_8312 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15284_reg_8324 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15285_reg_8336 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15286_reg_8348 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15287_reg_8360 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15288_reg_8372 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15289_reg_8384 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15290_reg_8396 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15291_reg_8408 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15292_reg_8420 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15293_reg_8432 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15294_reg_8444 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15295_reg_8456 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15296_reg_8468 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15297_reg_8480 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15298_reg_8492 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15299_reg_8504 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15300_reg_8516 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15301_reg_8528 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15302_reg_8540 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15303_reg_8552 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15304_reg_8564 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15305_reg_8576 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15306_reg_8588 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15307_reg_8600 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15308_reg_8612 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15309_reg_8624 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15310_reg_8636 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15311_reg_8648 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15312_reg_8660 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15313_reg_8672 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15314_reg_8684 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15315_reg_8696 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15316_reg_8708 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15317_reg_8720 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15318_reg_8732 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_456_reg_8744 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_457_reg_8756 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_458_reg_8768 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_459_reg_8780 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_460_reg_8792 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_461_reg_8804 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_462_reg_8816 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_463_reg_8828 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_464_reg_8840 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_465_reg_8852 | 9| 2| 16| 32| + |in_index74_reg_5394 | 9| 2| 32| 64| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15041_reg_5408 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15042_reg_5420 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15043_reg_5432 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15044_reg_5444 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15045_reg_5456 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15046_reg_5468 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15047_reg_5480 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15048_reg_5492 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15049_reg_5504 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15050_reg_5516 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15051_reg_5528 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15052_reg_5540 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15053_reg_5552 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15054_reg_5564 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15055_reg_5576 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15056_reg_5588 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15057_reg_5600 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15058_reg_5612 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15059_reg_5624 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15060_reg_5636 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15061_reg_5648 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15062_reg_5660 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15063_reg_5672 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15064_reg_5684 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15065_reg_5696 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15066_reg_5708 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15067_reg_5720 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15068_reg_5732 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15069_reg_5744 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15070_reg_5756 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15071_reg_5768 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15072_reg_5780 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15073_reg_5792 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15074_reg_5804 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15075_reg_5816 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15076_reg_5828 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15077_reg_5840 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15078_reg_5852 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15079_reg_5864 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15080_reg_5876 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15081_reg_5888 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15082_reg_5900 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15083_reg_5912 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15084_reg_5924 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15085_reg_5936 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15086_reg_5948 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15087_reg_5960 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15088_reg_5972 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15089_reg_5984 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15090_reg_5996 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15091_reg_6008 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15092_reg_6020 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15093_reg_6032 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15094_reg_6044 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15095_reg_6056 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15096_reg_6068 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15097_reg_6080 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15098_reg_6092 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15099_reg_6104 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15100_reg_6116 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15101_reg_6128 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15102_reg_6140 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15103_reg_6152 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15104_reg_6164 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15105_reg_6176 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15106_reg_6188 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15107_reg_6200 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15108_reg_6212 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15109_reg_6224 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15110_reg_6236 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15111_reg_6248 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15112_reg_6260 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15113_reg_6272 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15114_reg_6284 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15115_reg_6296 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15116_reg_6308 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15117_reg_6320 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15118_reg_6332 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15119_reg_6344 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15120_reg_6356 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15121_reg_6368 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15122_reg_6380 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15123_reg_6392 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15124_reg_6404 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15125_reg_6416 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15126_reg_6428 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15127_reg_6440 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15128_reg_6452 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15129_reg_6464 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15130_reg_6476 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15131_reg_6488 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15132_reg_6500 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15133_reg_6512 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15134_reg_6524 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15135_reg_6536 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15136_reg_6548 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15137_reg_6560 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15138_reg_6572 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15139_reg_6584 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15140_reg_6596 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15141_reg_6608 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15142_reg_6620 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15143_reg_6632 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15144_reg_6644 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15145_reg_6656 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15146_reg_6668 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15147_reg_6680 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15148_reg_6692 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15149_reg_6704 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15150_reg_6716 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15151_reg_6728 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15152_reg_6740 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15153_reg_6752 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15154_reg_6764 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15155_reg_6776 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15156_reg_6788 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15157_reg_6800 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15158_reg_6812 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15159_reg_6824 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15160_reg_6836 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15161_reg_6848 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15162_reg_6860 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15163_reg_6872 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15164_reg_6884 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15165_reg_6896 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15166_reg_6908 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15167_reg_6920 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15168_reg_6932 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15169_reg_6944 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15170_reg_6956 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15171_reg_6968 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15172_reg_6980 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15173_reg_6992 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15174_reg_7004 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15175_reg_7016 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15176_reg_7028 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15177_reg_7040 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15178_reg_7052 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15179_reg_7064 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15180_reg_7076 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15181_reg_7088 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15182_reg_7100 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15183_reg_7112 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15184_reg_7124 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15185_reg_7136 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15186_reg_7148 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15187_reg_7160 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15188_reg_7172 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15189_reg_7184 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15190_reg_7196 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15191_reg_7208 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15192_reg_7220 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15193_reg_7232 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15194_reg_7244 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15195_reg_7256 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15196_reg_7268 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15197_reg_7280 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15198_reg_7292 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15199_reg_7304 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15200_reg_7316 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15201_reg_7328 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15202_reg_7340 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15203_reg_7352 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15204_reg_7364 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15205_reg_7376 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15206_reg_7388 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15207_reg_7400 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15208_reg_7412 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15209_reg_7424 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15210_reg_7436 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15211_reg_7448 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15212_reg_7460 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15213_reg_7472 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15214_reg_7484 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15215_reg_7496 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15216_reg_7508 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15217_reg_7520 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15218_reg_7532 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15219_reg_7544 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15220_reg_7556 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15221_reg_7568 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15222_reg_7580 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15223_reg_7592 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15224_reg_7604 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15225_reg_7616 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15226_reg_7628 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15227_reg_7640 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15228_reg_7652 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15229_reg_7664 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15230_reg_7676 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15231_reg_7688 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15232_reg_7700 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15233_reg_7712 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15234_reg_7724 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15235_reg_7736 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15236_reg_7748 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15237_reg_7760 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15238_reg_7772 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15239_reg_7784 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15240_reg_7796 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15241_reg_7808 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15242_reg_7820 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15243_reg_7832 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15244_reg_7844 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15245_reg_7856 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15246_reg_7868 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15247_reg_7880 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15248_reg_7892 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15249_reg_7904 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15250_reg_7916 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15251_reg_7928 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15252_reg_7940 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15253_reg_7952 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15254_reg_7964 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15255_reg_7976 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15256_reg_7988 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15257_reg_8000 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15258_reg_8012 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15259_reg_8024 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15260_reg_8036 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15261_reg_8048 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15262_reg_8060 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15263_reg_8072 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15264_reg_8084 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15265_reg_8096 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15266_reg_8108 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15267_reg_8120 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15268_reg_8132 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15269_reg_8144 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15270_reg_8156 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15271_reg_8168 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15272_reg_8180 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15273_reg_8192 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15274_reg_8204 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15275_reg_8216 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15276_reg_8228 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15277_reg_8240 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15278_reg_8252 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15279_reg_8264 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15280_reg_8276 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15281_reg_8288 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15282_reg_8300 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15283_reg_8312 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15284_reg_8324 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15285_reg_8336 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15286_reg_8348 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15287_reg_8360 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15288_reg_8372 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15289_reg_8384 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15290_reg_8396 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15291_reg_8408 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15292_reg_8420 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15293_reg_8432 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15294_reg_8444 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15295_reg_8456 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15296_reg_8468 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15297_reg_8480 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15298_reg_8492 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15299_reg_8504 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15300_reg_8516 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15301_reg_8528 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15302_reg_8540 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15303_reg_8552 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15304_reg_8564 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15305_reg_8576 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15306_reg_8588 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15307_reg_8600 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15308_reg_8612 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15309_reg_8624 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15310_reg_8636 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15311_reg_8648 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15312_reg_8660 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15313_reg_8672 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15314_reg_8684 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15315_reg_8696 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15316_reg_8708 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15317_reg_8720 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15318_reg_8732 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_456_reg_8744 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_457_reg_8756 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_458_reg_8768 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_459_reg_8780 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_460_reg_8792 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_461_reg_8804 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_462_reg_8816 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_463_reg_8828 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_464_reg_8840 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_465_reg_8852 | 9| 2| 16| 32| + |w_index73_reg_1349 | 9| 2| 11| 22| + +-----------------------------------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + |Total |8590| 1905|16601| 34590| + +-----------------------------------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + + * Register: + +-----------------------------------------------------------------------------------------------------------------------+-----+----+-----+-----------+ + | Name | FF | LUT| Bits| Const Bits| + +-----------------------------------------------------------------------------------------------------------------------+-----+----+-----+-----------+ + |a_reg_14255 | 16| 0| 16| 0| + |acc72_reg_8864 | 42| 0| 42| 0| + |acc_126_reg_14340 | 42| 0| 42| 0| + |acc_127_reg_14334 | 42| 0| 42| 0| + |acc_128_reg_14328 | 42| 0| 42| 0| + |acc_129_reg_14370 | 42| 0| 42| 0| + |acc_130_reg_14364 | 42| 0| 42| 0| + |acc_131_reg_14358 | 42| 0| 42| 0| + |acc_132_reg_14352 | 42| 0| 42| 0| + |acc_133_reg_14394 | 42| 0| 42| 0| + |acc_134_reg_14388 | 42| 0| 42| 0| + |acc_135_reg_14382 | 42| 0| 42| 0| + |acc_136_reg_14376 | 42| 0| 42| 0| + |acc_138_reg_14422 | 42| 0| 42| 0| + |acc_139_reg_14416 | 42| 0| 42| 0| + |acc_140_reg_14410 | 42| 0| 42| 0| + |acc_141_reg_14446 | 42| 0| 42| 0| + |acc_142_reg_14440 | 42| 0| 42| 0| + |acc_143_reg_14434 | 42| 0| 42| 0| + |acc_144_reg_14428 | 42| 0| 42| 0| + |acc_145_reg_14470 | 42| 0| 42| 0| + |acc_146_reg_14464 | 42| 0| 42| 0| + |acc_147_reg_14458 | 42| 0| 42| 0| + |acc_148_reg_14452 | 42| 0| 42| 0| + |acc_149_reg_14494 | 42| 0| 42| 0| + |acc_150_reg_14488 | 42| 0| 42| 0| + |acc_151_reg_14482 | 42| 0| 42| 0| + |acc_152_reg_14476 | 42| 0| 42| 0| + |acc_153_reg_14524 | 42| 0| 42| 0| + |acc_154_reg_14518 | 42| 0| 42| 0| + |acc_16069_reg_8878 | 42| 0| 42| 0| + |acc_16167_reg_8892 | 42| 0| 42| 0| + |acc_16265_reg_8906 | 42| 0| 42| 0| + |acc_16364_reg_8920 | 42| 0| 42| 0| + |acc_16461_reg_8934 | 42| 0| 42| 0| + |acc_164_reg_14405 | 42| 0| 42| 0| + |acc_16559_reg_8948 | 42| 0| 42| 0| + |acc_16657_reg_8962 | 42| 0| 42| 0| + |acc_16756_reg_8976 | 42| 0| 42| 0| + |acc_16853_reg_8990 | 42| 0| 42| 0| + |acc_16951_reg_9004 | 42| 0| 42| 0| + |acc_17049_reg_9018 | 42| 0| 42| 0| + |acc_17148_reg_9032 | 42| 0| 42| 0| + |acc_17245_reg_9047 | 42| 0| 42| 0| + |acc_17343_reg_9061 | 42| 0| 42| 0| + |acc_173_reg_14512 | 42| 0| 42| 0| + |acc_17441_reg_9075 | 42| 0| 42| 0| + |acc_17540_reg_9089 | 42| 0| 42| 0| + |acc_17637_reg_9103 | 42| 0| 42| 0| + |acc_17735_reg_9117 | 42| 0| 42| 0| + |acc_17833_reg_9131 | 42| 0| 42| 0| + |acc_17932_reg_9145 | 42| 0| 42| 0| + |acc_18029_reg_9159 | 42| 0| 42| 0| + |acc_18127_reg_9173 | 42| 0| 42| 0| + |acc_18225_reg_9187 | 42| 0| 42| 0| + |acc_18324_reg_9201 | 42| 0| 42| 0| + |acc_18421_reg_9215 | 42| 0| 42| 0| + |acc_18519_reg_9229 | 42| 0| 42| 0| + |acc_18617_reg_9243 | 42| 0| 42| 0| + |acc_18715_reg_9257 | 42| 0| 42| 0| + |acc_18813_reg_9271 | 42| 0| 42| 0| + |acc_18912_reg_9285 | 42| 0| 42| 0| + |acc_19010_reg_9300 | 42| 0| 42| 0| + |acc_reg_14346 | 42| 0| 42| 0| + |ap_CS_fsm | 1| 0| 1| 0| + |ap_done_reg | 1| 0| 1| 0| + |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| + |ap_enable_reg_pp0_iter2 | 1| 0| 1| 0| + |ap_enable_reg_pp0_iter3 | 1| 0| 1| 0| + |ap_loop_exit_ready_pp0_iter1_reg | 1| 0| 1| 0| + |ap_loop_exit_ready_pp0_iter2_reg | 1| 0| 1| 0| + |ap_loop_exit_ready_pp0_iter3_reg | 1| 0| 1| 0| + |ap_loop_init_pp0_iter1_reg | 1| 0| 1| 0| + |ap_loop_init_pp0_iter2_reg | 1| 0| 1| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15041_reg_5408 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15042_reg_5420 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15043_reg_5432 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15044_reg_5444 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15045_reg_5456 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15046_reg_5468 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15047_reg_5480 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15048_reg_5492 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15049_reg_5504 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15050_reg_5516 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15051_reg_5528 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15052_reg_5540 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15053_reg_5552 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15054_reg_5564 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15055_reg_5576 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15056_reg_5588 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15057_reg_5600 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15058_reg_5612 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15059_reg_5624 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15060_reg_5636 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15061_reg_5648 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15062_reg_5660 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15063_reg_5672 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15064_reg_5684 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15065_reg_5696 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15066_reg_5708 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15067_reg_5720 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15068_reg_5732 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15069_reg_5744 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15070_reg_5756 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15071_reg_5768 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15072_reg_5780 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15073_reg_5792 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15074_reg_5804 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15075_reg_5816 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15076_reg_5828 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15077_reg_5840 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15078_reg_5852 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15079_reg_5864 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15080_reg_5876 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15081_reg_5888 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15082_reg_5900 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15083_reg_5912 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15084_reg_5924 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15085_reg_5936 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15086_reg_5948 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15087_reg_5960 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15088_reg_5972 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15089_reg_5984 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15090_reg_5996 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15091_reg_6008 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15092_reg_6020 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15093_reg_6032 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15094_reg_6044 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15095_reg_6056 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15096_reg_6068 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15097_reg_6080 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15098_reg_6092 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15099_reg_6104 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15100_reg_6116 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15101_reg_6128 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15102_reg_6140 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15103_reg_6152 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15104_reg_6164 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15105_reg_6176 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15106_reg_6188 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15107_reg_6200 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15108_reg_6212 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15109_reg_6224 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15110_reg_6236 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15111_reg_6248 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15112_reg_6260 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15113_reg_6272 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15114_reg_6284 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15115_reg_6296 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15116_reg_6308 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15117_reg_6320 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15118_reg_6332 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15119_reg_6344 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15120_reg_6356 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15121_reg_6368 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15122_reg_6380 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15123_reg_6392 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15124_reg_6404 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15125_reg_6416 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15126_reg_6428 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15127_reg_6440 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15128_reg_6452 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15129_reg_6464 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15130_reg_6476 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15131_reg_6488 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15132_reg_6500 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15133_reg_6512 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15134_reg_6524 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15135_reg_6536 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15136_reg_6548 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15137_reg_6560 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15138_reg_6572 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15139_reg_6584 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15140_reg_6596 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15141_reg_6608 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15142_reg_6620 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15143_reg_6632 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15144_reg_6644 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15145_reg_6656 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15146_reg_6668 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15147_reg_6680 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15148_reg_6692 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15149_reg_6704 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15150_reg_6716 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15151_reg_6728 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15152_reg_6740 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15153_reg_6752 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15154_reg_6764 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15155_reg_6776 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15156_reg_6788 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15157_reg_6800 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15158_reg_6812 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15159_reg_6824 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15160_reg_6836 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15161_reg_6848 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15162_reg_6860 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15163_reg_6872 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15164_reg_6884 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15165_reg_6896 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15166_reg_6908 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15167_reg_6920 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15168_reg_6932 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15169_reg_6944 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15170_reg_6956 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15171_reg_6968 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15172_reg_6980 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15173_reg_6992 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15174_reg_7004 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15175_reg_7016 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15176_reg_7028 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15177_reg_7040 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15178_reg_7052 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15179_reg_7064 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15180_reg_7076 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15181_reg_7088 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15182_reg_7100 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15183_reg_7112 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15184_reg_7124 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15185_reg_7136 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15186_reg_7148 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15187_reg_7160 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15188_reg_7172 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15189_reg_7184 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15190_reg_7196 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15191_reg_7208 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15192_reg_7220 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15193_reg_7232 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15194_reg_7244 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15195_reg_7256 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15196_reg_7268 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15197_reg_7280 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15198_reg_7292 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15199_reg_7304 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15200_reg_7316 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15201_reg_7328 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15202_reg_7340 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15203_reg_7352 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15204_reg_7364 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15205_reg_7376 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15206_reg_7388 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15207_reg_7400 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15208_reg_7412 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15209_reg_7424 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15210_reg_7436 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15211_reg_7448 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15212_reg_7460 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15213_reg_7472 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15214_reg_7484 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15215_reg_7496 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15216_reg_7508 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15217_reg_7520 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15218_reg_7532 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15219_reg_7544 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15220_reg_7556 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15221_reg_7568 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15222_reg_7580 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15223_reg_7592 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15224_reg_7604 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15225_reg_7616 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15226_reg_7628 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15227_reg_7640 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15228_reg_7652 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15229_reg_7664 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15230_reg_7676 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15231_reg_7688 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15232_reg_7700 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15233_reg_7712 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15234_reg_7724 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15235_reg_7736 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15236_reg_7748 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15237_reg_7760 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15238_reg_7772 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15239_reg_7784 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15240_reg_7796 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15241_reg_7808 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15242_reg_7820 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15243_reg_7832 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15244_reg_7844 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15245_reg_7856 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15246_reg_7868 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15247_reg_7880 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15248_reg_7892 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15249_reg_7904 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15250_reg_7916 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15251_reg_7928 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15252_reg_7940 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15253_reg_7952 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15254_reg_7964 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15255_reg_7976 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15256_reg_7988 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15257_reg_8000 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15258_reg_8012 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15259_reg_8024 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15260_reg_8036 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15261_reg_8048 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15262_reg_8060 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15263_reg_8072 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15264_reg_8084 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15265_reg_8096 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15266_reg_8108 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15267_reg_8120 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15268_reg_8132 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15269_reg_8144 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15270_reg_8156 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15271_reg_8168 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15272_reg_8180 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15273_reg_8192 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15274_reg_8204 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15275_reg_8216 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15276_reg_8228 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15277_reg_8240 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15278_reg_8252 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15279_reg_8264 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15280_reg_8276 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15281_reg_8288 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15282_reg_8300 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15283_reg_8312 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15284_reg_8324 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15285_reg_8336 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15286_reg_8348 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15287_reg_8360 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15288_reg_8372 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15289_reg_8384 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15290_reg_8396 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15291_reg_8408 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15292_reg_8420 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15293_reg_8432 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15294_reg_8444 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15295_reg_8456 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15296_reg_8468 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15297_reg_8480 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15298_reg_8492 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15299_reg_8504 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15300_reg_8516 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15301_reg_8528 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15302_reg_8540 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15303_reg_8552 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15304_reg_8564 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15305_reg_8576 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15306_reg_8588 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15307_reg_8600 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15308_reg_8612 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15309_reg_8624 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15310_reg_8636 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15311_reg_8648 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15312_reg_8660 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15313_reg_8672 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15314_reg_8684 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15315_reg_8696 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15316_reg_8708 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15317_reg_8720 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15318_reg_8732 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_456_reg_8744 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_457_reg_8756 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_458_reg_8768 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_459_reg_8780 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_460_reg_8792 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_461_reg_8804 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_462_reg_8816 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_463_reg_8828 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_464_reg_8840 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_465_reg_8852 | 16| 0| 16| 0| + |do_init_reg_1334 | 1| 0| 1| 0| + |icmp_ln135_reg_14235 | 1| 0| 1| 0| + |icmp_ln144_30_reg_14313 | 1| 0| 1| 0| + |icmp_ln144_31_reg_14321 | 1| 0| 1| 0| + |icmp_ln144_35_reg_14400 | 1| 0| 1| 0| + |icmp_ln144_38_reg_14500 | 1| 0| 1| 0| + |icmp_ln144_40_reg_14506 | 1| 0| 1| 0| + |icmp_ln144_reg_14306 | 1| 0| 1| 0| + |in_index74_reg_5394 | 32| 0| 32| 0| + |in_index_reg_14301 | 32| 0| 32| 0| + |out_index_reg_14239 | 2| 0| 2| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15041_reg_5408 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15042_reg_5420 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15043_reg_5432 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15044_reg_5444 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15045_reg_5456 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15046_reg_5468 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15047_reg_5480 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15048_reg_5492 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15049_reg_5504 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15050_reg_5516 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15051_reg_5528 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15052_reg_5540 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15053_reg_5552 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15054_reg_5564 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15055_reg_5576 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15056_reg_5588 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15057_reg_5600 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15058_reg_5612 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15059_reg_5624 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15060_reg_5636 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15061_reg_5648 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15062_reg_5660 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15063_reg_5672 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15064_reg_5684 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15065_reg_5696 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15066_reg_5708 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15067_reg_5720 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15068_reg_5732 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15069_reg_5744 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15070_reg_5756 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15071_reg_5768 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15072_reg_5780 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15073_reg_5792 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15074_reg_5804 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15075_reg_5816 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15076_reg_5828 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15077_reg_5840 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15078_reg_5852 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15079_reg_5864 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15080_reg_5876 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15081_reg_5888 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15082_reg_5900 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15083_reg_5912 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15084_reg_5924 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15085_reg_5936 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15086_reg_5948 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15087_reg_5960 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15088_reg_5972 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15089_reg_5984 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15090_reg_5996 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15091_reg_6008 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15092_reg_6020 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15093_reg_6032 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15094_reg_6044 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15095_reg_6056 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15096_reg_6068 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15097_reg_6080 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15098_reg_6092 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15099_reg_6104 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15100_reg_6116 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15101_reg_6128 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15102_reg_6140 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15103_reg_6152 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15104_reg_6164 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15105_reg_6176 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15106_reg_6188 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15107_reg_6200 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15108_reg_6212 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15109_reg_6224 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15110_reg_6236 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15111_reg_6248 | 16| 0| 16| 0| + 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|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15144_reg_6644 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15145_reg_6656 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15146_reg_6668 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15147_reg_6680 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15148_reg_6692 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15149_reg_6704 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15150_reg_6716 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15151_reg_6728 | 16| 0| 16| 0| + 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|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15184_reg_7124 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15185_reg_7136 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15186_reg_7148 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15187_reg_7160 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15188_reg_7172 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15189_reg_7184 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15190_reg_7196 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15191_reg_7208 | 16| 0| 16| 0| + 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|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15208_reg_7412 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15209_reg_7424 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15210_reg_7436 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15211_reg_7448 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15212_reg_7460 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15213_reg_7472 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15214_reg_7484 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15215_reg_7496 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15216_reg_7508 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15217_reg_7520 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15218_reg_7532 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15219_reg_7544 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15220_reg_7556 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15221_reg_7568 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15222_reg_7580 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15223_reg_7592 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15224_reg_7604 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15225_reg_7616 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15226_reg_7628 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15227_reg_7640 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15228_reg_7652 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15229_reg_7664 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15230_reg_7676 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15231_reg_7688 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15232_reg_7700 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15233_reg_7712 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15234_reg_7724 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15235_reg_7736 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15236_reg_7748 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15237_reg_7760 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15238_reg_7772 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15239_reg_7784 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15240_reg_7796 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15241_reg_7808 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15242_reg_7820 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15243_reg_7832 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15244_reg_7844 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15245_reg_7856 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15246_reg_7868 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15247_reg_7880 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15248_reg_7892 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15249_reg_7904 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15250_reg_7916 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15251_reg_7928 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15252_reg_7940 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15253_reg_7952 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15254_reg_7964 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15255_reg_7976 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15256_reg_7988 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15257_reg_8000 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15258_reg_8012 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15259_reg_8024 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15260_reg_8036 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15261_reg_8048 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15262_reg_8060 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15263_reg_8072 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15264_reg_8084 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15265_reg_8096 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15266_reg_8108 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15267_reg_8120 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15268_reg_8132 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15269_reg_8144 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15270_reg_8156 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15271_reg_8168 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15272_reg_8180 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15273_reg_8192 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15274_reg_8204 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15275_reg_8216 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15276_reg_8228 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15277_reg_8240 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15278_reg_8252 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15279_reg_8264 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15280_reg_8276 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15281_reg_8288 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15282_reg_8300 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15283_reg_8312 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15284_reg_8324 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15285_reg_8336 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15286_reg_8348 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15287_reg_8360 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15288_reg_8372 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15289_reg_8384 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15290_reg_8396 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15291_reg_8408 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15292_reg_8420 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15293_reg_8432 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15294_reg_8444 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15295_reg_8456 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15296_reg_8468 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15297_reg_8480 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15298_reg_8492 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15299_reg_8504 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15300_reg_8516 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15301_reg_8528 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15302_reg_8540 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15303_reg_8552 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15304_reg_8564 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15305_reg_8576 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15306_reg_8588 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15307_reg_8600 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15308_reg_8612 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15309_reg_8624 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15310_reg_8636 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15311_reg_8648 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15312_reg_8660 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15313_reg_8672 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15314_reg_8684 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15315_reg_8696 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15316_reg_8708 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15317_reg_8720 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_15318_reg_8732 | 16| 0| 16| 0| + |tmp_reg_14296 | 11| 0| 11| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_456_reg_8744 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_457_reg_8756 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_458_reg_8768 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_459_reg_8780 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_460_reg_8792 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_461_reg_8804 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_462_reg_8816 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_463_reg_8828 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_464_reg_8840 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_465_reg_8852 | 16| 0| 16| 0| + |w_75_reg_14266 | 16| 0| 16| 0| + |w_76_reg_14271 | 16| 0| 16| 0| + |w_77_reg_14276 | 16| 0| 16| 0| + |w_78_reg_14281 | 16| 0| 16| 0| + |w_79_reg_14286 | 16| 0| 16| 0| + |w_80_reg_14291 | 16| 0| 16| 0| + |w_index73_reg_1349 | 11| 0| 11| 0| + |w_index_reg_14230 | 11| 0| 11| 0| + |w_reg_14261 | 16| 0| 16| 0| + |icmp_ln135_reg_14235 | 64| 32| 1| 0| + +-----------------------------------------------------------------------------------------------------------------------+-----+----+-----+-----------+ + |Total |12171| 32|12108| 0| + +-----------------------------------------------------------------------------------------------------------------------+-----+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++----------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_rst | in| 1| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_start | in| 1| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_done | out| 1| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_idle | out| 1| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_ready | out| 1| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_0 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_1 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_2 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_3 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_4 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_5 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_6 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_7 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_8 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_9 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_10 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_11 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_12 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_13 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_14 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_15 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_16 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_17 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_18 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_19 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_20 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_21 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_22 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_23 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_24 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_25 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_26 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_27 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_28 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_29 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_30 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|ap_return_31 | out| 42| ap_ctrl_hs| dense_resource_rf_gt_nin_rem0| return value| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_79 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_79| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_78 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_78| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_77 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_77| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_76 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_76| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_75 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_75| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_74 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_74| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_73 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_73| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_72 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_72| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_71 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_71| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_70 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_70| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5096 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5096| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5108 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5108| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5120 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5120| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5132 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5132| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5145 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5145| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5157 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5157| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5169 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5169| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5181 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5181| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5193 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5193| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5205 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5205| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5217 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5217| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5229 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5229| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5241 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5241| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5253 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5253| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5266 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5266| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5278 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5278| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5290 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5290| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5302 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5302| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5314 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5314| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5324 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5324| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5325 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5325| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5326 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5326| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5327 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5327| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5328 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5328| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5329 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5329| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5330 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5330| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5332 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5332| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5333 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5333| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5334 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5334| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5335 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5335| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5336 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5336| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5337 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5337| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5338 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5338| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5339 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5339| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5340 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5340| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5341 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5341| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5343 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5343| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5344 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5344| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5345 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5345| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5346 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5346| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5347 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5347| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5348 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5348| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5349 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5349| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5350 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5350| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5351 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5351| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5352 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5352| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5354 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5354| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5355 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5355| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5356 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5356| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5357 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5357| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5358 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5358| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5359 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5359| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5360 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5360| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5361 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5361| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5362 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5362| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5363 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5363| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5369| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5370 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5370| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5371 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5371| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5372 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5372| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5373 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5373| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5379| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5380 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5380| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5381 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5381| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5382 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5382| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5383 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5383| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5389| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5390 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5390| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5391 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5391| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5392 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5392| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5393 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5393| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5399| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5400 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5400| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5401 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5401| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5097 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5097| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5098 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5098| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5104| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5105 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5105| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5106 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5106| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5107 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5107| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5109 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5109| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5115| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5116 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5116| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5117 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5117| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5118 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5118| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5119 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5119| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5126| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5127 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5127| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5128 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5128| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5129 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5129| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5130 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5130| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5137| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5138 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5138| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5139 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5139| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5140 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5140| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5141 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5141| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5148| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5149 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5149| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5150 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5150| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5151 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5151| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5152 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5152| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5159| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5160 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5160| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5161 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5161| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5162 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5162| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5163 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5163| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5170| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5171 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5171| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5172 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5172| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5173 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5173| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5174 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5174| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5180| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5182 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5182| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5183 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5183| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5184 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5184| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5185 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5185| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5191| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5192 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5192| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5194 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5194| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5195 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5195| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5196 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5196| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5202| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5203 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5203| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5204 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5204| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5206 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5206| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5207 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5207| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5213| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5214 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5214| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5215 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5215| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5216 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5216| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5218 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5218| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5224| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5225 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5225| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5226 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5226| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5227 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5227| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5228 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5228| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5235| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5236 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5236| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5237 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5237| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5238 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5238| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5239 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5239| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5246| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5247 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5247| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5248 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5248| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5249 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5249| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5250 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5250| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5257| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5258 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5258| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5259 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5259| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5260 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5260| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5261 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5261| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5268| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5269 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5269| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5270 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5270| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5271 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5271| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5272 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5272| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5279| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5280 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5280| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5281 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5281| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5282 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5282| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5283 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5283| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5289| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5291 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5291| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5292 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5292| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5293 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5293| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5294 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5294| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5300| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5301 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5301| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5303 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5303| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5304 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5304| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5305 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5305| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5311| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5312 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5312| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5313 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5313| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5315 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5315| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5316 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5316| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5317 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5317| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5318 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5318| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5319 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5319| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5321 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5321| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5322 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5322| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5323 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5323| pointer| ++----------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s_csynth.xml b/myproject_prj/solution1/syn/report/dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..b315b512e675267f1335806d6afe8b6f05f34d05 --- /dev/null +++ b/myproject_prj/solution1/syn/report/dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s_csynth.xml @@ -0,0 +1,246 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s +4.00 +1.35 +vivado + + + +loop rewind stp(delay=0 clock cycles(s)) + +ns +2.533 + + +clock cycles +8 +8 +9 +32.000 ns +32.000 ns +36.000 ns +8 +8 + + + +2.65 +8 +8 +32 +1 +2 + + + + + +- +- +firmware/nnet_utils/nnet_dense_resource.h:46 + + +ReuseLoop +- +- +firmware/nnet_utils/nnet_dense_resource.h:46 + + + + + + + +1 +229 +418 +0 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +dense_resource_rf_leq_nin<ap_fixed,ap_fixed<36,16,5,3,0>,config58_mult> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +dense_resource_rf_leq_nin<ap_fixed,ap_fixed<36,16,5,3,0>,config58_mult> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +dense_resource_rf_leq_nin<ap_fixed,ap_fixed<36,16,5,3,0>,config58_mult> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_done +dense_resource_rf_leq_nin<ap_fixed,ap_fixed<36,16,5,3,0>,config58_mult> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_idle +dense_resource_rf_leq_nin<ap_fixed,ap_fixed<36,16,5,3,0>,config58_mult> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +dense_resource_rf_leq_nin<ap_fixed,ap_fixed<36,16,5,3,0>,config58_mult> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_return +dense_resource_rf_leq_nin<ap_fixed,ap_fixed<36,16,5,3,0>,config58_mult> +return value + +ap_ctrl_hs + +out +30 +data + + +data_0_val +data_0_val +scalar + +ap_none + +in +16 +data + + +data_1_val +data_1_val +scalar + +ap_none + +in +16 +data + + +data_2_val +data_2_val +scalar + +ap_none + +in +16 +data + + +data_3_val +data_3_val +scalar + +ap_none + +in +16 +data + + +data_4_val +data_4_val +scalar + +ap_none + +in +16 +data + + +data_5_val +data_5_val +scalar + +ap_none + +in +16 +data + + +data_6_val +data_6_val +scalar + +ap_none + +in +16 +data + + +data_7_val +data_7_val +scalar + +ap_none + +in +16 +data + + + + diff --git a/myproject_prj/solution1/syn/report/dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_csynth.rpt b/myproject_prj/solution1/syn/report/dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..81e21d1672fdb2809d9501fe7dad29b1d3a29916 --- /dev/null +++ b/myproject_prj/solution1/syn/report/dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_csynth.rpt @@ -0,0 +1,1527 @@ + + +================================================================ +== Vitis HLS Report for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s' +================================================================ +* Date: Sun Apr 5 21:50:23 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 2.533 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+----------+----------+-----+-----+------------------------------------------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | min | max | min | max | min | max | Type | + +---------+---------+----------+----------+-----+-----+------------------------------------------+ + | 217| 218| 0.868 us| 0.872 us| 216| 216| loop rewind stp(delay=0 clock cycles(s))| + +---------+---------+----------+----------+-----+-----+------------------------------------------+ + + + Detail: + * Instance: + N/A + + * Loop: + +-------------+---------+---------+----------+-----------+-----------+------+----------+ + | | Latency (cycles) | Iteration| Initiation Interval | Trip | | + | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| + +-------------+---------+---------+----------+-----------+-----------+------+----------+ + |- ReuseLoop | 217| 217| 3| 1| 1| 216| yes| + +-------------+---------+---------+----------+-----------+-----------+------+----------+ + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| 8| -| -| -| +|Expression | -| -| 0| 36| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| 0| 1146| -| +|Memory | 4| -| 0| 0| -| +|Multiplexer | -| -| 0| 6103| -| +|Register | -| -| 7711| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 4| 8| 7711| 7285| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | ~0| ~0| ~0| 1| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | ~0| ~0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + +------------------------------+------------------------+---------+----+---+------+-----+ + | Instance | Module | BRAM_18K| DSP| FF| LUT | URAM| + +------------------------------+------------------------+---------+----+---+------+-----+ + |sparsemux_433_8_16_1_1_U8342 |sparsemux_433_8_16_1_1 | 0| 0| 0| 1146| 0| + +------------------------------+------------------------+---------+----+---+------+-----+ + |Total | | 0| 0| 0| 1146| 0| + +------------------------------+------------------------+---------+----+---+------+-----+ + + * DSP: + +-------------------------------------+-------------------------------+--------------+ + | Instance | Module | Expression | + +-------------------------------------+-------------------------------+--------------+ + |mac_muladd_16s_10s_33s_33_1_1_U8350 |mac_muladd_16s_10s_33s_33_1_1 | i0 * i1 + i2| + |mac_muladd_16s_16s_39s_39_1_1_U8343 |mac_muladd_16s_16s_39s_39_1_1 | i0 * i1 + i2| + |mac_muladd_16s_16s_39s_39_1_1_U8344 |mac_muladd_16s_16s_39s_39_1_1 | i0 * i1 + i2| + |mac_muladd_16s_16s_39s_39_1_1_U8345 |mac_muladd_16s_16s_39s_39_1_1 | i0 * i1 + i2| + |mac_muladd_16s_16s_39s_39_1_1_U8346 |mac_muladd_16s_16s_39s_39_1_1 | i0 * i1 + i2| + |mac_muladd_16s_16s_39s_39_1_1_U8347 |mac_muladd_16s_16s_39s_39_1_1 | i0 * i1 + i2| + |mac_muladd_16s_16s_39s_39_1_1_U8348 |mac_muladd_16s_16s_39s_39_1_1 | i0 * i1 + i2| + |mac_muladd_16s_16s_39s_39_1_1_U8349 |mac_muladd_16s_16s_39s_39_1_1 | i0 * i1 + i2| + +-------------------------------------+-------------------------------+--------------+ + + * Memory: + +-------+----------------------------------------------------------------------------------+---------+---+----+-----+------+-----+------+-------------+ + | Memory| Module | BRAM_18K| FF| LUT| URAM| Words| Bits| Banks| W*Bits*Banks| + +-------+----------------------------------------------------------------------------------+---------+---+----+-----+------+-----+------+-------------+ + |w35_U |dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_w35_Rn6c | 4| 0| 0| 0| 216| 122| 1| 26352| + +-------+----------------------------------------------------------------------------------+---------+---+----+-----+------+-----+------+-------------+ + |Total | | 4| 0| 0| 0| 216| 122| 1| 26352| + +-------+----------------------------------------------------------------------------------+---------+---+----+-----+------+-----+------+-------------+ + + * FIFO: + N/A + + * Expression: + +----------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +----------------------+----------+----+---+----+------------+------------+ + |w_index_fu_7589_p2 | +| 0| 0| 15| 8| 1| + |ap_condition_1604 | and| 0| 0| 2| 1| 1| + |ap_condition_1652 | and| 0| 0| 2| 1| 1| + |icmp_ln46_fu_7595_p2 | icmp| 0| 0| 15| 8| 7| + |ap_enable_pp0 | xor| 0| 0| 2| 1| 2| + +----------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0| 36| 19| 12| + +----------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +-----------------------------------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +-----------------------------------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + |ap_done_int | 9| 2| 1| 2| + |ap_loop_exit_ready_pp0_iter2_reg | 9| 2| 1| 2| + |ap_phi_mux_do_init_phi_fu_966_p6 | 14| 3| 1| 3| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13463_phi_fu_4020_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13464_phi_fu_4032_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13465_phi_fu_4044_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13466_phi_fu_4056_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13467_phi_fu_4068_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13468_phi_fu_4080_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13469_phi_fu_4092_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13470_phi_fu_4104_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13471_phi_fu_4116_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13472_phi_fu_4128_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13473_phi_fu_4140_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13474_phi_fu_4152_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13475_phi_fu_4164_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13476_phi_fu_4176_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13477_phi_fu_4188_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13478_phi_fu_4200_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13479_phi_fu_4212_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13480_phi_fu_4224_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13481_phi_fu_4236_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13482_phi_fu_4248_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13483_phi_fu_4260_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13484_phi_fu_4272_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13485_phi_fu_4284_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13486_phi_fu_4296_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13487_phi_fu_4308_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13488_phi_fu_4320_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13489_phi_fu_4332_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13490_phi_fu_4344_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13491_phi_fu_4356_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13492_phi_fu_4368_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13493_phi_fu_4380_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13494_phi_fu_4392_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13495_phi_fu_4404_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13496_phi_fu_4416_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13497_phi_fu_4428_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13498_phi_fu_4440_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13499_phi_fu_4452_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13500_phi_fu_4464_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13501_phi_fu_4476_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13502_phi_fu_4488_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13503_phi_fu_4500_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13504_phi_fu_4512_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13505_phi_fu_4524_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13506_phi_fu_4536_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13507_phi_fu_4548_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13508_phi_fu_4560_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13509_phi_fu_4572_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13510_phi_fu_4584_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13511_phi_fu_4596_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13512_phi_fu_4608_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13513_phi_fu_4620_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13514_phi_fu_4632_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13515_phi_fu_4644_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13516_phi_fu_4656_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13517_phi_fu_4668_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13518_phi_fu_4680_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13519_phi_fu_4692_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13520_phi_fu_4704_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13521_phi_fu_4716_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13522_phi_fu_4728_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13523_phi_fu_4740_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13524_phi_fu_4752_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13525_phi_fu_4764_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13526_phi_fu_4776_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13527_phi_fu_4788_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13528_phi_fu_4800_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13529_phi_fu_4812_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13530_phi_fu_4824_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13531_phi_fu_4836_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13532_phi_fu_4848_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13533_phi_fu_4860_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13534_phi_fu_4872_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13535_phi_fu_4884_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13536_phi_fu_4896_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13537_phi_fu_4908_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13538_phi_fu_4920_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13539_phi_fu_4932_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13540_phi_fu_4944_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13541_phi_fu_4956_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13542_phi_fu_4968_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13543_phi_fu_4980_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13544_phi_fu_4992_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13545_phi_fu_5004_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13546_phi_fu_5016_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13547_phi_fu_5028_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13548_phi_fu_5040_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13549_phi_fu_5052_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13550_phi_fu_5064_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13551_phi_fu_5076_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13552_phi_fu_5088_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13553_phi_fu_5100_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13554_phi_fu_5112_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13555_phi_fu_5124_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13556_phi_fu_5136_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13557_phi_fu_5148_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13558_phi_fu_5160_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13559_phi_fu_5172_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13560_phi_fu_5184_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13561_phi_fu_5196_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13562_phi_fu_5208_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13563_phi_fu_5220_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13564_phi_fu_5232_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13565_phi_fu_5244_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13566_phi_fu_5256_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13567_phi_fu_5268_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13568_phi_fu_5280_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13569_phi_fu_5292_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13570_phi_fu_5304_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13571_phi_fu_5316_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13572_phi_fu_5328_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13573_phi_fu_5340_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13574_phi_fu_5352_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13575_phi_fu_5364_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13576_phi_fu_5376_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13577_phi_fu_5388_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13578_phi_fu_5400_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13579_phi_fu_5412_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13580_phi_fu_5424_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13581_phi_fu_5436_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13582_phi_fu_5448_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13583_phi_fu_5460_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13584_phi_fu_5472_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13585_phi_fu_5484_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13586_phi_fu_5496_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13587_phi_fu_5508_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13588_phi_fu_5520_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13589_phi_fu_5532_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13590_phi_fu_5544_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13591_phi_fu_5556_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13592_phi_fu_5568_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13593_phi_fu_5580_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13594_phi_fu_5592_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13595_phi_fu_5604_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13596_phi_fu_5616_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13597_phi_fu_5628_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13598_phi_fu_5640_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13599_phi_fu_5652_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13600_phi_fu_5664_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13601_phi_fu_5676_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13602_phi_fu_5688_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13603_phi_fu_5700_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13604_phi_fu_5712_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13605_phi_fu_5724_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13606_phi_fu_5736_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13607_phi_fu_5748_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13608_phi_fu_5760_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13609_phi_fu_5772_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13610_phi_fu_5784_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13611_phi_fu_5796_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13612_phi_fu_5808_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13613_phi_fu_5820_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13614_phi_fu_5832_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13615_phi_fu_5844_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13616_phi_fu_5856_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13617_phi_fu_5868_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13618_phi_fu_5880_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13619_phi_fu_5892_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13620_phi_fu_5904_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13621_phi_fu_5916_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13622_phi_fu_5928_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13623_phi_fu_5940_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13624_phi_fu_5952_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13625_phi_fu_5964_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13626_phi_fu_5976_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13627_phi_fu_5988_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13628_phi_fu_6000_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13629_phi_fu_6012_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13630_phi_fu_6024_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13631_phi_fu_6036_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13632_phi_fu_6048_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13633_phi_fu_6060_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13634_phi_fu_6072_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13635_phi_fu_6084_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13636_phi_fu_6096_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13637_phi_fu_6108_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13638_phi_fu_6120_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13639_phi_fu_6132_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13640_phi_fu_6144_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13641_phi_fu_6156_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13642_phi_fu_6168_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13643_phi_fu_6180_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13644_phi_fu_6192_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13645_phi_fu_6204_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13646_phi_fu_6216_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13647_phi_fu_6228_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13648_phi_fu_6240_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13649_phi_fu_6252_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13650_phi_fu_6264_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13651_phi_fu_6276_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13652_phi_fu_6288_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13653_phi_fu_6300_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13654_phi_fu_6312_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13655_phi_fu_6324_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13656_phi_fu_6336_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13657_phi_fu_6348_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13658_phi_fu_6360_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13659_phi_fu_6372_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13660_phi_fu_6384_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13661_phi_fu_6396_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13662_phi_fu_6408_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13663_phi_fu_6420_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13664_phi_fu_6432_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13665_phi_fu_6444_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13666_phi_fu_6456_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13667_phi_fu_6468_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13668_phi_fu_6480_p4 | 9| 2| 16| 32| + |ap_phi_mux_res_0_0_i11_phi_fu_6612_p6 | 9| 2| 39| 78| + |ap_phi_mux_res_1_0_i10_phi_fu_6626_p6 | 9| 2| 39| 78| + |ap_phi_mux_res_2_0_i9_phi_fu_6640_p6 | 9| 2| 39| 78| + |ap_phi_mux_res_3_0_i8_phi_fu_6654_p6 | 9| 2| 39| 78| + |ap_phi_mux_res_4_0_i7_phi_fu_6668_p6 | 9| 2| 39| 78| + |ap_phi_mux_res_5_0_i6_phi_fu_6682_p6 | 9| 2| 39| 78| + |ap_phi_mux_res_6_0_i5_phi_fu_6696_p6 | 9| 2| 39| 78| + |ap_phi_mux_res_7_0_i4_phi_fu_6710_p6 | 9| 2| 33| 66| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_279_phi_fu_6492_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_280_phi_fu_6504_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_281_phi_fu_6516_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_282_phi_fu_6528_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_283_phi_fu_6540_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_284_phi_fu_6552_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_285_phi_fu_6564_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_286_phi_fu_6576_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_287_phi_fu_6588_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_288_phi_fu_6600_p4 | 9| 2| 16| 32| + |ap_phi_mux_w_index3_phi_fu_981_p6 | 14| 3| 8| 24| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13463_reg_4016 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13464_reg_4028 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13465_reg_4040 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13466_reg_4052 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13467_reg_4064 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13468_reg_4076 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13469_reg_4088 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13470_reg_4100 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13471_reg_4112 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13472_reg_4124 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13473_reg_4136 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13474_reg_4148 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13475_reg_4160 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13476_reg_4172 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13477_reg_4184 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13478_reg_4196 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13479_reg_4208 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13480_reg_4220 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13481_reg_4232 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13482_reg_4244 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13483_reg_4256 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13484_reg_4268 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13485_reg_4280 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13486_reg_4292 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13487_reg_4304 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13488_reg_4316 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13489_reg_4328 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13490_reg_4340 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13491_reg_4352 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13492_reg_4364 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13493_reg_4376 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13494_reg_4388 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13495_reg_4400 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13496_reg_4412 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13497_reg_4424 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13498_reg_4436 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13499_reg_4448 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13500_reg_4460 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13501_reg_4472 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13502_reg_4484 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13503_reg_4496 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13504_reg_4508 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13505_reg_4520 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13506_reg_4532 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13507_reg_4544 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13508_reg_4556 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13509_reg_4568 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13510_reg_4580 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13511_reg_4592 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13512_reg_4604 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13513_reg_4616 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13514_reg_4628 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13515_reg_4640 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13516_reg_4652 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13517_reg_4664 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13518_reg_4676 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13519_reg_4688 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13520_reg_4700 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13521_reg_4712 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13522_reg_4724 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13523_reg_4736 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13524_reg_4748 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13525_reg_4760 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13526_reg_4772 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13527_reg_4784 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13528_reg_4796 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13529_reg_4808 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13530_reg_4820 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13531_reg_4832 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13532_reg_4844 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13533_reg_4856 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13534_reg_4868 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13535_reg_4880 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13536_reg_4892 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13537_reg_4904 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13538_reg_4916 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13539_reg_4928 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13540_reg_4940 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13541_reg_4952 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13542_reg_4964 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13543_reg_4976 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13544_reg_4988 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13545_reg_5000 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13546_reg_5012 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13547_reg_5024 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13548_reg_5036 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13549_reg_5048 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13550_reg_5060 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13551_reg_5072 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13552_reg_5084 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13553_reg_5096 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13554_reg_5108 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13555_reg_5120 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13556_reg_5132 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13557_reg_5144 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13558_reg_5156 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13559_reg_5168 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13560_reg_5180 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13561_reg_5192 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13562_reg_5204 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13563_reg_5216 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13564_reg_5228 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13565_reg_5240 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13566_reg_5252 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13567_reg_5264 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13568_reg_5276 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13569_reg_5288 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13570_reg_5300 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13571_reg_5312 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13572_reg_5324 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13573_reg_5336 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13574_reg_5348 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13575_reg_5360 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13576_reg_5372 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13577_reg_5384 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13578_reg_5396 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13579_reg_5408 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13580_reg_5420 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13581_reg_5432 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13582_reg_5444 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13583_reg_5456 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13584_reg_5468 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13585_reg_5480 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13586_reg_5492 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13587_reg_5504 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13588_reg_5516 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13589_reg_5528 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13590_reg_5540 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13591_reg_5552 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13592_reg_5564 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13593_reg_5576 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13594_reg_5588 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13595_reg_5600 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13596_reg_5612 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13597_reg_5624 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13598_reg_5636 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13599_reg_5648 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13600_reg_5660 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13601_reg_5672 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13602_reg_5684 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13603_reg_5696 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13604_reg_5708 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13605_reg_5720 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13606_reg_5732 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13607_reg_5744 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13608_reg_5756 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13609_reg_5768 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13610_reg_5780 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13611_reg_5792 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13612_reg_5804 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13613_reg_5816 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13614_reg_5828 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13615_reg_5840 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13616_reg_5852 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13617_reg_5864 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13618_reg_5876 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13619_reg_5888 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13620_reg_5900 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13621_reg_5912 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13622_reg_5924 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13623_reg_5936 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13624_reg_5948 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13625_reg_5960 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13626_reg_5972 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13627_reg_5984 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13628_reg_5996 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13629_reg_6008 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13630_reg_6020 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13631_reg_6032 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13632_reg_6044 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13633_reg_6056 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13634_reg_6068 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13635_reg_6080 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13636_reg_6092 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13637_reg_6104 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13638_reg_6116 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13639_reg_6128 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13640_reg_6140 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13641_reg_6152 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13642_reg_6164 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13643_reg_6176 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13644_reg_6188 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13645_reg_6200 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13646_reg_6212 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13647_reg_6224 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13648_reg_6236 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13649_reg_6248 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13650_reg_6260 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13651_reg_6272 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13652_reg_6284 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13653_reg_6296 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13654_reg_6308 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13655_reg_6320 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13656_reg_6332 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13657_reg_6344 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13658_reg_6356 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13659_reg_6368 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13660_reg_6380 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13661_reg_6392 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13662_reg_6404 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13663_reg_6416 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13664_reg_6428 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13665_reg_6440 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13666_reg_6452 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13667_reg_6464 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13668_reg_6476 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_279_reg_6488 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_280_reg_6500 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_281_reg_6512 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_282_reg_6524 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_283_reg_6536 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_284_reg_6548 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_285_reg_6560 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_286_reg_6572 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_287_reg_6584 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_288_reg_6596 | 9| 2| 16| 32| + |ap_return_0 | 9| 2| 41| 82| + |ap_return_1 | 9| 2| 41| 82| + |ap_return_2 | 9| 2| 41| 82| + |ap_return_3 | 9| 2| 41| 82| + |ap_return_4 | 9| 2| 41| 82| + |ap_return_5 | 9| 2| 41| 82| + |ap_return_6 | 9| 2| 41| 82| + |ap_return_7 | 9| 2| 41| 82| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13463_reg_4016 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13464_reg_4028 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13465_reg_4040 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13466_reg_4052 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13467_reg_4064 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13468_reg_4076 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13469_reg_4088 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13470_reg_4100 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13471_reg_4112 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13472_reg_4124 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13473_reg_4136 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13474_reg_4148 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13475_reg_4160 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13476_reg_4172 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13477_reg_4184 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13478_reg_4196 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13479_reg_4208 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13480_reg_4220 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13481_reg_4232 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13482_reg_4244 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13483_reg_4256 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13484_reg_4268 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13485_reg_4280 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13486_reg_4292 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13487_reg_4304 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13488_reg_4316 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13489_reg_4328 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13490_reg_4340 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13491_reg_4352 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13492_reg_4364 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13493_reg_4376 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13494_reg_4388 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13495_reg_4400 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13496_reg_4412 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13497_reg_4424 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13498_reg_4436 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13499_reg_4448 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13500_reg_4460 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13501_reg_4472 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13502_reg_4484 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13503_reg_4496 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13504_reg_4508 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13505_reg_4520 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13506_reg_4532 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13507_reg_4544 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13508_reg_4556 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13509_reg_4568 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13510_reg_4580 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13511_reg_4592 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13512_reg_4604 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13513_reg_4616 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13514_reg_4628 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13515_reg_4640 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13516_reg_4652 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13517_reg_4664 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13518_reg_4676 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13519_reg_4688 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13520_reg_4700 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13521_reg_4712 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13522_reg_4724 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13523_reg_4736 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13524_reg_4748 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13525_reg_4760 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13526_reg_4772 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13527_reg_4784 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13528_reg_4796 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13529_reg_4808 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13530_reg_4820 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13531_reg_4832 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13532_reg_4844 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13533_reg_4856 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13534_reg_4868 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13535_reg_4880 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13536_reg_4892 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13537_reg_4904 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13538_reg_4916 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13539_reg_4928 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13540_reg_4940 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13541_reg_4952 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13542_reg_4964 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13543_reg_4976 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13544_reg_4988 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13545_reg_5000 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13546_reg_5012 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13547_reg_5024 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13548_reg_5036 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13549_reg_5048 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13550_reg_5060 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13551_reg_5072 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13552_reg_5084 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13553_reg_5096 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13554_reg_5108 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13555_reg_5120 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13556_reg_5132 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13557_reg_5144 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13558_reg_5156 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13559_reg_5168 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13560_reg_5180 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13561_reg_5192 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13562_reg_5204 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13563_reg_5216 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13564_reg_5228 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13565_reg_5240 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13566_reg_5252 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13567_reg_5264 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13568_reg_5276 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13569_reg_5288 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13570_reg_5300 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13571_reg_5312 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13572_reg_5324 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13573_reg_5336 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13574_reg_5348 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13575_reg_5360 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13576_reg_5372 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13577_reg_5384 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13578_reg_5396 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13579_reg_5408 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13580_reg_5420 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13581_reg_5432 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13582_reg_5444 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13583_reg_5456 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13584_reg_5468 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13585_reg_5480 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13586_reg_5492 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13587_reg_5504 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13588_reg_5516 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13589_reg_5528 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13590_reg_5540 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13591_reg_5552 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13592_reg_5564 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13593_reg_5576 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13594_reg_5588 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13595_reg_5600 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13596_reg_5612 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13597_reg_5624 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13598_reg_5636 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13599_reg_5648 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13600_reg_5660 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13601_reg_5672 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13602_reg_5684 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13603_reg_5696 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13604_reg_5708 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13605_reg_5720 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13606_reg_5732 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13607_reg_5744 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13608_reg_5756 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13609_reg_5768 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13610_reg_5780 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13611_reg_5792 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13612_reg_5804 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13613_reg_5816 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13614_reg_5828 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13615_reg_5840 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13616_reg_5852 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13617_reg_5864 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13618_reg_5876 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13619_reg_5888 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13620_reg_5900 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13621_reg_5912 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13622_reg_5924 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13623_reg_5936 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13624_reg_5948 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13625_reg_5960 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13626_reg_5972 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13627_reg_5984 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13628_reg_5996 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13629_reg_6008 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13630_reg_6020 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13631_reg_6032 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13632_reg_6044 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13633_reg_6056 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13634_reg_6068 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13635_reg_6080 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13636_reg_6092 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13637_reg_6104 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13638_reg_6116 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13639_reg_6128 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13640_reg_6140 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13641_reg_6152 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13642_reg_6164 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13643_reg_6176 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13644_reg_6188 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13645_reg_6200 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13646_reg_6212 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13647_reg_6224 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13648_reg_6236 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13649_reg_6248 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13650_reg_6260 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13651_reg_6272 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13652_reg_6284 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13653_reg_6296 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13654_reg_6308 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13655_reg_6320 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13656_reg_6332 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13657_reg_6344 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13658_reg_6356 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13659_reg_6368 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13660_reg_6380 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13661_reg_6392 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13662_reg_6404 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13663_reg_6416 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13664_reg_6428 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13665_reg_6440 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13666_reg_6452 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13667_reg_6464 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13668_reg_6476 | 9| 2| 16| 32| + |res_0_0_i11_reg_6608 | 9| 2| 39| 78| + |res_1_0_i10_reg_6622 | 9| 2| 39| 78| + |res_2_0_i9_reg_6636 | 9| 2| 39| 78| + |res_3_0_i8_reg_6650 | 9| 2| 39| 78| + |res_4_0_i7_reg_6664 | 9| 2| 39| 78| + |res_5_0_i6_reg_6678 | 9| 2| 39| 78| + |res_6_0_i5_reg_6692 | 9| 2| 39| 78| + |res_7_0_i4_reg_6706 | 9| 2| 33| 66| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_279_reg_6488 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_280_reg_6500 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_281_reg_6512 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_282_reg_6524 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_283_reg_6536 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_284_reg_6548 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_285_reg_6560 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_286_reg_6572 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_287_reg_6584 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_288_reg_6596 | 9| 2| 16| 32| + |w_index3_reg_978 | 9| 2| 8| 16| + +-----------------------------------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + |Total |6103| 1356|11327| 22663| + +-----------------------------------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + + * Register: + +-----------------------------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + | Name | FF | LUT| Bits| Const Bits| + +-----------------------------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + |a_reg_9819 | 16| 0| 16| 0| + |ap_CS_fsm | 1| 0| 1| 0| + |ap_done_reg | 1| 0| 1| 0| + |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| + |ap_enable_reg_pp0_iter2 | 1| 0| 1| 0| + |ap_loop_exit_ready_pp0_iter1_reg | 1| 0| 1| 0| + |ap_loop_exit_ready_pp0_iter2_reg | 1| 0| 1| 0| + |ap_loop_init_pp0_iter1_reg | 1| 0| 1| 0| + |ap_loop_init_pp0_iter2_reg | 1| 0| 1| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13463_reg_4016 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13464_reg_4028 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13465_reg_4040 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13466_reg_4052 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13467_reg_4064 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13468_reg_4076 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13469_reg_4088 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13470_reg_4100 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13471_reg_4112 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13472_reg_4124 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13473_reg_4136 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13474_reg_4148 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13475_reg_4160 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13476_reg_4172 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13477_reg_4184 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13478_reg_4196 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13479_reg_4208 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13480_reg_4220 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13481_reg_4232 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13482_reg_4244 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13483_reg_4256 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13484_reg_4268 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13485_reg_4280 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13486_reg_4292 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13487_reg_4304 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13488_reg_4316 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13489_reg_4328 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13490_reg_4340 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13491_reg_4352 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13492_reg_4364 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13493_reg_4376 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13494_reg_4388 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13495_reg_4400 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13496_reg_4412 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13497_reg_4424 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13498_reg_4436 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13499_reg_4448 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13500_reg_4460 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13501_reg_4472 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13502_reg_4484 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13503_reg_4496 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13504_reg_4508 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13505_reg_4520 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13506_reg_4532 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13507_reg_4544 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13508_reg_4556 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13509_reg_4568 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13510_reg_4580 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13511_reg_4592 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13512_reg_4604 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13513_reg_4616 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13514_reg_4628 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13515_reg_4640 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13516_reg_4652 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13517_reg_4664 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13518_reg_4676 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13519_reg_4688 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13520_reg_4700 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13521_reg_4712 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13522_reg_4724 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13523_reg_4736 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13524_reg_4748 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13525_reg_4760 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13526_reg_4772 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13527_reg_4784 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13528_reg_4796 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13529_reg_4808 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13530_reg_4820 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13531_reg_4832 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13532_reg_4844 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13533_reg_4856 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13534_reg_4868 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13535_reg_4880 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13536_reg_4892 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13537_reg_4904 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13538_reg_4916 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13539_reg_4928 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13540_reg_4940 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13541_reg_4952 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13542_reg_4964 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13543_reg_4976 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13544_reg_4988 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13545_reg_5000 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13546_reg_5012 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13547_reg_5024 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13548_reg_5036 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13549_reg_5048 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13550_reg_5060 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13551_reg_5072 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13552_reg_5084 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13553_reg_5096 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13554_reg_5108 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13555_reg_5120 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13556_reg_5132 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13557_reg_5144 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13558_reg_5156 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13559_reg_5168 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13560_reg_5180 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13561_reg_5192 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13562_reg_5204 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13563_reg_5216 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13564_reg_5228 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13565_reg_5240 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13566_reg_5252 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13567_reg_5264 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13568_reg_5276 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13569_reg_5288 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13570_reg_5300 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13571_reg_5312 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13572_reg_5324 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13573_reg_5336 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13574_reg_5348 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13575_reg_5360 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13576_reg_5372 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13577_reg_5384 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13578_reg_5396 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13579_reg_5408 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13580_reg_5420 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13581_reg_5432 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13582_reg_5444 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13583_reg_5456 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13584_reg_5468 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13585_reg_5480 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13586_reg_5492 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13587_reg_5504 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13588_reg_5516 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13589_reg_5528 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13590_reg_5540 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13591_reg_5552 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13592_reg_5564 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13593_reg_5576 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13594_reg_5588 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13595_reg_5600 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13596_reg_5612 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13597_reg_5624 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13598_reg_5636 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13599_reg_5648 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13600_reg_5660 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13601_reg_5672 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13602_reg_5684 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13603_reg_5696 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13604_reg_5708 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13605_reg_5720 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13606_reg_5732 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13607_reg_5744 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13608_reg_5756 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13609_reg_5768 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13610_reg_5780 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13611_reg_5792 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13612_reg_5804 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13613_reg_5816 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13614_reg_5828 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13615_reg_5840 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13616_reg_5852 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13617_reg_5864 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13618_reg_5876 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13619_reg_5888 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13620_reg_5900 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13621_reg_5912 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13622_reg_5924 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13623_reg_5936 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13624_reg_5948 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13625_reg_5960 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13626_reg_5972 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13627_reg_5984 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13628_reg_5996 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13629_reg_6008 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13630_reg_6020 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13631_reg_6032 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13632_reg_6044 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13633_reg_6056 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13634_reg_6068 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13635_reg_6080 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13636_reg_6092 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13637_reg_6104 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13638_reg_6116 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13639_reg_6128 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13640_reg_6140 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13641_reg_6152 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13642_reg_6164 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13643_reg_6176 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13644_reg_6188 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13645_reg_6200 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13646_reg_6212 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13647_reg_6224 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13648_reg_6236 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13649_reg_6248 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13650_reg_6260 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13651_reg_6272 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13652_reg_6284 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13653_reg_6296 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13654_reg_6308 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13655_reg_6320 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13656_reg_6332 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13657_reg_6344 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13658_reg_6356 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13659_reg_6368 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13660_reg_6380 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13661_reg_6392 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13662_reg_6404 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13663_reg_6416 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13664_reg_6428 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13665_reg_6440 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13666_reg_6452 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13667_reg_6464 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13668_reg_6476 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_279_reg_6488 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_280_reg_6500 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_281_reg_6512 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_282_reg_6524 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_283_reg_6536 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_284_reg_6548 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_285_reg_6560 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_286_reg_6572 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_287_reg_6584 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_288_reg_6596 | 16| 0| 16| 0| + |ap_return_0_preg | 41| 0| 41| 0| + |ap_return_1_preg | 41| 0| 41| 0| + |ap_return_2_preg | 41| 0| 41| 0| + |ap_return_3_preg | 41| 0| 41| 0| + |ap_return_4_preg | 41| 0| 41| 0| + |ap_return_5_preg | 41| 0| 41| 0| + |ap_return_6_preg | 41| 0| 41| 0| + |ap_return_7_preg | 41| 0| 41| 0| + |do_init_reg_963 | 1| 0| 1| 0| + |icmp_ln46_reg_9815 | 1| 0| 1| 0| + |icmp_ln46_reg_9815_pp0_iter1_reg | 1| 0| 1| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13463_reg_4016 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13464_reg_4028 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13465_reg_4040 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13466_reg_4052 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13467_reg_4064 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13468_reg_4076 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13469_reg_4088 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13470_reg_4100 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13471_reg_4112 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13472_reg_4124 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13473_reg_4136 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13474_reg_4148 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13475_reg_4160 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13476_reg_4172 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13477_reg_4184 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13478_reg_4196 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13479_reg_4208 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13480_reg_4220 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13481_reg_4232 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13482_reg_4244 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13483_reg_4256 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13484_reg_4268 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13485_reg_4280 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13486_reg_4292 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13487_reg_4304 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13488_reg_4316 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13489_reg_4328 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13490_reg_4340 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13491_reg_4352 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13492_reg_4364 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13493_reg_4376 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13494_reg_4388 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13495_reg_4400 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13496_reg_4412 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13497_reg_4424 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13498_reg_4436 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13499_reg_4448 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13500_reg_4460 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13501_reg_4472 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13502_reg_4484 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13503_reg_4496 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13504_reg_4508 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13505_reg_4520 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13506_reg_4532 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13507_reg_4544 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13508_reg_4556 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13509_reg_4568 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13510_reg_4580 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13511_reg_4592 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13512_reg_4604 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13513_reg_4616 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13514_reg_4628 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13515_reg_4640 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13516_reg_4652 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13517_reg_4664 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13518_reg_4676 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13519_reg_4688 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13520_reg_4700 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13521_reg_4712 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13522_reg_4724 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13523_reg_4736 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13524_reg_4748 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13525_reg_4760 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13526_reg_4772 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13527_reg_4784 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13528_reg_4796 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13529_reg_4808 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13530_reg_4820 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13531_reg_4832 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13532_reg_4844 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13533_reg_4856 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13534_reg_4868 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13535_reg_4880 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13536_reg_4892 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13537_reg_4904 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13538_reg_4916 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13539_reg_4928 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13540_reg_4940 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13541_reg_4952 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13542_reg_4964 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13543_reg_4976 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13544_reg_4988 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13545_reg_5000 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13546_reg_5012 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13547_reg_5024 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13548_reg_5036 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13549_reg_5048 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13550_reg_5060 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13551_reg_5072 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13552_reg_5084 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13553_reg_5096 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13554_reg_5108 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13555_reg_5120 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13556_reg_5132 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13557_reg_5144 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13558_reg_5156 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13559_reg_5168 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13560_reg_5180 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13561_reg_5192 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13562_reg_5204 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13563_reg_5216 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13564_reg_5228 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13565_reg_5240 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13566_reg_5252 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13567_reg_5264 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13568_reg_5276 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13569_reg_5288 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13570_reg_5300 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13571_reg_5312 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13572_reg_5324 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13573_reg_5336 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13574_reg_5348 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13575_reg_5360 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13576_reg_5372 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13577_reg_5384 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13578_reg_5396 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13579_reg_5408 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13580_reg_5420 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13581_reg_5432 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13582_reg_5444 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13583_reg_5456 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13584_reg_5468 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13585_reg_5480 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13586_reg_5492 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13587_reg_5504 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13588_reg_5516 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13589_reg_5528 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13590_reg_5540 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13591_reg_5552 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13592_reg_5564 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13593_reg_5576 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13594_reg_5588 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13595_reg_5600 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13596_reg_5612 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13597_reg_5624 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13598_reg_5636 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13599_reg_5648 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13600_reg_5660 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13601_reg_5672 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13602_reg_5684 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13603_reg_5696 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13604_reg_5708 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13605_reg_5720 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13606_reg_5732 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13607_reg_5744 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13608_reg_5756 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13609_reg_5768 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13610_reg_5780 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13611_reg_5792 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13612_reg_5804 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13613_reg_5816 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13614_reg_5828 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13615_reg_5840 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13616_reg_5852 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13617_reg_5864 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13618_reg_5876 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13619_reg_5888 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13620_reg_5900 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13621_reg_5912 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13622_reg_5924 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13623_reg_5936 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13624_reg_5948 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13625_reg_5960 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13626_reg_5972 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13627_reg_5984 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13628_reg_5996 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13629_reg_6008 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13630_reg_6020 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13631_reg_6032 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13632_reg_6044 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13633_reg_6056 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13634_reg_6068 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13635_reg_6080 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13636_reg_6092 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13637_reg_6104 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13638_reg_6116 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13639_reg_6128 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13640_reg_6140 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13641_reg_6152 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13642_reg_6164 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13643_reg_6176 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13644_reg_6188 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13645_reg_6200 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13646_reg_6212 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13647_reg_6224 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13648_reg_6236 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13649_reg_6248 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13650_reg_6260 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13651_reg_6272 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13652_reg_6284 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13653_reg_6296 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13654_reg_6308 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13655_reg_6320 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13656_reg_6332 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13657_reg_6344 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13658_reg_6356 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13659_reg_6368 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13660_reg_6380 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13661_reg_6392 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13662_reg_6404 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13663_reg_6416 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13664_reg_6428 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13665_reg_6440 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13666_reg_6452 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13667_reg_6464 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_13668_reg_6476 | 16| 0| 16| 0| + |res_0_0_i11_reg_6608 | 39| 0| 39| 0| + |res_1_0_i10_reg_6622 | 39| 0| 39| 0| + |res_2_0_i9_reg_6636 | 39| 0| 39| 0| + |res_3_0_i8_reg_6650 | 39| 0| 39| 0| + |res_4_0_i7_reg_6664 | 39| 0| 39| 0| + |res_5_0_i6_reg_6678 | 39| 0| 39| 0| + |res_6_0_i5_reg_6692 | 39| 0| 39| 0| + |res_7_0_i4_reg_6706 | 33| 0| 33| 0| + |tmp_reg_9860 | 10| 0| 10| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_279_reg_6488 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_280_reg_6500 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_281_reg_6512 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_282_reg_6524 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_283_reg_6536 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_284_reg_6548 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_285_reg_6560 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_286_reg_6572 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_287_reg_6584 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_288_reg_6596 | 16| 0| 16| 0| + |w_59_reg_9830 | 16| 0| 16| 0| + |w_60_reg_9835 | 16| 0| 16| 0| + |w_61_reg_9840 | 16| 0| 16| 0| + |w_62_reg_9845 | 16| 0| 16| 0| + |w_63_reg_9850 | 16| 0| 16| 0| + |w_64_reg_9855 | 16| 0| 16| 0| + |w_index3_reg_978 | 8| 0| 8| 0| + |w_index_reg_9810 | 8| 0| 8| 0| + |w_reg_9825 | 16| 0| 16| 0| + +-----------------------------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + |Total |7711| 0| 7711| 0| + +-----------------------------------------------------------------------------------------------------------------------+----+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++----------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| dense_resource_rf_leq_nin,config35_mult>| return value| +|ap_rst | in| 1| ap_ctrl_hs| dense_resource_rf_leq_nin,config35_mult>| return value| +|ap_start | in| 1| ap_ctrl_hs| dense_resource_rf_leq_nin,config35_mult>| return value| +|ap_done | out| 1| ap_ctrl_hs| dense_resource_rf_leq_nin,config35_mult>| return value| +|ap_idle | out| 1| ap_ctrl_hs| dense_resource_rf_leq_nin,config35_mult>| return value| +|ap_ready | out| 1| ap_ctrl_hs| dense_resource_rf_leq_nin,config35_mult>| return value| +|ap_return_0 | out| 41| ap_ctrl_hs| dense_resource_rf_leq_nin,config35_mult>| return value| +|ap_return_1 | out| 41| ap_ctrl_hs| dense_resource_rf_leq_nin,config35_mult>| return value| +|ap_return_2 | out| 41| ap_ctrl_hs| dense_resource_rf_leq_nin,config35_mult>| return value| +|ap_return_3 | out| 41| ap_ctrl_hs| dense_resource_rf_leq_nin,config35_mult>| return value| +|ap_return_4 | out| 41| ap_ctrl_hs| dense_resource_rf_leq_nin,config35_mult>| return value| +|ap_return_5 | out| 41| ap_ctrl_hs| dense_resource_rf_leq_nin,config35_mult>| return value| +|ap_return_6 | out| 41| ap_ctrl_hs| dense_resource_rf_leq_nin,config35_mult>| return value| +|ap_return_7 | out| 41| ap_ctrl_hs| dense_resource_rf_leq_nin,config35_mult>| return value| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_99 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_99| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_98 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_98| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_97 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_97| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_96 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_96| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_95 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_95| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_94 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_94| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_93 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_93| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_92 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_92| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_91 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_91| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_90 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_90| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4564 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4564| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4576 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4576| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4588 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4588| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4600 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4600| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4612 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4612| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4624 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4624| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4636 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4636| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4648 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4648| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4661 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4661| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4673 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4673| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4685 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4685| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4697 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4697| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4705 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4705| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4706 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4706| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4707 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4707| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4708 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4708| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4709 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4709| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4710 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4710| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4711 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4711| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4712 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4712| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4713 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4713| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4714 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4714| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4716 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4716| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4717 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4717| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4718 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4718| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4719 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4719| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4720 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4720| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4721 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4721| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4722 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4722| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4723 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4723| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4724 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4724| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4725 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4725| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4727 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4727| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4728 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4728| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4729 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4729| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4730 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4730| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4735| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4736 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4736| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4738 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4738| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4739 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4739| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4740 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4740| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4745| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4746 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4746| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4747 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4747| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4749 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4749| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4750 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4750| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4755| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4756 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4756| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4757 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4757| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4758 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4758| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4760 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4760| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4765| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4766 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4766| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4767 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4767| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4768 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4768| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4769 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4769| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4775| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4776 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4776| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4777 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4777| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4778 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4778| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4779 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4779| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4785| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4786 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4786| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4787 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4787| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4788 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4788| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4789 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4789| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4565 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4565| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4566 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4566| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4567 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4567| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4568 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4568| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4569 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4569| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4570 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4570| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4571 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4571| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4573 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4573| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4574 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4574| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4575 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4575| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4577 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4577| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4578 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4578| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4579 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4579| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4580 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4580| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4581 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4581| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4582 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4582| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4584 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4584| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4585 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4585| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4586 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4586| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4587 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4587| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4589 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4589| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4590 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4590| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4591 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4591| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4592 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4592| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4593 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4593| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4595 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4595| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4596 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4596| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4597 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4597| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4598 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4598| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4599 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4599| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4601 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4601| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4602 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4602| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4603 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4603| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4604 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4604| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4606 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4606| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4607 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4607| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4608 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4608| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4609 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4609| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4610 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4610| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4611 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4611| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4613 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4613| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4614 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4614| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4615 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4615| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4617 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4617| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4618 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4618| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4623| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4625 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4625| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4626 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4626| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4628 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4628| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4629 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4629| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4634| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4635 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4635| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4637 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4637| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4639 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4639| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4640 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4640| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4645| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4646 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4646| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4647 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4647| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4650 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4650| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4651 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4651| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4656| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4657 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4657| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4658 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4658| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4659 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4659| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4662 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4662| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4667| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4668 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4668| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4669 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4669| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4670 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4670| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4672 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4672| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4678| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4679 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4679| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4680 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4680| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4681 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4681| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4683 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4683| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4689| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4690 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4690| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4691 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4691| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4692 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4692| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4694 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4694| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4700| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4701 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4701| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4702 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4702| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4703 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4703| pointer| ++----------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_csynth.rpt b/myproject_prj/solution1/syn/report/dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..23a84eb5acc32a572b31528cd9ac91b15597d06d --- /dev/null +++ b/myproject_prj/solution1/syn/report/dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_csynth.rpt @@ -0,0 +1,2887 @@ + + +================================================================ +== Vitis HLS Report for 'dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s' +================================================================ +* Date: Sun Apr 5 21:49:37 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 2.533 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+----------+----------+-----+-----+------------------------------------------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | min | max | min | max | min | max | Type | + +---------+---------+----------+----------+-----+-----+------------------------------------------+ + | 433| 434| 1.732 us| 1.736 us| 432| 432| loop rewind stp(delay=0 clock cycles(s))| + +---------+---------+----------+----------+-----+-----+------------------------------------------+ + + + Detail: + * Instance: + N/A + + * Loop: + +-------------+---------+---------+----------+-----------+-----------+------+----------+ + | | Latency (cycles) | Iteration| Initiation Interval | Trip | | + | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| + +-------------+---------+---------+----------+-----------+-----------+------+----------+ + |- ReuseLoop | 433| 433| 3| 1| 1| 432| yes| + +-------------+---------+---------+----------+-----------+-----------+------+----------+ + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| 16| -| -| -| +|Expression | -| -| 0| 38| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| 0| 2277| -| +|Memory | 8| -| 0| 0| -| +|Multiplexer | -| -| 0| 12151| -| +|Register | -| -| 15423| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 8| 16| 15423| 14466| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | ~0| ~0| 1| 3| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | ~0| ~0| ~0| 1| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + +------------------------------+------------------------+---------+----+---+------+-----+ + | Instance | Module | BRAM_18K| DSP| FF| LUT | URAM| + +------------------------------+------------------------+---------+----+---+------+-----+ + |sparsemux_865_9_16_1_1_U7240 |sparsemux_865_9_16_1_1 | 0| 0| 0| 2277| 0| + +------------------------------+------------------------+---------+----+---+------+-----+ + |Total | | 0| 0| 0| 2277| 0| + +------------------------------+------------------------+---------+----+---+------+-----+ + + * DSP: + +-------------------------------------+-------------------------------+--------------+ + | Instance | Module | Expression | + +-------------------------------------+-------------------------------+--------------+ + |mac_muladd_16s_16s_40s_40_1_1_U7241 |mac_muladd_16s_16s_40s_40_1_1 | i0 * i1 + i2| + |mac_muladd_16s_16s_40s_40_1_1_U7242 |mac_muladd_16s_16s_40s_40_1_1 | i0 * i1 + i2| + |mac_muladd_16s_16s_40s_40_1_1_U7243 |mac_muladd_16s_16s_40s_40_1_1 | i0 * i1 + i2| + |mac_muladd_16s_16s_40s_40_1_1_U7244 |mac_muladd_16s_16s_40s_40_1_1 | i0 * i1 + i2| + |mac_muladd_16s_16s_40s_40_1_1_U7245 |mac_muladd_16s_16s_40s_40_1_1 | i0 * i1 + i2| + |mac_muladd_16s_16s_40s_40_1_1_U7246 |mac_muladd_16s_16s_40s_40_1_1 | i0 * i1 + i2| + |mac_muladd_16s_16s_40s_40_1_1_U7247 |mac_muladd_16s_16s_40s_40_1_1 | i0 * i1 + i2| + |mac_muladd_16s_16s_40s_40_1_1_U7248 |mac_muladd_16s_16s_40s_40_1_1 | i0 * i1 + i2| + |mac_muladd_16s_16s_40s_40_1_1_U7249 |mac_muladd_16s_16s_40s_40_1_1 | i0 * i1 + i2| + |mac_muladd_16s_16s_40s_40_1_1_U7250 |mac_muladd_16s_16s_40s_40_1_1 | i0 * i1 + i2| + |mac_muladd_16s_16s_40s_40_1_1_U7251 |mac_muladd_16s_16s_40s_40_1_1 | i0 * i1 + i2| + |mac_muladd_16s_16s_40s_40_1_1_U7252 |mac_muladd_16s_16s_40s_40_1_1 | i0 * i1 + i2| + |mac_muladd_16s_16s_40s_40_1_1_U7253 |mac_muladd_16s_16s_40s_40_1_1 | i0 * i1 + i2| + |mac_muladd_16s_16s_40s_40_1_1_U7254 |mac_muladd_16s_16s_40s_40_1_1 | i0 * i1 + i2| + |mac_muladd_16s_16s_40s_40_1_1_U7255 |mac_muladd_16s_16s_40s_40_1_1 | i0 * i1 + i2| + |mac_muladd_16s_9s_33s_33_1_1_U7256 |mac_muladd_16s_9s_33s_33_1_1 | i0 * i1 + i2| + +-------------------------------------+-------------------------------+--------------+ + + * Memory: + +-------+----------------------------------------------------------------------------------+---------+---+----+-----+------+-----+------+-------------+ + | Memory| Module | BRAM_18K| FF| LUT| URAM| Words| Bits| Banks| W*Bits*Banks| + +-------+----------------------------------------------------------------------------------+---------+---+----+-----+------+-----+------+-------------+ + |w29_U |dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_w29_RmLc | 8| 0| 0| 0| 432| 249| 1| 107568| + +-------+----------------------------------------------------------------------------------+---------+---+----+-----+------+-----+------+-------------+ + |Total | | 8| 0| 0| 0| 432| 249| 1| 107568| + +-------+----------------------------------------------------------------------------------+---------+---+----+-----+------+-----+------+-------------+ + + * FIFO: + N/A + + * Expression: + +-----------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +-----------------------+----------+----+---+----+------------+------------+ + |w_index_fu_15093_p2 | +| 0| 0| 16| 9| 1| + |ap_condition_3140 | and| 0| 0| 2| 1| 1| + |ap_condition_3220 | and| 0| 0| 2| 1| 1| + |icmp_ln46_fu_15099_p2 | icmp| 0| 0| 16| 9| 8| + |ap_enable_pp0 | xor| 0| 0| 2| 1| 2| + +-----------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0| 38| 21| 13| + +-----------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +------------------------------------------------------------------------------------------------------------------------+-----+-----------+-----+-----------+ + | Name | LUT | Input Size| Bits| Total Bits| + +------------------------------------------------------------------------------------------------------------------------+-----+-----------+-----+-----------+ + |ap_done_int | 9| 2| 1| 2| + |ap_loop_exit_ready_pp0_iter2_reg | 9| 2| 1| 2| + |ap_phi_mux_do_init_phi_fu_1878_p6 | 14| 3| 1| 3| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11795_phi_fu_7956_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11796_phi_fu_7968_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11797_phi_fu_7980_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11798_phi_fu_7992_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11799_phi_fu_8004_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11800_phi_fu_8016_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11801_phi_fu_8028_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11802_phi_fu_8040_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11803_phi_fu_8052_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11804_phi_fu_8064_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11805_phi_fu_8076_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11806_phi_fu_8088_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11807_phi_fu_8100_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11808_phi_fu_8112_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11809_phi_fu_8124_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11810_phi_fu_8136_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11811_phi_fu_8148_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11812_phi_fu_8160_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11813_phi_fu_8172_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11814_phi_fu_8184_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11815_phi_fu_8196_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11816_phi_fu_8208_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11817_phi_fu_8220_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11818_phi_fu_8232_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11819_phi_fu_8244_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11820_phi_fu_8256_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11821_phi_fu_8268_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11822_phi_fu_8280_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11823_phi_fu_8292_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11824_phi_fu_8304_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11825_phi_fu_8316_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11826_phi_fu_8328_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11827_phi_fu_8340_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11828_phi_fu_8352_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11829_phi_fu_8364_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11830_phi_fu_8376_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11831_phi_fu_8388_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11832_phi_fu_8400_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11833_phi_fu_8412_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11834_phi_fu_8424_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11835_phi_fu_8436_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11836_phi_fu_8448_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11837_phi_fu_8460_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11838_phi_fu_8472_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11839_phi_fu_8484_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11840_phi_fu_8496_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11841_phi_fu_8508_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11842_phi_fu_8520_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11843_phi_fu_8532_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11844_phi_fu_8544_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11845_phi_fu_8556_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11846_phi_fu_8568_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11847_phi_fu_8580_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11848_phi_fu_8592_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11849_phi_fu_8604_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11850_phi_fu_8616_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11851_phi_fu_8628_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11852_phi_fu_8640_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11853_phi_fu_8652_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11854_phi_fu_8664_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11855_phi_fu_8676_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11856_phi_fu_8688_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11857_phi_fu_8700_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11858_phi_fu_8712_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11859_phi_fu_8724_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11860_phi_fu_8736_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11861_phi_fu_8748_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11862_phi_fu_8760_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11863_phi_fu_8772_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11864_phi_fu_8784_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11865_phi_fu_8796_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11866_phi_fu_8808_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11867_phi_fu_8820_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11868_phi_fu_8832_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11869_phi_fu_8844_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11870_phi_fu_8856_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11871_phi_fu_8868_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11872_phi_fu_8880_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11873_phi_fu_8892_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11874_phi_fu_8904_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11875_phi_fu_8916_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11876_phi_fu_8928_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11877_phi_fu_8940_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11878_phi_fu_8952_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11879_phi_fu_8964_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11880_phi_fu_8976_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11881_phi_fu_8988_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11882_phi_fu_9000_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11883_phi_fu_9012_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11884_phi_fu_9024_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11885_phi_fu_9036_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11886_phi_fu_9048_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11887_phi_fu_9060_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11888_phi_fu_9072_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11889_phi_fu_9084_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11890_phi_fu_9096_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11891_phi_fu_9108_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11892_phi_fu_9120_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11893_phi_fu_9132_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11894_phi_fu_9144_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11895_phi_fu_9156_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11896_phi_fu_9168_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11897_phi_fu_9180_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11898_phi_fu_9192_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11899_phi_fu_9204_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11900_phi_fu_9216_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11901_phi_fu_9228_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11902_phi_fu_9240_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11903_phi_fu_9252_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11904_phi_fu_9264_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11905_phi_fu_9276_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11906_phi_fu_9288_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11907_phi_fu_9300_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11908_phi_fu_9312_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11909_phi_fu_9324_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11910_phi_fu_9336_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11911_phi_fu_9348_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11912_phi_fu_9360_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11913_phi_fu_9372_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11914_phi_fu_9384_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11915_phi_fu_9396_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11916_phi_fu_9408_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11917_phi_fu_9420_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11918_phi_fu_9432_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11919_phi_fu_9444_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11920_phi_fu_9456_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11921_phi_fu_9468_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11922_phi_fu_9480_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11923_phi_fu_9492_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11924_phi_fu_9504_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11925_phi_fu_9516_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11926_phi_fu_9528_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11927_phi_fu_9540_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11928_phi_fu_9552_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11929_phi_fu_9564_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11930_phi_fu_9576_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11931_phi_fu_9588_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11932_phi_fu_9600_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11933_phi_fu_9612_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11934_phi_fu_9624_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11935_phi_fu_9636_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11936_phi_fu_9648_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11937_phi_fu_9660_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11938_phi_fu_9672_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11939_phi_fu_9684_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11940_phi_fu_9696_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11941_phi_fu_9708_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11942_phi_fu_9720_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11943_phi_fu_9732_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11944_phi_fu_9744_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11945_phi_fu_9756_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11946_phi_fu_9768_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11947_phi_fu_9780_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11948_phi_fu_9792_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11949_phi_fu_9804_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11950_phi_fu_9816_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11951_phi_fu_9828_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11952_phi_fu_9840_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11953_phi_fu_9852_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11954_phi_fu_9864_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11955_phi_fu_9876_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11956_phi_fu_9888_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11957_phi_fu_9900_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11958_phi_fu_9912_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11959_phi_fu_9924_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11960_phi_fu_9936_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11961_phi_fu_9948_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11962_phi_fu_9960_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11963_phi_fu_9972_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11964_phi_fu_9984_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11965_phi_fu_9996_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11966_phi_fu_10008_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11967_phi_fu_10020_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11968_phi_fu_10032_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11969_phi_fu_10044_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11970_phi_fu_10056_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11971_phi_fu_10068_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11972_phi_fu_10080_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11973_phi_fu_10092_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11974_phi_fu_10104_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11975_phi_fu_10116_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11976_phi_fu_10128_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11977_phi_fu_10140_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11978_phi_fu_10152_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11979_phi_fu_10164_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11980_phi_fu_10176_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11981_phi_fu_10188_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11982_phi_fu_10200_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11983_phi_fu_10212_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11984_phi_fu_10224_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11985_phi_fu_10236_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11986_phi_fu_10248_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11987_phi_fu_10260_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11988_phi_fu_10272_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11989_phi_fu_10284_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11990_phi_fu_10296_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11991_phi_fu_10308_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11992_phi_fu_10320_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11993_phi_fu_10332_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11994_phi_fu_10344_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11995_phi_fu_10356_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11996_phi_fu_10368_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11997_phi_fu_10380_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11998_phi_fu_10392_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11999_phi_fu_10404_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12000_phi_fu_10416_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12001_phi_fu_10428_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12002_phi_fu_10440_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12003_phi_fu_10452_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12004_phi_fu_10464_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12005_phi_fu_10476_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12006_phi_fu_10488_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12007_phi_fu_10500_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12008_phi_fu_10512_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12009_phi_fu_10524_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12010_phi_fu_10536_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12011_phi_fu_10548_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12012_phi_fu_10560_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12013_phi_fu_10572_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12014_phi_fu_10584_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12015_phi_fu_10596_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12016_phi_fu_10608_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12017_phi_fu_10620_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12018_phi_fu_10632_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12019_phi_fu_10644_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12020_phi_fu_10656_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12021_phi_fu_10668_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12022_phi_fu_10680_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12023_phi_fu_10692_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12024_phi_fu_10704_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12025_phi_fu_10716_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12026_phi_fu_10728_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12027_phi_fu_10740_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12028_phi_fu_10752_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12029_phi_fu_10764_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12030_phi_fu_10776_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12031_phi_fu_10788_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12032_phi_fu_10800_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12033_phi_fu_10812_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12034_phi_fu_10824_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12035_phi_fu_10836_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12036_phi_fu_10848_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12037_phi_fu_10860_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12038_phi_fu_10872_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12039_phi_fu_10884_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12040_phi_fu_10896_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12041_phi_fu_10908_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12042_phi_fu_10920_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12043_phi_fu_10932_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12044_phi_fu_10944_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12045_phi_fu_10956_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12046_phi_fu_10968_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12047_phi_fu_10980_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12048_phi_fu_10992_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12049_phi_fu_11004_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12050_phi_fu_11016_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12051_phi_fu_11028_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12052_phi_fu_11040_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12053_phi_fu_11052_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12054_phi_fu_11064_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12055_phi_fu_11076_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12056_phi_fu_11088_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12057_phi_fu_11100_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12058_phi_fu_11112_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12059_phi_fu_11124_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12060_phi_fu_11136_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12061_phi_fu_11148_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12062_phi_fu_11160_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12063_phi_fu_11172_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12064_phi_fu_11184_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12065_phi_fu_11196_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12066_phi_fu_11208_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12067_phi_fu_11220_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12068_phi_fu_11232_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12069_phi_fu_11244_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12070_phi_fu_11256_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12071_phi_fu_11268_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12072_phi_fu_11280_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12073_phi_fu_11292_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12074_phi_fu_11304_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12075_phi_fu_11316_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12076_phi_fu_11328_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12077_phi_fu_11340_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12078_phi_fu_11352_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12079_phi_fu_11364_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12080_phi_fu_11376_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12081_phi_fu_11388_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12082_phi_fu_11400_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12083_phi_fu_11412_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12084_phi_fu_11424_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12085_phi_fu_11436_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12086_phi_fu_11448_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12087_phi_fu_11460_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12088_phi_fu_11472_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12089_phi_fu_11484_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12090_phi_fu_11496_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12091_phi_fu_11508_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12092_phi_fu_11520_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12093_phi_fu_11532_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12094_phi_fu_11544_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12095_phi_fu_11556_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12096_phi_fu_11568_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12097_phi_fu_11580_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12098_phi_fu_11592_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12099_phi_fu_11604_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12100_phi_fu_11616_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12101_phi_fu_11628_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12102_phi_fu_11640_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12103_phi_fu_11652_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12104_phi_fu_11664_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12105_phi_fu_11676_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12106_phi_fu_11688_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12107_phi_fu_11700_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12108_phi_fu_11712_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12109_phi_fu_11724_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12110_phi_fu_11736_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12111_phi_fu_11748_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12112_phi_fu_11760_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12113_phi_fu_11772_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12114_phi_fu_11784_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12115_phi_fu_11796_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12116_phi_fu_11808_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12117_phi_fu_11820_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12118_phi_fu_11832_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12119_phi_fu_11844_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12120_phi_fu_11856_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12121_phi_fu_11868_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12122_phi_fu_11880_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12123_phi_fu_11892_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12124_phi_fu_11904_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12125_phi_fu_11916_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12126_phi_fu_11928_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12127_phi_fu_11940_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12128_phi_fu_11952_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12129_phi_fu_11964_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12130_phi_fu_11976_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12131_phi_fu_11988_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12132_phi_fu_12000_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12133_phi_fu_12012_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12134_phi_fu_12024_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12135_phi_fu_12036_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12136_phi_fu_12048_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12137_phi_fu_12060_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12138_phi_fu_12072_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12139_phi_fu_12084_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12140_phi_fu_12096_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12141_phi_fu_12108_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12142_phi_fu_12120_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12143_phi_fu_12132_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12144_phi_fu_12144_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12145_phi_fu_12156_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12146_phi_fu_12168_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12147_phi_fu_12180_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12148_phi_fu_12192_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12149_phi_fu_12204_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12150_phi_fu_12216_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12151_phi_fu_12228_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12152_phi_fu_12240_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12153_phi_fu_12252_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12154_phi_fu_12264_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12155_phi_fu_12276_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12156_phi_fu_12288_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12157_phi_fu_12300_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12158_phi_fu_12312_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12159_phi_fu_12324_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12160_phi_fu_12336_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12161_phi_fu_12348_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12162_phi_fu_12360_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12163_phi_fu_12372_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12164_phi_fu_12384_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12165_phi_fu_12396_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12166_phi_fu_12408_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12167_phi_fu_12420_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12168_phi_fu_12432_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12169_phi_fu_12444_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12170_phi_fu_12456_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12171_phi_fu_12468_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12172_phi_fu_12480_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12173_phi_fu_12492_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12174_phi_fu_12504_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12175_phi_fu_12516_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12176_phi_fu_12528_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12177_phi_fu_12540_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12178_phi_fu_12552_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12179_phi_fu_12564_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12180_phi_fu_12576_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12181_phi_fu_12588_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12182_phi_fu_12600_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12183_phi_fu_12612_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12184_phi_fu_12624_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12185_phi_fu_12636_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12186_phi_fu_12648_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12187_phi_fu_12660_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12188_phi_fu_12672_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12189_phi_fu_12684_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12190_phi_fu_12696_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12191_phi_fu_12708_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12192_phi_fu_12720_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12193_phi_fu_12732_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12194_phi_fu_12744_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12195_phi_fu_12756_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12196_phi_fu_12768_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12197_phi_fu_12780_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12198_phi_fu_12792_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12199_phi_fu_12804_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12200_phi_fu_12816_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12201_phi_fu_12828_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12202_phi_fu_12840_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12203_phi_fu_12852_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12204_phi_fu_12864_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12205_phi_fu_12876_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12206_phi_fu_12888_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12207_phi_fu_12900_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12208_phi_fu_12912_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12209_phi_fu_12924_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12210_phi_fu_12936_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12211_phi_fu_12948_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12212_phi_fu_12960_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12213_phi_fu_12972_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12214_phi_fu_12984_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12215_phi_fu_12996_p4 | 9| 2| 16| 32| + |ap_phi_mux_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12216_phi_fu_13008_p4 | 9| 2| 16| 32| + |ap_phi_mux_res_0_0_i19_phi_fu_13140_p6 | 9| 2| 40| 80| + |ap_phi_mux_res_10_0_i9_phi_fu_13280_p6 | 9| 2| 40| 80| + |ap_phi_mux_res_11_0_i8_phi_fu_13294_p6 | 9| 2| 40| 80| + |ap_phi_mux_res_12_0_i7_phi_fu_13308_p6 | 9| 2| 40| 80| + |ap_phi_mux_res_13_0_i6_phi_fu_13322_p6 | 9| 2| 40| 80| + |ap_phi_mux_res_1445_0_i5_phi_fu_13336_p6 | 9| 2| 40| 80| + |ap_phi_mux_res_15_0_i4_phi_fu_13350_p6 | 9| 2| 33| 66| + |ap_phi_mux_res_1_0_i18_phi_fu_13154_p6 | 9| 2| 40| 80| + |ap_phi_mux_res_2_0_i17_phi_fu_13168_p6 | 9| 2| 40| 80| + |ap_phi_mux_res_3_0_i16_phi_fu_13182_p6 | 9| 2| 40| 80| + |ap_phi_mux_res_4_0_i15_phi_fu_13196_p6 | 9| 2| 40| 80| + |ap_phi_mux_res_5_0_i14_phi_fu_13210_p6 | 9| 2| 40| 80| + |ap_phi_mux_res_6_0_i13_phi_fu_13224_p6 | 9| 2| 40| 80| + |ap_phi_mux_res_7_0_i12_phi_fu_13238_p6 | 9| 2| 40| 80| + |ap_phi_mux_res_8_0_i11_phi_fu_13252_p6 | 9| 2| 40| 80| + |ap_phi_mux_res_9_0_i10_phi_fu_13266_p6 | 9| 2| 40| 80| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_219_phi_fu_13020_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_220_phi_fu_13032_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_221_phi_fu_13044_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_222_phi_fu_13056_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_223_phi_fu_13068_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_224_phi_fu_13080_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_225_phi_fu_13092_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_226_phi_fu_13104_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_227_phi_fu_13116_p4 | 9| 2| 16| 32| + |ap_phi_mux_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_228_phi_fu_13128_p4 | 9| 2| 16| 32| + |ap_phi_mux_w_index3_phi_fu_1893_p6 | 14| 3| 9| 27| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11795_reg_7952 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11796_reg_7964 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11797_reg_7976 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11798_reg_7988 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11799_reg_8000 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11800_reg_8012 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11801_reg_8024 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11802_reg_8036 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11803_reg_8048 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11804_reg_8060 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11805_reg_8072 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11806_reg_8084 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11807_reg_8096 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11808_reg_8108 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11809_reg_8120 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11810_reg_8132 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11811_reg_8144 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11812_reg_8156 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11813_reg_8168 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11814_reg_8180 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11815_reg_8192 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11816_reg_8204 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11817_reg_8216 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11818_reg_8228 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11819_reg_8240 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11820_reg_8252 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11821_reg_8264 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11822_reg_8276 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11823_reg_8288 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11824_reg_8300 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11825_reg_8312 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11826_reg_8324 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11827_reg_8336 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11828_reg_8348 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11829_reg_8360 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11830_reg_8372 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11831_reg_8384 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11832_reg_8396 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11833_reg_8408 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11834_reg_8420 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11835_reg_8432 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11836_reg_8444 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11837_reg_8456 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11838_reg_8468 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11839_reg_8480 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11840_reg_8492 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11841_reg_8504 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11842_reg_8516 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11843_reg_8528 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11844_reg_8540 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11845_reg_8552 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11846_reg_8564 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11847_reg_8576 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11848_reg_8588 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11849_reg_8600 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11850_reg_8612 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11851_reg_8624 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11852_reg_8636 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11853_reg_8648 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11854_reg_8660 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11855_reg_8672 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11856_reg_8684 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11857_reg_8696 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11858_reg_8708 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11859_reg_8720 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11860_reg_8732 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11861_reg_8744 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11862_reg_8756 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11863_reg_8768 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11864_reg_8780 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11865_reg_8792 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11866_reg_8804 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11867_reg_8816 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11868_reg_8828 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11869_reg_8840 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11870_reg_8852 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11871_reg_8864 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11872_reg_8876 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11873_reg_8888 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11874_reg_8900 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11875_reg_8912 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11876_reg_8924 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11877_reg_8936 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11878_reg_8948 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11879_reg_8960 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11880_reg_8972 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11881_reg_8984 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11882_reg_8996 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11883_reg_9008 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11884_reg_9020 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11885_reg_9032 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11886_reg_9044 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11887_reg_9056 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11888_reg_9068 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11889_reg_9080 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11890_reg_9092 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11891_reg_9104 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11892_reg_9116 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11893_reg_9128 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11894_reg_9140 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11895_reg_9152 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11896_reg_9164 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11897_reg_9176 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11898_reg_9188 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11899_reg_9200 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11900_reg_9212 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11901_reg_9224 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11902_reg_9236 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11903_reg_9248 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11904_reg_9260 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11905_reg_9272 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11906_reg_9284 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11907_reg_9296 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11908_reg_9308 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11909_reg_9320 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11910_reg_9332 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11911_reg_9344 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11912_reg_9356 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11913_reg_9368 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11914_reg_9380 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11915_reg_9392 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11916_reg_9404 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11917_reg_9416 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11918_reg_9428 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11919_reg_9440 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11920_reg_9452 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11921_reg_9464 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11922_reg_9476 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11923_reg_9488 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11924_reg_9500 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11925_reg_9512 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11926_reg_9524 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11927_reg_9536 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11928_reg_9548 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11929_reg_9560 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11930_reg_9572 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11931_reg_9584 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11932_reg_9596 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11933_reg_9608 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11934_reg_9620 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11935_reg_9632 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11936_reg_9644 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11937_reg_9656 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11938_reg_9668 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11939_reg_9680 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11940_reg_9692 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11941_reg_9704 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11942_reg_9716 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11943_reg_9728 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11944_reg_9740 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11945_reg_9752 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11946_reg_9764 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11947_reg_9776 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11948_reg_9788 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11949_reg_9800 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11950_reg_9812 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11951_reg_9824 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11952_reg_9836 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11953_reg_9848 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11954_reg_9860 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11955_reg_9872 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11956_reg_9884 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11957_reg_9896 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11958_reg_9908 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11959_reg_9920 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11960_reg_9932 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11961_reg_9944 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11962_reg_9956 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11963_reg_9968 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11964_reg_9980 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11965_reg_9992 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11966_reg_10004 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11967_reg_10016 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11968_reg_10028 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11969_reg_10040 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11970_reg_10052 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11971_reg_10064 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11972_reg_10076 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11973_reg_10088 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11974_reg_10100 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11975_reg_10112 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11976_reg_10124 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11977_reg_10136 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11978_reg_10148 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11979_reg_10160 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11980_reg_10172 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11981_reg_10184 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11982_reg_10196 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11983_reg_10208 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11984_reg_10220 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11985_reg_10232 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11986_reg_10244 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11987_reg_10256 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11988_reg_10268 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11989_reg_10280 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11990_reg_10292 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11991_reg_10304 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11992_reg_10316 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11993_reg_10328 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11994_reg_10340 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11995_reg_10352 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11996_reg_10364 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11997_reg_10376 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11998_reg_10388 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11999_reg_10400 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12000_reg_10412 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12001_reg_10424 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12002_reg_10436 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12003_reg_10448 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12004_reg_10460 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12005_reg_10472 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12006_reg_10484 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12007_reg_10496 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12008_reg_10508 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12009_reg_10520 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12010_reg_10532 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12011_reg_10544 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12012_reg_10556 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12013_reg_10568 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12014_reg_10580 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12015_reg_10592 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12016_reg_10604 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12017_reg_10616 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12018_reg_10628 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12019_reg_10640 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12020_reg_10652 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12021_reg_10664 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12022_reg_10676 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12023_reg_10688 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12024_reg_10700 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12025_reg_10712 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12026_reg_10724 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12027_reg_10736 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12028_reg_10748 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12029_reg_10760 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12030_reg_10772 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12031_reg_10784 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12032_reg_10796 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12033_reg_10808 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12034_reg_10820 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12035_reg_10832 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12036_reg_10844 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12037_reg_10856 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12038_reg_10868 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12039_reg_10880 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12040_reg_10892 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12041_reg_10904 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12042_reg_10916 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12043_reg_10928 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12044_reg_10940 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12045_reg_10952 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12046_reg_10964 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12047_reg_10976 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12048_reg_10988 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12049_reg_11000 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12050_reg_11012 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12051_reg_11024 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12052_reg_11036 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12053_reg_11048 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12054_reg_11060 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12055_reg_11072 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12056_reg_11084 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12057_reg_11096 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12058_reg_11108 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12059_reg_11120 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12060_reg_11132 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12061_reg_11144 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12062_reg_11156 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12063_reg_11168 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12064_reg_11180 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12065_reg_11192 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12066_reg_11204 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12067_reg_11216 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12068_reg_11228 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12069_reg_11240 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12070_reg_11252 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12071_reg_11264 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12072_reg_11276 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12073_reg_11288 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12074_reg_11300 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12075_reg_11312 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12076_reg_11324 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12077_reg_11336 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12078_reg_11348 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12079_reg_11360 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12080_reg_11372 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12081_reg_11384 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12082_reg_11396 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12083_reg_11408 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12084_reg_11420 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12085_reg_11432 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12086_reg_11444 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12087_reg_11456 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12088_reg_11468 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12089_reg_11480 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12090_reg_11492 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12091_reg_11504 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12092_reg_11516 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12093_reg_11528 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12094_reg_11540 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12095_reg_11552 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12096_reg_11564 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12097_reg_11576 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12098_reg_11588 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12099_reg_11600 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12100_reg_11612 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12101_reg_11624 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12102_reg_11636 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12103_reg_11648 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12104_reg_11660 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12105_reg_11672 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12106_reg_11684 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12107_reg_11696 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12108_reg_11708 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12109_reg_11720 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12110_reg_11732 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12111_reg_11744 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12112_reg_11756 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12113_reg_11768 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12114_reg_11780 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12115_reg_11792 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12116_reg_11804 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12117_reg_11816 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12118_reg_11828 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12119_reg_11840 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12120_reg_11852 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12121_reg_11864 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12122_reg_11876 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12123_reg_11888 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12124_reg_11900 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12125_reg_11912 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12126_reg_11924 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12127_reg_11936 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12128_reg_11948 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12129_reg_11960 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12130_reg_11972 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12131_reg_11984 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12132_reg_11996 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12133_reg_12008 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12134_reg_12020 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12135_reg_12032 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12136_reg_12044 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12137_reg_12056 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12138_reg_12068 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12139_reg_12080 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12140_reg_12092 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12141_reg_12104 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12142_reg_12116 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12143_reg_12128 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12144_reg_12140 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12145_reg_12152 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12146_reg_12164 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12147_reg_12176 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12148_reg_12188 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12149_reg_12200 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12150_reg_12212 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12151_reg_12224 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12152_reg_12236 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12153_reg_12248 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12154_reg_12260 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12155_reg_12272 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12156_reg_12284 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12157_reg_12296 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12158_reg_12308 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12159_reg_12320 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12160_reg_12332 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12161_reg_12344 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12162_reg_12356 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12163_reg_12368 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12164_reg_12380 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12165_reg_12392 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12166_reg_12404 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12167_reg_12416 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12168_reg_12428 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12169_reg_12440 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12170_reg_12452 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12171_reg_12464 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12172_reg_12476 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12173_reg_12488 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12174_reg_12500 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12175_reg_12512 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12176_reg_12524 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12177_reg_12536 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12178_reg_12548 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12179_reg_12560 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12180_reg_12572 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12181_reg_12584 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12182_reg_12596 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12183_reg_12608 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12184_reg_12620 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12185_reg_12632 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12186_reg_12644 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12187_reg_12656 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12188_reg_12668 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12189_reg_12680 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12190_reg_12692 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12191_reg_12704 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12192_reg_12716 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12193_reg_12728 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12194_reg_12740 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12195_reg_12752 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12196_reg_12764 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12197_reg_12776 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12198_reg_12788 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12199_reg_12800 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12200_reg_12812 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12201_reg_12824 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12202_reg_12836 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12203_reg_12848 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12204_reg_12860 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12205_reg_12872 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12206_reg_12884 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12207_reg_12896 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12208_reg_12908 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12209_reg_12920 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12210_reg_12932 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12211_reg_12944 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12212_reg_12956 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12213_reg_12968 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12214_reg_12980 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12215_reg_12992 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12216_reg_13004 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_219_reg_13016 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_220_reg_13028 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_221_reg_13040 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_222_reg_13052 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_223_reg_13064 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_224_reg_13076 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_225_reg_13088 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_226_reg_13100 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_227_reg_13112 | 9| 2| 16| 32| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_228_reg_13124 | 9| 2| 16| 32| + |ap_return_0 | 9| 2| 42| 84| + |ap_return_1 | 9| 2| 42| 84| + |ap_return_10 | 9| 2| 42| 84| + |ap_return_11 | 9| 2| 42| 84| + |ap_return_12 | 9| 2| 42| 84| + |ap_return_13 | 9| 2| 42| 84| + |ap_return_14 | 9| 2| 42| 84| + |ap_return_15 | 9| 2| 42| 84| + |ap_return_2 | 9| 2| 42| 84| + |ap_return_3 | 9| 2| 42| 84| + |ap_return_4 | 9| 2| 42| 84| + |ap_return_5 | 9| 2| 42| 84| + |ap_return_6 | 9| 2| 42| 84| + |ap_return_7 | 9| 2| 42| 84| + |ap_return_8 | 9| 2| 42| 84| + |ap_return_9 | 9| 2| 42| 84| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11795_reg_7952 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11796_reg_7964 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11797_reg_7976 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11798_reg_7988 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11799_reg_8000 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11800_reg_8012 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11801_reg_8024 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11802_reg_8036 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11803_reg_8048 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11804_reg_8060 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11805_reg_8072 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11806_reg_8084 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11807_reg_8096 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11808_reg_8108 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11809_reg_8120 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11810_reg_8132 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11811_reg_8144 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11812_reg_8156 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11813_reg_8168 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11814_reg_8180 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11815_reg_8192 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11816_reg_8204 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11817_reg_8216 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11818_reg_8228 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11819_reg_8240 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11820_reg_8252 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11821_reg_8264 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11822_reg_8276 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11823_reg_8288 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11824_reg_8300 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11825_reg_8312 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11826_reg_8324 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11827_reg_8336 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11828_reg_8348 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11829_reg_8360 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11830_reg_8372 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11831_reg_8384 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11832_reg_8396 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11833_reg_8408 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11834_reg_8420 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11835_reg_8432 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11836_reg_8444 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11837_reg_8456 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11838_reg_8468 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11839_reg_8480 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11840_reg_8492 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11841_reg_8504 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11842_reg_8516 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11843_reg_8528 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11844_reg_8540 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11845_reg_8552 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11846_reg_8564 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11847_reg_8576 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11848_reg_8588 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11849_reg_8600 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11850_reg_8612 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11851_reg_8624 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11852_reg_8636 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11853_reg_8648 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11854_reg_8660 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11855_reg_8672 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11856_reg_8684 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11857_reg_8696 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11858_reg_8708 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11859_reg_8720 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11860_reg_8732 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11861_reg_8744 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11862_reg_8756 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11863_reg_8768 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11864_reg_8780 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11865_reg_8792 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11866_reg_8804 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11867_reg_8816 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11868_reg_8828 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11869_reg_8840 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11870_reg_8852 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11871_reg_8864 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11872_reg_8876 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11873_reg_8888 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11874_reg_8900 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11875_reg_8912 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11876_reg_8924 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11877_reg_8936 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11878_reg_8948 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11879_reg_8960 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11880_reg_8972 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11881_reg_8984 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11882_reg_8996 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11883_reg_9008 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11884_reg_9020 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11885_reg_9032 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11886_reg_9044 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11887_reg_9056 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11888_reg_9068 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11889_reg_9080 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11890_reg_9092 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11891_reg_9104 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11892_reg_9116 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11893_reg_9128 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11894_reg_9140 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11895_reg_9152 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11896_reg_9164 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11897_reg_9176 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11898_reg_9188 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11899_reg_9200 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11900_reg_9212 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11901_reg_9224 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11902_reg_9236 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11903_reg_9248 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11904_reg_9260 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11905_reg_9272 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11906_reg_9284 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11907_reg_9296 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11908_reg_9308 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11909_reg_9320 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11910_reg_9332 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11911_reg_9344 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11912_reg_9356 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11913_reg_9368 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11914_reg_9380 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11915_reg_9392 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11916_reg_9404 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11917_reg_9416 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11918_reg_9428 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11919_reg_9440 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11920_reg_9452 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11921_reg_9464 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11922_reg_9476 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11923_reg_9488 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11924_reg_9500 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11925_reg_9512 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11926_reg_9524 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11927_reg_9536 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11928_reg_9548 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11929_reg_9560 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11930_reg_9572 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11931_reg_9584 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11932_reg_9596 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11933_reg_9608 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11934_reg_9620 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11935_reg_9632 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11936_reg_9644 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11937_reg_9656 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11938_reg_9668 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11939_reg_9680 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11940_reg_9692 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11941_reg_9704 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11942_reg_9716 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11943_reg_9728 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11944_reg_9740 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11945_reg_9752 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11946_reg_9764 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11947_reg_9776 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11948_reg_9788 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11949_reg_9800 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11950_reg_9812 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11951_reg_9824 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11952_reg_9836 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11953_reg_9848 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11954_reg_9860 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11955_reg_9872 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11956_reg_9884 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11957_reg_9896 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11958_reg_9908 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11959_reg_9920 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11960_reg_9932 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11961_reg_9944 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11962_reg_9956 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11963_reg_9968 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11964_reg_9980 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11965_reg_9992 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11966_reg_10004 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11967_reg_10016 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11968_reg_10028 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11969_reg_10040 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11970_reg_10052 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11971_reg_10064 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11972_reg_10076 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11973_reg_10088 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11974_reg_10100 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11975_reg_10112 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11976_reg_10124 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11977_reg_10136 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11978_reg_10148 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11979_reg_10160 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11980_reg_10172 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11981_reg_10184 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11982_reg_10196 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11983_reg_10208 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11984_reg_10220 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11985_reg_10232 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11986_reg_10244 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11987_reg_10256 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11988_reg_10268 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11989_reg_10280 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11990_reg_10292 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11991_reg_10304 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11992_reg_10316 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11993_reg_10328 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11994_reg_10340 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11995_reg_10352 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11996_reg_10364 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11997_reg_10376 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11998_reg_10388 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11999_reg_10400 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12000_reg_10412 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12001_reg_10424 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12002_reg_10436 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12003_reg_10448 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12004_reg_10460 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12005_reg_10472 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12006_reg_10484 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12007_reg_10496 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12008_reg_10508 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12009_reg_10520 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12010_reg_10532 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12011_reg_10544 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12012_reg_10556 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12013_reg_10568 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12014_reg_10580 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12015_reg_10592 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12016_reg_10604 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12017_reg_10616 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12018_reg_10628 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12019_reg_10640 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12020_reg_10652 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12021_reg_10664 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12022_reg_10676 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12023_reg_10688 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12024_reg_10700 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12025_reg_10712 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12026_reg_10724 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12027_reg_10736 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12028_reg_10748 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12029_reg_10760 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12030_reg_10772 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12031_reg_10784 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12032_reg_10796 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12033_reg_10808 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12034_reg_10820 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12035_reg_10832 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12036_reg_10844 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12037_reg_10856 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12038_reg_10868 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12039_reg_10880 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12040_reg_10892 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12041_reg_10904 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12042_reg_10916 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12043_reg_10928 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12044_reg_10940 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12045_reg_10952 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12046_reg_10964 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12047_reg_10976 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12048_reg_10988 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12049_reg_11000 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12050_reg_11012 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12051_reg_11024 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12052_reg_11036 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12053_reg_11048 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12054_reg_11060 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12055_reg_11072 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12056_reg_11084 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12057_reg_11096 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12058_reg_11108 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12059_reg_11120 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12060_reg_11132 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12061_reg_11144 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12062_reg_11156 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12063_reg_11168 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12064_reg_11180 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12065_reg_11192 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12066_reg_11204 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12067_reg_11216 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12068_reg_11228 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12069_reg_11240 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12070_reg_11252 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12071_reg_11264 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12072_reg_11276 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12073_reg_11288 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12074_reg_11300 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12075_reg_11312 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12076_reg_11324 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12077_reg_11336 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12078_reg_11348 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12079_reg_11360 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12080_reg_11372 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12081_reg_11384 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12082_reg_11396 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12083_reg_11408 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12084_reg_11420 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12085_reg_11432 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12086_reg_11444 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12087_reg_11456 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12088_reg_11468 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12089_reg_11480 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12090_reg_11492 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12091_reg_11504 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12092_reg_11516 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12093_reg_11528 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12094_reg_11540 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12095_reg_11552 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12096_reg_11564 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12097_reg_11576 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12098_reg_11588 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12099_reg_11600 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12100_reg_11612 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12101_reg_11624 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12102_reg_11636 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12103_reg_11648 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12104_reg_11660 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12105_reg_11672 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12106_reg_11684 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12107_reg_11696 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12108_reg_11708 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12109_reg_11720 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12110_reg_11732 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12111_reg_11744 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12112_reg_11756 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12113_reg_11768 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12114_reg_11780 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12115_reg_11792 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12116_reg_11804 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12117_reg_11816 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12118_reg_11828 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12119_reg_11840 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12120_reg_11852 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12121_reg_11864 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12122_reg_11876 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12123_reg_11888 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12124_reg_11900 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12125_reg_11912 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12126_reg_11924 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12127_reg_11936 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12128_reg_11948 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12129_reg_11960 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12130_reg_11972 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12131_reg_11984 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12132_reg_11996 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12133_reg_12008 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12134_reg_12020 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12135_reg_12032 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12136_reg_12044 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12137_reg_12056 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12138_reg_12068 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12139_reg_12080 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12140_reg_12092 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12141_reg_12104 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12142_reg_12116 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12143_reg_12128 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12144_reg_12140 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12145_reg_12152 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12146_reg_12164 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12147_reg_12176 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12148_reg_12188 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12149_reg_12200 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12150_reg_12212 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12151_reg_12224 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12152_reg_12236 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12153_reg_12248 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12154_reg_12260 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12155_reg_12272 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12156_reg_12284 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12157_reg_12296 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12158_reg_12308 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12159_reg_12320 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12160_reg_12332 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12161_reg_12344 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12162_reg_12356 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12163_reg_12368 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12164_reg_12380 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12165_reg_12392 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12166_reg_12404 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12167_reg_12416 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12168_reg_12428 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12169_reg_12440 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12170_reg_12452 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12171_reg_12464 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12172_reg_12476 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12173_reg_12488 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12174_reg_12500 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12175_reg_12512 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12176_reg_12524 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12177_reg_12536 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12178_reg_12548 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12179_reg_12560 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12180_reg_12572 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12181_reg_12584 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12182_reg_12596 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12183_reg_12608 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12184_reg_12620 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12185_reg_12632 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12186_reg_12644 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12187_reg_12656 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12188_reg_12668 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12189_reg_12680 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12190_reg_12692 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12191_reg_12704 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12192_reg_12716 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12193_reg_12728 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12194_reg_12740 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12195_reg_12752 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12196_reg_12764 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12197_reg_12776 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12198_reg_12788 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12199_reg_12800 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12200_reg_12812 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12201_reg_12824 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12202_reg_12836 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12203_reg_12848 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12204_reg_12860 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12205_reg_12872 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12206_reg_12884 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12207_reg_12896 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12208_reg_12908 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12209_reg_12920 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12210_reg_12932 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12211_reg_12944 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12212_reg_12956 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12213_reg_12968 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12214_reg_12980 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12215_reg_12992 | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12216_reg_13004 | 9| 2| 16| 32| + |res_0_0_i19_reg_13136 | 9| 2| 40| 80| + |res_10_0_i9_reg_13276 | 9| 2| 40| 80| + |res_11_0_i8_reg_13290 | 9| 2| 40| 80| + |res_12_0_i7_reg_13304 | 9| 2| 40| 80| + |res_13_0_i6_reg_13318 | 9| 2| 40| 80| + |res_1445_0_i5_reg_13332 | 9| 2| 40| 80| + |res_15_0_i4_reg_13346 | 9| 2| 33| 66| + |res_1_0_i18_reg_13150 | 9| 2| 40| 80| + |res_2_0_i17_reg_13164 | 9| 2| 40| 80| + |res_3_0_i16_reg_13178 | 9| 2| 40| 80| + |res_4_0_i15_reg_13192 | 9| 2| 40| 80| + |res_5_0_i14_reg_13206 | 9| 2| 40| 80| + |res_6_0_i13_reg_13220 | 9| 2| 40| 80| + |res_7_0_i12_reg_13234 | 9| 2| 40| 80| + |res_8_0_i11_reg_13248 | 9| 2| 40| 80| + |res_9_0_i10_reg_13262 | 9| 2| 40| 80| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_219_reg_13016 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_220_reg_13028 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_221_reg_13040 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_222_reg_13052 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_223_reg_13064 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_224_reg_13076 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_225_reg_13088 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_226_reg_13100 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_227_reg_13112 | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_228_reg_13124 | 9| 2| 16| 32| + |w_index3_reg_1890 | 9| 2| 9| 18| + +------------------------------------------------------------------------------------------------------------------------+-----+-----------+-----+-----------+ + |Total |12151| 2700|22695| 45400| + +------------------------------------------------------------------------------------------------------------------------+-----+-----------+-----+-----------+ + + * Register: + +------------------------------------------------------------------------------------------------------------------------+-----+----+-----+-----------+ + | Name | FF | LUT| Bits| Const Bits| + +------------------------------------------------------------------------------------------------------------------------+-----+----+-----+-----------+ + |a_reg_19515 | 16| 0| 16| 0| + |ap_CS_fsm | 1| 0| 1| 0| + |ap_done_reg | 1| 0| 1| 0| + |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| + |ap_enable_reg_pp0_iter2 | 1| 0| 1| 0| + |ap_loop_exit_ready_pp0_iter1_reg | 1| 0| 1| 0| + |ap_loop_exit_ready_pp0_iter2_reg | 1| 0| 1| 0| + |ap_loop_init_pp0_iter1_reg | 1| 0| 1| 0| + |ap_loop_init_pp0_iter2_reg | 1| 0| 1| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11795_reg_7952 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11796_reg_7964 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11797_reg_7976 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11798_reg_7988 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11799_reg_8000 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11800_reg_8012 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11801_reg_8024 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11802_reg_8036 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11803_reg_8048 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11804_reg_8060 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11805_reg_8072 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11806_reg_8084 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11807_reg_8096 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11808_reg_8108 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11809_reg_8120 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11810_reg_8132 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11811_reg_8144 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11812_reg_8156 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11813_reg_8168 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11814_reg_8180 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11815_reg_8192 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11816_reg_8204 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11817_reg_8216 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11818_reg_8228 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11819_reg_8240 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11820_reg_8252 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11821_reg_8264 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11822_reg_8276 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11823_reg_8288 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11824_reg_8300 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11825_reg_8312 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11826_reg_8324 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11827_reg_8336 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11828_reg_8348 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11829_reg_8360 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11830_reg_8372 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11831_reg_8384 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11832_reg_8396 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11833_reg_8408 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11834_reg_8420 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11835_reg_8432 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11836_reg_8444 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11837_reg_8456 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11838_reg_8468 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11839_reg_8480 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11840_reg_8492 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11841_reg_8504 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11842_reg_8516 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11843_reg_8528 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11844_reg_8540 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11845_reg_8552 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11846_reg_8564 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11847_reg_8576 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11848_reg_8588 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11849_reg_8600 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11850_reg_8612 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11851_reg_8624 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11852_reg_8636 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11853_reg_8648 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11854_reg_8660 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11855_reg_8672 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11856_reg_8684 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11857_reg_8696 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11858_reg_8708 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11859_reg_8720 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11860_reg_8732 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11861_reg_8744 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11862_reg_8756 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11863_reg_8768 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11864_reg_8780 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11865_reg_8792 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11866_reg_8804 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11867_reg_8816 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11868_reg_8828 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11869_reg_8840 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11870_reg_8852 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11871_reg_8864 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11872_reg_8876 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11873_reg_8888 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11874_reg_8900 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11875_reg_8912 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11876_reg_8924 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11877_reg_8936 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11878_reg_8948 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11879_reg_8960 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11880_reg_8972 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11881_reg_8984 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11882_reg_8996 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11883_reg_9008 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11884_reg_9020 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11885_reg_9032 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11886_reg_9044 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11887_reg_9056 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11888_reg_9068 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11889_reg_9080 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11890_reg_9092 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11891_reg_9104 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11892_reg_9116 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11893_reg_9128 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11894_reg_9140 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11895_reg_9152 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11896_reg_9164 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11897_reg_9176 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11898_reg_9188 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11899_reg_9200 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11900_reg_9212 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11901_reg_9224 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11902_reg_9236 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11903_reg_9248 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11904_reg_9260 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11905_reg_9272 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11906_reg_9284 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11907_reg_9296 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11908_reg_9308 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11909_reg_9320 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11910_reg_9332 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11911_reg_9344 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11912_reg_9356 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11913_reg_9368 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11914_reg_9380 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11915_reg_9392 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11916_reg_9404 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11917_reg_9416 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11918_reg_9428 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11919_reg_9440 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11920_reg_9452 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11921_reg_9464 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11922_reg_9476 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11923_reg_9488 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11924_reg_9500 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11925_reg_9512 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11926_reg_9524 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11927_reg_9536 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11928_reg_9548 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11929_reg_9560 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11930_reg_9572 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11931_reg_9584 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11932_reg_9596 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11933_reg_9608 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11934_reg_9620 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11935_reg_9632 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11936_reg_9644 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11937_reg_9656 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11938_reg_9668 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11939_reg_9680 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11940_reg_9692 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11941_reg_9704 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11942_reg_9716 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11943_reg_9728 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11944_reg_9740 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11945_reg_9752 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11946_reg_9764 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11947_reg_9776 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11948_reg_9788 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11949_reg_9800 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11950_reg_9812 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11951_reg_9824 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11952_reg_9836 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11953_reg_9848 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11954_reg_9860 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11955_reg_9872 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11956_reg_9884 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11957_reg_9896 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11958_reg_9908 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11959_reg_9920 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11960_reg_9932 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11961_reg_9944 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11962_reg_9956 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11963_reg_9968 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11964_reg_9980 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11965_reg_9992 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11966_reg_10004 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11967_reg_10016 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11968_reg_10028 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11969_reg_10040 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11970_reg_10052 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11971_reg_10064 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11972_reg_10076 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11973_reg_10088 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11974_reg_10100 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11975_reg_10112 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11976_reg_10124 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11977_reg_10136 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11978_reg_10148 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11979_reg_10160 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11980_reg_10172 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11981_reg_10184 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11982_reg_10196 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11983_reg_10208 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11984_reg_10220 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11985_reg_10232 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11986_reg_10244 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11987_reg_10256 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11988_reg_10268 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11989_reg_10280 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11990_reg_10292 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11991_reg_10304 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11992_reg_10316 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11993_reg_10328 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11994_reg_10340 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11995_reg_10352 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11996_reg_10364 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11997_reg_10376 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11998_reg_10388 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11999_reg_10400 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12000_reg_10412 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12001_reg_10424 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12002_reg_10436 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12003_reg_10448 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12004_reg_10460 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12005_reg_10472 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12006_reg_10484 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12007_reg_10496 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12008_reg_10508 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12009_reg_10520 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12010_reg_10532 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12011_reg_10544 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12012_reg_10556 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12013_reg_10568 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12014_reg_10580 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12015_reg_10592 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12016_reg_10604 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12017_reg_10616 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12018_reg_10628 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12019_reg_10640 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12020_reg_10652 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12021_reg_10664 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12022_reg_10676 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12023_reg_10688 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12024_reg_10700 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12025_reg_10712 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12026_reg_10724 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12027_reg_10736 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12028_reg_10748 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12029_reg_10760 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12030_reg_10772 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12031_reg_10784 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12032_reg_10796 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12033_reg_10808 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12034_reg_10820 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12035_reg_10832 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12036_reg_10844 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12037_reg_10856 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12038_reg_10868 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12039_reg_10880 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12040_reg_10892 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12041_reg_10904 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12042_reg_10916 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12043_reg_10928 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12044_reg_10940 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12045_reg_10952 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12046_reg_10964 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12047_reg_10976 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12048_reg_10988 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12049_reg_11000 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12050_reg_11012 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12051_reg_11024 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12052_reg_11036 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12053_reg_11048 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12054_reg_11060 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12055_reg_11072 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12056_reg_11084 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12057_reg_11096 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12058_reg_11108 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12059_reg_11120 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12060_reg_11132 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12061_reg_11144 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12062_reg_11156 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12063_reg_11168 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12064_reg_11180 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12065_reg_11192 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12066_reg_11204 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12067_reg_11216 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12068_reg_11228 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12069_reg_11240 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12070_reg_11252 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12071_reg_11264 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12072_reg_11276 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12073_reg_11288 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12074_reg_11300 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12075_reg_11312 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12076_reg_11324 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12077_reg_11336 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12078_reg_11348 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12079_reg_11360 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12080_reg_11372 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12081_reg_11384 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12082_reg_11396 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12083_reg_11408 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12084_reg_11420 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12085_reg_11432 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12086_reg_11444 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12087_reg_11456 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12088_reg_11468 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12089_reg_11480 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12090_reg_11492 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12091_reg_11504 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12092_reg_11516 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12093_reg_11528 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12094_reg_11540 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12095_reg_11552 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12096_reg_11564 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12097_reg_11576 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12098_reg_11588 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12099_reg_11600 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12100_reg_11612 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12101_reg_11624 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12102_reg_11636 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12103_reg_11648 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12104_reg_11660 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12105_reg_11672 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12106_reg_11684 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12107_reg_11696 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12108_reg_11708 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12109_reg_11720 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12110_reg_11732 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12111_reg_11744 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12112_reg_11756 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12113_reg_11768 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12114_reg_11780 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12115_reg_11792 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12116_reg_11804 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12117_reg_11816 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12118_reg_11828 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12119_reg_11840 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12120_reg_11852 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12121_reg_11864 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12122_reg_11876 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12123_reg_11888 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12124_reg_11900 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12125_reg_11912 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12126_reg_11924 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12127_reg_11936 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12128_reg_11948 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12129_reg_11960 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12130_reg_11972 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12131_reg_11984 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12132_reg_11996 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12133_reg_12008 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12134_reg_12020 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12135_reg_12032 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12136_reg_12044 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12137_reg_12056 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12138_reg_12068 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12139_reg_12080 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12140_reg_12092 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12141_reg_12104 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12142_reg_12116 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12143_reg_12128 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12144_reg_12140 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12145_reg_12152 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12146_reg_12164 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12147_reg_12176 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12148_reg_12188 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12149_reg_12200 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12150_reg_12212 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12151_reg_12224 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12152_reg_12236 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12153_reg_12248 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12154_reg_12260 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12155_reg_12272 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12156_reg_12284 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12157_reg_12296 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12158_reg_12308 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12159_reg_12320 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12160_reg_12332 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12161_reg_12344 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12162_reg_12356 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12163_reg_12368 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12164_reg_12380 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12165_reg_12392 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12166_reg_12404 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12167_reg_12416 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12168_reg_12428 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12169_reg_12440 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12170_reg_12452 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12171_reg_12464 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12172_reg_12476 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12173_reg_12488 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12174_reg_12500 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12175_reg_12512 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12176_reg_12524 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12177_reg_12536 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12178_reg_12548 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12179_reg_12560 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12180_reg_12572 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12181_reg_12584 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12182_reg_12596 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12183_reg_12608 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12184_reg_12620 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12185_reg_12632 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12186_reg_12644 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12187_reg_12656 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12188_reg_12668 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12189_reg_12680 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12190_reg_12692 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12191_reg_12704 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12192_reg_12716 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12193_reg_12728 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12194_reg_12740 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12195_reg_12752 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12196_reg_12764 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12197_reg_12776 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12198_reg_12788 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12199_reg_12800 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12200_reg_12812 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12201_reg_12824 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12202_reg_12836 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12203_reg_12848 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12204_reg_12860 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12205_reg_12872 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12206_reg_12884 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12207_reg_12896 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12208_reg_12908 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12209_reg_12920 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12210_reg_12932 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12211_reg_12944 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12212_reg_12956 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12213_reg_12968 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12214_reg_12980 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12215_reg_12992 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12216_reg_13004 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_219_reg_13016 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_220_reg_13028 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_221_reg_13040 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_222_reg_13052 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_223_reg_13064 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_224_reg_13076 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_225_reg_13088 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_226_reg_13100 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_227_reg_13112 | 16| 0| 16| 0| + |ap_phi_reg_pp0_iter1_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_228_reg_13124 | 16| 0| 16| 0| + |ap_return_0_preg | 42| 0| 42| 0| + |ap_return_10_preg | 42| 0| 42| 0| + |ap_return_11_preg | 42| 0| 42| 0| + |ap_return_12_preg | 42| 0| 42| 0| + |ap_return_13_preg | 42| 0| 42| 0| + |ap_return_14_preg | 42| 0| 42| 0| + |ap_return_15_preg | 42| 0| 42| 0| + |ap_return_1_preg | 42| 0| 42| 0| + |ap_return_2_preg | 42| 0| 42| 0| + |ap_return_3_preg | 42| 0| 42| 0| + |ap_return_4_preg | 42| 0| 42| 0| + |ap_return_5_preg | 42| 0| 42| 0| + |ap_return_6_preg | 42| 0| 42| 0| + |ap_return_7_preg | 42| 0| 42| 0| + |ap_return_8_preg | 42| 0| 42| 0| + |ap_return_9_preg | 42| 0| 42| 0| + |do_init_reg_1875 | 1| 0| 1| 0| + |icmp_ln46_reg_19511 | 1| 0| 1| 0| + |icmp_ln46_reg_19511_pp0_iter1_reg | 1| 0| 1| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11795_reg_7952 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11796_reg_7964 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11797_reg_7976 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11798_reg_7988 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11799_reg_8000 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11800_reg_8012 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11801_reg_8024 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11802_reg_8036 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11803_reg_8048 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11804_reg_8060 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11805_reg_8072 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11806_reg_8084 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11807_reg_8096 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11808_reg_8108 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11809_reg_8120 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11810_reg_8132 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11811_reg_8144 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11812_reg_8156 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11813_reg_8168 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11814_reg_8180 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11815_reg_8192 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11816_reg_8204 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11817_reg_8216 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11818_reg_8228 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11819_reg_8240 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11820_reg_8252 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11821_reg_8264 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11822_reg_8276 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11823_reg_8288 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11824_reg_8300 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11825_reg_8312 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11826_reg_8324 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11827_reg_8336 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11828_reg_8348 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11829_reg_8360 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11830_reg_8372 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11831_reg_8384 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11832_reg_8396 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11833_reg_8408 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11834_reg_8420 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11835_reg_8432 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11836_reg_8444 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11837_reg_8456 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11838_reg_8468 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11839_reg_8480 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11840_reg_8492 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11841_reg_8504 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11842_reg_8516 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11843_reg_8528 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11844_reg_8540 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11845_reg_8552 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11846_reg_8564 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11847_reg_8576 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11848_reg_8588 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11849_reg_8600 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11850_reg_8612 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11851_reg_8624 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11852_reg_8636 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11853_reg_8648 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11854_reg_8660 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11855_reg_8672 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11856_reg_8684 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11857_reg_8696 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11858_reg_8708 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11859_reg_8720 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11860_reg_8732 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11861_reg_8744 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11862_reg_8756 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11863_reg_8768 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11864_reg_8780 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11865_reg_8792 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11866_reg_8804 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11867_reg_8816 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11868_reg_8828 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11869_reg_8840 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11870_reg_8852 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11871_reg_8864 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11872_reg_8876 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11873_reg_8888 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11874_reg_8900 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11875_reg_8912 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11876_reg_8924 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11877_reg_8936 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11878_reg_8948 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11879_reg_8960 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11880_reg_8972 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11881_reg_8984 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11882_reg_8996 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11883_reg_9008 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11884_reg_9020 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11885_reg_9032 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11886_reg_9044 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11887_reg_9056 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11888_reg_9068 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11889_reg_9080 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11890_reg_9092 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11891_reg_9104 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11892_reg_9116 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11893_reg_9128 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11894_reg_9140 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11895_reg_9152 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11896_reg_9164 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11897_reg_9176 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11898_reg_9188 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11899_reg_9200 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11900_reg_9212 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11901_reg_9224 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11902_reg_9236 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11903_reg_9248 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11904_reg_9260 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11905_reg_9272 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11906_reg_9284 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11907_reg_9296 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11908_reg_9308 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11909_reg_9320 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11910_reg_9332 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11911_reg_9344 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11912_reg_9356 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11913_reg_9368 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11914_reg_9380 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11915_reg_9392 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11916_reg_9404 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11917_reg_9416 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11918_reg_9428 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11919_reg_9440 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11920_reg_9452 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11921_reg_9464 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11922_reg_9476 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11923_reg_9488 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11924_reg_9500 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11925_reg_9512 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11926_reg_9524 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11927_reg_9536 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11928_reg_9548 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11929_reg_9560 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11930_reg_9572 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11931_reg_9584 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11932_reg_9596 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11933_reg_9608 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11934_reg_9620 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11935_reg_9632 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11936_reg_9644 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11937_reg_9656 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11938_reg_9668 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11939_reg_9680 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11940_reg_9692 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11941_reg_9704 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11942_reg_9716 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11943_reg_9728 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11944_reg_9740 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11945_reg_9752 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11946_reg_9764 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11947_reg_9776 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11948_reg_9788 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_11949_reg_9800 | 16| 0| 16| 0| + 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|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12022_reg_10676 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12023_reg_10688 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12024_reg_10700 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12025_reg_10712 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12026_reg_10724 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12027_reg_10736 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12028_reg_10748 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12029_reg_10760 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12030_reg_10772 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12031_reg_10784 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12032_reg_10796 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12033_reg_10808 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12034_reg_10820 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12035_reg_10832 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12036_reg_10844 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12037_reg_10856 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12038_reg_10868 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12039_reg_10880 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12040_reg_10892 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12041_reg_10904 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12042_reg_10916 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12043_reg_10928 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12044_reg_10940 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12045_reg_10952 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12046_reg_10964 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12047_reg_10976 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12048_reg_10988 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12049_reg_11000 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12050_reg_11012 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12051_reg_11024 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12052_reg_11036 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12053_reg_11048 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12054_reg_11060 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12055_reg_11072 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12056_reg_11084 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12057_reg_11096 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12058_reg_11108 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12059_reg_11120 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12060_reg_11132 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12061_reg_11144 | 16| 0| 16| 0| + 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|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12110_reg_11732 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12111_reg_11744 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12112_reg_11756 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12113_reg_11768 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12114_reg_11780 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12115_reg_11792 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12116_reg_11804 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12117_reg_11816 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12118_reg_11828 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12119_reg_11840 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12120_reg_11852 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12121_reg_11864 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12122_reg_11876 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12123_reg_11888 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12124_reg_11900 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12125_reg_11912 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12126_reg_11924 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12127_reg_11936 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12128_reg_11948 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12129_reg_11960 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12130_reg_11972 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12131_reg_11984 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12132_reg_11996 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12133_reg_12008 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12134_reg_12020 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12135_reg_12032 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12136_reg_12044 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12137_reg_12056 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12138_reg_12068 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12139_reg_12080 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12140_reg_12092 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12141_reg_12104 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12142_reg_12116 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12143_reg_12128 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12144_reg_12140 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12145_reg_12152 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12146_reg_12164 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12147_reg_12176 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12148_reg_12188 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12149_reg_12200 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12150_reg_12212 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12151_reg_12224 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12152_reg_12236 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12153_reg_12248 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12154_reg_12260 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12155_reg_12272 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12156_reg_12284 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12157_reg_12296 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12158_reg_12308 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12159_reg_12320 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12160_reg_12332 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12161_reg_12344 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12162_reg_12356 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12163_reg_12368 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12164_reg_12380 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12165_reg_12392 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12166_reg_12404 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12167_reg_12416 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12168_reg_12428 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12169_reg_12440 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12170_reg_12452 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12171_reg_12464 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12172_reg_12476 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12173_reg_12488 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12174_reg_12500 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12175_reg_12512 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12176_reg_12524 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12177_reg_12536 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12178_reg_12548 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12179_reg_12560 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12180_reg_12572 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12181_reg_12584 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12182_reg_12596 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12183_reg_12608 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12184_reg_12620 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12185_reg_12632 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12186_reg_12644 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12187_reg_12656 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12188_reg_12668 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12189_reg_12680 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12190_reg_12692 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12191_reg_12704 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12192_reg_12716 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12193_reg_12728 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12194_reg_12740 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12195_reg_12752 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12196_reg_12764 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12197_reg_12776 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12198_reg_12788 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12199_reg_12800 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12200_reg_12812 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12201_reg_12824 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12202_reg_12836 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12203_reg_12848 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12204_reg_12860 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12205_reg_12872 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12206_reg_12884 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12207_reg_12896 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12208_reg_12908 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12209_reg_12920 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12210_reg_12932 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12211_reg_12944 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12212_reg_12956 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12213_reg_12968 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12214_reg_12980 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12215_reg_12992 | 16| 0| 16| 0| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_12216_reg_13004 | 16| 0| 16| 0| + |res_0_0_i19_reg_13136 | 40| 0| 40| 0| + |res_10_0_i9_reg_13276 | 40| 0| 40| 0| + |res_11_0_i8_reg_13290 | 40| 0| 40| 0| + |res_12_0_i7_reg_13304 | 40| 0| 40| 0| + |res_13_0_i6_reg_13318 | 40| 0| 40| 0| + |res_1445_0_i5_reg_13332 | 40| 0| 40| 0| + |res_15_0_i4_reg_13346 | 33| 0| 33| 0| + |res_1_0_i18_reg_13150 | 40| 0| 40| 0| + |res_2_0_i17_reg_13164 | 40| 0| 40| 0| + |res_3_0_i16_reg_13178 | 40| 0| 40| 0| + |res_4_0_i15_reg_13192 | 40| 0| 40| 0| + |res_5_0_i14_reg_13206 | 40| 0| 40| 0| + |res_6_0_i13_reg_13220 | 40| 0| 40| 0| + |res_7_0_i12_reg_13234 | 40| 0| 40| 0| + |res_8_0_i11_reg_13248 | 40| 0| 40| 0| + |res_9_0_i10_reg_13262 | 40| 0| 40| 0| + |tmp_reg_19596 | 9| 0| 9| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_219_reg_13016 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_220_reg_13028 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_221_reg_13040 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_222_reg_13052 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_223_reg_13064 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_224_reg_13076 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_225_reg_13088 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_226_reg_13100 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_227_reg_13112 | 16| 0| 16| 0| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_228_reg_13124 | 16| 0| 16| 0| + |w_31_reg_19526 | 16| 0| 16| 0| + |w_32_reg_19531 | 16| 0| 16| 0| + |w_33_reg_19536 | 16| 0| 16| 0| + |w_34_reg_19541 | 16| 0| 16| 0| + |w_35_reg_19546 | 16| 0| 16| 0| + |w_36_reg_19551 | 16| 0| 16| 0| + |w_37_reg_19556 | 16| 0| 16| 0| + |w_38_reg_19561 | 16| 0| 16| 0| + |w_39_reg_19566 | 16| 0| 16| 0| + |w_40_reg_19571 | 16| 0| 16| 0| + |w_41_reg_19576 | 16| 0| 16| 0| + |w_42_reg_19581 | 16| 0| 16| 0| + |w_43_reg_19586 | 16| 0| 16| 0| + |w_44_reg_19591 | 16| 0| 16| 0| + |w_index3_reg_1890 | 9| 0| 9| 0| + |w_index_reg_19506 | 9| 0| 9| 0| + |w_reg_19521 | 16| 0| 16| 0| + +------------------------------------------------------------------------------------------------------------------------+-----+----+-----+-----------+ + |Total |15423| 0|15423| 0| + +------------------------------------------------------------------------------------------------------------------------+-----+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++----------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| dense_resource_rf_leq_nin,config29_mult>| return value| +|ap_rst | in| 1| ap_ctrl_hs| dense_resource_rf_leq_nin,config29_mult>| return value| +|ap_start | in| 1| ap_ctrl_hs| dense_resource_rf_leq_nin,config29_mult>| return value| +|ap_done | out| 1| ap_ctrl_hs| dense_resource_rf_leq_nin,config29_mult>| return value| +|ap_idle | out| 1| ap_ctrl_hs| dense_resource_rf_leq_nin,config29_mult>| return value| +|ap_ready | out| 1| ap_ctrl_hs| dense_resource_rf_leq_nin,config29_mult>| return value| +|ap_return_0 | out| 42| ap_ctrl_hs| dense_resource_rf_leq_nin,config29_mult>| return value| +|ap_return_1 | out| 42| ap_ctrl_hs| dense_resource_rf_leq_nin,config29_mult>| return value| +|ap_return_2 | out| 42| ap_ctrl_hs| dense_resource_rf_leq_nin,config29_mult>| return value| +|ap_return_3 | out| 42| ap_ctrl_hs| dense_resource_rf_leq_nin,config29_mult>| return value| +|ap_return_4 | out| 42| ap_ctrl_hs| dense_resource_rf_leq_nin,config29_mult>| return value| +|ap_return_5 | out| 42| ap_ctrl_hs| dense_resource_rf_leq_nin,config29_mult>| return value| +|ap_return_6 | out| 42| ap_ctrl_hs| dense_resource_rf_leq_nin,config29_mult>| return value| +|ap_return_7 | out| 42| ap_ctrl_hs| dense_resource_rf_leq_nin,config29_mult>| return value| +|ap_return_8 | out| 42| ap_ctrl_hs| dense_resource_rf_leq_nin,config29_mult>| return value| +|ap_return_9 | out| 42| ap_ctrl_hs| dense_resource_rf_leq_nin,config29_mult>| return value| +|ap_return_10 | out| 42| ap_ctrl_hs| dense_resource_rf_leq_nin,config29_mult>| return value| +|ap_return_11 | out| 42| ap_ctrl_hs| dense_resource_rf_leq_nin,config29_mult>| return value| +|ap_return_12 | out| 42| ap_ctrl_hs| dense_resource_rf_leq_nin,config29_mult>| return value| +|ap_return_13 | out| 42| ap_ctrl_hs| dense_resource_rf_leq_nin,config29_mult>| return value| +|ap_return_14 | out| 42| ap_ctrl_hs| dense_resource_rf_leq_nin,config29_mult>| return value| +|ap_return_15 | out| 42| ap_ctrl_hs| dense_resource_rf_leq_nin,config29_mult>| return value| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_59 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_59| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_58 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_58| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_57 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_57| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_56 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_56| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_55 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_55| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_54 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_54| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_53 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_53| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_52 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_52| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_51 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_51| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_50 | in| 16| ap_none| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_50| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5708 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5708| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5720 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5720| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5732 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5732| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5744 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5744| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5756 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5756| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5768 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5768| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5780 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5780| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5792 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5792| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5805 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5805| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5817 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5817| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5829 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5829| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5841 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5841| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5853 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5853| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5865 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5865| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5877 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5877| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5889 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5889| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5901 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5901| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5913 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5913| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5926 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5926| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5938 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5938| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5950 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5950| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5962 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5962| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5974 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5974| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5986 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5986| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5998 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5998| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6010 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6010| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6022 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6022| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6034 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6034| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6047 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6047| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6059 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6059| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6071 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6071| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6083 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6083| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6095 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6095| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6107 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6107| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6110 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6110| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6111 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6111| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6113 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6113| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6114 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6114| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6115 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6115| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6116 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6116| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6117 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6117| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6118 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6118| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6119 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6119| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6120 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6120| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6121 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6121| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6122 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6122| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6124 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6124| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6125 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6125| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6126 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6126| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6127 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6127| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6132| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6133 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6133| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6135 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6135| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6136 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6136| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6137 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6137| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6138 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6138| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6139 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6139| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6140 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6140| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6141 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6141| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6142 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6142| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6143 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6143| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6144 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6144| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6146 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6146| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6147 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6147| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6148 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6148| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6149 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6149| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6150 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6150| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6151 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6151| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6152 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6152| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6153 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6153| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6154 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6154| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6155 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6155| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6157 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6157| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6158 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6158| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6159 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6159| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6160 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6160| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6161 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6161| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6162 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6162| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6163 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6163| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6164 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6164| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6165 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6165| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6166 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6166| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5709| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5710 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5710| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5711 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5711| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5712 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5712| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5713 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5713| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5719| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5721 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5721| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5722 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5722| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5723 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5723| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5724 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5724| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5730| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5731 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5731| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5733 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5733| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5734 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5734| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5735 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5735| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5741| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5742 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5742| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5743 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5743| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5745 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5745| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5746 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5746| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5752| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5753 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5753| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5754 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5754| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5755 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5755| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5757 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5757| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5763| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5764 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5764| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5765 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5765| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5766 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5766| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5767 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5767| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5774| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5775 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5775| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5776 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5776| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5777 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5777| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5778 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5778| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5785| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5786 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5786| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5787 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5787| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5788 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5788| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5789 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5789| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5796| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5797 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5797| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5798 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5798| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5799 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5799| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5800 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5800| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5807| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5808 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5808| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5809 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5809| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5810 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5810| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5811 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5811| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5818| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5819 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5819| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5820 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5820| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5821 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5821| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5822 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5822| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5828| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5830 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5830| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5831 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5831| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5832 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5832| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5833 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5833| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5834 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5834| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5835 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5835| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5836 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5836| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5838 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5838| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5839 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5839| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5840 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5840| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5842 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5842| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5843 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5843| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5844 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5844| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5850| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5851 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5851| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5852 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5852| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5854 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5854| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5855 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5855| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5861| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5862 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5862| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5863 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5863| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5864 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5864| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5866 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5866| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5872| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5873 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5873| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5874 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5874| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5875 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5875| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5876 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5876| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5883| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5884 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5884| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5885 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5885| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5886 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5886| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5887 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5887| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5894| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5895 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5895| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5896 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5896| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5897 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5897| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5898 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5898| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5905| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5906 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5906| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5907 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5907| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5908 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5908| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5909 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5909| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5916| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5917 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5917| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5918 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5918| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5919 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5919| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5920 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5920| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5927| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5928 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5928| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5929 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5929| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5930 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5930| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5931 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5931| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5937| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5939 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5939| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5940 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5940| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5941 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5941| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5942 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5942| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5948| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5949 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5949| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5951 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5951| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5952 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5952| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5953 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5953| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5959| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5960 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5960| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5961 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5961| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5963 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5963| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5964 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5964| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5965 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5965| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5966 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5966| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5967 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5967| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5968 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5968| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5970 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5970| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5971 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5971| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5972 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5972| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5973 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5973| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5975 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5975| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5981| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5982 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5982| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5983 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5983| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5984 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5984| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5985 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5985| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5987 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5987| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5988 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5988| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5989 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5989| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5990 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5990| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5992 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5992| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5993 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5993| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5994 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5994| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5995 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5995| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5996 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5996| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5997 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5997| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5999 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5999| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6000 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6000| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6001 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6001| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6003 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6003| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6004 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6004| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6005 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6005| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6006 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6006| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6007 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6007| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6008 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6008| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6009 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6009| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6011 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6011| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6012 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6012| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6014 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6014| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6015 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6015| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6016 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6016| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6017 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6017| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6018 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6018| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6019 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6019| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6020 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6020| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6021 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6021| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6023 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6023| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6025 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6025| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6026 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6026| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6027 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6027| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6028 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6028| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6029 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6029| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6030 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6030| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6031 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6031| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6032 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6032| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6033 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6033| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6036 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6036| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6037 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6037| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6038 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6038| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6039 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6039| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6040 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6040| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6045| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6048 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6048| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6049 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6049| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6050 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6050| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6051 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6051| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6052 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6052| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6053 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6053| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6054 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6054| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6055 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6055| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6056 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6056| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6058 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6058| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6060 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6060| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6061 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6061| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6062 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6062| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6063 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6063| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6064 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6064| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6065 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6065| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6066 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6066| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6067 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6067| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6069 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6069| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6070 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6070| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6072 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6072| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6073 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6073| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6074 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6074| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6075 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6075| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6076 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6076| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6077 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6077| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6078 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6078| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6080 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6080| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6081 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6081| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6082 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6082| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6084 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6084| pointer| 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p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6089| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6091 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6091| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6092 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6092| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6093 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6093| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6094 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6094| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6096 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6096| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6097 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6097| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6098 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6098| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6099 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6099| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6100 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6100| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6102 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6102| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6103 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6103| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6104 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6104| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6105 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6105| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6106 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6106| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6108 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6108| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6109 | in| 16| ap_none| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6109| pointer| ++----------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/myproject_csynth.rpt b/myproject_prj/solution1/syn/report/myproject_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..6e019521f2b448d64c7f90c485bd796cac6237aa --- /dev/null +++ b/myproject_prj/solution1/syn/report/myproject_csynth.rpt @@ -0,0 +1,307 @@ + + +================================================================ +== Vitis HLS Report for 'myproject' +================================================================ +* Date: Sun Apr 5 21:50:55 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 4.449 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+----------+----------+-------+---------+----------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | min | max | min | max | min | max | Type | + +---------+---------+----------+----------+-------+---------+----------+ + | 1285112| 1285393| 5.718 ms| 5.719 ms| 45058| 1285022| dataflow| + +---------+---------+----------+----------+-------+---------+----------+ + + + Detail: + * Instance: + +-------------------------------------------------------------------------+------------------------------------------------------------------------+---------+---------+-----------+-----------+-------+---------+-----------------------------------------------+ + | | | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | Instance | Module | min | max | min | max | min | max | Type | + +-------------------------------------------------------------------------+------------------------------------------------------------------------+---------+---------+-----------+-----------+-------+---------+-----------------------------------------------+ + |zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_U0 |zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s | 4369| 4369| 17.476 us| 17.476 us| 4369| 4369| no| + |conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_U0 |conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s | 17425| 344125| 76.860 us| 1.518 ms| 17425| 344125| no| + |relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0 |relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s | 4098| 4098| 16.392 us| 16.392 us| 4096| 4096| loop auto-rewind stp(delay=0 clock cycles(s))| + |zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_U0 |zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s | 4369| 4369| 17.476 us| 17.476 us| 4369| 4369| no| + |conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_U0 |conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s | 17425| 657757| 71.080 us| 2.683 ms| 17425| 657757| no| + |relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_U0 |relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s | 4098| 4098| 16.392 us| 16.392 us| 4096| 4096| loop auto-rewind stp(delay=0 clock cycles(s))| + |clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0 |clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s | 4097| 4097| 16.388 us| 16.388 us| 4096| 4096| loop auto-rewind stp(delay=0 clock cycles(s))| + |pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_U0 |pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s | 8195| 8195| 32.780 us| 32.780 us| 8192| 8192| loop auto-rewind stp(delay=0 clock cycles(s))| + |zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_U0 |zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_s | 1169| 1169| 4.676 us| 4.676 us| 1169| 1169| no| + |conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_U0 |conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s | 4625| 174557| 18.866 us| 0.712 ms| 4625| 174557| no| + |relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_U0 |relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s | 1026| 1026| 4.104 us| 4.104 us| 1024| 1024| loop auto-rewind stp(delay=0 clock cycles(s))| + |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_U0 |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s | 1169| 1169| 4.676 us| 4.676 us| 1169| 1169| no| + |conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_U0 |conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s | 4625| 174557| 18.500 us| 0.698 ms| 4625| 174557| no| + |relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_U0 |relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s | 1026| 1026| 4.104 us| 4.104 us| 1024| 1024| loop auto-rewind stp(delay=0 clock cycles(s))| + |clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_U0 |clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s | 1025| 1025| 4.100 us| 4.100 us| 1024| 1024| loop auto-rewind stp(delay=0 clock cycles(s))| + |pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0 |pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s | 2051| 2051| 8.204 us| 8.204 us| 2048| 2048| loop auto-rewind stp(delay=0 clock cycles(s))| + |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_U0 |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_s | 337| 337| 1.348 us| 1.348 us| 337| 337| no| + |conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0 |conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s | 1297| 188893| 5.754 us| 0.838 ms| 1297| 188893| no| + |relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_U0 |relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s | 258| 258| 1.032 us| 1.032 us| 256| 256| loop auto-rewind stp(delay=0 clock cycles(s))| + |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0 |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s | 337| 337| 1.348 us| 1.348 us| 337| 337| no| + |conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_U0 |conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s | 1297| 188893| 5.341 us| 0.778 ms| 1297| 188893| no| + |relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_U0 |relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s | 258| 258| 1.032 us| 1.032 us| 256| 256| loop auto-rewind stp(delay=0 clock cycles(s))| + |clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0 |clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s | 257| 257| 1.028 us| 1.028 us| 256| 256| loop auto-rewind stp(delay=0 clock cycles(s))| + |pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_U0 |pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s | 515| 515| 2.060 us| 2.060 us| 512| 512| loop auto-rewind stp(delay=0 clock cycles(s))| + |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_U0 |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_s | 113| 113| 0.452 us| 0.452 us| 113| 113| no| + |conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_U0 |conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s | 401| 115901| 1.735 us| 0.502 ms| 401| 115901| no| + |relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_U0 |relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s | 66| 66| 0.264 us| 0.264 us| 64| 64| loop auto-rewind stp(delay=0 clock cycles(s))| + |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_U0 |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_s | 113| 113| 0.452 us| 0.452 us| 113| 113| no| + |conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_U0 |conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s | 401| 115901| 1.659 us| 0.480 ms| 401| 115901| no| + |relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_U0 |relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s | 66| 66| 0.264 us| 0.264 us| 64| 64| loop auto-rewind stp(delay=0 clock cycles(s))| + |resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_U0 |resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s | 257| 257| 1.028 us| 1.028 us| 256| 256| loop auto-rewind stp(delay=0 clock cycles(s))| + |concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0 |concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s | 259| 259| 1.036 us| 1.036 us| 259| 259| no| + |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_U0 |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_s | 337| 337| 1.348 us| 1.348 us| 337| 337| no| + |conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0 |conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s | 1297| 282205| 5.188 us| 1.129 ms| 1297| 282205| no| + |relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_U0 |relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s | 258| 258| 1.032 us| 1.032 us| 256| 256| loop auto-rewind stp(delay=0 clock cycles(s))| + |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_U0 |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_s | 337| 337| 1.348 us| 1.348 us| 337| 337| no| + |conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_U0 |conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s | 1297| 375517| 5.771 us| 1.671 ms| 1297| 375517| no| + |relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_U0 |relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s | 258| 258| 1.032 us| 1.032 us| 256| 256| loop auto-rewind stp(delay=0 clock cycles(s))| + |resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_U0 |resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s | 1025| 1025| 4.100 us| 4.100 us| 1024| 1024| loop auto-rewind stp(delay=0 clock cycles(s))| + |concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0 |concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s | 1027| 1027| 4.108 us| 4.108 us| 1027| 1027| no| + |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_U0 |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_s | 1169| 1169| 4.676 us| 4.676 us| 1169| 1169| no| + |conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_U0 |conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s | 4625| 507485| 18.500 us| 2.030 ms| 4625| 507485| no| + |relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_U0 |relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s | 1026| 1026| 4.104 us| 4.104 us| 1024| 1024| loop auto-rewind stp(delay=0 clock cycles(s))| + |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_U0 |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s | 1169| 1169| 4.676 us| 4.676 us| 1169| 1169| no| + |conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_U0 |conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s | 4625| 673949| 19.955 us| 2.908 ms| 4625| 673949| no| + |relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_U0 |relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s | 1026| 1026| 4.104 us| 4.104 us| 1024| 1024| loop auto-rewind stp(delay=0 clock cycles(s))| + |resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_U0 |resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s | 4097| 4097| 16.388 us| 16.388 us| 4096| 4096| loop auto-rewind stp(delay=0 clock cycles(s))| + |concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0 |concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s | 4099| 4099| 16.396 us| 16.396 us| 4099| 4099| no| + |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_U0 |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s | 4369| 4369| 17.476 us| 17.476 us| 4369| 4369| no| + |conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_U0 |conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s | 17425| 971389| 69.700 us| 3.886 ms| 17425| 971389| no| + |relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_U0 |relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s | 4098| 4098| 16.392 us| 16.392 us| 4096| 4096| loop auto-rewind stp(delay=0 clock cycles(s))| + |zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_U0 |zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_s | 4369| 4369| 17.476 us| 17.476 us| 4369| 4369| no| + |conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_U0 |conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s | 17425| 1285021| 77.087 us| 5.685 ms| 17425| 1285021| no| + |relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_U0 |relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s | 4098| 4098| 16.392 us| 16.392 us| 4096| 4096| loop auto-rewind stp(delay=0 clock cycles(s))| + |pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_U0 |pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_s | 45057| 49153| 0.180 ms| 0.197 ms| 45057| 49153| no| + |sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_U0 |sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s | 4101| 4101| 16.404 us| 16.404 us| 4096| 4096| loop auto-rewind stp(delay=0 clock cycles(s))| + +-------------------------------------------------------------------------+------------------------------------------------------------------------+---------+---------+-----------+-----------+-------+---------+-----------------------------------------------+ + + * Loop: + N/A + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 8| -| +|FIFO | 908| -| 64460| 33783| -| +|Instance | 161| 172| 304980| 263468| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| -| -| -| +|Register | -| -| -| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 1069| 172| 369440| 297259| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 79| 5| 42| 68| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | 26| 1| 14| 22| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + +-------------------------------------------------------------------------+------------------------------------------------------------------------+---------+----+-------+-------+-----+ + | Instance | Module | BRAM_18K| DSP| FF | LUT | URAM| + +-------------------------------------------------------------------------+------------------------------------------------------------------------+---------+----+-------+-------+-----+ + |clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_U0 |clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s | 0| 0| 13| 99| 0| + |clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0 |clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s | 0| 0| 11| 95| 0| + |clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0 |clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s | 0| 0| 15| 103| 0| + |concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0 |concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s | 0| 0| 21| 171| 0| + |concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0 |concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s | 0| 0| 19| 167| 0| + |concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0 |concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s | 0| 0| 17| 163| 0| + |conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_U0 |conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_s | 8| 16| 11594| 7740| 0| + |conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_U0 |conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s | 1| 1| 1519| 2052| 0| + |conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_U0 |conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s | 4| 8| 15106| 10803| 0| + |conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_U0 |conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s | 4| 8| 5646| 7190| 0| + |conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_U0 |conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s | 1| 2| 5573| 4991| 0| + |conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_U0 |conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s | 2| 4| 4684| 5698| 0| + |conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_U0 |conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s | 4| 4| 10881| 9083| 0| + |conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0 |conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s | 8| 8| 12257| 10563| 0| + |conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_U0 |conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s | 8| 16| 30072| 20812| 0| + |conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_U0 |conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s | 15| 16| 18136| 20548| 0| + |conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_U0 |conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_s | 16| 8| 21537| 17123| 0| + |conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_U0 |conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s | 30| 16| 24349| 20127| 0| + |conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0 |conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_s | 25| 32| 60056| 38986| 0| + |conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_U0 |conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s | 33| 32| 36198| 40011| 0| + |pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_U0 |pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_s | 0| 1| 420| 534| 0| + |pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_U0 |pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_s | 0| 0| 1339| 2057| 0| + |pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0 |pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_s | 0| 0| 2489| 3437| 0| + |pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_U0 |pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_s | 0| 0| 4791| 6201| 0| + |relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_U0 |relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_s | 0| 0| 271| 1129| 0| + |relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_U0 |relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s | 0| 0| 271| 1145| 0| + |relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_U0 |relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_s | 0| 0| 271| 1129| 0| + |relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_U0 |relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_s | 0| 0| 271| 1113| 0| + |relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_U0 |relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_s | 0| 0| 525| 2149| 0| + |relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_U0 |relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_s | 0| 0| 525| 2181| 0| + |relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_U0 |relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s | 0| 0| 525| 2213| 0| + |relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_U0 |relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s | 0| 0| 525| 2181| 0| + |relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_U0 |relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s | 0| 0| 1035| 4257| 0| + |relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_U0 |relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s | 0| 0| 1035| 4321| 0| + |relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_U0 |relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_s | 0| 0| 145| 621| 0| + |relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_U0 |relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_s | 0| 0| 145| 613| 0| + |relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0 |relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s | 0| 0| 145| 589| 0| + |relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_U0 |relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_s | 0| 0| 145| 613| 0| + |resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_U0 |resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s | 0| 0| 8326| 897| 0| + |resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_U0 |resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_s | 0| 0| 8261| 429| 0| + |resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_U0 |resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_s | 0| 0| 8228| 266| 0| + |sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_U0 |sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s | 2| 0| 118| 278| 0| + |zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_U0 |zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s | 0| 0| 126| 811| 0| + |zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_U0 |zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s | 0| 0| 238| 811| 0| + |zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_U0 |zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_s | 0| 0| 203| 608| 0| + |zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_U0 |zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_s | 0| 0| 238| 811| 0| + |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_U0 |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s | 0| 0| 331| 608| 0| + |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_U0 |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_s | 0| 0| 312| 502| 0| + |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_U0 |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s | 0| 0| 331| 608| 0| + |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_U0 |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s | 0| 0| 494| 811| 0| + |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0 |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s | 0| 0| 568| 502| 0| + |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_U0 |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_s | 0| 0| 557| 453| 0| + |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_U0 |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_s | 0| 0| 568| 502| 0| + |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_U0 |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_s | 0| 0| 843| 608| 0| + |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_U0 |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_s | 0| 0| 1069| 453| 0| + |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_U0 |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_s | 0| 0| 1592| 502| 0| + +-------------------------------------------------------------------------+------------------------------------------------------------------------+---------+----+-------+-------+-----+ + |Total | | 161| 172| 304980| 263468| 0| + +-------------------------------------------------------------------------+------------------------------------------------------------------------+---------+----+-------+-------+-----+ + + * DSP: + N/A + + * Memory: + N/A + + * FIFO: + +----------------+---------+------+----+-----+------+------+---------+ + | Name | BRAM_18K| FF | LUT| URAM| Depth| Bits | Size:D*B| + +----------------+---------+------+----+-----+------+------+---------+ + |layer10_out_U | 8| 543| 0| -| 1024| 256| 262144| + |layer11_out_U | 8| 541| 0| -| 256| 256| 65536| + |layer12_out_U | 29| 2084| 0| -| 256| 1312| 335872| + |layer13_out_U | 15| 1053| 0| -| 256| 512| 131072| + |layer14_out_U | 29| 2084| 0| -| 256| 1344| 344064| + |layer15_out_U | 15| 1053| 0| -| 256| 512| 131072| + |layer16_out_U | 15| 1046| 0| -| 64| 512| 32768| + |layer17_out_U | 29| 2077| 0| -| 64| 2688| 172032| + |layer18_out_U | 29| 2077| 0| -| 64| 1024| 65536| + |layer19_out_U | 29| 2077| 0| -| 64| 2752| 176128| + |layer20_out_U | 29| 2077| 0| -| 64| 1024| 65536| + |layer21_out_U | 29| 2084| 0| -| 256| 1024| 262144| + |layer22_out_U | 29| 2084| 0| -| 256| 1536| 393216| + |layer23_out_U | 29| 2084| 0| -| 256| 1376| 352256| + |layer24_out_U | 15| 1053| 0| -| 256| 512| 131072| + |layer25_out_U | 29| 2084| 0| -| 256| 1344| 344064| + |layer26_out_U | 15| 1053| 0| -| 256| 512| 131072| + |layer27_out_U | 15| 1056| 0| -| 1024| 512| 524288| + |layer28_out_U | 29| 2084| 0| -| 1024| 768| 786432| + |layer29_out_U | 29| 2084| 0| -| 1024| 672| 688128| + |layer2_out_U | 15| 1056| 0| -| 4096| 296| 1212416| + |layer30_out_U | 8| 543| 0| -| 1024| 256| 262144| + |layer31_out_U | 29| 2084| 0| -| 1024| 656| 671744| + |layer32_out_U | 8| 543| 0| -| 1024| 256| 262144| + |layer33_out_U | 8| 543| 0| -| 4096| 256| 1048576| + |layer34_out_U | 15| 1056| 0| -| 4096| 384| 1572864| + |layer35_out_U | 15| 1056| 0| -| 4096| 328| 1343488| + |layer36_out_U | 4| 287| 0| -| 4096| 128| 524288| + |layer37_out_U | 15| 1056| 0| -| 4096| 320| 1310720| + |layer38_out_U | 4| 287| 0| -| 4096| 128| 524288| + |layer39_out_U | 2| 159| 0| -| 4096| 36| 147456| + |layer3_out_U | 4| 287| 0| -| 4096| 128| 524288| + |layer41_cpy1_U | 4| 287| 0| -| 4096| 128| 524288| + |layer41_cpy2_U | 4| 287| 0| -| 4096| 128| 524288| + |layer42_cpy1_U | 8| 543| 0| -| 1024| 256| 262144| + |layer42_cpy2_U | 8| 543| 0| -| 1024| 256| 262144| + |layer43_cpy1_U | 15| 1053| 0| -| 256| 512| 131072| + |layer43_cpy2_U | 15| 1053| 0| -| 256| 512| 131072| + |layer44_out_U | 1| 63| 0| -| 4356| 16| 69696| + |layer45_out_U | 4| 287| 0| -| 4356| 128| 557568| + |layer46_out_U | 4| 287| 0| -| 1156| 128| 147968| + |layer47_out_U | 8| 543| 0| -| 1156| 256| 295936| + |layer48_out_U | 8| 543| 0| -| 324| 256| 82944| + |layer49_out_U | 15| 1056| 0| -| 324| 512| 165888| + |layer4_out_U | 15| 1056| 0| -| 4096| 320| 1310720| + |layer50_out_U | 15| 1050| 0| -| 100| 512| 51200| + |layer51_out_U | 29| 2079| 0| -| 100| 1024| 102400| + |layer52_out_U | 29| 2084| 0| -| 324| 1536| 497664| + |layer53_out_U | 15| 1056| 0| -| 324| 512| 165888| + |layer54_out_U | 29| 2084| 0| -| 1156| 768| 887808| + |layer55_out_U | 8| 543| 0| -| 1156| 256| 295936| + |layer56_out_U | 15| 1056| 0| -| 4356| 384| 1672704| + |layer57_out_U | 4| 287| 0| -| 4356| 128| 557568| + |layer5_out_U | 4| 287| 0| -| 4096| 128| 524288| + |layer6_out_U | 4| 287| 0| -| 1024| 128| 131072| + |layer7_out_U | 29| 2084| 0| -| 1024| 640| 655360| + |layer8_out_U | 8| 543| 0| -| 1024| 256| 262144| + |layer9_out_U | 29| 2084| 0| -| 1024| 656| 671744| + +----------------+---------+------+----+-----+------+------+---------+ + |Total | 908| 64460| 0| 0| 93752| 33956| 25740352| + +----------------+---------+------+----+-----+------+------+---------+ + + * Expression: + +-------------------------------------------------------------------------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +-------------------------------------------------------------------------------------+----------+----+---+----+------------+------------+ + |ap_idle | and| 0| 0| 2| 1| 1| + |clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_U0_start_full_n | and| 0| 0| 2| 1| 1| + |clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0_start_full_n | and| 0| 0| 2| 1| 1| + |clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0_start_full_n | and| 0| 0| 2| 1| 1| + +-------------------------------------------------------------------------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0| 8| 4| 4| + +-------------------------------------------------------------------------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + N/A + + * Register: + N/A + + + +================================================================ +== Interface +================================================================ +* Summary: ++--------------------+-----+-----+------------+--------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object| C Type | ++--------------------+-----+-----+------------+--------------+--------------+ +|x_TDATA | in| 16| axis| x| pointer| +|x_TVALID | in| 1| axis| x| pointer| +|x_TREADY | out| 1| axis| x| pointer| +|layer40_out_TDATA | out| 16| axis| layer40_out| pointer| +|layer40_out_TVALID | out| 1| axis| layer40_out| pointer| +|layer40_out_TREADY | in| 1| axis| layer40_out| pointer| +|ap_clk | in| 1| ap_ctrl_hs| myproject| return value| +|ap_rst_n | in| 1| ap_ctrl_hs| myproject| return value| +|ap_start | in| 1| ap_ctrl_hs| myproject| return value| +|ap_done | out| 1| ap_ctrl_hs| myproject| return value| +|ap_ready | out| 1| ap_ctrl_hs| myproject| return value| +|ap_idle | out| 1| ap_ctrl_hs| myproject| return value| ++--------------------+-----+-----+------------+--------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s_csynth.xml b/myproject_prj/solution1/syn/report/relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..1e89a28a49e70540a780c83a98a025dc1fc1bc53 --- /dev/null +++ b/myproject_prj/solution1/syn/report/relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s_csynth.xml @@ -0,0 +1,301 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_s +4.00 +1.35 +vivado + + + +loop auto-rewind stp(delay=0 clock cycles(s)) + +ns +2.530 + + +clock cycles +258 +258 +258 +1.032 us +1.032 us +1.032 us +256 +256 + + + +2.65 +256 +256 +1024 +1 +2 + + + + + +- +- +firmware/nnet_utils/nnet_activation_stream.h:41 + + +ReLUActLoop +- +- +firmware/nnet_utils/nnet_activation_stream.h:41 + + + + + + + +525 +2213 +0 +0 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +relu<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,relu_config24> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +relu<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,relu_config24> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +relu<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,relu_config24> +return value + +ap_ctrl_hs + +in +1 +control + + +start_full_n +relu<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,relu_config24> +return value + +ap_ctrl_hs + +in +1 +unknown + + +ap_done +relu<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,relu_config24> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_continue +relu<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,relu_config24> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_idle +relu<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,relu_config24> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +relu<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,relu_config24> +return value + +ap_ctrl_hs + +out +1 +control + + +start_out +relu<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,relu_config24> +return value + +ap_ctrl_hs + +out +1 +unknown + + +start_write +relu<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,relu_config24> +return value + +ap_ctrl_hs + +out +1 +unknown + + +layer23_out_dout +layer23_out +pointer + +ap_fifo + +in +1376 +control + + +layer23_out_num_data_valid +layer23_out +pointer + +ap_fifo + +in +9 +control + + +layer23_out_fifo_cap +layer23_out +pointer + +ap_fifo + +in +9 +unknown + + +layer23_out_empty_n +layer23_out +pointer + +ap_fifo + +in +1 +control + + +layer23_out_read +layer23_out +pointer + +ap_fifo + +out +1 +control + + +layer24_out_din +layer24_out +pointer + +ap_fifo + +out +512 +control + + +layer24_out_num_data_valid +layer24_out +pointer + +ap_fifo + +in +9 +control + + +layer24_out_fifo_cap +layer24_out +pointer + +ap_fifo + +in +9 +unknown + + +layer24_out_full_n +layer24_out +pointer + +ap_fifo + +in +1 +control + + +layer24_out_write +layer24_out +pointer + +ap_fifo + +out +1 +control + + + + diff --git a/myproject_prj/solution1/syn/report/relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s_csynth.xml b/myproject_prj/solution1/syn/report/relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..d9ccc9487527f816018024ec2d396cfba531d757 --- /dev/null +++ b/myproject_prj/solution1/syn/report/relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s_csynth.xml @@ -0,0 +1,301 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_s +4.00 +1.35 +vivado + + + +loop auto-rewind stp(delay=0 clock cycles(s)) + +ns +2.530 + + +clock cycles +258 +258 +258 +1.032 us +1.032 us +1.032 us +256 +256 + + + +2.65 +256 +256 +1024 +1 +2 + + + + + +- +- +firmware/nnet_utils/nnet_activation_stream.h:41 + + +ReLUActLoop +- +- +firmware/nnet_utils/nnet_activation_stream.h:41 + + + + + + + +525 +2181 +0 +0 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +relu<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,relu_config26> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +relu<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,relu_config26> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +relu<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,relu_config26> +return value + +ap_ctrl_hs + +in +1 +control + + +start_full_n +relu<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,relu_config26> +return value + +ap_ctrl_hs + +in +1 +unknown + + +ap_done +relu<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,relu_config26> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_continue +relu<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,relu_config26> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_idle +relu<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,relu_config26> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +relu<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,relu_config26> +return value + +ap_ctrl_hs + +out +1 +control + + +start_out +relu<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,relu_config26> +return value + +ap_ctrl_hs + +out +1 +unknown + + +start_write +relu<array<ap_fixed,32u>,array<ap_fixed<16,6,5,3,0>,32u>,relu_config26> +return value + +ap_ctrl_hs + +out +1 +unknown + + +layer25_out_dout +layer25_out +pointer + +ap_fifo + +in +1344 +control + + +layer25_out_num_data_valid +layer25_out +pointer + +ap_fifo + +in +9 +control + + +layer25_out_fifo_cap +layer25_out +pointer + +ap_fifo + +in +9 +unknown + + +layer25_out_empty_n +layer25_out +pointer + +ap_fifo + +in +1 +control + + +layer25_out_read +layer25_out +pointer + +ap_fifo + +out +1 +control + + +layer26_out_din +layer26_out +pointer + +ap_fifo + +out +512 +control + + +layer26_out_num_data_valid +layer26_out +pointer + +ap_fifo + +in +9 +control + + +layer26_out_fifo_cap +layer26_out +pointer + +ap_fifo + +in +9 +unknown + + +layer26_out_full_n +layer26_out +pointer + +ap_fifo + +in +1 +control + + +layer26_out_write +layer26_out +pointer + +ap_fifo + +out +1 +control + + + + diff --git a/myproject_prj/solution1/syn/report/relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s_csynth.rpt b/myproject_prj/solution1/syn/report/relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..c398a54430147018fe908937701df31e6b5fcc1f --- /dev/null +++ b/myproject_prj/solution1/syn/report/relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s_csynth.rpt @@ -0,0 +1,353 @@ + + +================================================================ +== Vitis HLS Report for 'relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s' +================================================================ +* Date: Sun Apr 5 21:48:07 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 2.508 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+----------+----------+-----+-----+-----------------------------------------------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | min | max | min | max | min | max | Type | + +---------+---------+----------+----------+-----+-----+-----------------------------------------------+ + | 66| 66| 0.264 us| 0.264 us| 64| 64| loop auto-rewind stp(delay=0 clock cycles(s))| + +---------+---------+----------+----------+-----+-----+-----------------------------------------------+ + + + Detail: + * Instance: + N/A + + * Loop: + +---------------+---------+---------+----------+-----------+-----------+------+----------+ + | | Latency (cycles) | Iteration| Initiation Interval | Trip | | + | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| + +---------------+---------+---------+----------+-----------+-----------+------+----------+ + |- ReLUActLoop | 64| 64| 2| 1| 1| 64| yes| + +---------------+---------+---------+----------+-----------+-----------+------+----------+ + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 4258| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| -| -| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| 0| 63| -| +|Register | -| -| 1035| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 0| 0| 1035| 4321| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + N/A + + * DSP: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +----------------------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +----------------------------------+----------+----+---+----+------------+------------+ + |i_fu_2749_p2 | +| 0| 0| 13| 6| 1| + |ap_condition_235 | and| 0| 0| 2| 1| 1| + |icmp_ln41_fu_2755_p2 | icmp| 0| 0| 13| 6| 2| + |icmp_ln51_10_fu_1453_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_11_fu_1477_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_12_fu_1501_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_13_fu_1525_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_14_fu_1549_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_15_fu_1573_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_16_fu_1597_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_17_fu_1621_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_18_fu_1645_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_19_fu_1669_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_1_fu_1237_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_20_fu_1693_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_21_fu_1717_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_22_fu_1741_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_23_fu_1765_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_24_fu_1789_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_25_fu_1813_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_26_fu_1837_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_27_fu_1861_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_28_fu_1885_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_29_fu_1909_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_2_fu_1261_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_30_fu_1933_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_31_fu_1957_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_32_fu_1981_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_33_fu_2005_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_34_fu_2029_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_35_fu_2053_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_36_fu_2077_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_37_fu_2101_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_38_fu_2125_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_39_fu_2149_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_3_fu_1285_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_40_fu_2173_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_41_fu_2197_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_42_fu_2221_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_43_fu_2245_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_44_fu_2269_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_45_fu_2293_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_46_fu_2317_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_47_fu_2341_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_48_fu_2365_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_49_fu_2389_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_4_fu_1309_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_50_fu_2413_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_51_fu_2437_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_52_fu_2461_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_53_fu_2485_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_54_fu_2509_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_55_fu_2533_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_56_fu_2557_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_57_fu_2581_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_58_fu_2605_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_59_fu_2629_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_5_fu_1333_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_60_fu_2653_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_61_fu_2677_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_62_fu_2701_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_63_fu_2725_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_6_fu_1357_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_7_fu_1381_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_8_fu_1405_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_9_fu_1429_p2 | icmp| 0| 0| 50| 43| 1| + |icmp_ln51_fu_1213_p2 | icmp| 0| 0| 50| 43| 1| + |ap_block_pp0_stage0_01001 | or| 0| 0| 2| 1| 1| + |ap_block_state1_pp0_stage0_iter0 | or| 0| 0| 2| 1| 1| + |out_data_29_fu_1229_p3 | select| 0| 0| 16| 1| 16| + |out_data_30_fu_1253_p3 | select| 0| 0| 16| 1| 16| + |out_data_31_fu_1277_p3 | select| 0| 0| 16| 1| 16| + |out_data_32_fu_1301_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_10_fu_1565_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_11_fu_1589_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_12_fu_1613_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_13_fu_1637_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_14_fu_1661_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_15_fu_1685_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_16_fu_1709_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_17_fu_1733_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_18_fu_1757_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_19_fu_1781_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_1_fu_1349_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_20_fu_1805_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_21_fu_1829_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_22_fu_1853_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_23_fu_1877_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_24_fu_1901_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_25_fu_1925_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_26_fu_1949_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_27_fu_1973_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_28_fu_1997_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_29_fu_2021_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_2_fu_1373_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_30_fu_2045_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_31_fu_2069_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_32_fu_2093_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_33_fu_2117_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_34_fu_2141_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_35_fu_2165_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_36_fu_2189_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_37_fu_2213_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_38_fu_2237_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_39_fu_2261_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_3_fu_1397_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_40_fu_2285_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_41_fu_2309_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_42_fu_2333_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_43_fu_2357_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_44_fu_2381_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_45_fu_2405_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_46_fu_2429_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_47_fu_2453_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_48_fu_2477_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_49_fu_2501_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_4_fu_1421_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_50_fu_2525_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_51_fu_2549_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_52_fu_2573_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_53_fu_2597_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_54_fu_2621_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_55_fu_2645_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_56_fu_2669_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_57_fu_2693_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_58_fu_2717_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_59_fu_2741_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_5_fu_1445_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_6_fu_1469_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_7_fu_1493_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_8_fu_1517_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_9_fu_1541_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_fu_1325_p3 | select| 0| 0| 16| 1| 16| + |ap_enable_pp0 | xor| 0| 0| 2| 1| 2| + +----------------------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0|4258| 2832| 1096| + +----------------------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +----------------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +----------------------------------+----+-----------+-----+-----------+ + |ap_done_int | 9| 2| 1| 2| + |ap_loop_exit_ready_pp0_iter1_reg | 9| 2| 1| 2| + |ap_sig_allocacmp_i1_load | 9| 2| 6| 12| + |i1_fu_554 | 9| 2| 6| 12| + |layer19_out_blk_n | 9| 2| 1| 2| + |layer20_out_blk_n | 9| 2| 1| 2| + |real_start | 9| 2| 1| 2| + +----------------------------------+----+-----------+-----+-----------+ + |Total | 63| 14| 17| 34| + +----------------------------------+----+-----------+-----+-----------+ + + * Register: + +----------------------------------+----+----+-----+-----------+ + | Name | FF | LUT| Bits| Const Bits| + +----------------------------------+----+----+-----+-----------+ + |ap_CS_fsm | 1| 0| 1| 0| + |ap_done_reg | 1| 0| 1| 0| + |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| + |ap_loop_exit_ready_pp0_iter1_reg | 1| 0| 1| 0| + |i1_fu_554 | 6| 0| 6| 0| + |out_data_29_reg_2842 | 16| 0| 16| 0| + |out_data_30_reg_2847 | 16| 0| 16| 0| + |out_data_31_reg_2852 | 16| 0| 16| 0| + |out_data_32_reg_2857 | 16| 0| 16| 0| + |select_ln51_10_reg_2912 | 16| 0| 16| 0| + |select_ln51_11_reg_2917 | 16| 0| 16| 0| + |select_ln51_12_reg_2922 | 16| 0| 16| 0| + |select_ln51_13_reg_2927 | 16| 0| 16| 0| + |select_ln51_14_reg_2932 | 16| 0| 16| 0| + |select_ln51_15_reg_2937 | 16| 0| 16| 0| + |select_ln51_16_reg_2942 | 16| 0| 16| 0| + |select_ln51_17_reg_2947 | 16| 0| 16| 0| + |select_ln51_18_reg_2952 | 16| 0| 16| 0| + |select_ln51_19_reg_2957 | 16| 0| 16| 0| + |select_ln51_1_reg_2867 | 16| 0| 16| 0| + |select_ln51_20_reg_2962 | 16| 0| 16| 0| + |select_ln51_21_reg_2967 | 16| 0| 16| 0| + |select_ln51_22_reg_2972 | 16| 0| 16| 0| + |select_ln51_23_reg_2977 | 16| 0| 16| 0| + |select_ln51_24_reg_2982 | 16| 0| 16| 0| + |select_ln51_25_reg_2987 | 16| 0| 16| 0| + |select_ln51_26_reg_2992 | 16| 0| 16| 0| + |select_ln51_27_reg_2997 | 16| 0| 16| 0| + |select_ln51_28_reg_3002 | 16| 0| 16| 0| + |select_ln51_29_reg_3007 | 16| 0| 16| 0| + |select_ln51_2_reg_2872 | 16| 0| 16| 0| + |select_ln51_30_reg_3012 | 16| 0| 16| 0| + |select_ln51_31_reg_3017 | 16| 0| 16| 0| + |select_ln51_32_reg_3022 | 16| 0| 16| 0| + |select_ln51_33_reg_3027 | 16| 0| 16| 0| + |select_ln51_34_reg_3032 | 16| 0| 16| 0| + |select_ln51_35_reg_3037 | 16| 0| 16| 0| + |select_ln51_36_reg_3042 | 16| 0| 16| 0| + |select_ln51_37_reg_3047 | 16| 0| 16| 0| + |select_ln51_38_reg_3052 | 16| 0| 16| 0| + |select_ln51_39_reg_3057 | 16| 0| 16| 0| + |select_ln51_3_reg_2877 | 16| 0| 16| 0| + |select_ln51_40_reg_3062 | 16| 0| 16| 0| + |select_ln51_41_reg_3067 | 16| 0| 16| 0| + |select_ln51_42_reg_3072 | 16| 0| 16| 0| + |select_ln51_43_reg_3077 | 16| 0| 16| 0| + |select_ln51_44_reg_3082 | 16| 0| 16| 0| + |select_ln51_45_reg_3087 | 16| 0| 16| 0| + |select_ln51_46_reg_3092 | 16| 0| 16| 0| + |select_ln51_47_reg_3097 | 16| 0| 16| 0| + |select_ln51_48_reg_3102 | 16| 0| 16| 0| + |select_ln51_49_reg_3107 | 16| 0| 16| 0| + |select_ln51_4_reg_2882 | 16| 0| 16| 0| + |select_ln51_50_reg_3112 | 16| 0| 16| 0| + |select_ln51_51_reg_3117 | 16| 0| 16| 0| + |select_ln51_52_reg_3122 | 16| 0| 16| 0| + |select_ln51_53_reg_3127 | 16| 0| 16| 0| + |select_ln51_54_reg_3132 | 16| 0| 16| 0| + |select_ln51_55_reg_3137 | 16| 0| 16| 0| + |select_ln51_56_reg_3142 | 16| 0| 16| 0| + |select_ln51_57_reg_3147 | 16| 0| 16| 0| + |select_ln51_58_reg_3152 | 16| 0| 16| 0| + |select_ln51_59_reg_3157 | 16| 0| 16| 0| + |select_ln51_5_reg_2887 | 16| 0| 16| 0| + |select_ln51_6_reg_2892 | 16| 0| 16| 0| + |select_ln51_7_reg_2897 | 16| 0| 16| 0| + |select_ln51_8_reg_2902 | 16| 0| 16| 0| + |select_ln51_9_reg_2907 | 16| 0| 16| 0| + |select_ln51_reg_2862 | 16| 0| 16| 0| + |start_once_reg | 1| 0| 1| 0| + +----------------------------------+----+----+-----+-----------+ + |Total |1035| 0| 1035| 0| + +----------------------------------+----+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------+-----+------+------------+-------------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits | Protocol | Source Object | C Type | ++----------------------------+-----+------+------------+-------------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| relu,array,64u>,relu_config20>| return value| +|ap_rst | in| 1| ap_ctrl_hs| relu,array,64u>,relu_config20>| return value| +|ap_start | in| 1| ap_ctrl_hs| relu,array,64u>,relu_config20>| return value| +|start_full_n | in| 1| ap_ctrl_hs| relu,array,64u>,relu_config20>| return value| +|ap_done | out| 1| ap_ctrl_hs| relu,array,64u>,relu_config20>| return value| +|ap_continue | in| 1| ap_ctrl_hs| relu,array,64u>,relu_config20>| return value| +|ap_idle | out| 1| ap_ctrl_hs| relu,array,64u>,relu_config20>| return value| +|ap_ready | out| 1| ap_ctrl_hs| relu,array,64u>,relu_config20>| return value| +|start_out | out| 1| ap_ctrl_hs| relu,array,64u>,relu_config20>| return value| +|start_write | out| 1| ap_ctrl_hs| relu,array,64u>,relu_config20>| return value| +|layer19_out_dout | in| 2752| ap_fifo| layer19_out| pointer| +|layer19_out_num_data_valid | in| 7| ap_fifo| layer19_out| pointer| +|layer19_out_fifo_cap | in| 7| ap_fifo| layer19_out| pointer| +|layer19_out_empty_n | in| 1| ap_fifo| layer19_out| pointer| +|layer19_out_read | out| 1| ap_fifo| layer19_out| pointer| +|layer20_out_din | out| 1024| ap_fifo| layer20_out| pointer| +|layer20_out_num_data_valid | in| 7| ap_fifo| layer20_out| pointer| +|layer20_out_fifo_cap | in| 7| ap_fifo| layer20_out| pointer| +|layer20_out_full_n | in| 1| ap_fifo| layer20_out| pointer| +|layer20_out_write | out| 1| ap_fifo| layer20_out| pointer| ++----------------------------+-----+------+------------+-------------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s_csynth.xml b/myproject_prj/solution1/syn/report/relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..35e872f8fafe6fc5462d197a9dd42d5f355311da --- /dev/null +++ b/myproject_prj/solution1/syn/report/relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s_csynth.xml @@ -0,0 +1,301 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_s +4.00 +1.35 +vivado + + + +loop auto-rewind stp(delay=0 clock cycles(s)) + +ns +2.508 + + +clock cycles +66 +66 +66 +0.264 us +0.264 us +0.264 us +64 +64 + + + +2.65 +64 +64 +256 +1 +2 + + + + + +- +- +firmware/nnet_utils/nnet_activation_stream.h:41 + + +ReLUActLoop +- +- +firmware/nnet_utils/nnet_activation_stream.h:41 + + + + + + + +1035 +4321 +0 +0 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +relu<array<ap_fixed,64u>,array<ap_fixed<16,6,5,3,0>,64u>,relu_config20> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +relu<array<ap_fixed,64u>,array<ap_fixed<16,6,5,3,0>,64u>,relu_config20> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +relu<array<ap_fixed,64u>,array<ap_fixed<16,6,5,3,0>,64u>,relu_config20> +return value + +ap_ctrl_hs + +in +1 +control + + +start_full_n +relu<array<ap_fixed,64u>,array<ap_fixed<16,6,5,3,0>,64u>,relu_config20> +return value + +ap_ctrl_hs + +in +1 +unknown + + +ap_done +relu<array<ap_fixed,64u>,array<ap_fixed<16,6,5,3,0>,64u>,relu_config20> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_continue +relu<array<ap_fixed,64u>,array<ap_fixed<16,6,5,3,0>,64u>,relu_config20> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_idle +relu<array<ap_fixed,64u>,array<ap_fixed<16,6,5,3,0>,64u>,relu_config20> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +relu<array<ap_fixed,64u>,array<ap_fixed<16,6,5,3,0>,64u>,relu_config20> +return value + +ap_ctrl_hs + +out +1 +control + + +start_out +relu<array<ap_fixed,64u>,array<ap_fixed<16,6,5,3,0>,64u>,relu_config20> +return value + +ap_ctrl_hs + +out +1 +unknown + + +start_write +relu<array<ap_fixed,64u>,array<ap_fixed<16,6,5,3,0>,64u>,relu_config20> +return value + +ap_ctrl_hs + +out +1 +unknown + + +layer19_out_dout +layer19_out +pointer + +ap_fifo + +in +2752 +control + + +layer19_out_num_data_valid +layer19_out +pointer + +ap_fifo + +in +7 +control + + +layer19_out_fifo_cap +layer19_out +pointer + +ap_fifo + +in +7 +unknown + + +layer19_out_empty_n +layer19_out +pointer + +ap_fifo + +in +1 +control + + +layer19_out_read +layer19_out +pointer + +ap_fifo + +out +1 +control + + +layer20_out_din +layer20_out +pointer + +ap_fifo + +out +1024 +control + + +layer20_out_num_data_valid +layer20_out +pointer + +ap_fifo + +in +7 +control + + +layer20_out_fifo_cap +layer20_out +pointer + +ap_fifo + +in +7 +unknown + + +layer20_out_full_n +layer20_out +pointer + +ap_fifo + +in +1 +control + + +layer20_out_write +layer20_out +pointer + +ap_fifo + +out +1 +control + + + + diff --git a/myproject_prj/solution1/syn/report/relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s_csynth.rpt b/myproject_prj/solution1/syn/report/relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..4fc0d3136418b918a6c1dc6b28493f2946c5e5c0 --- /dev/null +++ b/myproject_prj/solution1/syn/report/relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s_csynth.rpt @@ -0,0 +1,185 @@ + + +================================================================ +== Vitis HLS Report for 'relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_s' +================================================================ +* Date: Sun Apr 5 21:46:31 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 2.411 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+-----------+-----------+------+------+-----------------------------------------------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | min | max | min | max | min | max | Type | + +---------+---------+-----------+-----------+------+------+-----------------------------------------------+ + | 4098| 4098| 16.392 us| 16.392 us| 4096| 4096| loop auto-rewind stp(delay=0 clock cycles(s))| + +---------+---------+-----------+-----------+------+------+-----------------------------------------------+ + + + Detail: + * Instance: + N/A + + * Loop: + +---------------+---------+---------+----------+-----------+-----------+------+----------+ + | | Latency (cycles) | Iteration| Initiation Interval | Trip | | + | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| + +---------------+---------+---------+----------+-----------+-----------+------+----------+ + |- ReLUActLoop | 4096| 4096| 2| 1| 1| 4096| yes| + +---------------+---------+---------+----------+-----------+-----------+------+----------+ + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 526| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| -| -| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| 0| 63| -| +|Register | -| -| 145| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 0| 0| 145| 589| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + N/A + + * DSP: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +----------------------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +----------------------------------+----------+----+---+----+------------+------------+ + |i_fu_397_p2 | +| 0| 0| 19| 12| 1| + |ap_condition_123 | and| 0| 0| 2| 1| 1| + |icmp_ln41_fu_403_p2 | icmp| 0| 0| 19| 12| 2| + |icmp_ln51_10_fu_277_p2 | icmp| 0| 0| 44| 37| 1| + |icmp_ln51_11_fu_301_p2 | icmp| 0| 0| 44| 37| 1| + |icmp_ln51_12_fu_325_p2 | icmp| 0| 0| 44| 37| 1| + |icmp_ln51_13_fu_349_p2 | icmp| 0| 0| 44| 37| 1| + |icmp_ln51_14_fu_373_p2 | icmp| 0| 0| 44| 37| 1| + |icmp_ln51_8_fu_229_p2 | icmp| 0| 0| 44| 37| 1| + |icmp_ln51_9_fu_253_p2 | icmp| 0| 0| 44| 37| 1| + |icmp_ln51_fu_205_p2 | icmp| 0| 0| 44| 37| 1| + |ap_block_pp0_stage0_01001 | or| 0| 0| 2| 1| 1| + |ap_block_state1_pp0_stage0_iter0 | or| 0| 0| 2| 1| 1| + |out_data_10_fu_245_p3 | select| 0| 0| 16| 1| 16| + |out_data_12_fu_269_p3 | select| 0| 0| 16| 1| 16| + |out_data_14_fu_293_p3 | select| 0| 0| 16| 1| 16| + |out_data_8_fu_221_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_12_fu_341_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_13_fu_365_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_14_fu_389_p3 | select| 0| 0| 16| 1| 16| + |select_ln51_fu_317_p3 | select| 0| 0| 16| 1| 16| + |ap_enable_pp0 | xor| 0| 0| 2| 1| 2| + +----------------------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0| 526| 332| 144| + +----------------------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +----------------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +----------------------------------+----+-----------+-----+-----------+ + |ap_done_int | 9| 2| 1| 2| + |ap_loop_exit_ready_pp0_iter1_reg | 9| 2| 1| 2| + |ap_sig_allocacmp_i1_load | 9| 2| 12| 24| + |i1_fu_106 | 9| 2| 12| 24| + |layer2_out_blk_n | 9| 2| 1| 2| + |layer3_out_blk_n | 9| 2| 1| 2| + |real_start | 9| 2| 1| 2| + +----------------------------------+----+-----------+-----+-----------+ + |Total | 63| 14| 29| 58| + +----------------------------------+----+-----------+-----+-----------+ + + * Register: + +----------------------------------+----+----+-----+-----------+ + | Name | FF | LUT| Bits| Const Bits| + +----------------------------------+----+----+-----+-----------+ + |ap_CS_fsm | 1| 0| 1| 0| + |ap_done_reg | 1| 0| 1| 0| + |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| + |ap_loop_exit_ready_pp0_iter1_reg | 1| 0| 1| 0| + |i1_fu_106 | 12| 0| 12| 0| + |out_data_10_reg_439 | 16| 0| 16| 0| + |out_data_12_reg_444 | 16| 0| 16| 0| + |out_data_14_reg_449 | 16| 0| 16| 0| + |out_data_8_reg_434 | 16| 0| 16| 0| + |select_ln51_12_reg_459 | 16| 0| 16| 0| + |select_ln51_13_reg_464 | 16| 0| 16| 0| + |select_ln51_14_reg_469 | 16| 0| 16| 0| + |select_ln51_reg_454 | 16| 0| 16| 0| + |start_once_reg | 1| 0| 1| 0| + +----------------------------------+----+----+-----+-----------+ + |Total | 145| 0| 145| 0| + +----------------------------------+----+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++---------------------------+-----+-----+------------+----------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++---------------------------+-----+-----+------------+----------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| relu,array,8u>,relu_config3>| return value| +|ap_rst | in| 1| ap_ctrl_hs| relu,array,8u>,relu_config3>| return value| +|ap_start | in| 1| ap_ctrl_hs| relu,array,8u>,relu_config3>| return value| +|start_full_n | in| 1| ap_ctrl_hs| relu,array,8u>,relu_config3>| return value| +|ap_done | out| 1| ap_ctrl_hs| relu,array,8u>,relu_config3>| return value| +|ap_continue | in| 1| ap_ctrl_hs| relu,array,8u>,relu_config3>| return value| +|ap_idle | out| 1| ap_ctrl_hs| relu,array,8u>,relu_config3>| return value| +|ap_ready | out| 1| ap_ctrl_hs| relu,array,8u>,relu_config3>| return value| +|start_out | out| 1| ap_ctrl_hs| relu,array,8u>,relu_config3>| return value| +|start_write | out| 1| ap_ctrl_hs| relu,array,8u>,relu_config3>| return value| +|layer2_out_dout | in| 296| ap_fifo| layer2_out| pointer| +|layer2_out_num_data_valid | in| 13| ap_fifo| layer2_out| pointer| +|layer2_out_fifo_cap | in| 13| ap_fifo| layer2_out| pointer| +|layer2_out_empty_n | in| 1| ap_fifo| layer2_out| pointer| +|layer2_out_read | out| 1| ap_fifo| layer2_out| pointer| +|layer3_out_din | out| 128| ap_fifo| layer3_out| pointer| +|layer3_out_num_data_valid | in| 13| ap_fifo| layer3_out| pointer| +|layer3_out_fifo_cap | in| 13| ap_fifo| layer3_out| pointer| +|layer3_out_full_n | in| 1| ap_fifo| layer3_out| pointer| +|layer3_out_write | out| 1| ap_fifo| layer3_out| pointer| ++---------------------------+-----+-----+------------+----------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s_csynth.xml b/myproject_prj/solution1/syn/report/resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..296cd2689b925a43f98e3f22625b74f9879c36e4 --- /dev/null +++ b/myproject_prj/solution1/syn/report/resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s_csynth.xml @@ -0,0 +1,269 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_s +4.00 +1.35 +vivado + + + +loop auto-rewind stp(delay=0 clock cycles(s)) + +ns +1.978 + + +clock cycles +4097 +4097 +4097 +16.388 us +16.388 us +16.388 us +4096 +4096 + + + +2.65 +32 +4095 +16380 +128 +128 + + + + + +- +- +firmware/nnet_utils/nnet_image_stream.h:16 + + +ImageHeight +II Violation +Memory Dependency +1 +firmware/nnet_utils/nnet_image_stream.h:16 + + + + + + + +8326 +897 +0 +0 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +resize_nearest<array<ap_fixed<16, 6, 5, 3, 0>, 16u>, config33> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +resize_nearest<array<ap_fixed<16, 6, 5, 3, 0>, 16u>, config33> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +resize_nearest<array<ap_fixed<16, 6, 5, 3, 0>, 16u>, config33> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_done +resize_nearest<array<ap_fixed<16, 6, 5, 3, 0>, 16u>, config33> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_continue +resize_nearest<array<ap_fixed<16, 6, 5, 3, 0>, 16u>, config33> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_idle +resize_nearest<array<ap_fixed<16, 6, 5, 3, 0>, 16u>, config33> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +resize_nearest<array<ap_fixed<16, 6, 5, 3, 0>, 16u>, config33> +return value + +ap_ctrl_hs + +out +1 +control + + +layer33_out_din +layer33_out +pointer + +ap_fifo + +out +256 +control + + +layer33_out_num_data_valid +layer33_out +pointer + +ap_fifo + +in +13 +control + + +layer33_out_fifo_cap +layer33_out +pointer + +ap_fifo + +in +13 +unknown + + +layer33_out_full_n +layer33_out +pointer + +ap_fifo + +in +1 +control + + +layer33_out_write +layer33_out +pointer + +ap_fifo + +out +1 +control + + +layer32_out_dout +layer32_out +pointer + +ap_fifo + +in +256 +control + + +layer32_out_num_data_valid +layer32_out +pointer + +ap_fifo + +in +11 +control + + +layer32_out_fifo_cap +layer32_out +pointer + +ap_fifo + +in +11 +unknown + + +layer32_out_empty_n +layer32_out +pointer + +ap_fifo + +in +1 +control + + +layer32_out_read +layer32_out +pointer + +ap_fifo + +out +1 +control + + + + diff --git a/myproject_prj/solution1/syn/report/shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_csynth.rpt b/myproject_prj/solution1/syn/report/shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..eb24863399be906e72a0de623a18e38d74125812 --- /dev/null +++ b/myproject_prj/solution1/syn/report/shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_csynth.rpt @@ -0,0 +1,916 @@ + + +================================================================ +== Vitis HLS Report for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s' +================================================================ +* Date: Sun Apr 5 21:50:22 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 1.222 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+----------+----------+-----+-----+---------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline| + | min | max | min | max | min | max | Type | + +---------+---------+----------+----------+-----+-----+---------+ + | 0| 0| 0 ns| 0 ns| 1| 1| yes| + +---------+---------+----------+----------+-----+-----+---------+ + + + Detail: + * Instance: + N/A + + * Loop: + N/A + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| -| -| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| -| -| -| +|Memory | -| -| 3072| 1536| -| +|Multiplexer | -| -| 0| 1296| -| +|Register | -| -| 1| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 0| 0| 3073| 2832| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + N/A + + * DSP: + N/A + + * Memory: + +-----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+---------+----+----+-----+------+-----+------+-------------+ + | Memory | Module | BRAM_18K| FF | LUT| URAM| Words| Bits| Banks| W*Bits*Banks| + +-----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+---------+----+----+-----+------+-----+------+-------------+ + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_895_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_919_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_896_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_920_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_907_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_931_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_912_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_936_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_913_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_937_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_914_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_938_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_915_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_939_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_916_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_940_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_917_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_941_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_918_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_942_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_897_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_921_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_898_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_922_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_899_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_923_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_900_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_924_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_901_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_925_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_902_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_926_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_903_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_927_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_904_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_928_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_905_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_929_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_906_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_930_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_908_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_932_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_909_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_933_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_910_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_934_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_911_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_935_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + +-----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+---------+----+----+-----+------+-----+------+-------------+ + |Total | | 0|3072|1536| 0| 3168| 768| 48| 50688| + +-----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+---------+----+----+-----+------+-----+------+-------------+ + + * FIFO: + N/A + + * Expression: + N/A + + * Multiplexer: + +------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4565_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4566_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4567_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4568_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4569_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4570_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4571_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4573_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4574_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4575_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4577_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4578_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4579_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4580_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4581_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4582_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4584_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4585_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4586_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4587_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4589_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4590_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4591_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4592_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4593_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4595_o | 9| 2| 16| 32| + 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|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4753_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4754_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4755_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4756_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4757_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4758_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4786_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4787_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4788_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4789_o | 9| 2| 16| 32| + +------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + |Total |1296| 288| 2304| 4608| + +------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + + * Register: + +-----------+---+----+-----+-----------+ + | Name | FF| LUT| Bits| Const Bits| + +-----------+---+----+-----+-----------+ + |ap_CS_fsm | 1| 0| 1| 0| + +-----------+---+----+-----+-----------+ + |Total | 1| 0| 1| 0| + +-----------+---+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++-------------------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++-------------------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| shift_line_buffer, 24u>, config35>| return value| +|ap_rst | in| 1| ap_ctrl_hs| shift_line_buffer, 24u>, config35>| return value| +|ap_start | in| 1| ap_ctrl_hs| shift_line_buffer, 24u>, config35>| return value| +|ap_done | out| 1| ap_ctrl_hs| shift_line_buffer, 24u>, config35>| return value| +|ap_idle | out| 1| ap_ctrl_hs| shift_line_buffer, 24u>, config35>| return value| +|ap_ready | out| 1| ap_ctrl_hs| shift_line_buffer, 24u>, config35>| return value| +|p_read | in| 16| ap_none| p_read| scalar| +|p_read1 | in| 16| ap_none| p_read1| scalar| +|p_read2 | in| 16| ap_none| p_read2| scalar| +|p_read3 | in| 16| ap_none| p_read3| scalar| +|p_read4 | in| 16| ap_none| p_read4| scalar| +|p_read5 | in| 16| ap_none| p_read5| scalar| +|p_read6 | in| 16| ap_none| p_read6| scalar| +|p_read7 | in| 16| ap_none| p_read7| scalar| +|p_read8 | in| 16| ap_none| p_read8| scalar| +|p_read9 | in| 16| ap_none| p_read9| scalar| +|p_read10 | in| 16| ap_none| p_read10| scalar| +|p_read11 | in| 16| ap_none| p_read11| scalar| +|p_read12 | in| 16| ap_none| p_read12| scalar| +|p_read13 | in| 16| ap_none| p_read13| scalar| +|p_read14 | in| 16| ap_none| p_read14| scalar| +|p_read15 | in| 16| ap_none| p_read15| scalar| +|p_read16 | in| 16| ap_none| p_read16| scalar| +|p_read17 | in| 16| ap_none| p_read17| scalar| +|p_read18 | in| 16| ap_none| p_read18| scalar| +|p_read19 | in| 16| ap_none| p_read19| scalar| +|p_read20 | in| 16| ap_none| p_read20| scalar| +|p_read21 | in| 16| ap_none| p_read21| scalar| +|p_read22 | in| 16| ap_none| p_read22| scalar| +|p_read23 | in| 16| ap_none| p_read23| scalar| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4707_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4707| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4707_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4707| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4707_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4707| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_99 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_99| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_99_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_99| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4708_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4708| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4708_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4708| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4708_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4708| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_98 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_98| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_98_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_98| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4709_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4709| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4709_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4709| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4709_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4709| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_97 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_97| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_97_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_97| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4710_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4710| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4710_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4710| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4710_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4710| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_96 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_96| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_96_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_96| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4711_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4711| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4711_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4711| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4711_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4711| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_95 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_95| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_95_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_95| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4712_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4712| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4712_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4712| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4712_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4712| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_94 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_94| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_94_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_94| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4713_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4713| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4713_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4713| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4713_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4713| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_93 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_93| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_93_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_93| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4714_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4714| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4714_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4714| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4714_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4714| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_92 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_92| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_92_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_92| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4716_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4716| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4716_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4716| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4716_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4716| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_91 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_91| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_91_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_91| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4717_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4717| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4717_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4717| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4717_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4717| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_90 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_90| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_90_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_90| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4718_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4718| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4718_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4718| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4718_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4718| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4564 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4564| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4564_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4564| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4719_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4719| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4719_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4719| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4719_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4719| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4576 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4576| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4576_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4576| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4720_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4720| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4720_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4720| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4720_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4720| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4588 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4588| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4588_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4588| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4721_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4721| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4721_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4721| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4721_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4721| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4600 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4600| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4600_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4600| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4722_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4722| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4722_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4722| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4722_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4722| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4612 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4612| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4612_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4612| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4723_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4723| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4723_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4723| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4723_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4723| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4624 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4624| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4624_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4624| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4724_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4724| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4724_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4724| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4724_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4724| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4636 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4636| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4636_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4636| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4725_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4725| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4725_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4725| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4725_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4725| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4648 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4648| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4648_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4648| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4727_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4727| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4727_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4727| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4727_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4727| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4661 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4661| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4661_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4661| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4728_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4728| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4728_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4728| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4728_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4728| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4673 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4673| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4673_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4673| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4729_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4729| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4729_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4729| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4729_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4729| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4685 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4685| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4685_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4685| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4730_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4730| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4730_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4730| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4730_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4730| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4697 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4697| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4697_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4697| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4731_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4731| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4731_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4731| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4731_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4731| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4705 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4705| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4705_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4705| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4732_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4732| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4732_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4732| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4732_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4732| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4706 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4706| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4706_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4706| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4786_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4786| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4786_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4786| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4786_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4786| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4760 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4760| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4760_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4760| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4787_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4787| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4787_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4787| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4787_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4787| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4761 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4761| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4761_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4761| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4788_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4788| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4788_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4788| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4788_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4788| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4762 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4762| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4762_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4762| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4789_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4789| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4789_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4789| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4789_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4789| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4763 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4763| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4763_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4763| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4565_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4565| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4565_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4565| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4565_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4565| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4764 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4764| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4764_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4764| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4566_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4566| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4566_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4566| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4566_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4566| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4765 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4765| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4765_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4765| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4567_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4567| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4567_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4567| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4567_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4567| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4766 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4766| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4766_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4766| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4568_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4568| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4568_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4568| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4568_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4568| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4767 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4767| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4767_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4767| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4569_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4569| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4569_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4569| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4569_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4569| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4768 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4768| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4768_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4768| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4570_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4570| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4570_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4570| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4570_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4570| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4769 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4769| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4769_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4769| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4571_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4571| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4571_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4571| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4571_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4571| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4771 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4771| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4771_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4771| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4573_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4573| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4573_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4573| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4573_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4573| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4772 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4772| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4772_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4772| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4574_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4574| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4574_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4574| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4574_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4574| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4773 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4773| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4773_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4773| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4575_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4575| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4575_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4575| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4575_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4575| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4774 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4774| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4774_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4774| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4577_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4577| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4577_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4577| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4577_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4577| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4775 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4775| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4775_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4775| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4578_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4578| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4578_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4578| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4578_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4578| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4776 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4776| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4776_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4776| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4579_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4579| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4579_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4579| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4579_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4579| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4777 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4777| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4777_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4777| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4580_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4580| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4580_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4580| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4580_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4580| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4778 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4778| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4778_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4778| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4581_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4581| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4581_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4581| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4581_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4581| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4779 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4779| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4779_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4779| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4582_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4582| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4582_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4582| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4582_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4582| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4780 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4780| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4780_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4780| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4584_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4584| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4584_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4584| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4584_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4584| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4782 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4782| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4782_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4782| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4585_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4585| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4585_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4585| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4585_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4585| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4783 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4783| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4783_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4783| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4586_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4586| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4586_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4586| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4586_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4586| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4784 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4784| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4784_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4784| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4587_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4587| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4587_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4587| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4587_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4587| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4785 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4785| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4785_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4785| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4646_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4646| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4646_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4646| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4646_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4646| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4618 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4618| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4618_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4618| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4647_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4647| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4647_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4647| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4647_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4647| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4619 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4619| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4619_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4619| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4650_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4650| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4650_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4650| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4650_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4650| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4620 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4620| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4620_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4620| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4651_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4651| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4651_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4651| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4651_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4651| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4621 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4621| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4621_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4621| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4652_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4652| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4652_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4652| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4652_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4652| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4622 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4622| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4622_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4622| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4653_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4653| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4653_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4653| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4653_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4653| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4623 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4623| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4623_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4623| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4654_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4654| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4654_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4654| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4654_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4654| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4625 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4625| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4625_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4625| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4655_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4655| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4655_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4655| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4655_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4655| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4626 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4626| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4626_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4626| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4656_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4656| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4656_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4656| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4656_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4656| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4628 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4628| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4628_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4628| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4657_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4657| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4657_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4657| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4657_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4657| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4629 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4629| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4629_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4629| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4658_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4658| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4658_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4658| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4658_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4658| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4630 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4630| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4630_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4630| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4659_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4659| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4659_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4659| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4659_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4659| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4631 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4631| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4631_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4631| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4662_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4662| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4662_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4662| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4662_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4662| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4632 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4632| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4632_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4632| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4663_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4663| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4663_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4663| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4663_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4663| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4633 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4633| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4633_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4633| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4664_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4664| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4664_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4664| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4664_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4664| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4634 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4634| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4634_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4634| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4665_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4665| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4665_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4665| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4665_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4665| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4635 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4635| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4635_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4635| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4666_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4666| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4666_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4666| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4666_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4666| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4637 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4637| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4637_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4637| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4667_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4667| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4667_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4667| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4667_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4667| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4639 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4639| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4639_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4639| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4668_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4668| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4668_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4668| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4668_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4668| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4640 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4640| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4640_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4640| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4669_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4669| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4669_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4669| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4669_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4669| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4641 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4641| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4641_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4641| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4670_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4670| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4670_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4670| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4670_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4670| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4642 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4642| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4642_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4642| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4672_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4672| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4672_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4672| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4672_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4672| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4643 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4643| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4643_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4643| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4674_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4674| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4674_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4674| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4674_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4674| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4644 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4644| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4644_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4644| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4675_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4675| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4675_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4675| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4675_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4675| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4645 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4645| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4645_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4645| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4733_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4733| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4733_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4733| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4733_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4733| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4734_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4734| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4734_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4734| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4734_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4734| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4735_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4735| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4735_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4735| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4735_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4735| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4736_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4736| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4736_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4736| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4736_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4736| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4738_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4738| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4738_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4738| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4738_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4738| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4739_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4739| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4739_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4739| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4739_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4739| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4740_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4740| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4740_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4740| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4740_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4740| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4741_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4741| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4741_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4741| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4741_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4741| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4742_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4742| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4742_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4742| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4742_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4742| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4743_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4743| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4743_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4743| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4743_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4743| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4744_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4744| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4744_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4744| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4744_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4744| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4745_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4745| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4745_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4745| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4745_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4745| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4746_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4746| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4746_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4746| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4746_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4746| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4747_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4747| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4747_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4747| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4747_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4747| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4749_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4749| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4749_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4749| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4749_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4749| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4750_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4750| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4750_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4750| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4750_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4750| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4751_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4751| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4751_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4751| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4751_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4751| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4752_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4752| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4752_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4752| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4752_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4752| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4753_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4753| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4753_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4753| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4753_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4753| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4754_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4754| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4754_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4754| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4754_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4754| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4755_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4755| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4755_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4755| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4755_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4755| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4756_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4756| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4756_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4756| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4756_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4756| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4757_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4757| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4757_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4757| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4757_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4757| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4758_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4758| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4758_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4758| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4758_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4758| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4589_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4589| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4589_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4589| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4589_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4589| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4590_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4590| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4590_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4590| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4590_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4590| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4591_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4591| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4591_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4591| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4591_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4591| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4592_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4592| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4592_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4592| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4592_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4592| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4593_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4593| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4593_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4593| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4593_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4593| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4595_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4595| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4595_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4595| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4595_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4595| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4596_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4596| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4596_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4596| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4596_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4596| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4597_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4597| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4597_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4597| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4597_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4597| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4598_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4598| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4598_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4598| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4598_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4598| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4599_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4599| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4599_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4599| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4599_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4599| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4601_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4601| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4601_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4601| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4601_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4601| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4602_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4602| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4602_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4602| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4602_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4602| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4603_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4603| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4603_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4603| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4603_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4603| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4604_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4604| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4604_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4604| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4604_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4604| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4606_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4606| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4606_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4606| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4606_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4606| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4607_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4607| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4607_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4607| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4607_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4607| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4608_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4608| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4608_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4608| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4608_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4608| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4609_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4609| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4609_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4609| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4609_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4609| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4610_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4610| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4610_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4610| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4610_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4610| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4611_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4611| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4611_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4611| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4611_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4611| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4613_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4613| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4613_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4613| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4613_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4613| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4614_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4614| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4614_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4614| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4614_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4614| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4615_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4615| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4615_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4615| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4615_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4615| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4617_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4617| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4617_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4617| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4617_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4617| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4676_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4676| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4676_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4676| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4676_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4676| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4677_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4677| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4677_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4677| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4677_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4677| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4678_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4678| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4678_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4678| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4678_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4678| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4679_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4679| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4679_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4679| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4679_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4679| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4680_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4680| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4680_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4680| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4680_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4680| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4681_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4681| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4681_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4681| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4681_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4681| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4683_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4683| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4683_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4683| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4683_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4683| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4684_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4684| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4684_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4684| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4684_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4684| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4686_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4686| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4686_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4686| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4686_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4686| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4687_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4687| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4687_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4687| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4687_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4687| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4688_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4688| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4688_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4688| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4688_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4688| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4689_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4689| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4689_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4689| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4689_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4689| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4690_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4690| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4690_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4690| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4690_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4690| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4691_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4691| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4691_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4691| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4691_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4691| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4692_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4692| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4692_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4692| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4692_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4692| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4694_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4694| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4694_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4694| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4694_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4694| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4695_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4695| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4695_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4695| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4695_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4695| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4696_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4696| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4696_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4696| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4696_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4696| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4698_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4698| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4698_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4698| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4698_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4698| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4699_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4699| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4699_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4699| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4699_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4699| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4700_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4700| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4700_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4700| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4700_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4700| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4701_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4701| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4701_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4701| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4701_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4701| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4702_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4702| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4702_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4702| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4702_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4702| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4703_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4703| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4703_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4703| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4703_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4703| pointer| ++-------------------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_csynth.rpt b/myproject_prj/solution1/syn/report/shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..3f492b5f656d63542eedff1e22130724a1a52198 --- /dev/null +++ b/myproject_prj/solution1/syn/report/shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_csynth.rpt @@ -0,0 +1,1180 @@ + + +================================================================ +== Vitis HLS Report for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s' +================================================================ +* Date: Sun Apr 5 21:47:03 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 1.222 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+----------+----------+-----+-----+---------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline| + | min | max | min | max | min | max | Type | + +---------+---------+----------+----------+-----+-----+---------+ + | 0| 0| 0 ns| 0 ns| 1| 1| yes| + +---------+---------+----------+----------+-----+-----+---------+ + + + Detail: + * Instance: + N/A + + * Loop: + N/A + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| -| -| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| -| -| -| +|Memory | -| -| 4096| 2048| -| +|Multiplexer | -| -| 0| 1728| -| +|Register | -| -| 1| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 0| 0| 4097| 3776| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + N/A + + * DSP: + N/A + + * Memory: + +------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+---------+----+----+-----+------+-----+------+-------------+ + | Memory | Module | BRAM_18K| FF | LUT| URAM| Words| Bits| Banks| W*Bits*Banks| + +------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+---------+----+----+-----+------+-----+------+-------------+ + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_943_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_975_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_944_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_976_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_955_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_987_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_966_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_998_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_969_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1001_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_970_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1002_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_971_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1003_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_972_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1004_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_973_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1005_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_974_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1006_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_945_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_977_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_946_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_978_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_947_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_979_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_948_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_980_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_949_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_981_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_950_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_982_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_951_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_983_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_952_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_984_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_953_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_985_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_954_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_986_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_956_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_988_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_957_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_989_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_958_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_990_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_959_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_991_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_960_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_992_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_961_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_993_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_962_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_994_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_963_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_995_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_964_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_996_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_965_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_p_ZZN4nnet26conv_2bKp | 0| 64| 32| 0| 18| 16| 1| 288| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_997_U 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|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5030_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5031_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5032_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5033_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5035_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5036_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5037_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5038_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5039_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5040_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5041_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5042_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5043_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5044_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5046_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5047_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5048_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5049_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5050_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5051_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5052_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5053_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5054_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5055_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5057_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5058_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5059_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5060_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5061_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5062_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5063_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5064_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5065_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5066_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5068_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5069_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5070_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5071_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5072_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5073_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5074_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5075_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5076_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5077_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5079_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5080_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5081_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5082_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5083_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5084_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5085_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5086_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5087_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5088_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5090_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5091_o | 9| 2| 16| 32| + +------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + |Total |1728| 384| 3072| 6144| + +------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + + * Register: + +-----------+---+----+-----+-----------+ + | Name | FF| LUT| Bits| Const Bits| + +-----------+---+----+-----+-----------+ + |ap_CS_fsm | 1| 0| 1| 0| + +-----------+---+----+-----+-----------+ + |Total | 1| 0| 1| 0| + +-----------+---+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++-------------------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++-------------------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| shift_line_buffer, 32u>, config14>| return value| +|ap_rst | in| 1| ap_ctrl_hs| shift_line_buffer, 32u>, config14>| return value| +|ap_start | in| 1| ap_ctrl_hs| shift_line_buffer, 32u>, config14>| return value| +|ap_done | out| 1| ap_ctrl_hs| shift_line_buffer, 32u>, config14>| return value| +|ap_idle | out| 1| ap_ctrl_hs| shift_line_buffer, 32u>, config14>| return value| +|ap_ready | out| 1| ap_ctrl_hs| shift_line_buffer, 32u>, config14>| return value| +|p_read | in| 16| ap_none| p_read| scalar| +|p_read1 | in| 16| ap_none| p_read1| scalar| +|p_read2 | in| 16| ap_none| p_read2| scalar| +|p_read3 | in| 16| ap_none| p_read3| scalar| +|p_read4 | in| 16| ap_none| p_read4| scalar| +|p_read5 | in| 16| ap_none| p_read5| scalar| +|p_read6 | in| 16| ap_none| p_read6| scalar| +|p_read7 | in| 16| ap_none| p_read7| scalar| +|p_read8 | in| 16| ap_none| p_read8| scalar| +|p_read9 | in| 16| ap_none| p_read9| scalar| +|p_read10 | in| 16| ap_none| p_read10| scalar| +|p_read11 | in| 16| ap_none| p_read11| scalar| +|p_read12 | in| 16| ap_none| p_read12| scalar| +|p_read13 | in| 16| ap_none| p_read13| scalar| +|p_read14 | in| 16| ap_none| p_read14| scalar| +|p_read15 | in| 16| ap_none| p_read15| scalar| +|p_read16 | in| 16| ap_none| p_read16| scalar| +|p_read17 | in| 16| ap_none| p_read17| scalar| +|p_read18 | in| 16| ap_none| p_read18| scalar| +|p_read19 | in| 16| ap_none| p_read19| scalar| +|p_read20 | in| 16| ap_none| p_read20| scalar| +|p_read21 | in| 16| ap_none| p_read21| scalar| +|p_read22 | in| 16| ap_none| p_read22| scalar| +|p_read23 | in| 16| ap_none| p_read23| scalar| +|p_read24 | in| 16| ap_none| p_read24| scalar| +|p_read25 | in| 16| ap_none| p_read25| scalar| +|p_read26 | in| 16| ap_none| p_read26| scalar| +|p_read27 | in| 16| ap_none| p_read27| scalar| +|p_read28 | in| 16| ap_none| p_read28| scalar| +|p_read29 | in| 16| ap_none| p_read29| scalar| +|p_read30 | in| 16| ap_none| p_read30| scalar| +|p_read31 | in| 16| ap_none| p_read31| scalar| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5021_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5021| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5021_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5021| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5021_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5021| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_89 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_89| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_89_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_89| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5022_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5022| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5022_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5022| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5022_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5022| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_88 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_88| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_88_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_88| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5024_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5024| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5024_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5024| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5024_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5024| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_87 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_87| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_87_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_87| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5025_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5025| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5025_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5025| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5025_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5025| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_86 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_86| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_86_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_86| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5026_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5026| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5026_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5026| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5026_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5026| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_85 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_85| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_85_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_85| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5027_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5027| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5027_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5027| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5027_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5027| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_84 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_84| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_84_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_84| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5028_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5028| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5028_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5028| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5028_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5028| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_83 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_83| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_83_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_83| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5029_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5029| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5029_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5029| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5029_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5029| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_82 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_82| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_82_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_82| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5030_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5030| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5030_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5030| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5030_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5030| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_81 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_81| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_81_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_81| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5031_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5031| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5031_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5031| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5031_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5031| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_80 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_80| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_80_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_80| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5032_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5032| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5032_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5032| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5032_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5032| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4790 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4790| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4790_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4790| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5033_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5033| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5033_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5033| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5033_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5033| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4802 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4802| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4802_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4802| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5035_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5035| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5035_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5035| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5035_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5035| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4815 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4815| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4815_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4815| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5036_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5036| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5036_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5036| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5036_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5036| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4827 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4827| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4827_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4827| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5037_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5037| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5037_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5037| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5037_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5037| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4839 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4839| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4839_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4839| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5038_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5038| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5038_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5038| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5038_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5038| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4851 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4851| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4851_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4851| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5039_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5039| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5039_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5039| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5039_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5039| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4863 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4863| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4863_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4863| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5040_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5040| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5040_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5040| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5040_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5040| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4875 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4875| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4875_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4875| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5041_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5041| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5041_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5041| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5041_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5041| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4887 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4887| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4887_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4887| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5042_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5042| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5042_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5042| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5042_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5042| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4899 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4899| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4899_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4899| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5043_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5043| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5043_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5043| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5043_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5043| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4911 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4911| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4911_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4911| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5044_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5044| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5044_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5044| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5044_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5044| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4923 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4923| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4923_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4923| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5046_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5046| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5046_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5046| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5046_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5046| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4936 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4936| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4936_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4936| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5047_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5047| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5047_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5047| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5047_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5047| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4948 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4948| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4948_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4948| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5048_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5048| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5048_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5048| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5048_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5048| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4960 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4960| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4960_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4960| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5049_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5049| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5049_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5049| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5049_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5049| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4972 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4972| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4972_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4972| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5050_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5050| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5050_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5050| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5050_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5050| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4984 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4984| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4984_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4984| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5051_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5051| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5051_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5051| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5051_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5051| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4996 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4996| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4996_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4996| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5052_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5052| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5052_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5052| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5052_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5052| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5008 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5008| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5008_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5008| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5053_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5053| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5053_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5053| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5053_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5053| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5018 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5018| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5018_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5018| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5054_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5054| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5054_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5054| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5054_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5054| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5019 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5019| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5019_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5019| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5055_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5055| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5055_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5055| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5055_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5055| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5020 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5020| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5020_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5020| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4824_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4824| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4824_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4824| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4824_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4824| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5092 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5092| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5092_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5092| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4826_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4826| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4826_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4826| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4826_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4826| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5093 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5093| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5093_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5093| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4828_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4828| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4828_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4828| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4828_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4828| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5094 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5094| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5094_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5094| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4829_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4829| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4829_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4829| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4829_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4829| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5095 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5095| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5095_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5095| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4830_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4830| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4830_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4830| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4830_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4830| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4791 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4791| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4791_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4791| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4831_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4831| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4831_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4831| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4831_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4831| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4793 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4793| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4793_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4793| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4832_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4832| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4832_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4832| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4832_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4832| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4794 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4794| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4794_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4794| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4833_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4833| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4833_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4833| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4833_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4833| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4795 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4795| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4795_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4795| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4834_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4834| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4834_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4834| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4834_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4834| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4796 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4796| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4796_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4796| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4835_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4835| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4835_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4835| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4835_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4835| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4797 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4797| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4797_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4797| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4837_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4837| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4837_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4837| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4837_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4837| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4798 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4798| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4798_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4798| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4838_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4838| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4838_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4838| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4838_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4838| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4799 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4799| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4799_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4799| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4840_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4840| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4840_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4840| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4840_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4840| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4800 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4800| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4800_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4800| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4841_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4841| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4841_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4841| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4841_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4841| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4801 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4801| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4801_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4801| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4842_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4842| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4842_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4842| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4842_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4842| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4804 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4804| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4804_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4804| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4843_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4843| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4843_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4843| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4843_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4843| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4805 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4805| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4805_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4805| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4844_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4844| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4844_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4844| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4844_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4844| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4806 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4806| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4806_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4806| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4845_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4845| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4845_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4845| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4845_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4845| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4807 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4807| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4807_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4807| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4846_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4846| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4846_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4846| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4846_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4846| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4808 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4808| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4808_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4808| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4848_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4848| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4848_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4848| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4848_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4848| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4809 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4809| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4809_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4809| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4849_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4849| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4849_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4849| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4849_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4849| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4810 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4810| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4810_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4810| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4850_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4850| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4850_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4850| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4850_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4850| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4811 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4811| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4811_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4811| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4852_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4852| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4852_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4852| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4852_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4852| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4812 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4812| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4812_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4812| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4853_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4853| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4853_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4853| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4853_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4853| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4813 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4813| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4813_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4813| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4854_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4854| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4854_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4854| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4854_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4854| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4816 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4816| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4816_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4816| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4855_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4855| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4855_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4855| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4855_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4855| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4817 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4817| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4817_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4817| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4856_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4856| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4856_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4856| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4856_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4856| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4818 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4818| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4818_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4818| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4857_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4857| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4857_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4857| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4857_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4857| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4819 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4819| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4819_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4819| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4859_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4859| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4859_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4859| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4859_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4859| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4820 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4820| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4820_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4820| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4860_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4860| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4860_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4860| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4860_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4860| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4821 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4821| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4821_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4821| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4861_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4861| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4861_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4861| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4861_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4861| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4822 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4822| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4822_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4822| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4862_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4862| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4862_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4862| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4862_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4862| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4823 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4823| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4823_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4823| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4941_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4941| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4941_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4941| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4941_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4941| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4903 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4903| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4903_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4903| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4942_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4942| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4942_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4942| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4942_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4942| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4904 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4904| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4904_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4904| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4943_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4943| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4943_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4943| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4943_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4943| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4905 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4905| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4905_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4905| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4944_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4944| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4944_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4944| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4944_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4944| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4906 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4906| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4906_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4906| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4945_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4945| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4945_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4945| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4945_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4945| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4907 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4907| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4907_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4907| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4947_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4947| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4947_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4947| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4947_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4947| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4908 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4908| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4908_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4908| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4949_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4949| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4949_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4949| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4949_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4949| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4909 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4909| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4909_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4909| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4950_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4950| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4950_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4950| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4950_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4950| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4910 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4910| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4910_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4910| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4951_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4951| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4951_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4951| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4951_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4951| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4912 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4912| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4912_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4912| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4952_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4952| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4952_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4952| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4952_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4952| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4914 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4914| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4914_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4914| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4953_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4953| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4953_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4953| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4953_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4953| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4915 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4915| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4915_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4915| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4954_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4954| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4954_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4954| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4954_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4954| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4916 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4916| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4916_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4916| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4955_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4955| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4955_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4955| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4955_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4955| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4917 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4917| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4917_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4917| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4956_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4956| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4956_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4956| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4956_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4956| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4918 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4918| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4918_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4918| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4958_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4958| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4958_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4958| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4958_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4958| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4919 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4919| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4919_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4919| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4959_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4959| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4959_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4959| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4959_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4959| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4920 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4920| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4920_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4920| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4961_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4961| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4961_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4961| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4961_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4961| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4921 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4921| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4921_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4921| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4962_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4962| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4962_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4962| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4962_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4962| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4922 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4922| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4922_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4922| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4963_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4963| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4963_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4963| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4963_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4963| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4925 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4925| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4925_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4925| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4964_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4964| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4964_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4964| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4964_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4964| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4926 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4926| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4926_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4926| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4965_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4965| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4965_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4965| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4965_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4965| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4927 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4927| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4927_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4927| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4966_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4966| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4966_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4966| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4966_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4966| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4928 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4928| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4928_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4928| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4967_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4967| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4967_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4967| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4967_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4967| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4929 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4929| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4929_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4929| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4969_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4969| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4969_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4969| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4969_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4969| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4930 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4930| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4930_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4930| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4970_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4970| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4970_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4970| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4970_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4970| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4931 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4931| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4931_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4931| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4971_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4971| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4971_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4971| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4971_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4971| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4932 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4932| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4932_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4932| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4973_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4973| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4973_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4973| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4973_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4973| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4933 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4933| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4933_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4933| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4974_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4974| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4974_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4974| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4974_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4974| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4934 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4934| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4934_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4934| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4975_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4975| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4975_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4975| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4975_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4975| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4937 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4937| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4937_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4937| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4976_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4976| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4976_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4976| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4976_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4976| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4938 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4938| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4938_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4938| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4977_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4977| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4977_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4977| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4977_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4977| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4939 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4939| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4939_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4939| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4978_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4978| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4978_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4978| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4978_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4978| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4940 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4940| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4940_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4940| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5057_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5057| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5057_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5057| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5057_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5057| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5058_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5058| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5058_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5058| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5058_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5058| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5059_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5059| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5059_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5059| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5059_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5059| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5060_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5060| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5060_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5060| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5060_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5060| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5061_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5061| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5061_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5061| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5061_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5061| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5062_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5062| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5062_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5062| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5062_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5062| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5063_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5063| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5063_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5063| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5063_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5063| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5064_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5064| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5064_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5064| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5064_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5064| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5065_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5065| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5065_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5065| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5065_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5065| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5066_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5066| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5066_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5066| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5066_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5066| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5068_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5068| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5068_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5068| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5068_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5068| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5069_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5069| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5069_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5069| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5069_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5069| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5070_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5070| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5070_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5070| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5070_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5070| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5071_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5071| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5071_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5071| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5071_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5071| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5072_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5072| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5072_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5072| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5072_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5072| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5073_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5073| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5073_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5073| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5073_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5073| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5074_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5074| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5074_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5074| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5074_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5074| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5075_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5075| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5075_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5075| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5075_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5075| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5076_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5076| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5076_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5076| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5076_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5076| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5077_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5077| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5077_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5077| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5077_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5077| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5079_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5079| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5079_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5079| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5079_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5079| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5080_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5080| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5080_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5080| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5080_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5080| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5081_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5081| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5081_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5081| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5081_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5081| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5082_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5082| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5082_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5082| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5082_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5082| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5083_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5083| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5083_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5083| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5083_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5083| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5084_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5084| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5084_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5084| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5084_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5084| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5085_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5085| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5085_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5085| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5085_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5085| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5086_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5086| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5086_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5086| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5086_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5086| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5087_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5087| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5087_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5087| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5087_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5087| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5088_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5088| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5088_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5088| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5088_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5088| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5090_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5090| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5090_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5090| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5090_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5090| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5091_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5091| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5091_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5091| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5091_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5091| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4864_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4864| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4864_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4864| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4864_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4864| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4865_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4865| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4865_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4865| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4865_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4865| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4866_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4866| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4866_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4866| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4866_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4866| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4867_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4867| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4867_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4867| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4867_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4867| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4868_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4868| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4868_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4868| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4868_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4868| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4870_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4870| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4870_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4870| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4870_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4870| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4871_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4871| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4871_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4871| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4871_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4871| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4872_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4872| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4872_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4872| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4872_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4872| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4873_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4873| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4873_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4873| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4873_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4873| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4874_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4874| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4874_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4874| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4874_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4874| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4876_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4876| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4876_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4876| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4876_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4876| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4877_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4877| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4877_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4877| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4877_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4877| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4878_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4878| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4878_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4878| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4878_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4878| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4879_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4879| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4879_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4879| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4879_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4879| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4881_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4881| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4881_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4881| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4881_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4881| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4882_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4882| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4882_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4882| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4882_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4882| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4883_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4883| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4883_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4883| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4883_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4883| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4884_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4884| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4884_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4884| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4884_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4884| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4885_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4885| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4885_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4885| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4885_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4885| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4886_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4886| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4886_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4886| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4886_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4886| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4888_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4888| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4888_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4888| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4888_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4888| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4889_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4889| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4889_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4889| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4889_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4889| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4890_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4890| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4890_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4890| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4890_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4890| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4892_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4892| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4892_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4892| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4892_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4892| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4893_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4893| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4893_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4893| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4893_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4893| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4894_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4894| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4894_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4894| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4894_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4894| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4895_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4895| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4895_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4895| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4895_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4895| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4896_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4896| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4896_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4896| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4896_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4896| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4897_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4897| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4897_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4897| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4897_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4897| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4898_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4898| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4898_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4898| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4898_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4898| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4900_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4900| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4900_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4900| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4900_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4900| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4901_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4901| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4901_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4901| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4901_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4901| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4980_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4980| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4980_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4980| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4980_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4980| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4981_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4981| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4981_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4981| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4981_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4981| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4982_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4982| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4982_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4982| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4982_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4982| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4983_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4983| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4983_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4983| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4983_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4983| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4985_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4985| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4985_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4985| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4985_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4985| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4986_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4986| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4986_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4986| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4986_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4986| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4987_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4987| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4987_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4987| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4987_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4987| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4988_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4988| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4988_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4988| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4988_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4988| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4989_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4989| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4989_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4989| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4989_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4989| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4991_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4991| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4991_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4991| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4991_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4991| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4992_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4992| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4992_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4992| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4992_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4992| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4993_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4993| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4993_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4993| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4993_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4993| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4994_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4994| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4994_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4994| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4994_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4994| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4995_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4995| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4995_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4995| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4995_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4995| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4997_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4997| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4997_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4997| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4997_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4997| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4998_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4998| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4998_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4998| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4998_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4998| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4999_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4999| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4999_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4999| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4999_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4999| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5000_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5000| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5000_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5000| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5000_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5000| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5002_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5002| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5002_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5002| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5002_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5002| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5003_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5003| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5003_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5003| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5003_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5003| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5004_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5004| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5004_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5004| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5004_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5004| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5005_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5005| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5005_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5005| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5005_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5005| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5006_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5006| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5006_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5006| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5006_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5006| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5007_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5007| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5007_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5007| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5007_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5007| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5009_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5009| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5009_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5009| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5009_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5009| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5010_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5010| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5010_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5010| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5010_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5010| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5011_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5011| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5011_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5011| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5011_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5011| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5013_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5013| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5013_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5013| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5013_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5013| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5014_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5014| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5014_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5014| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5014_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5014| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5015_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5015| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5015_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5015| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5015_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5015| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5016_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5016| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5016_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5016| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5016_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5016| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5017_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5017| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5017_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5017| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5017_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5017| pointer| ++-------------------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_csynth.xml b/myproject_prj/solution1/syn/report/shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..a5b4ecf191cc95cb671f97bff6cee1a9d00f7ade --- /dev/null +++ b/myproject_prj/solution1/syn/report/shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_csynth.xml @@ -0,0 +1,8930 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s +4.00 +1.35 +4294967295 +vivado + + + +yes + +ns +1.222 + + +clock cycles +0 +0 +0 +0 ns +0 ns +0 ns +1 +1 +1 +1 + + +- +- +firmware/nnet_utils/nnet_conv_stream.h:232 + + + + + +4097 +3776 +0 +0 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 32u>, config14> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 32u>, config14> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 32u>, config14> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_done +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 32u>, config14> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_idle +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 32u>, config14> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 32u>, config14> +return value + +ap_ctrl_hs + +out +1 +control + + +p_read +p_read +scalar + +ap_none + +in +16 +data + + +p_read1 +p_read1 +scalar + +ap_none + +in +16 +data + + +p_read2 +p_read2 +scalar + +ap_none + +in +16 +data + + +p_read3 +p_read3 +scalar + +ap_none + +in +16 +data + + +p_read4 +p_read4 +scalar + +ap_none + +in +16 +data + + +p_read5 +p_read5 +scalar + +ap_none + +in +16 +data + + +p_read6 +p_read6 +scalar + +ap_none + +in +16 +data + + +p_read7 +p_read7 +scalar + +ap_none + +in +16 +data + + +p_read8 +p_read8 +scalar + +ap_none + +in +16 +data + + +p_read9 +p_read9 +scalar + +ap_none + +in +16 +data + + +p_read10 +p_read10 +scalar + +ap_none + +in +16 +data + + +p_read11 +p_read11 +scalar + +ap_none + +in +16 +data + + +p_read12 +p_read12 +scalar + +ap_none + +in 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+ +out +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_89_ap_vld +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_89 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5022_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5022 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5022_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5022 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5022_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5022 +pointer +global +ap_ovld + +out +1 +control + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_88 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_88 +pointer +global +ap_vld + +out +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_88_ap_vld +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_88 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5024_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5024 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5024_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5024 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5024_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5024 +pointer +global +ap_ovld + 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a/myproject_prj/solution1/syn/report/shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_csynth.xml b/myproject_prj/solution1/syn/report/shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..0f31e4598763264022261840b2552a625c7f1bc5 --- /dev/null +++ b/myproject_prj/solution1/syn/report/shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_csynth.xml @@ -0,0 +1,4013 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s +4.00 +1.35 +4294967295 +vivado + + + +yes + +ns +0.611 + + +clock cycles +0 +0 +0 +0 ns +0 ns +0 ns +1 +1 +1 +1 + + +- +- +firmware/nnet_utils/nnet_conv_stream.h:232 + + + + + +2049 +1600 +0 +0 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 32u>, config16> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 32u>, config16> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 32u>, config16> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_done +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 32u>, config16> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_idle +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 32u>, config16> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 32u>, config16> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ce +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 32u>, config16> +return value + +ap_ctrl_hs + +in +1 +control + + +p_read +p_read +scalar + +ap_none + +in +16 +data + + +p_read1 +p_read1 +scalar + +ap_none + +in +16 +data + + +p_read2 +p_read2 +scalar + +ap_none + +in +16 +data + + +p_read3 +p_read3 +scalar + +ap_none + +in +16 +data + + +p_read4 +p_read4 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+void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_15_ap_vld +void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_15 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_84_i +p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_84 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_84_o +p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_84 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_84_o_ap_vld +p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_84 +pointer +global +ap_ovld + +out +1 +control + + +void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_14 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+control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5637_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5637 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5637_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5637 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5637_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5637 +pointer +global +ap_ovld + +out +1 +control + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_65 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_65 +pointer +global +ap_vld + +out +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_65_ap_vld +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_65 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5638_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5638 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5638_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5638 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5638_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5638 +pointer +global +ap_ovld + +out +1 +control + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_64 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_64 +pointer +global +ap_vld + +out +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_64_ap_vld +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_64 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5640_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5640 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5640_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5640 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5640_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5640 +pointer +global +ap_ovld + +out +1 +control + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_63 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_63 +pointer +global +ap_vld + +out +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_63_ap_vld +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_63 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5641_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5641 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5641_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5641 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5641_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5641 +pointer +global +ap_ovld + +out +1 +control + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_62 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_62 +pointer +global +ap_vld + +out +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_62_ap_vld +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_62 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5642_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5642 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5642_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5642 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5642_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5642 +pointer +global +ap_ovld + +out +1 +control + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_61 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_61 +pointer +global +ap_vld + +out +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_61_ap_vld +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_61 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5643_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5643 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5643_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5643 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5643_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5643 +pointer +global +ap_ovld + +out +1 +control + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_60 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_60 +pointer +global +ap_vld + +out +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_60_ap_vld +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_60 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5644_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5644 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5644_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5644 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5644_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5644 +pointer +global +ap_ovld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5402 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5402 +pointer +global +ap_vld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5402_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5402 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5645_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5645 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5645_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5645 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5645_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5645 +pointer +global +ap_ovld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5414 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5414 +pointer +global +ap_vld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5414_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5414 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5646_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5646 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5646_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5646 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5646_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5646 +pointer +global +ap_ovld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5426 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5426 +pointer +global +ap_vld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5426_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5426 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5647_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5647 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5647_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5647 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5647_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5647 +pointer +global +ap_ovld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5438 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5438 +pointer +global +ap_vld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5438_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5438 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5648_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5648 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5648_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5648 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5648_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5648 +pointer +global +ap_ovld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5450 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5450 +pointer +global +ap_vld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5450_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5450 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5649_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5649 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5649_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5649 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5649_o_ap_vld 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+2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s +4.00 +1.35 +4294967295 +vivado + + + +yes + +ns +1.222 + + +clock cycles +0 +0 +0 +0 ns +0 ns +0 ns +1 +1 +1 +1 + + +- +- +firmware/nnet_utils/nnet_conv_stream.h:232 + + + + + +6145 +5664 +0 +0 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 48u>, config29> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 48u>, config29> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 48u>, config29> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_done +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 48u>, config29> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_idle +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 48u>, config29> +return value + +ap_ctrl_hs + +out +1 +control + + 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+p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6109_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6109 +pointer +global +ap_ovld + +out +1 +control + + + + diff --git a/myproject_prj/solution1/syn/report/shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_csynth.rpt b/myproject_prj/solution1/syn/report/shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..de31a3c2f1e62cde4164a18f85b6b901a36a0338 --- /dev/null +++ b/myproject_prj/solution1/syn/report/shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_csynth.rpt @@ -0,0 +1,388 @@ + + +================================================================ +== Vitis HLS Report for 'shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s' +================================================================ +* Date: Sun Apr 5 21:50:39 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 1.222 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+----------+----------+-----+-----+---------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline| + | min | max | min | max | min | max | Type | + +---------+---------+----------+----------+-----+-----+---------+ + | 0| 0| 0 ns| 0 ns| 1| 1| yes| + +---------+---------+----------+----------+-----+-----+---------+ + + + Detail: + * Instance: + N/A + + * Loop: + N/A + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| -| -| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| -| -| -| +|Memory | -| -| 1024| 512| -| +|Multiplexer | -| -| 0| 432| -| +|Register | -| -| 1| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 0| 0| 1025| 944| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + N/A + + * DSP: + N/A + + * Memory: + +------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+---------+----+----+-----+------+-----+------+-------------+ + | Memory | Module | BRAM_18K| FF | LUT| URAM| Words| Bits| Banks| W*Bits*Banks| + +------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+---------+----+----+-----+------+-----+------+-------------+ + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1391_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1399_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1392_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1400_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1393_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1401_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1394_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1402_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1395_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1403_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1396_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1404_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1397_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1405_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1398_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1406_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + +------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+---------+----+----+-----+------+-----+------+-------------+ + |Total | | 0|1024| 512| 0| 1056| 256| 16| 16896| + +------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+---------+----+----+-----+------+-----+------+-------------+ + + * FIFO: + N/A + + * Expression: + N/A + + * Multiplexer: + +------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3553_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3554_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3555_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3556_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3557_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3558_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3559_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3560_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3561_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3562_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3563_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3564_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3565_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3566_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3575_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3576_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3577_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3578_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3579_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3580_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3581_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3582_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3583_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3584_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3585_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3586_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3587_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3588_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3589_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3590_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3599_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3600_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3601_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3602_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3603_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3604_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3605_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3606_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3607_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3608_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3609_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3610_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3611_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3612_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3613_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3614_o | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_20_o | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_21_o | 9| 2| 16| 32| + +------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + |Total | 432| 96| 768| 1536| + +------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + + * Register: + +-----------+---+----+-----+-----------+ + | Name | FF| LUT| Bits| Const Bits| + +-----------+---+----+-----+-----------+ + |ap_CS_fsm | 1| 0| 1| 0| + +-----------+---+----+-----+-----------+ + |Total | 1| 0| 1| 0| + +-----------+---+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++-------------------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++-------------------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| shift_line_buffer, 8u>, config37>| return value| +|ap_rst | in| 1| ap_ctrl_hs| shift_line_buffer, 8u>, config37>| return value| +|ap_start | in| 1| ap_ctrl_hs| shift_line_buffer, 8u>, config37>| return value| +|ap_done | out| 1| ap_ctrl_hs| shift_line_buffer, 8u>, config37>| return value| +|ap_idle | out| 1| ap_ctrl_hs| shift_line_buffer, 8u>, config37>| return value| +|ap_ready | out| 1| ap_ctrl_hs| shift_line_buffer, 8u>, config37>| return value| +|p_read | in| 16| ap_none| p_read| scalar| +|p_read1 | in| 16| ap_none| p_read1| scalar| +|p_read2 | in| 16| ap_none| p_read2| scalar| +|p_read3 | in| 16| ap_none| p_read3| scalar| +|p_read4 | in| 16| ap_none| p_read4| scalar| +|p_read5 | in| 16| ap_none| p_read5| scalar| +|p_read6 | in| 16| ap_none| p_read6| scalar| +|p_read7 | in| 16| ap_none| p_read7| scalar| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_21_i | in| 16| ap_ovld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_21| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_21_o | out| 16| ap_ovld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_21| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_21_o_ap_vld | out| 1| ap_ovld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_21| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_29 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_29| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_29_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_29| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_20_i | in| 16| ap_ovld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_20| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_20_o | out| 16| ap_ovld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_20| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_20_o_ap_vld | out| 1| ap_ovld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_20| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_28 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_28| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_28_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_28| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3553_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3553| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3553_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3553| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3553_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3553| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_27 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_27| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_27_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_27| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3554_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3554| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3554_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3554| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3554_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3554| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_26 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_26| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_26_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_26| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3555_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3555| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3555_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3555| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3555_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3555| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_25 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_25| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_25_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_25| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3556_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3556| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3556_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3556| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3556_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3556| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_24 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_24| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_24_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_24| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3557_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3557| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3557_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3557| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3557_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3557| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_23 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_23| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_23_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_23| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3558_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3558| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3558_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3558| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3558_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3558| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_22 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_22| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_22_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_22| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3575_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3575| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3575_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3575| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3575_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3575| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3567 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3567| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3567_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3567| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3576_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3576| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3576_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3576| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3576_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3576| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3568 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3568| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3568_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3568| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3577_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3577| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3577_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3577| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3577_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3577| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3569 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3569| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3569_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3569| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3578_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3578| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3578_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3578| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3578_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3578| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3570 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3570| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3570_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3570| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3579_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3579| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3579_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3579| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3579_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3579| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3571 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3571| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3571_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3571| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3580_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3580| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3580_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3580| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3580_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3580| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3572 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3572| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3572_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3572| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3581_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3581| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3581_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3581| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3581_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3581| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3573 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3573| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3573_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3573| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3582_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3582| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3582_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3582| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3582_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3582| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3574 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3574| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3574_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3574| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3599_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3599| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3599_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3599| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3599_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3599| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3591 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3591| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3591_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3591| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3600_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3600| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3600_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3600| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3600_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3600| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3592 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3592| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3592_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3592| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3601_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3601| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3601_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3601| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3601_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3601| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3593 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3593| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3593_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3593| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3602_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3602| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3602_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3602| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3602_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3602| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3594 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3594| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3594_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3594| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3603_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3603| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3603_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3603| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3603_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3603| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3595 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3595| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3595_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3595| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3604_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3604| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3604_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3604| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3604_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3604| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3596 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3596| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3596_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3596| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3605_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3605| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3605_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3605| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3605_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3605| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3597 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3597| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3597_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3597| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3606_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3606| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3606_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3606| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3606_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3606| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3598 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3598| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3598_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3598| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3559_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3559| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3559_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3559| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3559_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3559| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3560_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3560| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3560_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3560| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3560_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3560| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3561_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3561| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3561_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3561| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3561_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3561| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3562_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3562| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3562_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3562| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3562_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3562| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3563_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3563| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3563_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3563| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3563_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3563| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3564_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3564| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3564_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3564| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3564_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3564| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3565_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3565| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3565_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3565| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3565_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3565| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3566_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3566| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3566_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3566| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3566_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3566| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3583_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3583| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3583_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3583| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3583_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3583| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3584_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3584| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3584_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3584| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3584_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3584| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3585_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3585| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3585_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3585| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3585_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3585| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3586_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3586| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3586_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3586| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3586_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3586| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3587_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3587| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3587_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3587| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3587_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3587| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3588_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3588| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3588_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3588| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3588_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3588| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3589_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3589| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3589_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3589| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3589_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3589| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3590_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3590| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3590_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3590| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3590_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3590| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3607_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3607| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3607_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3607| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3607_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3607| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3608_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3608| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3608_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3608| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3608_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3608| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3609_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3609| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3609_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3609| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3609_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3609| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3610_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3610| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3610_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3610| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3610_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3610| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3611_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3611| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3611_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3611| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3611_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3611| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3612_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3612| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3612_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3612| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3612_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3612| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3613_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3613| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3613_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3613| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3613_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3613| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3614_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3614| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3614_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3614| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3614_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3614| pointer| ++-------------------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_csynth.xml b/myproject_prj/solution1/syn/report/shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..2bfe30b9ce3cb06447c57f0e7a23d16ec64946ef --- /dev/null +++ b/myproject_prj/solution1/syn/report/shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_csynth.xml @@ -0,0 +1,2330 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s +4.00 +1.35 +4294967295 +vivado + + + +yes + +ns +1.222 + + +clock cycles +0 +0 +0 +0 ns +0 ns +0 ns +1 +1 +1 +1 + + +- +- +firmware/nnet_utils/nnet_conv_stream.h:232 + + + + + +1025 +944 +0 +0 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 8u>, config37> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 8u>, config37> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 8u>, config37> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_done +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 8u>, config37> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_idle +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 8u>, config37> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +shift_line_buffer<array<ap_fixed<16, 6, 5, 3, 0>, 8u>, config37> +return value + +ap_ctrl_hs + +out +1 +control + + +p_read +p_read +scalar + +ap_none + +in +16 +data + + +p_read1 +p_read1 +scalar + +ap_none + +in +16 +data + + +p_read2 +p_read2 +scalar + +ap_none + +in +16 +data + + +p_read3 +p_read3 +scalar + +ap_none + +in +16 +data + + +p_read4 +p_read4 +scalar + +ap_none + +in +16 +data + + +p_read5 +p_read5 +scalar + +ap_none + +in +16 +data + + +p_read6 +p_read6 +scalar + +ap_none + +in +16 +data + + +p_read7 +p_read7 +scalar + +ap_none + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_21_i +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_21 +pointer +global +ap_ovld + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_21_o +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_21 +pointer +global +ap_ovld + +out +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_21_o_ap_vld +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_21 +pointer +global +ap_ovld + +out +1 +control + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_29 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_29 +pointer +global +ap_vld + +out +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_29_ap_vld +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_29 +pointer +global +ap_vld + +out +1 +control + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_20_i +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_20 +pointer +global +ap_ovld + +in +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_20_o +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_20 +pointer +global +ap_ovld + +out +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_20_o_ap_vld +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_20 +pointer +global +ap_ovld + +out +1 +control + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_28 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_28 +pointer +global +ap_vld + +out +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_28_ap_vld +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_28 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3553_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3553 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3553_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3553 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3553_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3553 +pointer +global +ap_ovld + +out +1 +control + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_27 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_27 +pointer +global +ap_vld + +out +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_27_ap_vld +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_27 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3554_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3554 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3554_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3554 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3554_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3554 +pointer +global +ap_ovld + +out +1 +control + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_26 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_26 +pointer +global +ap_vld + +out +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_26_ap_vld +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_26 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3555_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3555 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3555_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3555 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3555_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3555 +pointer +global +ap_ovld + +out +1 +control + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_25 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_25 +pointer +global +ap_vld + +out +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_25_ap_vld +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_25 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3556_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3556 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3556_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3556 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3556_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3556 +pointer +global +ap_ovld + +out +1 +control + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_24 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_24 +pointer +global +ap_vld + +out +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_24_ap_vld +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_24 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3557_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3557 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3557_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3557 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3557_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3557 +pointer +global +ap_ovld + +out +1 +control + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_23 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_23 +pointer +global +ap_vld + +out +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_23_ap_vld +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_23 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3558_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3558 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3558_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3558 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3558_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3558 +pointer +global +ap_ovld + +out +1 +control + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_22 +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_22 +pointer +global +ap_vld + +out +16 +data + + +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_22_ap_vld +void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_22 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3575_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3575 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3575_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3575 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3575_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3575 +pointer +global +ap_ovld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3567 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3567 +pointer +global +ap_vld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3567_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3567 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3576_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3576 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3576_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3576 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3576_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3576 +pointer +global +ap_ovld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3568 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3568 +pointer +global +ap_vld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3568_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3568 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3577_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3577 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3577_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3577 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3577_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3577 +pointer +global +ap_ovld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3569 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3569 +pointer +global +ap_vld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3569_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3569 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3578_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3578 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3578_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3578 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3578_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3578 +pointer +global +ap_ovld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3570 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3570 +pointer +global +ap_vld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3570_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3570 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3579_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3579 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3579_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3579 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3579_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3579 +pointer +global +ap_ovld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3571 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3571 +pointer +global +ap_vld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3571_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3571 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3580_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3580 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3580_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3580 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3580_o_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3580 +pointer +global +ap_ovld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3572 +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3572 +pointer +global +ap_vld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3572_ap_vld +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3572 +pointer +global +ap_vld + +out +1 +control + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3581_i +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3581 +pointer +global +ap_ovld + +in +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3581_o +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3581 +pointer +global +ap_ovld + +out +16 +data + + +p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3581_o_ap_vld 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on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 1.222 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+----------+----------+-----+-----+---------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline| + | min | max | min | max | min | max | Type | + +---------+---------+----------+----------+-----+-----+---------+ + | 0| 0| 0 ns| 0 ns| 1| 1| yes| + +---------+---------+----------+----------+-----+-----+---------+ + + + Detail: + * Instance: + N/A + + * Loop: + N/A + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| -| -| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| -| -| -| +|Memory | -| -| 1024| 512| -| +|Multiplexer | -| -| 0| 432| -| +|Register | -| -| 1| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 0| 0| 1025| 944| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + N/A + + * DSP: + N/A + + * Memory: + +------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+---------+----+----+-----+------+-----+------+-------------+ + | Memory | Module | BRAM_18K| FF | LUT| URAM| Words| Bits| Banks| W*Bits*Banks| + +------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+---------+----+----+-----+------+-----+------+-------------+ + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1375_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1383_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1376_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1384_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1377_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1385_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1378_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1386_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1379_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1387_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1380_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1388_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1381_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1389_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1382_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + |p_ZZN4nnet26conv_2d_buffer_resource_clINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5E_1390_U |shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb | 0| 64| 32| 0| 66| 16| 1| 1056| + +------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+---------+----+----+-----+------+-----+------+-------------+ + |Total | | 0|1024| 512| 0| 1056| 256| 16| 16896| + +------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+---------+----+----+-----+------+-----+------+-------------+ + + * FIFO: + N/A + + * Expression: + N/A + + * Multiplexer: + +------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3491_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3492_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3493_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3494_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3495_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3496_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3497_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3498_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3499_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3500_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3501_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3502_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3503_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3504_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3513_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3514_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3515_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3516_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3517_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3518_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3519_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3520_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3521_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3522_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3523_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3524_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3525_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3526_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3527_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3528_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3537_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3538_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3539_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3540_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3541_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3542_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3543_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3544_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3545_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3546_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3547_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3548_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3549_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3550_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3551_o | 9| 2| 16| 32| + |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3552_o | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_18_o | 9| 2| 16| 32| + |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_19_o | 9| 2| 16| 32| + +------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + |Total | 432| 96| 768| 1536| + +------------------------------------------------------------------------------------------+----+-----------+-----+-----------+ + + * Register: + +-----------+---+----+-----+-----------+ + | Name | FF| LUT| Bits| Const Bits| + +-----------+---+----+-----+-----------+ + |ap_CS_fsm | 1| 0| 1| 0| + +-----------+---+----+-----+-----------+ + |Total | 1| 0| 1| 0| + +-----------+---+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++-------------------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++-------------------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| shift_line_buffer, 8u>, config4>| return value| +|ap_rst | in| 1| ap_ctrl_hs| shift_line_buffer, 8u>, config4>| return value| +|ap_start | in| 1| ap_ctrl_hs| shift_line_buffer, 8u>, config4>| return value| +|ap_done | out| 1| ap_ctrl_hs| shift_line_buffer, 8u>, config4>| return value| +|ap_idle | out| 1| ap_ctrl_hs| shift_line_buffer, 8u>, config4>| return value| +|ap_ready | out| 1| ap_ctrl_hs| shift_line_buffer, 8u>, config4>| return value| +|p_read | in| 16| ap_none| p_read| scalar| +|p_read1 | in| 16| ap_none| p_read1| scalar| +|p_read2 | in| 16| ap_none| p_read2| scalar| +|p_read3 | in| 16| ap_none| p_read3| scalar| +|p_read4 | in| 16| ap_none| p_read4| scalar| +|p_read5 | in| 16| ap_none| p_read5| scalar| +|p_read6 | in| 16| ap_none| p_read6| scalar| +|p_read7 | in| 16| ap_none| p_read7| scalar| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_18_i | in| 16| ap_ovld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_18| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_18_o | out| 16| ap_ovld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_18| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_18_o_ap_vld | out| 1| ap_ovld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_18| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_10 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_10| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_10_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_10| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_19_i | in| 16| ap_ovld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_19| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_19_o | out| 16| ap_ovld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_19| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_19_o_ap_vld | out| 1| ap_ovld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_19| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_11 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_11| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_11_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_11| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3491_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3491| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3491_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3491| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3491_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3491| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_12 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_12| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_12_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_12| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3492_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3492| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3492_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3492| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3492_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3492| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_13 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_13| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_13_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_13| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3493_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3493| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3493_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3493| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3493_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3493| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_14 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_14| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_14_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_14| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3494_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3494| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3494_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3494| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3494_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3494| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_15 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_15| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_15_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_15| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3495_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3495| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3495_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3495| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3495_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3495| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_16 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_16| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_16_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_16| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3496_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3496| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3496_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3496| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3496_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3496| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_17 | out| 16| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_17| pointer| +|void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_17_ap_vld | out| 1| ap_vld| void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_17| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3513_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3513| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3513_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3513| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3513_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3513| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3505 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3505| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3505_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3505| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3514_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3514| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3514_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3514| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3514_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3514| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3506 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3506| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3506_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3506| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3515_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3515| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3515_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3515| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3515_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3515| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3507 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3507| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3507_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3507| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3516_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3516| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3516_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3516| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3516_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3516| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3508 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3508| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3508_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3508| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3517_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3517| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3517_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3517| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3517_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3517| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3509 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3509| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3509_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3509| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3518_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3518| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3518_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3518| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3518_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3518| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3510 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3510| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3510_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3510| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3519_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3519| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3519_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3519| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3519_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3519| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3511 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3511| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3511_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3511| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3520_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3520| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3520_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3520| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3520_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3520| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3512 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3512| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3512_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3512| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3537_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3537| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3537_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3537| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3537_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3537| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3529 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3529| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3529_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3529| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3538_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3538| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3538_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3538| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3538_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3538| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3530 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3530| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3530_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3530| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3539_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3539| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3539_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3539| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3539_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3539| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3531 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3531| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3531_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3531| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3540_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3540| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3540_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3540| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3540_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3540| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3532 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3532| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3532_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3532| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3541_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3541| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3541_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3541| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3541_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3541| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3533 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3533| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3533_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3533| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3542_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3542| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3542_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3542| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3542_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3542| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3534 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3534| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3534_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3534| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3543_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3543| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3543_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3543| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3543_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3543| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3535 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3535| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3535_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3535| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3544_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3544| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3544_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3544| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3544_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3544| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3536 | out| 16| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3536| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3536_ap_vld | out| 1| ap_vld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3536| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3497_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3497| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3497_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3497| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3497_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3497| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3498_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3498| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3498_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3498| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3498_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3498| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3499_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3499| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3499_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3499| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3499_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3499| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3500_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3500| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3500_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3500| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3500_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3500| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3501_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3501| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3501_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3501| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3501_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3501| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3502_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3502| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3502_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3502| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3502_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3502| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3503_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3503| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3503_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3503| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3503_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3503| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3504_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3504| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3504_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3504| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3504_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3504| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3521_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3521| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3521_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3521| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3521_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3521| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3522_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3522| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3522_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3522| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3522_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3522| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3523_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3523| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3523_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3523| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3523_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3523| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3524_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3524| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3524_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3524| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3524_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3524| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3525_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3525| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3525_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3525| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3525_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3525| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3526_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3526| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3526_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3526| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3526_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3526| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3527_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3527| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3527_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3527| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3527_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3527| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3528_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3528| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3528_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3528| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3528_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3528| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3545_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3545| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3545_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3545| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3545_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3545| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3546_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3546| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3546_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3546| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3546_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3546| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3547_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3547| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3547_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3547| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3547_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3547| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3548_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3548| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3548_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3548| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3548_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3548| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3549_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3549| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3549_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3549| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3549_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3549| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3550_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3550| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3550_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3550| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3550_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3550| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3551_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3551| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3551_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3551| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3551_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3551| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3552_i | in| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3552| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3552_o | out| 16| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3552| pointer| +|p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3552_o_ap_vld | out| 1| ap_ovld| p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_3552| pointer| ++-------------------------------------------------------------------------------------------------+-----+-----+------------+----------------------------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s_csynth.xml b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..b69479cef944b40fa27d12a9fdb6bd969125cd7e --- /dev/null +++ b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s_csynth.xml @@ -0,0 +1,281 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_s +4.00 +1.35 +vivado + + + +no + +ns +1.480 + + +clock cycles +4369 +4369 +4369 +17.476 us +17.476 us +17.476 us +4369 +4369 + + +- +- +firmware/nnet_utils/nnet_padding_stream.h:81 + + + + + +238 +811 +0 +0 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +zeropad2d_cl<array<ap_fixed,8u>,array<ap_fixed<16,6,5,3,0>,8u>,config45> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +zeropad2d_cl<array<ap_fixed,8u>,array<ap_fixed<16,6,5,3,0>,8u>,config45> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +zeropad2d_cl<array<ap_fixed,8u>,array<ap_fixed<16,6,5,3,0>,8u>,config45> +return value + +ap_ctrl_hs + +in +1 +control + + +start_full_n +zeropad2d_cl<array<ap_fixed,8u>,array<ap_fixed<16,6,5,3,0>,8u>,config45> +return value + +ap_ctrl_hs + +in +1 +unknown + + +ap_done +zeropad2d_cl<array<ap_fixed,8u>,array<ap_fixed<16,6,5,3,0>,8u>,config45> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_continue +zeropad2d_cl<array<ap_fixed,8u>,array<ap_fixed<16,6,5,3,0>,8u>,config45> +return value + +ap_ctrl_hs + +in +1 +control + + +ap_idle +zeropad2d_cl<array<ap_fixed,8u>,array<ap_fixed<16,6,5,3,0>,8u>,config45> +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +zeropad2d_cl<array<ap_fixed,8u>,array<ap_fixed<16,6,5,3,0>,8u>,config45> +return value + +ap_ctrl_hs + +out +1 +control + + +start_out +zeropad2d_cl<array<ap_fixed,8u>,array<ap_fixed<16,6,5,3,0>,8u>,config45> +return value + +ap_ctrl_hs + +out +1 +unknown + + +start_write +zeropad2d_cl<array<ap_fixed,8u>,array<ap_fixed<16,6,5,3,0>,8u>,config45> +return value + +ap_ctrl_hs + +out +1 +unknown + + +layer3_out_dout +layer3_out +pointer + +ap_fifo + +in +128 +control + + +layer3_out_num_data_valid +layer3_out +pointer + +ap_fifo + +in +13 +control + + +layer3_out_fifo_cap +layer3_out +pointer + +ap_fifo + +in +13 +unknown + + +layer3_out_empty_n +layer3_out +pointer + +ap_fifo + +in +1 +control + + +layer3_out_read +layer3_out +pointer + +ap_fifo + +out +1 +control + + +layer45_out_din +layer45_out +pointer + +ap_fifo + +out +128 +control + + +layer45_out_num_data_valid +layer45_out +pointer + +ap_fifo + +in +14 +control + + +layer45_out_fifo_cap +layer45_out +pointer + +ap_fifo + +in +14 +unknown + + +layer45_out_full_n +layer45_out +pointer + +ap_fifo + +in +1 +control + + +layer45_out_write +layer45_out +pointer + +ap_fifo + +out +1 +control + + + + diff --git a/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain_csynth.xml b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..ec762391a64c3d21454731b8e512d8903f49a27f --- /dev/null +++ b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain_csynth.xml @@ -0,0 +1,258 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain +4.00 +1.35 +vivado + + + +loop auto-rewind stp(delay=0 clock cycles(s)) + +ns +1.480 + + +clock cycles +1090 +1090 +1090 +4.360 us +4.360 us +4.360 us +1089 +1089 + + + +2.65 +32 +1088 +4352 +34 +35 + + + + + +- +- +firmware/nnet_utils/nnet_padding_stream.h:59 + + +PadMain +II Violation +Memory Dependency +1 +firmware/nnet_utils/nnet_padding_stream.h:59 + + + + + + + +300 +346 +0 +0 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,16u>,config47>_Pipeline_PadMain +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,16u>,config47>_Pipeline_PadMain +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,16u>,config47>_Pipeline_PadMain +return value + +ap_ctrl_hs + +in +1 +control + + +ap_done +zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,16u>,config47>_Pipeline_PadMain +return value + +ap_ctrl_hs + +out +1 +control + + +ap_idle +zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,16u>,config47>_Pipeline_PadMain +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,16u>,config47>_Pipeline_PadMain +return value + +ap_ctrl_hs + +out +1 +control + + +layer47_out_din +layer47_out +pointer + +ap_fifo + +out +256 +control + + +layer47_out_num_data_valid +layer47_out +pointer + +ap_fifo + +in +12 +control + + +layer47_out_fifo_cap +layer47_out +pointer + +ap_fifo + +in +12 +unknown + + +layer47_out_full_n +layer47_out +pointer + +ap_fifo + +in +1 +control + + +layer47_out_write +layer47_out +pointer + +ap_fifo + +out +1 +control + + +layer8_out_dout +layer8_out +pointer + +ap_fifo + +in +256 +control + + +layer8_out_num_data_valid +layer8_out +pointer + +ap_fifo + +in +11 +control + + +layer8_out_fifo_cap +layer8_out +pointer + +ap_fifo + +in +11 +unknown + + +layer8_out_empty_n +layer8_out +pointer + +ap_fifo + +in +1 +control + + +layer8_out_read +layer8_out +pointer + +ap_fifo + +out +1 +control + + + + diff --git a/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth_csynth.rpt b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..6a2d53f1b01063c4155982a933234405465bcd56 --- /dev/null +++ b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth_csynth.rpt @@ -0,0 +1,146 @@ + + +================================================================ +== Vitis HLS Report for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth' +================================================================ +* Date: Sun Apr 5 21:46:29 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 1.480 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+----------+----------+-----+-----+-----------------------------------------------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | min | max | min | max | min | max | Type | + +---------+---------+----------+----------+-----+-----+-----------------------------------------------+ + | 68| 68| 0.272 us| 0.272 us| 67| 67| loop auto-rewind stp(delay=0 clock cycles(s))| + +---------+---------+----------+----------+-----+-----+-----------------------------------------------+ + + + Detail: + * Instance: + N/A + + * Loop: + +---------------+---------+---------+----------+-----------+-----------+------+----------+ + | | Latency (cycles) | Iteration| Initiation Interval | Trip | | + | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| + +---------------+---------+---------+----------+-----------+-----------+------+----------+ + |- PadTopWidth | 66| 66| 2| 1| 1| 66| yes| + +---------------+---------+---------+----------+-----------+-----------+------+----------+ + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 32| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| -| -| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| 0| 45| -| +|Register | -| -| 10| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 0| 0| 10| 77| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + N/A + + * DSP: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +---------------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +---------------------------+----------+----+---+----+------------+------------+ + |j_8_fu_60_p2 | +| 0| 0| 14| 7| 1| + |ap_block_pp0_stage0_01001 | and| 0| 0| 2| 1| 1| + |icmp_ln53_fu_54_p2 | icmp| 0| 0| 14| 7| 7| + |ap_enable_pp0 | xor| 0| 0| 2| 1| 2| + +---------------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0| 32| 16| 11| + +---------------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +-------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +-------------------------+----+-----------+-----+-----------+ + |ap_done_int | 9| 2| 1| 2| + |ap_enable_reg_pp0_iter1 | 9| 2| 1| 2| + |ap_sig_allocacmp_j_7 | 9| 2| 7| 14| + |j_fu_34 | 9| 2| 7| 14| + |layer44_out_blk_n | 9| 2| 1| 2| + +-------------------------+----+-----------+-----+-----------+ + |Total | 45| 10| 17| 34| + +-------------------------+----+-----------+-----+-----------+ + + * Register: + +-------------------------+---+----+-----+-----------+ + | Name | FF| LUT| Bits| Const Bits| + +-------------------------+---+----+-----+-----------+ + |ap_CS_fsm | 1| 0| 1| 0| + |ap_done_reg | 1| 0| 1| 0| + |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| + |j_fu_34 | 7| 0| 7| 0| + +-------------------------+---+----+-----+-----------+ + |Total | 10| 0| 10| 0| + +-------------------------+---+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------+-----+-----+------------+----------------------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++----------------------------+-----+-----+------------+----------------------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| zeropad2d_cl,1u>,config44>_Pipeline_PadTopWidth| return value| +|ap_rst | in| 1| ap_ctrl_hs| zeropad2d_cl,1u>,config44>_Pipeline_PadTopWidth| return value| +|ap_start | in| 1| ap_ctrl_hs| zeropad2d_cl,1u>,config44>_Pipeline_PadTopWidth| return value| +|ap_done | out| 1| ap_ctrl_hs| zeropad2d_cl,1u>,config44>_Pipeline_PadTopWidth| return value| +|ap_idle | out| 1| ap_ctrl_hs| zeropad2d_cl,1u>,config44>_Pipeline_PadTopWidth| return value| +|ap_ready | out| 1| ap_ctrl_hs| zeropad2d_cl,1u>,config44>_Pipeline_PadTopWidth| return value| +|layer44_out_din | out| 16| ap_fifo| layer44_out| pointer| +|layer44_out_num_data_valid | in| 14| ap_fifo| layer44_out| pointer| +|layer44_out_fifo_cap | in| 14| ap_fifo| layer44_out| pointer| +|layer44_out_full_n | in| 1| ap_fifo| layer44_out| pointer| +|layer44_out_write | out| 1| ap_fifo| layer44_out| pointer| ++----------------------------+-----+-----+------------+----------------------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s_csynth.rpt b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..7c23160f5d3352ec96465ac4a2937f9af7e25097 --- /dev/null +++ b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s_csynth.rpt @@ -0,0 +1,165 @@ + + +================================================================ +== Vitis HLS Report for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_s' +================================================================ +* Date: Sun Apr 5 21:50:18 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 1.480 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+-----------+-----------+------+------+---------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline| + | min | max | min | max | min | max | Type | + +---------+---------+-----------+-----------+------+------+---------+ + | 4369| 4369| 17.476 us| 17.476 us| 4369| 4369| no| + +---------+---------+-----------+-----------+------+------+---------+ + + + Detail: + * Instance: + +--------------------------------------------------------------------------------------+----------------------------------------------------------------------------+---------+---------+-----------+-----------+------+------+-----------------------------------------------+ + | | | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | Instance | Module | min | max | min | max | min | max | Type | + +--------------------------------------------------------------------------------------+----------------------------------------------------------------------------+---------+---------+-----------+-----------+------+------+-----------------------------------------------+ + |grp_zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth_fu_22 |zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth | 68| 68| 0.272 us| 0.272 us| 67| 67| loop auto-rewind stp(delay=0 clock cycles(s))| + |grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain_fu_28 |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain | 4226| 4226| 16.904 us| 16.904 us| 4225| 4225| loop auto-rewind stp(delay=0 clock cycles(s))| + |grp_zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth_fu_36 |zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth | 68| 68| 0.272 us| 0.272 us| 67| 67| loop auto-rewind stp(delay=0 clock cycles(s))| + +--------------------------------------------------------------------------------------+----------------------------------------------------------------------------+---------+---------+-----------+-----------+------+------+-----------------------------------------------+ + + * Loop: + N/A + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 2| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| 481| 699| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| 0| 110| -| +|Register | -| -| 13| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 0| 0| 494| 811| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + +--------------------------------------------------------------------------------------+----------------------------------------------------------------------------+---------+----+-----+-----+-----+ + | Instance | Module | BRAM_18K| DSP| FF | LUT | URAM| + +--------------------------------------------------------------------------------------+----------------------------------------------------------------------------+---------+----+-----+-----+-----+ + |grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain_fu_28 |zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain | 0| 0| 461| 545| 0| + |grp_zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth_fu_36 |zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth | 0| 0| 10| 77| 0| + |grp_zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth_fu_22 |zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth | 0| 0| 10| 77| 0| + +--------------------------------------------------------------------------------------+----------------------------------------------------------------------------+---------+----+-----+-----+-----+ + |Total | | 0| 0| 481| 699| 0| + +--------------------------------------------------------------------------------------+----------------------------------------------------------------------------+---------+----+-----+-----+-----+ + + * DSP: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +-----------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +-----------------+----------+----+---+----+------------+------------+ + |ap_block_state1 | or| 0| 0| 2| 1| 1| + +-----------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0| 2| 1| 1| + +-----------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +-------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +-------------------+----+-----------+-----+-----------+ + |ap_NS_fsm | 49| 9| 1| 9| + |ap_done | 9| 2| 1| 2| + |layer34_out_read | 9| 2| 1| 2| + |layer56_out_din | 14| 3| 384| 1152| + |layer56_out_write | 20| 4| 1| 4| + |real_start | 9| 2| 1| 2| + +-------------------+----+-----------+-----+-----------+ + |Total | 110| 22| 389| 1171| + +-------------------+----+-----------+-----+-----------+ + + * Register: + +---------------------------------------------------------------------------------------------------+---+----+-----+-----------+ + | Name | FF| LUT| Bits| Const Bits| + +---------------------------------------------------------------------------------------------------+---+----+-----+-----------+ + |ap_CS_fsm | 8| 0| 8| 0| + |ap_done_reg | 1| 0| 1| 0| + |grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain_fu_28_ap_start_reg | 1| 0| 1| 0| + |grp_zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth_fu_36_ap_start_reg | 1| 0| 1| 0| + |grp_zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth_fu_22_ap_start_reg | 1| 0| 1| 0| + |start_once_reg | 1| 0| 1| 0| + +---------------------------------------------------------------------------------------------------+---+----+-----+-----------+ + |Total | 13| 0| 13| 0| + +---------------------------------------------------------------------------------------------------+---+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------+-----+-----+------------+--------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++----------------------------+-----+-----+------------+--------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| zeropad2d_cl,24u>,config56>| return value| +|ap_rst | in| 1| ap_ctrl_hs| zeropad2d_cl,24u>,config56>| return value| +|ap_start | in| 1| ap_ctrl_hs| zeropad2d_cl,24u>,config56>| return value| +|start_full_n | in| 1| ap_ctrl_hs| zeropad2d_cl,24u>,config56>| return value| +|ap_done | out| 1| ap_ctrl_hs| zeropad2d_cl,24u>,config56>| return value| +|ap_continue | in| 1| ap_ctrl_hs| zeropad2d_cl,24u>,config56>| return value| +|ap_idle | out| 1| ap_ctrl_hs| zeropad2d_cl,24u>,config56>| return value| +|ap_ready | out| 1| ap_ctrl_hs| zeropad2d_cl,24u>,config56>| return value| +|start_out | out| 1| ap_ctrl_hs| zeropad2d_cl,24u>,config56>| return value| +|start_write | out| 1| ap_ctrl_hs| zeropad2d_cl,24u>,config56>| return value| +|layer34_out_dout | in| 384| ap_fifo| layer34_out| pointer| +|layer34_out_num_data_valid | in| 13| ap_fifo| layer34_out| pointer| +|layer34_out_fifo_cap | in| 13| ap_fifo| layer34_out| pointer| +|layer34_out_empty_n | in| 1| ap_fifo| layer34_out| pointer| +|layer34_out_read | out| 1| ap_fifo| layer34_out| pointer| +|layer56_out_din | out| 384| ap_fifo| layer56_out| pointer| +|layer56_out_num_data_valid | in| 14| ap_fifo| layer56_out| pointer| +|layer56_out_fifo_cap | in| 14| ap_fifo| layer56_out| pointer| +|layer56_out_full_n | in| 1| ap_fifo| layer56_out| pointer| +|layer56_out_write | out| 1| ap_fifo| layer56_out| pointer| ++----------------------------+-----+-----+------------+--------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth_csynth.xml b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..6ca5852e50f8dae3786dd25c4ae2c70ac8525b0a --- /dev/null +++ b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth_csynth.xml @@ -0,0 +1,202 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth +4.00 +1.35 +vivado + + + +loop auto-rewind stp(delay=0 clock cycles(s)) + +ns +1.480 + + +clock cycles +68 +68 +68 +0.272 us +0.272 us +0.272 us +67 +67 + + + +2.65 +66 +66 +264 +1 +2 + + + + + +- +- +firmware/nnet_utils/nnet_padding_stream.h:53 + + +PadTopWidth +- +- +firmware/nnet_utils/nnet_padding_stream.h:53 + + + + + + + +10 +77 +0 +0 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,8u>,config45>_Pipeline_PadTopWidth +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,8u>,config45>_Pipeline_PadTopWidth +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,8u>,config45>_Pipeline_PadTopWidth +return value + +ap_ctrl_hs + +in +1 +control + + +ap_done +zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,8u>,config45>_Pipeline_PadTopWidth +return value + +ap_ctrl_hs + +out +1 +control + + +ap_idle +zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,8u>,config45>_Pipeline_PadTopWidth +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,8u>,config45>_Pipeline_PadTopWidth +return value + +ap_ctrl_hs + +out +1 +control + + +layer45_out_din +layer45_out +pointer + +ap_fifo + +out +128 +control + + +layer45_out_num_data_valid +layer45_out +pointer + +ap_fifo + +in +14 +control + + +layer45_out_fifo_cap +layer45_out +pointer + +ap_fifo + +in +14 +unknown + + +layer45_out_full_n +layer45_out +pointer + +ap_fifo + +in +1 +control + + +layer45_out_write +layer45_out +pointer + +ap_fifo + +out +1 +control + + + + diff --git a/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth_csynth.rpt b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..ba842df2414356eab364f1926d5c19fefd3ae6a5 --- /dev/null +++ b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth_csynth.rpt @@ -0,0 +1,146 @@ + + +================================================================ +== Vitis HLS Report for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth' +================================================================ +* Date: Sun Apr 5 21:50:37 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 1.480 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+----------+----------+-----+-----+-----------------------------------------------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | min | max | min | max | min | max | Type | + +---------+---------+----------+----------+-----+-----+-----------------------------------------------+ + | 68| 68| 0.272 us| 0.272 us| 67| 67| loop auto-rewind stp(delay=0 clock cycles(s))| + +---------+---------+----------+----------+-----+-----+-----------------------------------------------+ + + + Detail: + * Instance: + N/A + + * Loop: + +---------------+---------+---------+----------+-----------+-----------+------+----------+ + | | Latency (cycles) | Iteration| Initiation Interval | Trip | | + | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| + +---------------+---------+---------+----------+-----------+-----------+------+----------+ + |- PadTopWidth | 66| 66| 2| 1| 1| 66| yes| + +---------------+---------+---------+----------+-----------+-----------+------+----------+ + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 32| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| -| -| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| 0| 45| -| +|Register | -| -| 10| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 0| 0| 10| 77| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + N/A + + * DSP: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +---------------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +---------------------------+----------+----+---+----+------------+------------+ + |j_2_fu_60_p2 | +| 0| 0| 14| 7| 1| + |ap_block_pp0_stage0_01001 | and| 0| 0| 2| 1| 1| + |icmp_ln53_fu_54_p2 | icmp| 0| 0| 14| 7| 7| + |ap_enable_pp0 | xor| 0| 0| 2| 1| 2| + +---------------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0| 32| 16| 11| + +---------------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +-------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +-------------------------+----+-----------+-----+-----------+ + |ap_done_int | 9| 2| 1| 2| + |ap_enable_reg_pp0_iter1 | 9| 2| 1| 2| + |ap_sig_allocacmp_j_1 | 9| 2| 7| 14| + |j_fu_34 | 9| 2| 7| 14| + |layer57_out_blk_n | 9| 2| 1| 2| + +-------------------------+----+-----------+-----+-----------+ + |Total | 45| 10| 17| 34| + +-------------------------+----+-----------+-----+-----------+ + + * Register: + +-------------------------+---+----+-----+-----------+ + | Name | FF| LUT| Bits| Const Bits| + +-------------------------+---+----+-----+-----------+ + |ap_CS_fsm | 1| 0| 1| 0| + |ap_done_reg | 1| 0| 1| 0| + |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| + |j_fu_34 | 7| 0| 7| 0| + +-------------------------+---+----+-----+-----------+ + |Total | 10| 0| 10| 0| + +-------------------------+---+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------+-----+-----+------------+----------------------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++----------------------------+-----+-----+------------+----------------------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| zeropad2d_cl,8u>,config57>_Pipeline_PadTopWidth| return value| +|ap_rst | in| 1| ap_ctrl_hs| zeropad2d_cl,8u>,config57>_Pipeline_PadTopWidth| return value| +|ap_start | in| 1| ap_ctrl_hs| zeropad2d_cl,8u>,config57>_Pipeline_PadTopWidth| return value| +|ap_done | out| 1| ap_ctrl_hs| zeropad2d_cl,8u>,config57>_Pipeline_PadTopWidth| return value| +|ap_idle | out| 1| ap_ctrl_hs| zeropad2d_cl,8u>,config57>_Pipeline_PadTopWidth| return value| +|ap_ready | out| 1| ap_ctrl_hs| zeropad2d_cl,8u>,config57>_Pipeline_PadTopWidth| return value| +|layer57_out_din | out| 128| ap_fifo| layer57_out| pointer| +|layer57_out_num_data_valid | in| 14| ap_fifo| layer57_out| pointer| +|layer57_out_fifo_cap | in| 14| ap_fifo| layer57_out| pointer| +|layer57_out_full_n | in| 1| ap_fifo| layer57_out| pointer| +|layer57_out_write | out| 1| ap_fifo| layer57_out| pointer| ++----------------------------+-----+-----+------------+----------------------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain_csynth.xml b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..b228e29e4dc474e193363504b3020473580a6292 --- /dev/null +++ b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain_csynth.xml @@ -0,0 +1,258 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain +4.00 +1.35 +vivado + + + +loop auto-rewind stp(delay=0 clock cycles(s)) + +ns +1.481 + + +clock cycles +290 +290 +290 +1.160 us +1.160 us +1.160 us +289 +289 + + + +2.65 +16 +288 +1152 +18 +19 + + + + + +- +- +firmware/nnet_utils/nnet_padding_stream.h:59 + + +PadMain +II Violation +Memory Dependency +1 +firmware/nnet_utils/nnet_padding_stream.h:59 + + + + + + + +1563 +244 +0 +0 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,96u>,config52>_Pipeline_PadMain +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,96u>,config52>_Pipeline_PadMain +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,96u>,config52>_Pipeline_PadMain +return value + +ap_ctrl_hs + +in +1 +control + + +ap_done +zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,96u>,config52>_Pipeline_PadMain +return value + +ap_ctrl_hs + +out +1 +control + + +ap_idle +zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,96u>,config52>_Pipeline_PadMain +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,96u>,config52>_Pipeline_PadMain +return value + +ap_ctrl_hs + +out +1 +control + + +layer52_out_din +layer52_out +pointer + +ap_fifo + +out +1536 +control + + +layer52_out_num_data_valid +layer52_out +pointer + +ap_fifo + +in +10 +control + + +layer52_out_fifo_cap +layer52_out +pointer + +ap_fifo + +in +10 +unknown + + +layer52_out_full_n +layer52_out +pointer + +ap_fifo + +in +1 +control + + +layer52_out_write +layer52_out +pointer + +ap_fifo + +out +1 +control + + +layer22_out_dout +layer22_out +pointer + +ap_fifo + +in +1536 +control + + +layer22_out_num_data_valid +layer22_out +pointer + +ap_fifo + +in +9 +control + + +layer22_out_fifo_cap +layer22_out +pointer + +ap_fifo + +in +9 +unknown + + +layer22_out_empty_n +layer22_out +pointer + +ap_fifo + +in +1 +control + + +layer22_out_read +layer22_out +pointer + +ap_fifo + +out +1 +control + + + + diff --git a/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth_csynth.rpt b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..f6b71b7f80ca9eb7af216ec852fd5d309999386f --- /dev/null +++ b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth_csynth.rpt @@ -0,0 +1,146 @@ + + +================================================================ +== Vitis HLS Report for 'zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth' +================================================================ +* Date: Sun Apr 5 21:46:43 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 1.480 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+----------+----------+-----+-----+-----------------------------------------------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | min | max | min | max | min | max | Type | + +---------+---------+----------+----------+-----+-----+-----------------------------------------------+ + | 36| 36| 0.144 us| 0.144 us| 35| 35| loop auto-rewind stp(delay=0 clock cycles(s))| + +---------+---------+----------+----------+-----+-----+-----------------------------------------------+ + + + Detail: + * Instance: + N/A + + * Loop: + +------------------+---------+---------+----------+-----------+-----------+------+----------+ + | | Latency (cycles) | Iteration| Initiation Interval | Trip | | + | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| + +------------------+---------+---------+----------+-----------+-----------+------+----------+ + |- PadBottomWidth | 34| 34| 2| 1| 1| 34| yes| + +------------------+---------+---------+----------+-----------+-----------+------+----------+ + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 30| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| -| -| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| 0| 45| -| +|Register | -| -| 9| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 0| 0| 9| 75| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + N/A + + * DSP: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +---------------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +---------------------------+----------+----+---+----+------------+------------+ + |j_42_fu_60_p2 | +| 0| 0| 13| 6| 1| + |ap_block_pp0_stage0_01001 | and| 0| 0| 2| 1| 1| + |icmp_ln77_fu_54_p2 | icmp| 0| 0| 13| 6| 6| + |ap_enable_pp0 | xor| 0| 0| 2| 1| 2| + +---------------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0| 30| 14| 10| + +---------------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +-------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +-------------------------+----+-----------+-----+-----------+ + |ap_done_int | 9| 2| 1| 2| + |ap_enable_reg_pp0_iter1 | 9| 2| 1| 2| + |ap_sig_allocacmp_j | 9| 2| 6| 12| + |j_40_fu_34 | 9| 2| 6| 12| + |layer47_out_blk_n | 9| 2| 1| 2| + +-------------------------+----+-----------+-----+-----------+ + |Total | 45| 10| 15| 30| + +-------------------------+----+-----------+-----+-----------+ + + * Register: + +-------------------------+---+----+-----+-----------+ + | Name | FF| LUT| Bits| Const Bits| + +-------------------------+---+----+-----+-----------+ + |ap_CS_fsm | 1| 0| 1| 0| + |ap_done_reg | 1| 0| 1| 0| + |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| + |j_40_fu_34 | 6| 0| 6| 0| + +-------------------------+---+----+-----+-----------+ + |Total | 9| 0| 9| 0| + +-------------------------+---+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------+-----+-----+------------+--------------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++----------------------------+-----+-----+------------+--------------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| zeropad2d_cl,config47>_Pipeline_PadBottomWidth| return value| +|ap_rst | in| 1| ap_ctrl_hs| zeropad2d_cl,config47>_Pipeline_PadBottomWidth| return value| +|ap_start | in| 1| ap_ctrl_hs| zeropad2d_cl,config47>_Pipeline_PadBottomWidth| return value| +|ap_done | out| 1| ap_ctrl_hs| zeropad2d_cl,config47>_Pipeline_PadBottomWidth| return value| +|ap_idle | out| 1| ap_ctrl_hs| zeropad2d_cl,config47>_Pipeline_PadBottomWidth| return value| +|ap_ready | out| 1| ap_ctrl_hs| zeropad2d_cl,config47>_Pipeline_PadBottomWidth| return value| +|layer47_out_din | out| 256| ap_fifo| layer47_out| pointer| +|layer47_out_num_data_valid | in| 12| ap_fifo| layer47_out| pointer| +|layer47_out_fifo_cap | in| 12| ap_fifo| layer47_out| pointer| +|layer47_out_full_n | in| 1| ap_fifo| layer47_out| pointer| +|layer47_out_write | out| 1| ap_fifo| layer47_out| pointer| ++----------------------------+-----+-----+------------+--------------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth_csynth.rpt b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..0e7681008574276509e14eebcd1e417980daa73d --- /dev/null +++ b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth_csynth.rpt @@ -0,0 +1,146 @@ + + +================================================================ +== Vitis HLS Report for 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth' +================================================================ +* Date: Sun Apr 5 21:46:53 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 1.481 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+-----------+-----------+-----+-----+-----------------------------------------------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | min | max | min | max | min | max | Type | + +---------+---------+-----------+-----------+-----+-----+-----------------------------------------------+ + | 20| 20| 80.000 ns| 80.000 ns| 19| 19| loop auto-rewind stp(delay=0 clock cycles(s))| + +---------+---------+-----------+-----------+-----+-----+-----------------------------------------------+ + + + Detail: + * Instance: + N/A + + * Loop: + +------------------+---------+---------+----------+-----------+-----------+------+----------+ + | | Latency (cycles) | Iteration| Initiation Interval | Trip | | + | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| + +------------------+---------+---------+----------+-----------+-----------+------+----------+ + |- PadBottomWidth | 18| 18| 2| 1| 1| 18| yes| + +------------------+---------+---------+----------+-----------+-----------+------+----------+ + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 28| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| -| -| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| 0| 45| -| +|Register | -| -| 8| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 0| 0| 8| 73| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + N/A + + * DSP: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +---------------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +---------------------------+----------+----+---+----+------------+------------+ + |j_39_fu_60_p2 | +| 0| 0| 12| 5| 1| + |ap_block_pp0_stage0_01001 | and| 0| 0| 2| 1| 1| + |icmp_ln77_fu_54_p2 | icmp| 0| 0| 12| 5| 5| + |ap_enable_pp0 | xor| 0| 0| 2| 1| 2| + +---------------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0| 28| 12| 9| + +---------------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +-------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +-------------------------+----+-----------+-----+-----------+ + |ap_done_int | 9| 2| 1| 2| + |ap_enable_reg_pp0_iter1 | 9| 2| 1| 2| + |ap_sig_allocacmp_j | 9| 2| 5| 10| + |j_37_fu_34 | 9| 2| 5| 10| + |layer48_out_blk_n | 9| 2| 1| 2| + +-------------------------+----+-----------+-----+-----------+ + |Total | 45| 10| 13| 26| + +-------------------------+----+-----------+-----+-----------+ + + * Register: + +-------------------------+---+----+-----+-----------+ + | Name | FF| LUT| Bits| Const Bits| + +-------------------------+---+----+-----+-----------+ + |ap_CS_fsm | 1| 0| 1| 0| + |ap_done_reg | 1| 0| 1| 0| + |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| + |j_37_fu_34 | 5| 0| 5| 0| + +-------------------------+---+----+-----+-----------+ + |Total | 8| 0| 8| 0| + +-------------------------+---+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------+-----+-----+------------+--------------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++----------------------------+-----+-----+------------+--------------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| zeropad2d_cl,config48>_Pipeline_PadBottomWidth| return value| +|ap_rst | in| 1| ap_ctrl_hs| zeropad2d_cl,config48>_Pipeline_PadBottomWidth| return value| +|ap_start | in| 1| ap_ctrl_hs| zeropad2d_cl,config48>_Pipeline_PadBottomWidth| return value| +|ap_done | out| 1| ap_ctrl_hs| zeropad2d_cl,config48>_Pipeline_PadBottomWidth| return value| +|ap_idle | out| 1| ap_ctrl_hs| zeropad2d_cl,config48>_Pipeline_PadBottomWidth| return value| +|ap_ready | out| 1| ap_ctrl_hs| zeropad2d_cl,config48>_Pipeline_PadBottomWidth| return value| +|layer48_out_din | out| 256| ap_fifo| layer48_out| pointer| +|layer48_out_num_data_valid | in| 10| ap_fifo| layer48_out| pointer| +|layer48_out_fifo_cap | in| 10| ap_fifo| layer48_out| pointer| +|layer48_out_full_n | in| 1| ap_fifo| layer48_out| pointer| +|layer48_out_write | out| 1| ap_fifo| layer48_out| pointer| ++----------------------------+-----+-----+------------+--------------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth_csynth.rpt b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..618cb0385bfc967946f1bd3dba3372a1c3326390 --- /dev/null +++ b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth_csynth.rpt @@ -0,0 +1,146 @@ + + +================================================================ +== Vitis HLS Report for 'zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth' +================================================================ +* Date: Sun Apr 5 21:46:52 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 1.481 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+-----------+-----------+-----+-----+-----------------------------------------------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | min | max | min | max | min | max | Type | + +---------+---------+-----------+-----------+-----+-----+-----------------------------------------------+ + | 20| 20| 80.000 ns| 80.000 ns| 19| 19| loop auto-rewind stp(delay=0 clock cycles(s))| + +---------+---------+-----------+-----------+-----+-----+-----------------------------------------------+ + + + Detail: + * Instance: + N/A + + * Loop: + +---------------+---------+---------+----------+-----------+-----------+------+----------+ + | | Latency (cycles) | Iteration| Initiation Interval | Trip | | + | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| + +---------------+---------+---------+----------+-----------+-----------+------+----------+ + |- PadTopWidth | 18| 18| 2| 1| 1| 18| yes| + +---------------+---------+---------+----------+-----------+-----------+------+----------+ + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 28| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| -| -| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| 0| 45| -| +|Register | -| -| 8| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 0| 0| 8| 73| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + N/A + + * DSP: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +---------------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +---------------------------+----------+----+---+----+------------+------------+ + |j_38_fu_60_p2 | +| 0| 0| 12| 5| 1| + |ap_block_pp0_stage0_01001 | and| 0| 0| 2| 1| 1| + |icmp_ln53_fu_54_p2 | icmp| 0| 0| 12| 5| 5| + |ap_enable_pp0 | xor| 0| 0| 2| 1| 2| + +---------------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0| 28| 12| 9| + +---------------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +-------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +-------------------------+----+-----------+-----+-----------+ + |ap_done_int | 9| 2| 1| 2| + |ap_enable_reg_pp0_iter1 | 9| 2| 1| 2| + |ap_sig_allocacmp_j_37 | 9| 2| 5| 10| + |j_fu_34 | 9| 2| 5| 10| + |layer48_out_blk_n | 9| 2| 1| 2| + +-------------------------+----+-----------+-----+-----------+ + |Total | 45| 10| 13| 26| + +-------------------------+----+-----------+-----+-----------+ + + * Register: + +-------------------------+---+----+-----+-----------+ + | Name | FF| LUT| Bits| Const Bits| + +-------------------------+---+----+-----+-----------+ + |ap_CS_fsm | 1| 0| 1| 0| + |ap_done_reg | 1| 0| 1| 0| + |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| + |j_fu_34 | 5| 0| 5| 0| + +-------------------------+---+----+-----+-----------+ + |Total | 8| 0| 8| 0| + +-------------------------+---+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------+-----+-----+------------+-----------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++----------------------------+-----+-----+------------+-----------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| zeropad2d_cl,config48>_Pipeline_PadTopWidth| return value| +|ap_rst | in| 1| ap_ctrl_hs| zeropad2d_cl,config48>_Pipeline_PadTopWidth| return value| +|ap_start | in| 1| ap_ctrl_hs| zeropad2d_cl,config48>_Pipeline_PadTopWidth| return value| +|ap_done | out| 1| ap_ctrl_hs| zeropad2d_cl,config48>_Pipeline_PadTopWidth| return value| +|ap_idle | out| 1| ap_ctrl_hs| zeropad2d_cl,config48>_Pipeline_PadTopWidth| return value| +|ap_ready | out| 1| ap_ctrl_hs| zeropad2d_cl,config48>_Pipeline_PadTopWidth| return value| +|layer48_out_din | out| 256| ap_fifo| layer48_out| pointer| +|layer48_out_num_data_valid | in| 10| ap_fifo| layer48_out| pointer| +|layer48_out_fifo_cap | in| 10| ap_fifo| layer48_out| pointer| +|layer48_out_full_n | in| 1| ap_fifo| layer48_out| pointer| +|layer48_out_write | out| 1| ap_fifo| layer48_out| pointer| ++----------------------------+-----+-----+------------+-----------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth_csynth.rpt b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..74e6f0d310c1864b224206beadb0bb4b37a4fad9 --- /dev/null +++ b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth_csynth.rpt @@ -0,0 +1,146 @@ + + +================================================================ +== Vitis HLS Report for 'zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth' +================================================================ +* Date: Sun Apr 5 21:50:16 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 1.480 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+----------+----------+-----+-----+-----------------------------------------------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | min | max | min | max | min | max | Type | + +---------+---------+----------+----------+-----+-----+-----------------------------------------------+ + | 68| 68| 0.272 us| 0.272 us| 67| 67| loop auto-rewind stp(delay=0 clock cycles(s))| + +---------+---------+----------+----------+-----+-----+-----------------------------------------------+ + + + Detail: + * Instance: + N/A + + * Loop: + +---------------+---------+---------+----------+-----------+-----------+------+----------+ + | | Latency (cycles) | Iteration| Initiation Interval | Trip | | + | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| + +---------------+---------+---------+----------+-----------+-----------+------+----------+ + |- PadTopWidth | 66| 66| 2| 1| 1| 66| yes| + +---------------+---------+---------+----------+-----------+-----------+------+----------+ + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 32| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| -| -| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| 0| 45| -| +|Register | -| -| 10| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 0| 0| 10| 77| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + N/A + + * DSP: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +---------------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +---------------------------+----------+----+---+----+------------+------------+ + |j_31_fu_60_p2 | +| 0| 0| 14| 7| 1| + |ap_block_pp0_stage0_01001 | and| 0| 0| 2| 1| 1| + |icmp_ln53_fu_54_p2 | icmp| 0| 0| 14| 7| 7| + |ap_enable_pp0 | xor| 0| 0| 2| 1| 2| + +---------------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0| 32| 16| 11| + +---------------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +-------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +-------------------------+----+-----------+-----+-----------+ + |ap_done_int | 9| 2| 1| 2| + |ap_enable_reg_pp0_iter1 | 9| 2| 1| 2| + |ap_sig_allocacmp_j_30 | 9| 2| 7| 14| + |j_fu_34 | 9| 2| 7| 14| + |layer56_out_blk_n | 9| 2| 1| 2| + +-------------------------+----+-----------+-----+-----------+ + |Total | 45| 10| 17| 34| + +-------------------------+----+-----------+-----+-----------+ + + * Register: + +-------------------------+---+----+-----+-----------+ + | Name | FF| LUT| Bits| Const Bits| + +-------------------------+---+----+-----+-----------+ + |ap_CS_fsm | 1| 0| 1| 0| + |ap_done_reg | 1| 0| 1| 0| + |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| + |j_fu_34 | 7| 0| 7| 0| + +-------------------------+---+----+-----+-----------+ + |Total | 10| 0| 10| 0| + +-------------------------+---+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------+-----+-----+------------+-----------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++----------------------------+-----+-----+------------+-----------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| zeropad2d_cl,config56>_Pipeline_PadTopWidth| return value| +|ap_rst | in| 1| ap_ctrl_hs| zeropad2d_cl,config56>_Pipeline_PadTopWidth| return value| +|ap_start | in| 1| ap_ctrl_hs| zeropad2d_cl,config56>_Pipeline_PadTopWidth| return value| +|ap_done | out| 1| ap_ctrl_hs| zeropad2d_cl,config56>_Pipeline_PadTopWidth| return value| +|ap_idle | out| 1| ap_ctrl_hs| zeropad2d_cl,config56>_Pipeline_PadTopWidth| return value| +|ap_ready | out| 1| ap_ctrl_hs| zeropad2d_cl,config56>_Pipeline_PadTopWidth| return value| +|layer56_out_din | out| 384| ap_fifo| layer56_out| pointer| +|layer56_out_num_data_valid | in| 14| ap_fifo| layer56_out| pointer| +|layer56_out_fifo_cap | in| 14| ap_fifo| layer56_out| pointer| +|layer56_out_full_n | in| 1| ap_fifo| layer56_out| pointer| +|layer56_out_write | out| 1| ap_fifo| layer56_out| pointer| ++----------------------------+-----+-----+------------+-----------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth_csynth.rpt b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..ce6396cb6d87bf5320f6354fb489ed3251a77e9b --- /dev/null +++ b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth_csynth.rpt @@ -0,0 +1,146 @@ + + +================================================================ +== Vitis HLS Report for 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth' +================================================================ +* Date: Sun Apr 5 21:47:01 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 1.481 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+-----------+-----------+-----+-----+-----------------------------------------------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | min | max | min | max | min | max | Type | + +---------+---------+-----------+-----------+-----+-----+-----------------------------------------------+ + | 20| 20| 80.000 ns| 80.000 ns| 19| 19| loop auto-rewind stp(delay=0 clock cycles(s))| + +---------+---------+-----------+-----------+-----+-----+-----------------------------------------------+ + + + Detail: + * Instance: + N/A + + * Loop: + +------------------+---------+---------+----------+-----------+-----------+------+----------+ + | | Latency (cycles) | Iteration| Initiation Interval | Trip | | + | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| + +------------------+---------+---------+----------+-----------+-----------+------+----------+ + |- PadBottomWidth | 18| 18| 2| 1| 1| 18| yes| + +------------------+---------+---------+----------+-----------+-----------+------+----------+ + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 28| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| -| -| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| 0| 45| -| +|Register | -| -| 8| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 0| 0| 8| 73| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + N/A + + * DSP: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +---------------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +---------------------------+----------+----+---+----+------------+------------+ + |j_29_fu_60_p2 | +| 0| 0| 12| 5| 1| + |ap_block_pp0_stage0_01001 | and| 0| 0| 2| 1| 1| + |icmp_ln77_fu_54_p2 | icmp| 0| 0| 12| 5| 5| + |ap_enable_pp0 | xor| 0| 0| 2| 1| 2| + +---------------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0| 28| 12| 9| + +---------------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +-------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +-------------------------+----+-----------+-----+-----------+ + |ap_done_int | 9| 2| 1| 2| + |ap_enable_reg_pp0_iter1 | 9| 2| 1| 2| + |ap_sig_allocacmp_j | 9| 2| 5| 10| + |j_26_fu_34 | 9| 2| 5| 10| + |layer49_out_blk_n | 9| 2| 1| 2| + +-------------------------+----+-----------+-----+-----------+ + |Total | 45| 10| 13| 26| + +-------------------------+----+-----------+-----+-----------+ + + * Register: + +-------------------------+---+----+-----+-----------+ + | Name | FF| LUT| Bits| Const Bits| + +-------------------------+---+----+-----+-----------+ + |ap_CS_fsm | 1| 0| 1| 0| + |ap_done_reg | 1| 0| 1| 0| + |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| + |j_26_fu_34 | 5| 0| 5| 0| + +-------------------------+---+----+-----+-----------+ + |Total | 8| 0| 8| 0| + +-------------------------+---+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------+-----+-----+------------+--------------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++----------------------------+-----+-----+------------+--------------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| zeropad2d_cl,config49>_Pipeline_PadBottomWidth| return value| +|ap_rst | in| 1| ap_ctrl_hs| zeropad2d_cl,config49>_Pipeline_PadBottomWidth| return value| +|ap_start | in| 1| ap_ctrl_hs| zeropad2d_cl,config49>_Pipeline_PadBottomWidth| return value| +|ap_done | out| 1| ap_ctrl_hs| zeropad2d_cl,config49>_Pipeline_PadBottomWidth| return value| +|ap_idle | out| 1| ap_ctrl_hs| zeropad2d_cl,config49>_Pipeline_PadBottomWidth| return value| +|ap_ready | out| 1| ap_ctrl_hs| zeropad2d_cl,config49>_Pipeline_PadBottomWidth| return value| +|layer49_out_din | out| 512| ap_fifo| layer49_out| pointer| +|layer49_out_num_data_valid | in| 10| ap_fifo| layer49_out| pointer| +|layer49_out_fifo_cap | in| 10| ap_fifo| layer49_out| pointer| +|layer49_out_full_n | in| 1| ap_fifo| layer49_out| pointer| +|layer49_out_write | out| 1| ap_fifo| layer49_out| pointer| ++----------------------------+-----+-----+------------+--------------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth_csynth.rpt b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..f6e0e7d5571a7b8653b9325e0bcebd0e9a25f199 --- /dev/null +++ b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth_csynth.rpt @@ -0,0 +1,146 @@ + + +================================================================ +== Vitis HLS Report for 'zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth' +================================================================ +* Date: Sun Apr 5 21:47:00 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 1.481 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+-----------+-----------+-----+-----+-----------------------------------------------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | min | max | min | max | min | max | Type | + +---------+---------+-----------+-----------+-----+-----+-----------------------------------------------+ + | 20| 20| 80.000 ns| 80.000 ns| 19| 19| loop auto-rewind stp(delay=0 clock cycles(s))| + +---------+---------+-----------+-----------+-----+-----+-----------------------------------------------+ + + + Detail: + * Instance: + N/A + + * Loop: + +---------------+---------+---------+----------+-----------+-----------+------+----------+ + | | Latency (cycles) | Iteration| Initiation Interval | Trip | | + | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| + +---------------+---------+---------+----------+-----------+-----------+------+----------+ + |- PadTopWidth | 18| 18| 2| 1| 1| 18| yes| + +---------------+---------+---------+----------+-----------+-----------+------+----------+ + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 28| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| -| -| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| 0| 45| -| +|Register | -| -| 8| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 0| 0| 8| 73| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + N/A + + * DSP: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +---------------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +---------------------------+----------+----+---+----+------------+------------+ + |j_28_fu_60_p2 | +| 0| 0| 12| 5| 1| + |ap_block_pp0_stage0_01001 | and| 0| 0| 2| 1| 1| + |icmp_ln53_fu_54_p2 | icmp| 0| 0| 12| 5| 5| + |ap_enable_pp0 | xor| 0| 0| 2| 1| 2| + +---------------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0| 28| 12| 9| + +---------------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +-------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +-------------------------+----+-----------+-----+-----------+ + |ap_done_int | 9| 2| 1| 2| + |ap_enable_reg_pp0_iter1 | 9| 2| 1| 2| + |ap_sig_allocacmp_j_27 | 9| 2| 5| 10| + |j_fu_34 | 9| 2| 5| 10| + |layer49_out_blk_n | 9| 2| 1| 2| + +-------------------------+----+-----------+-----+-----------+ + |Total | 45| 10| 13| 26| + +-------------------------+----+-----------+-----+-----------+ + + * Register: + +-------------------------+---+----+-----+-----------+ + | Name | FF| LUT| Bits| Const Bits| + +-------------------------+---+----+-----+-----------+ + |ap_CS_fsm | 1| 0| 1| 0| + |ap_done_reg | 1| 0| 1| 0| + |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| + |j_fu_34 | 5| 0| 5| 0| + +-------------------------+---+----+-----+-----------+ + |Total | 8| 0| 8| 0| + +-------------------------+---+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------+-----+-----+------------+-----------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++----------------------------+-----+-----+------------+-----------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| zeropad2d_cl,config49>_Pipeline_PadTopWidth| return value| +|ap_rst | in| 1| ap_ctrl_hs| zeropad2d_cl,config49>_Pipeline_PadTopWidth| return value| +|ap_start | in| 1| ap_ctrl_hs| zeropad2d_cl,config49>_Pipeline_PadTopWidth| return value| +|ap_done | out| 1| ap_ctrl_hs| zeropad2d_cl,config49>_Pipeline_PadTopWidth| return value| +|ap_idle | out| 1| ap_ctrl_hs| zeropad2d_cl,config49>_Pipeline_PadTopWidth| return value| +|ap_ready | out| 1| ap_ctrl_hs| zeropad2d_cl,config49>_Pipeline_PadTopWidth| return value| +|layer49_out_din | out| 512| ap_fifo| layer49_out| pointer| +|layer49_out_num_data_valid | in| 10| ap_fifo| layer49_out| pointer| +|layer49_out_fifo_cap | in| 10| ap_fifo| layer49_out| pointer| +|layer49_out_full_n | in| 1| ap_fifo| layer49_out| pointer| +|layer49_out_write | out| 1| ap_fifo| layer49_out| pointer| ++----------------------------+-----+-----+------------+-----------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth_csynth.xml b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..0b946f310e914e85a33b4e63261e0286be4e9a79 --- /dev/null +++ b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth_csynth.xml @@ -0,0 +1,202 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth +4.00 +1.35 +vivado + + + +loop auto-rewind stp(delay=0 clock cycles(s)) + +ns +1.482 + + +clock cycles +12 +12 +12 +48.000 ns +48.000 ns +48.000 ns +11 +11 + + + +2.65 +10 +10 +40 +1 +2 + + + + + +- +- +firmware/nnet_utils/nnet_padding_stream.h:53 + + +PadTopWidth +- +- +firmware/nnet_utils/nnet_padding_stream.h:53 + + + + + + + +7 +73 +0 +0 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +zeropad2d_cl<array,array<ap_fixed,64u>,config51>_Pipeline_PadTopWidth +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +zeropad2d_cl<array,array<ap_fixed,64u>,config51>_Pipeline_PadTopWidth +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +zeropad2d_cl<array,array<ap_fixed,64u>,config51>_Pipeline_PadTopWidth +return value + +ap_ctrl_hs + +in +1 +control + + +ap_done +zeropad2d_cl<array,array<ap_fixed,64u>,config51>_Pipeline_PadTopWidth +return value + +ap_ctrl_hs + +out +1 +control + + +ap_idle +zeropad2d_cl<array,array<ap_fixed,64u>,config51>_Pipeline_PadTopWidth +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +zeropad2d_cl<array,array<ap_fixed,64u>,config51>_Pipeline_PadTopWidth +return value + +ap_ctrl_hs + +out +1 +control + + +layer51_out_din +layer51_out +pointer + +ap_fifo + +out +1024 +control + + +layer51_out_num_data_valid +layer51_out +pointer + +ap_fifo + +in +8 +control + + +layer51_out_fifo_cap +layer51_out +pointer + +ap_fifo + +in +8 +unknown + + +layer51_out_full_n +layer51_out +pointer + +ap_fifo + +in +1 +control + + +layer51_out_write +layer51_out +pointer + +ap_fifo + +out +1 +control + + + + diff --git a/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth_csynth.rpt b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth_csynth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..a65d28fae1f33653a4d2467da84f05350462d4dc --- /dev/null +++ b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth_csynth.rpt @@ -0,0 +1,146 @@ + + +================================================================ +== Vitis HLS Report for 'zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth' +================================================================ +* Date: Sun Apr 5 21:48:09 2026 + +* Version: 2024.1 (Build 5069499 on May 21 2024) +* Project: myproject_prj +* Solution: solution1 (Vivado IP Flow Target) +* Product family: virtexuplusHBM +* Target device: xcvu47p-fsvh2892-2L-e + + +================================================================ +== Performance Estimates +================================================================ ++ Timing: + * Summary: + +--------+---------+----------+------------+ + | Clock | Target | Estimated| Uncertainty| + +--------+---------+----------+------------+ + |ap_clk | 4.00 ns| 1.481 ns| 1.35 ns| + +--------+---------+----------+------------+ + ++ Latency: + * Summary: + +---------+---------+-----------+-----------+-----+-----+-----------------------------------------------+ + | Latency (cycles) | Latency (absolute) | Interval | Pipeline | + | min | max | min | max | min | max | Type | + +---------+---------+-----------+-----------+-----+-----+-----------------------------------------------+ + | 20| 20| 80.000 ns| 80.000 ns| 19| 19| loop auto-rewind stp(delay=0 clock cycles(s))| + +---------+---------+-----------+-----------+-----+-----+-----------------------------------------------+ + + + Detail: + * Instance: + N/A + + * Loop: + +------------------+---------+---------+----------+-----------+-----------+------+----------+ + | | Latency (cycles) | Iteration| Initiation Interval | Trip | | + | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| + +------------------+---------+---------+----------+-----------+-----------+------+----------+ + |- PadBottomWidth | 18| 18| 2| 1| 1| 18| yes| + +------------------+---------+---------+----------+-----------+-----------+------+----------+ + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++---------------------+---------+------+---------+---------+-----+ +| Name | BRAM_18K| DSP | FF | LUT | URAM| ++---------------------+---------+------+---------+---------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 28| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| -| -| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| 0| 45| -| +|Register | -| -| 8| -| -| ++---------------------+---------+------+---------+---------+-----+ +|Total | 0| 0| 8| 73| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available SLR | 1344| 3008| 869120| 434560| 320| ++---------------------+---------+------+---------+---------+-----+ +|Utilization SLR (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ +|Available | 4032| 9024| 2607360| 1303680| 960| ++---------------------+---------+------+---------+---------+-----+ +|Utilization (%) | 0| 0| ~0| ~0| 0| ++---------------------+---------+------+---------+---------+-----+ + ++ Detail: + * Instance: + N/A + + * DSP: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +---------------------------+----------+----+---+----+------------+------------+ + | Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1| + +---------------------------+----------+----+---+----+------------+------------+ + |j_11_fu_60_p2 | +| 0| 0| 12| 5| 1| + |ap_block_pp0_stage0_01001 | and| 0| 0| 2| 1| 1| + |icmp_ln77_fu_54_p2 | icmp| 0| 0| 12| 5| 5| + |ap_enable_pp0 | xor| 0| 0| 2| 1| 2| + +---------------------------+----------+----+---+----+------------+------------+ + |Total | | 0| 0| 28| 12| 9| + +---------------------------+----------+----+---+----+------------+------------+ + + * Multiplexer: + +-------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +-------------------------+----+-----------+-----+-----------+ + |ap_done_int | 9| 2| 1| 2| + |ap_enable_reg_pp0_iter1 | 9| 2| 1| 2| + |ap_sig_allocacmp_j | 9| 2| 5| 10| + |j_2_fu_34 | 9| 2| 5| 10| + |layer52_out_blk_n | 9| 2| 1| 2| + +-------------------------+----+-----------+-----+-----------+ + |Total | 45| 10| 13| 26| + +-------------------------+----+-----------+-----+-----------+ + + * Register: + +-------------------------+---+----+-----+-----------+ + | Name | FF| LUT| Bits| Const Bits| + +-------------------------+---+----+-----+-----------+ + |ap_CS_fsm | 1| 0| 1| 0| + |ap_done_reg | 1| 0| 1| 0| + |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| + |j_2_fu_34 | 5| 0| 5| 0| + +-------------------------+---+----+-----+-----------+ + |Total | 8| 0| 8| 0| + +-------------------------+---+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++----------------------------+-----+------+------------+--------------------------------------------------------------------------+--------------+ +| RTL Ports | Dir | Bits | Protocol | Source Object | C Type | ++----------------------------+-----+------+------------+--------------------------------------------------------------------------+--------------+ +|ap_clk | in| 1| ap_ctrl_hs| zeropad2d_cl,config52>_Pipeline_PadBottomWidth| return value| +|ap_rst | in| 1| ap_ctrl_hs| zeropad2d_cl,config52>_Pipeline_PadBottomWidth| return value| +|ap_start | in| 1| ap_ctrl_hs| zeropad2d_cl,config52>_Pipeline_PadBottomWidth| return value| +|ap_done | out| 1| ap_ctrl_hs| zeropad2d_cl,config52>_Pipeline_PadBottomWidth| return value| +|ap_idle | out| 1| ap_ctrl_hs| zeropad2d_cl,config52>_Pipeline_PadBottomWidth| return value| +|ap_ready | out| 1| ap_ctrl_hs| zeropad2d_cl,config52>_Pipeline_PadBottomWidth| return value| +|layer52_out_din | out| 1536| ap_fifo| layer52_out| pointer| +|layer52_out_num_data_valid | in| 10| ap_fifo| layer52_out| pointer| +|layer52_out_fifo_cap | in| 10| ap_fifo| layer52_out| pointer| +|layer52_out_full_n | in| 1| ap_fifo| layer52_out| pointer| +|layer52_out_write | out| 1| ap_fifo| layer52_out| pointer| ++----------------------------+-----+------+------------+--------------------------------------------------------------------------+--------------+ + diff --git a/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth_csynth.xml b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth_csynth.xml new file mode 100644 index 0000000000000000000000000000000000000000..76155d3ef34cff9285130fb591e447f8288ba849 --- /dev/null +++ b/myproject_prj/solution1/syn/report/zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth_csynth.xml @@ -0,0 +1,202 @@ + + + +2024.1 + + + +ns +virtexuplusHBM +xcvu47p-fsvh2892-2L-e +zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth +4.00 +1.35 +vivado + + + +loop auto-rewind stp(delay=0 clock cycles(s)) + +ns +1.481 + + +clock cycles +20 +20 +20 +80.000 ns +80.000 ns +80.000 ns +19 +19 + + + +2.65 +18 +18 +72 +1 +2 + + + + + +- +- +firmware/nnet_utils/nnet_padding_stream.h:77 + + +PadBottomWidth +- +- +firmware/nnet_utils/nnet_padding_stream.h:77 + + + + + + + +8 +73 +0 +0 +0 + + +4032 +9024 +2607360 +1303680 +960 + + + + + +ap_clk +zeropad2d_cl<array,array<ap_fixed,96u>,config52>_Pipeline_PadBottomWidth +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +zeropad2d_cl<array,array<ap_fixed,96u>,config52>_Pipeline_PadBottomWidth +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +zeropad2d_cl<array,array<ap_fixed,96u>,config52>_Pipeline_PadBottomWidth +return value + +ap_ctrl_hs + +in +1 +control + + +ap_done +zeropad2d_cl<array,array<ap_fixed,96u>,config52>_Pipeline_PadBottomWidth +return value + +ap_ctrl_hs + +out +1 +control + + +ap_idle +zeropad2d_cl<array,array<ap_fixed,96u>,config52>_Pipeline_PadBottomWidth +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +zeropad2d_cl<array,array<ap_fixed,96u>,config52>_Pipeline_PadBottomWidth +return value + +ap_ctrl_hs + +out +1 +control + + +layer52_out_din +layer52_out +pointer + +ap_fifo + +out +1536 +control + + +layer52_out_num_data_valid +layer52_out +pointer + +ap_fifo + +in +10 +control + + +layer52_out_fifo_cap +layer52_out +pointer + +ap_fifo + +in +10 +unknown + + +layer52_out_full_n +layer52_out +pointer + +ap_fifo + +in +1 +control + + +layer52_out_write +layer52_out +pointer + +ap_fifo + +out +1 +control + + + +